1 /*-------------------------------------------------------------------------
2 Register Declarations for ATMEL 89S8252 and 89LS8252 Processors
4 Written By - Dipl.-Ing. (FH) Michael Schmitt
5 mschmitt@mainz-online.de
6 michael.schmitt@t-online.de
10 Additional definitions Nov 23 1999
11 by Bernd Krueger-Knauber <bkk@infratec-plus.de>
13 based on reg51.h by Sandeep Dutta sandeep.dutta@usa.net
14 KEIL C compatible definitions are included
16 This program is free software; you can redistribute it and/or modify it
17 under the terms of the GNU General Public License as published by the
18 Free Software Foundation; either version 2, or (at your option) any
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the Free Software
28 Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 In other words, you are welcome to use, share and improve this program.
31 You are forbidden to forbid anyone else to use, share and improve
32 what you give them. Help stamp out software-hoarding!
33 -------------------------------------------------------------------------*/
38 /* BYTE addressable registers */
42 __sfr __at 0x82 DP0L ; /* as called by Atmel */
44 __sfr __at 0x83 DP0H ; /* as called by Atmel */
45 __sfr __at 0x84 DP1L ; /* at89S8252 specific register */
46 __sfr __at 0x85 DP1H ; /* at89S8252 specific register */
47 __sfr __at 0x86 SPDR ; /* at89S8252 specific register */
48 __sfr __at 0x87 PCON ;
49 __sfr __at 0x88 TCON ;
50 __sfr __at 0x89 TMOD ;
56 __sfr __at 0x96 WMCON ; /* at89S8252 specific register */
57 __sfr __at 0x98 SCON ;
58 __sfr __at 0x99 SBUF ;
61 __sfr __at 0xAA SPSR ; /* at89S8252 specific register */
64 __sfr __at 0xC8 T2CON ;
65 __sfr __at 0xC9 T2MOD ;
66 __sfr __at 0xCA RCAP2L ;
67 __sfr __at 0xCB RCAP2H ;
71 __sfr __at 0xD5 SPCR ; /* at89S8252 specific register */
77 /* BIT addressable registers */
79 __sbit __at 0x80 P0_0 ;
80 __sbit __at 0x81 P0_1 ;
81 __sbit __at 0x82 P0_2 ;
82 __sbit __at 0x83 P0_3 ;
83 __sbit __at 0x84 P0_4 ;
84 __sbit __at 0x85 P0_5 ;
85 __sbit __at 0x86 P0_6 ;
86 __sbit __at 0x87 P0_7 ;
89 __sbit __at 0x88 IT0 ;
90 __sbit __at 0x89 IE0 ;
91 __sbit __at 0x8A IT1 ;
92 __sbit __at 0x8B IE1 ;
93 __sbit __at 0x8C TR0 ;
94 __sbit __at 0x8D TF0 ;
95 __sbit __at 0x8E TR1 ;
96 __sbit __at 0x8F TF1 ;
99 __sbit __at 0x90 P1_0 ;
100 __sbit __at 0x91 P1_1 ;
101 __sbit __at 0x92 P1_2 ;
102 __sbit __at 0x93 P1_3 ;
103 __sbit __at 0x94 P1_4 ;
104 __sbit __at 0x95 P1_5 ;
105 __sbit __at 0x96 P1_6 ;
106 __sbit __at 0x97 P1_7 ;
108 __sbit __at 0x90 T2 ;
109 __sbit __at 0x91 T2EX ;
111 /* P1 SPI portpins */
112 __sbit __at 0x94 SS; /* SPI: SS - Slave port select input */
113 __sbit __at 0x95 MOSI; /* SPI: MOSI - Master data output, slave data input */
114 __sbit __at 0x96 MISO; /* SPI: MISO - Master data input, slave data output */
115 __sbit __at 0x97 SCK; /* SPI: SCK - Master clock output, slave clock input */
119 __sbit __at 0x98 RI ;
120 __sbit __at 0x99 TI ;
121 __sbit __at 0x9A RB8 ;
122 __sbit __at 0x9B TB8 ;
123 __sbit __at 0x9C REN ;
124 __sbit __at 0x9D SM2 ;
125 __sbit __at 0x9E SM1 ;
126 __sbit __at 0x9F SM0 ;
129 __sbit __at 0xA0 P2_0 ;
130 __sbit __at 0xA1 P2_1 ;
131 __sbit __at 0xA2 P2_2 ;
132 __sbit __at 0xA3 P2_3 ;
133 __sbit __at 0xA4 P2_4 ;
134 __sbit __at 0xA5 P2_5 ;
135 __sbit __at 0xA6 P2_6 ;
136 __sbit __at 0xA7 P2_7 ;
139 __sbit __at 0xA8 EX0 ;
140 __sbit __at 0xA9 ET0 ;
141 __sbit __at 0xAA EX1 ;
142 __sbit __at 0xAB ET1 ;
143 __sbit __at 0xAC ES ;
144 __sbit __at 0xAD ET2 ;
145 __sbit __at 0xAF EA ;
148 __sbit __at 0xB0 P3_0 ;
149 __sbit __at 0xB1 P3_1 ;
150 __sbit __at 0xB2 P3_2 ;
151 __sbit __at 0xB3 P3_3 ;
152 __sbit __at 0xB4 P3_4 ;
153 __sbit __at 0xB5 P3_5 ;
154 __sbit __at 0xB6 P3_6 ;
155 __sbit __at 0xB7 P3_7 ;
157 __sbit __at 0xB0 RXD ;
158 __sbit __at 0xB1 TXD ;
159 __sbit __at 0xB2 INT0 ;
160 __sbit __at 0xB3 INT1 ;
161 __sbit __at 0xB4 T0 ;
162 __sbit __at 0xB5 T1 ;
163 __sbit __at 0xB6 WR ;
164 __sbit __at 0xB7 RD ;
167 __sbit __at 0xB8 PX0 ;
168 __sbit __at 0xB9 PT0 ;
169 __sbit __at 0xBA PX1 ;
170 __sbit __at 0xBB PT1 ;
171 __sbit __at 0xBC PS ;
172 __sbit __at 0xBD PT2 ;
175 __sbit __at 0xC8 T2CON_0 ;
176 __sbit __at 0xC9 T2CON_1 ;
177 __sbit __at 0xCA T2CON_2 ;
178 __sbit __at 0xCB T2CON_3 ;
179 __sbit __at 0xCC T2CON_4 ;
180 __sbit __at 0xCD T2CON_5 ;
181 __sbit __at 0xCE T2CON_6 ;
182 __sbit __at 0xCF T2CON_7 ;
184 __sbit __at 0xC8 CP_RL2 ;
185 __sbit __at 0xC9 C_T2 ;
186 __sbit __at 0xCA TR2 ;
187 __sbit __at 0xCB EXEN2 ;
188 __sbit __at 0xCC TCLK ;
189 __sbit __at 0xCD RCLK ;
190 __sbit __at 0xCE EXF2 ;
191 __sbit __at 0xCF TF2 ;
195 __sbit __at 0xD1 FL ;
196 __sbit __at 0xD2 OV ;
197 __sbit __at 0xD3 RS0 ;
198 __sbit __at 0xD4 RS1 ;
199 __sbit __at 0xD5 F0 ;
200 __sbit __at 0xD6 AC ;
201 __sbit __at 0xD7 CY ;
204 __sbit __at 0xF0 BREG_F0 ;
205 __sbit __at 0xF1 BREG_F1 ;
206 __sbit __at 0xF2 BREG_F2 ;
207 __sbit __at 0xF3 BREG_F3 ;
208 __sbit __at 0xF4 BREG_F4 ;
209 __sbit __at 0xF5 BREG_F5 ;
210 __sbit __at 0xF6 BREG_F6 ;
211 __sbit __at 0xF7 BREG_F7 ;
214 /* BIT definitions for bits that are not directly accessible */
259 #define T0_GATE_ 0x08
263 #define T1_GATE_ 0x80
268 #define T0_MASK_ 0x0F
269 #define T1_MASK_ 0xF0
279 #define WMCON_WDTEN 0x01
280 #define WMCON_WDTRST 0x02
281 #define WMCON_DPS 0x04
282 #define WMCON_EEMEN 0x08
283 #define WMCON_EEMWE 0x10
284 #define WMCON_PS0 0x20
285 #define WMCON_PS1 0x40
286 #define WMCON_PS2 0x80
289 #define SPCR_SPR0 0x01
290 #define SPCR_SPR1 0x02
291 #define SPCR_CPHA 0x04
292 #define SPCR_CPOL 0x08
293 #define SPCR_MSTR 0x10
294 #define SPCR_DORD 0x20
295 #define SPCR_SPE 0x40
296 #define SPCR_SPIE 0x80
299 #define SPSR_WCOL 0x40
300 #define SPSR_SPIF 0x80
303 #define SPDR_SPD0 0x10
304 #define SPDR_SPD1 0x20
305 #define SPDR_SPD2 0x40
306 #define SPDR_SPD3 0x80
307 #define SPDR_SPD4 0x10
308 #define SPDR_SPD5 0x20
309 #define SPDR_SPD6 0x40
310 #define SPDR_SPD7 0x80
312 /* Interrupt numbers: address = (number * 8) + 3 */
313 #define IE0_VECTOR 0 /* 0x03 external interrupt 0 */
314 #define EX0_VECTOR 0 /* 0x03 external interrupt 0 */
315 #define TF0_VECTOR 1 /* 0x0b timer 0 */
316 #define IE1_VECTOR 2 /* 0x13 external interrupt 1 */
317 #define EX1_VECTOR 2 /* 0x13 external interrupt 1 */
318 #define TF1_VECTOR 3 /* 0x1b timer 1 */
319 #define SI0_VECTOR 4 /* 0x23 serial port 0 */
320 #define TF2_VECTOR 5 /* 0x2B timer 2 */
321 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
324 /* This is one of the addons comming from Bernd Krueger-Knauber */
326 /* ALE (0x8E) Bit Values */
327 __sfr __at 0x8E ALE; /* at89S8252 specific register */
329 /* Macro to enable and disable the toggling of the ALE-pin (EMV) */
331 /* Explanation : Orignal Intel 8051 Cores (Atmel has to use the */
332 /* Intel Core) have a festure that ALE is only active during */
333 /* MOVX or MOVC instruction. Otherwise the ALE-Pin is weakly */
334 /* pulled high. This can be used to force some external devices */
335 /* into stanby mode and reduced EMI noise */
337 #define ALE_OFF ALE = ALE | 0x01
338 #define ALE_ON ALE = ALE & 0xFE