1 /*-------------------------------------------------------------------------
2 Register Declarations for ATMEL 89S8252 and 89LS8252 Processors
4 Written By - Dipl.-Ing. (FH) Michael Schmitt
5 mschmitt@mainz-online.de
6 michael.schmitt@t-online.de
10 Additional definitions Nov 23 1999
11 by Bernd Krueger-Knauber <bkk@infratec-plus.de>
13 based on reg51.h by Sandeep Dutta sandeep.dutta@usa.net
14 KEIL C compatible definitions are included
17 by Krzysztof Polomka <del_p@op.pl>
19 This program is free software; you can redistribute it and/or modify it
20 under the terms of the GNU General Public License as published by the
21 Free Software Foundation; either version 2, or (at your option) any
24 This program is distributed in the hope that it will be useful,
25 but WITHOUT ANY WARRANTY; without even the implied warranty of
26 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 GNU General Public License for more details.
29 You should have received a copy of the GNU General Public License
30 along with this program; if not, write to the Free Software
31 Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
33 In other words, you are welcome to use, share and improve this program.
34 You are forbidden to forbid anyone else to use, share and improve
35 what you give them. Help stamp out software-hoarding!
36 -------------------------------------------------------------------------*/
41 /* BYTE addressable registers */
42 __sfr __at (0x80) P0 ;
43 __sfr __at (0x81) SP ;
44 __sfr __at (0x82) DPL ;
45 __sfr __at (0x82) DP0L ; /* as called by Atmel */
46 __sfr __at (0x83) DPH ;
47 __sfr __at (0x83) DP0H ; /* as called by Atmel */
48 __sfr __at (0x84) DP1L ; /* at89S8252 specific register */
49 __sfr __at (0x85) DP1H ; /* at89S8252 specific register */
50 __sfr __at (0x86) SPDR ; /* at89S8252 specific register */
51 __sfr __at (0x87) PCON ;
52 __sfr __at (0x88) TCON ;
53 __sfr __at (0x89) TMOD ;
54 __sfr __at (0x8A) TL0 ;
55 __sfr __at (0x8B) TL1 ;
56 __sfr __at (0x8C) TH0 ;
57 __sfr __at (0x8D) TH1 ;
58 __sfr __at (0x90) P1 ;
59 __sfr __at (0x96) WMCON ; /* at89S8252 specific register */
60 __sfr __at (0x98) SCON ;
61 __sfr __at (0x99) SBUF ;
62 __sfr __at (0xA0) P2 ;
63 __sfr __at (0xA8) IE ;
64 __sfr __at (0xAA) SPSR ; /* at89S8252 specific register */
65 __sfr __at (0xB0) P3 ;
66 __sfr __at (0xB8) IP ;
67 __sfr __at (0xC8) T2CON ;
68 __sfr __at (0xC9) T2MOD ;
69 __sfr __at (0xCA) RCAP2L ;
70 __sfr __at (0xCB) RCAP2H ;
71 __sfr __at (0xCC) TL2 ;
72 __sfr __at (0xCD) TH2 ;
73 __sfr __at (0xD0) PSW ;
74 __sfr __at (0xD5) SPCR ; /* at89S8252 specific register */
75 __sfr __at (0xE0) ACC ;
80 /* BIT addressable registers */
82 __sbit __at (0x80) P0_0 ;
83 __sbit __at (0x81) P0_1 ;
84 __sbit __at (0x82) P0_2 ;
85 __sbit __at (0x83) P0_3 ;
86 __sbit __at (0x84) P0_4 ;
87 __sbit __at (0x85) P0_5 ;
88 __sbit __at (0x86) P0_6 ;
89 __sbit __at (0x87) P0_7 ;
92 __sbit __at (0x88) IT0 ;
93 __sbit __at (0x89) IE0 ;
94 __sbit __at (0x8A) IT1 ;
95 __sbit __at (0x8B) IE1 ;
96 __sbit __at (0x8C) TR0 ;
97 __sbit __at (0x8D) TF0 ;
98 __sbit __at (0x8E) TR1 ;
99 __sbit __at (0x8F) TF1 ;
102 __sbit __at (0x90) P1_0 ;
103 __sbit __at (0x91) P1_1 ;
104 __sbit __at (0x92) P1_2 ;
105 __sbit __at (0x93) P1_3 ;
106 __sbit __at (0x94) P1_4 ;
107 __sbit __at (0x95) P1_5 ;
108 __sbit __at (0x96) P1_6 ;
109 __sbit __at (0x97) P1_7 ;
111 __sbit __at (0x90) T2 ;
112 __sbit __at (0x91) T2EX ;
114 /* P1 SPI portpins */
115 __sbit __at (0x94) SS ; /* SPI: SS - Slave port select input */
116 __sbit __at (0x95) MOSI ; /* SPI: MOSI - Master data output, slave data input */
117 __sbit __at (0x96) MISO ; /* SPI: MISO - Master data input, slave data output */
118 __sbit __at (0x97) SCK ; /* SPI: SCK - Master clock output, slave clock input */
122 __sbit __at (0x98) RI ;
123 __sbit __at (0x99) TI ;
124 __sbit __at (0x9A) RB8 ;
125 __sbit __at (0x9B) TB8 ;
126 __sbit __at (0x9C) REN ;
127 __sbit __at (0x9D) SM2 ;
128 __sbit __at (0x9E) SM1 ;
129 __sbit __at (0x9F) SM0 ;
132 __sbit __at (0xA0) P2_0 ;
133 __sbit __at (0xA1) P2_1 ;
134 __sbit __at (0xA2) P2_2 ;
135 __sbit __at (0xA3) P2_3 ;
136 __sbit __at (0xA4) P2_4 ;
137 __sbit __at (0xA5) P2_5 ;
138 __sbit __at (0xA6) P2_6 ;
139 __sbit __at (0xA7) P2_7 ;
142 __sbit __at (0xA8) EX0 ;
143 __sbit __at (0xA9) ET0 ;
144 __sbit __at (0xAA) EX1 ;
145 __sbit __at (0xAB) ET1 ;
146 __sbit __at (0xAC) ES ;
147 __sbit __at (0xAD) ET2 ;
148 __sbit __at (0xAF) EA ;
151 __sbit __at (0xB0) P3_0 ;
152 __sbit __at (0xB1) P3_1 ;
153 __sbit __at (0xB2) P3_2 ;
154 __sbit __at (0xB3) P3_3 ;
155 __sbit __at (0xB4) P3_4 ;
156 __sbit __at (0xB5) P3_5 ;
157 __sbit __at (0xB6) P3_6 ;
158 __sbit __at (0xB7) P3_7 ;
160 __sbit __at (0xB0) RXD ;
161 __sbit __at (0xB1) TXD ;
162 __sbit __at (0xB2) INT0 ;
163 __sbit __at (0xB3) INT1 ;
164 __sbit __at (0xB4) T0 ;
165 __sbit __at (0xB5) T1 ;
166 __sbit __at (0xB6) WR ;
167 __sbit __at (0xB7) RD ;
170 __sbit __at (0xB8) PX0 ;
171 __sbit __at (0xB9) PT0 ;
172 __sbit __at (0xBA) PX1 ;
173 __sbit __at (0xBB) PT1 ;
174 __sbit __at (0xBC) PS ;
175 __sbit __at (0xBD) PT2 ;
178 __sbit __at (0xC8) T2CON_0 ;
179 __sbit __at (0xC9) T2CON_1 ;
180 __sbit __at (0xCA) T2CON_2 ;
181 __sbit __at (0xCB) T2CON_3 ;
182 __sbit __at (0xCC) T2CON_4 ;
183 __sbit __at (0xCD) T2CON_5 ;
184 __sbit __at (0xCE) T2CON_6 ;
185 __sbit __at (0xCF) T2CON_7 ;
187 __sbit __at (0xC8) CP_RL2 ;
188 __sbit __at (0xC9) C_T2 ;
189 __sbit __at (0xCA) TR2 ;
190 __sbit __at (0xCB) EXEN2 ;
191 __sbit __at (0xCC) TCLK ;
192 __sbit __at (0xCD) RCLK ;
193 __sbit __at (0xCE) EXF2 ;
194 __sbit __at (0xCF) TF2 ;
197 __sbit __at (0xD0) P ;
198 __sbit __at (0xD1) FL ;
199 __sbit __at (0xD2) OV ;
200 __sbit __at (0xD3) RS0 ;
201 __sbit __at (0xD4) RS1 ;
202 __sbit __at (0xD5) F0 ;
203 __sbit __at (0xD6) AC ;
204 __sbit __at (0xD7) CY ;
207 __sbit __at (0xF0) BREG_F0 ;
208 __sbit __at (0xF1) BREG_F1 ;
209 __sbit __at (0xF2) BREG_F2 ;
210 __sbit __at (0xF3) BREG_F3 ;
211 __sbit __at (0xF4) BREG_F4 ;
212 __sbit __at (0xF5) BREG_F5 ;
213 __sbit __at (0xF6) BREG_F6 ;
214 __sbit __at (0xF7) BREG_F7 ;
217 /* BIT definitions for bits that are not directly accessible */
262 #define T0_GATE_ 0x08
266 #define T1_GATE_ 0x80
271 #define T0_MASK_ 0x0F
272 #define T1_MASK_ 0xF0
282 #define WMCON_WDTEN 0x01
283 #define WMCON_WDTRST 0x02
284 #define WMCON_DPS 0x04
285 #define WMCON_EEMEN 0x08
286 #define WMCON_EEMWE 0x10
287 #define WMCON_PS0 0x20
288 #define WMCON_PS1 0x40
289 #define WMCON_PS2 0x80
292 #define SPCR_SPR0 0x01
293 #define SPCR_SPR1 0x02
294 #define SPCR_CPHA 0x04
295 #define SPCR_CPOL 0x08
296 #define SPCR_MSTR 0x10
297 #define SPCR_DORD 0x20
298 #define SPCR_SPE 0x40
299 #define SPCR_SPIE 0x80
302 #define SPSR_WCOL 0x40
303 #define SPSR_SPIF 0x80
306 #define SPDR_SPD0 0x01
307 #define SPDR_SPD1 0x02
308 #define SPDR_SPD2 0x04
309 #define SPDR_SPD3 0x08
310 #define SPDR_SPD4 0x10
311 #define SPDR_SPD5 0x20
312 #define SPDR_SPD6 0x40
313 #define SPDR_SPD7 0x80
315 /* Interrupt numbers: address = (number * 8) + 3 */
316 #define IE0_VECTOR 0 /* 0x03 external interrupt 0 */
317 #define EX0_VECTOR 0 /* 0x03 external interrupt 0 */
318 #define TF0_VECTOR 1 /* 0x0b timer 0 */
319 #define IE1_VECTOR 2 /* 0x13 external interrupt 1 */
320 #define EX1_VECTOR 2 /* 0x13 external interrupt 1 */
321 #define TF1_VECTOR 3 /* 0x1b timer 1 */
322 #define SI0_VECTOR 4 /* 0x23 serial port 0 */
323 #define TF2_VECTOR 5 /* 0x2B timer 2 */
324 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
327 /* This is one of the addons coming from Bernd Krueger-Knauber */
329 /* ALE (0x8E) Bit Values */
330 __sfr __at 0x8E ALE; /* at89S8252 specific register */
332 /* Macro to enable and disable the toggling of the ALE-pin (EMV) */
334 /* Explanation : Original Intel 8051 Cores (Atmel has to use the */
335 /* Intel Core) have a feature that ALE is only active during */
336 /* MOVX or MOVC instruction. Otherwise the ALE-Pin is weakly */
337 /* pulled high. This can be used to force some external devices */
338 /* into standby mode and reduced EMI noise */
340 #define ALE_OFF ALE = ALE | 0x01
341 #define ALE_ON ALE = ALE & 0xFE