1 /*-------------------------------------------------------------------------
2 Register Declarations for the Infineon XC866
4 Copyright (C) 2005 - Llewellyn van Zyl, eduprep@myconnection.co.za
6 This library is free software; you can redistribute it and/or
7 modify it under the terms of the GNU Lesser General Public
8 License as published by the Free Software Foundation; either
9 version 2.1 of the License, or (at your option) any later version.
11 This library is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 Lesser General Public License for more details.
16 You should have received a copy of the GNU Lesser General Public
17 License along with this library; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------*/
24 // SFR byte definitions
26 __sfr __at (0xCA) ADC_CHCTR0;
27 __sfr __at (0xCB) ADC_CHCTR1;
28 __sfr __at (0xCC) ADC_CHCTR2;
29 __sfr __at (0xCD) ADC_CHCTR3;
30 __sfr __at (0xCE) ADC_CHCTR4;
31 __sfr __at (0xCF) ADC_CHCTR5;
32 __sfr __at (0xD2) ADC_CHCTR6;
33 __sfr __at (0xD3) ADC_CHCTR7;
34 __sfr __at (0xCB) ADC_CHINCR;
35 __sfr __at (0xCA) ADC_CHINFR;
36 __sfr __at (0xCD) ADC_CHINPR;
37 __sfr __at (0xCC) ADC_CHINSR;
38 __sfr __at (0xCA) ADC_CRCR1;
39 __sfr __at (0xCC) ADC_CRMR1;
40 __sfr __at (0xCB) ADC_CRPR1;
41 __sfr __at (0xCF) ADC_ETRCR;
42 __sfr __at (0xCF) ADC_EVINCR;
43 __sfr __at (0xCE) ADC_EVINFR;
44 __sfr __at (0xD3) ADC_EVINPR;
45 __sfr __at (0xD2) ADC_EVINSR;
46 __sfr __at (0xCA) ADC_GLOBCTR;
47 __sfr __at (0xCB) ADC_GLOBSTR;
48 __sfr __at (0xCE) ADC_INPCR0;
49 __sfr __at (0xCD) ADC_LCBR;
50 __sfr __at (0xD1) ADC_PAGE;
51 __sfr __at (0xCC) ADC_PRAR;
52 __sfr __at (0xCF) ADC_Q0R0;
53 __sfr __at (0xD2) ADC_QBUR0;
54 __sfr __at (0xD2) ADC_QINR0;
55 __sfr __at (0xCD) ADC_QMR0;
56 __sfr __at (0xCE) ADC_QSR0;
57 __sfr __at (0xCA) ADC_RCR0;
58 __sfr __at (0xCB) ADC_RCR1;
59 __sfr __at (0xCC) ADC_RCR2;
60 __sfr __at (0xCD) ADC_RCR3;
61 __sfr __at (0xCB) ADC_RESR0H;
62 __sfr __at (0xCA) ADC_RESR0L;
63 __sfr __at (0xCD) ADC_RESR1H;
64 __sfr __at (0xCC) ADC_RESR1L;
65 __sfr __at (0xCF) ADC_RESR2H;
66 __sfr __at (0xCE) ADC_RESR2L;
67 __sfr __at (0xD3) ADC_RESR3H;
68 __sfr __at (0xD2) ADC_RESR3L;
69 __sfr __at (0xCB) ADC_RESRA0H;
70 __sfr __at (0xCA) ADC_RESRA0L;
71 __sfr __at (0xCD) ADC_RESRA1H;
72 __sfr __at (0xCC) ADC_RESRA1L;
73 __sfr __at (0xCF) ADC_RESRA2H;
74 __sfr __at (0xCE) ADC_RESRA2L;
75 __sfr __at (0xD3) ADC_RESRA3H;
76 __sfr __at (0xD2) ADC_RESRA3L;
77 __sfr __at (0xCE) ADC_VFCR;
79 __sfr __at (0xBD) BCON;
81 __sfr __at (0xFB) CCU6_CC60RH;
82 __sfr __at (0xFA) CCU6_CC60RL;
83 __sfr __at (0xFB) CCU6_CC60SRH;
84 __sfr __at (0xFA) CCU6_CC60SRL;
85 __sfr __at (0xFD) CCU6_CC61RH;
86 __sfr __at (0xFC) CCU6_CC61RL;
87 __sfr __at (0xFD) CCU6_CC61SRH;
88 __sfr __at (0xFC) CCU6_CC61SRL;
89 __sfr __at (0xFF) CCU6_CC62RH;
90 __sfr __at (0xFE) CCU6_CC62RL;
91 __sfr __at (0xFF) CCU6_CC62SRH;
92 __sfr __at (0xFE) CCU6_CC62SRL;
93 __sfr __at (0x9B) CCU6_CC63RH;
94 __sfr __at (0x9A) CCU6_CC63RL;
95 __sfr __at (0x9B) CCU6_CC63SRH;
96 __sfr __at (0x9A) CCU6_CC63SRL;
97 __sfr __at (0xA7) CCU6_CMPMODIFH;
98 __sfr __at (0xA6) CCU6_CMPMODIFL;
99 __sfr __at (0xFF) CCU6_CMPSTATH;
100 __sfr __at (0xFE) CCU6_CMPSTATL;
101 __sfr __at (0x9D) CCU6_IENH;
102 __sfr __at (0x9C) CCU6_IENL;
103 __sfr __at (0x9F) CCU6_INPH;
104 __sfr __at (0x9E) CCU6_INPL;
105 __sfr __at (0x9D) CCU6_ISH;
106 __sfr __at (0x9C) CCU6_ISL;
107 __sfr __at (0xA5) CCU6_ISRH;
108 __sfr __at (0xA4) CCU6_ISRL;
109 __sfr __at (0xA5) CCU6_ISSH;
110 __sfr __at (0xA4) CCU6_ISSL;
111 __sfr __at (0xA7) CCU6_MCMCTR;
112 __sfr __at (0x9B) CCU6_MCMOUTH;
113 __sfr __at (0x9A) CCU6_MCMOUTL;
114 __sfr __at (0x9F) CCU6_MCMOUTSH;
115 __sfr __at (0x9E) CCU6_MCMOUTSL;
116 __sfr __at (0xFD) CCU6_MODCTRH;
117 __sfr __at (0xFC) CCU6_MODCTRL;
118 __sfr __at (0xA3) CCU6_PAGE;
119 __sfr __at (0x9F) CCU6_PISEL0H;
120 __sfr __at (0x9E) CCU6_PISEL0L;
121 __sfr __at (0xA4) CCU6_PISEL2;
122 __sfr __at (0xA6) CCU6_PSLR;
123 __sfr __at (0xA5) CCU6_T12DTCH;
124 __sfr __at (0xA4) CCU6_T12DTCL;
125 __sfr __at (0xFB) CCU6_T12H;
126 __sfr __at (0xFA) CCU6_T12L;
127 __sfr __at (0x9B) CCU6_T12MSELH;
128 __sfr __at (0x9A) CCU6_T12MSELL;
129 __sfr __at (0x9D) CCU6_T12PRH;
130 __sfr __at (0x9C) CCU6_T12PRL;
131 __sfr __at (0xFD) CCU6_T13H;
132 __sfr __at (0xFC) CCU6_T13L;
133 __sfr __at (0x9F) CCU6_T13PRH;
134 __sfr __at (0x9E) CCU6_T13PRL;
135 __sfr __at (0xA7) CCU6_TCTR0H;
136 __sfr __at (0xA6) CCU6_TCTR0L;
137 __sfr __at (0xFB) CCU6_TCTR2H;
138 __sfr __at (0xFA) CCU6_TCTR2L;
139 __sfr __at (0x9D) CCU6_TCTR4H;
140 __sfr __at (0x9C) CCU6_TCTR4L;
141 __sfr __at (0xFF) CCU6_TRPCTRH;
142 __sfr __at (0xFE) CCU6_TRPCTRL;
143 __sfr __at (0xBA) CMCON;
144 __sfr __at (0x83) DPH;
145 __sfr __at (0x82) DPL;
146 __sfr __at (0xA2) EO;
147 __sfr __at (0xB7) EXICON0;
148 __sfr __at (0xBA) EXICON1;
149 __sfr __at (0xBD) FEAH;
150 __sfr __at (0xBC) FEAL;
151 __sfr __at (0xF7) HWBPDR;
152 __sfr __at (0xF6) HWBPSR;
153 __sfr __at (0xB3) ID;
154 __sfr __at (0xA8) IEN0;
155 __sfr __at (0xE8) IEN1;
156 __sfr __at (0xB8) IP;
157 __sfr __at (0xF8) IP1;
158 __sfr __at (0xB9) IPH;
159 __sfr __at (0xF9) IPH1;
160 __sfr __at (0xB4) IRCON0;
161 __sfr __at (0xB5) IRCON1;
162 __sfr __at (0xF3) MMBPCR;
163 __sfr __at (0xF1) MMCR;
164 __sfr __at (0xE9) MMCR2;
165 __sfr __at (0xF5) MMDR;
166 __sfr __at (0xF4) MMICR;
167 __sfr __at (0xF2) MMSR;
168 __sfr __at (0xB3) MODPISEL;
169 __sfr __at (0xBB) NMICON;
170 __sfr __at (0xBC) NMISR;
171 __sfr __at (0xB6) OSC_CON;
172 __sfr __at (0x80) P0_ALTSEL0;
173 __sfr __at (0x86) P0_ALTSEL1;
174 __sfr __at (0x80) P0_DATA;
175 __sfr __at (0x86) P0_DIR;
176 __sfr __at (0x80) P0_OD;
177 __sfr __at (0x86) P0_PUDEN;
178 __sfr __at (0x80) P0_PUDSEL;
179 __sfr __at (0x90) P1_ALTSEL0;
180 __sfr __at (0x91) P1_ALTSEL1;
181 __sfr __at (0x90) P1_DATA;
182 __sfr __at (0x91) P1_DIR;
183 __sfr __at (0x90) P1_OD;
184 __sfr __at (0x91) P1_PUDEN;
185 __sfr __at (0x90) P1_PUDSEL;
186 __sfr __at (0xA0) P2_DATA;
187 __sfr __at (0xA1) P2_PUDEN;
188 __sfr __at (0xA0) P2_PUDSEL;
189 __sfr __at (0xB0) P3_ALTSEL0;
190 __sfr __at (0xB1) P3_ALTSEL1;
191 __sfr __at (0xB0) P3_DATA;
192 __sfr __at (0xB1) P3_DIR;
193 __sfr __at (0xB0) P3_OD;
194 __sfr __at (0xB1) P3_PUDEN;
195 __sfr __at (0xB0) P3_PUDSEL;
196 __sfr __at (0xBB) PASSWD;
197 __sfr __at (0x87) PCON;
198 __sfr __at (0xB7) PLL_CON;
199 __sfr __at (0xB4) PMCON0;
200 __sfr __at (0xB5) PMCON1;
201 __sfr __at (0xB2) PORT_PAGE;
202 __sfr __at (0xD0) PSW;
203 __sfr __at (0x99) SBUF;
204 __sfr __at (0x98) SCON;
205 __sfr __at (0xBF) SCU_PAGE;
206 __sfr __at (0x81) SP;
207 __sfr __at (0xAF) SSC_BRH;
208 __sfr __at (0xAE) SSC_BRL;
209 __sfr __at (0xAB) SSC_CONH_O;
210 __sfr __at (0xAB) SSC_CONH_P;
211 __sfr __at (0xAA) SSC_CONL_O;
212 __sfr __at (0xAA) SSC_CONL_P;
213 __sfr __at (0xA9) SSC_PISEL;
214 __sfr __at (0xAD) SSC_RBL;
215 __sfr __at (0xAC) SSC_TBL;
216 __sfr __at (0x8F) SYSCON0;
217 __sfr __at (0xC3) T2_RC2H;
218 __sfr __at (0xC2) T2_RC2L;
219 __sfr __at (0xC0) T2_T2CON;
220 __sfr __at (0xC5) T2_T2H;
221 __sfr __at (0xC4) T2_T2L;
222 __sfr __at (0xC1) T2_T2MOD;
223 __sfr __at (0x88) TCON;
224 __sfr __at (0x8C) TH0;
225 __sfr __at (0x8D) TH1;
226 __sfr __at (0x8A) TL0;
227 __sfr __at (0x8B) TL1;
228 __sfr __at (0x89) TMOD;
229 __sfr __at (0xBB) WDTCON; // located in the mapped SFR area
230 __sfr __at (0xBF) WDTH; // located in the mapped SFR area
231 __sfr __at (0xBE) WDTL; // located in the mapped SFR area
232 __sfr __at (0xBC) WDTREL; // located in the mapped SFR area
233 __sfr __at (0xBD) WDTWINB; // located in the mapped SFR area
235 __sfr __at (0xB3) XADDRH; // beware this is in an sfr page!
236 __sfr __at (0xB3) _XPAGE; // this is the name SDCC expects for this sfr
238 // SFR bit definitions
241 __sbit __at (0x80) P0_0 ;
242 __sbit __at (0x81) P0_1 ;
243 __sbit __at (0x82) P0_2 ;
244 __sbit __at (0x83) P0_3 ;
245 __sbit __at (0x84) P0_4 ;
246 __sbit __at (0x85) P0_5 ;
249 __sbit __at (0x90) P1_0 ;
250 __sbit __at (0x91) P1_1 ;
251 __sbit __at (0x92) P1_5 ;
252 __sbit __at (0x93) P1_6 ;
253 __sbit __at (0x94) P1_7 ;
256 __sbit __at (0xA0) P2_0 ;
257 __sbit __at (0xA1) P2_1 ;
258 __sbit __at (0xA2) P2_2 ;
259 __sbit __at (0xA3) P2_3 ;
260 __sbit __at (0xA4) P2_4 ;
261 __sbit __at (0xA5) P2_5 ;
262 __sbit __at (0xA6) P2_6 ;
263 __sbit __at (0xA7) P2_7 ;
266 __sbit __at (0xB0) P3_0 ;
267 __sbit __at (0xB1) P3_1 ;
268 __sbit __at (0xB2) P3_2 ;
269 __sbit __at (0xB3) P3_3 ;
270 __sbit __at (0xB4) P3_4 ;
271 __sbit __at (0xB5) P3_5 ;
272 __sbit __at (0xB6) P3_6 ;
273 __sbit __at (0xB7) P3_7 ;
277 __sbit __at (0xAF) EA;
278 __sbit __at (0xAC) ES;
279 __sbit __at (0xA9) ET0;
280 __sbit __at (0xAB) ET1;
281 __sbit __at (0xAD) ET2;
282 __sbit __at (0xA8) EX0;
283 __sbit __at (0xAA) EX1;
286 __sbit __at (0xE8) EADC;
287 __sbit __at (0xEC) ECCIP0;
288 __sbit __at (0xED) ECCIP1;
289 __sbit __at (0xEE) ECCIP2;
290 __sbit __at (0xEF) ECCIP3;
291 __sbit __at (0xE9) ESSC;
292 __sbit __at (0xEA) EX2;
293 __sbit __at (0xEB) EXM;
296 __sbit __at (0xF8) PADC;
297 __sbit __at (0xFC) PCCIP0;
298 __sbit __at (0xFD) PCCIP1;
299 __sbit __at (0xFE) PCCIP2;
300 __sbit __at (0xFF) PCCIP3;
301 __sbit __at (0xF9) PSSC;
302 __sbit __at (0xFA) PX2;
303 __sbit __at (0xFB) PXM;
306 __sbit __at (0xBC) PS;
307 __sbit __at (0xB9) PT0;
308 __sbit __at (0xBB) PT1;
309 __sbit __at (0xBD) PT2;
310 __sbit __at (0xB8) PX0;
311 __sbit __at (0xBA) PX1;
314 __sbit __at (0xD6) AC;
315 __sbit __at (0xD7) CY;
316 __sbit __at (0xD5) F0;
317 __sbit __at (0xD1) F1;
318 __sbit __at (0xD2) OV;
319 __sbit __at (0xD0) P;
320 __sbit __at (0xD3) RS0;
321 __sbit __at (0xD4) RS1;
324 __sbit __at (0x9A) RB8;
325 __sbit __at (0x9C) REN;
326 __sbit __at (0x98) RI;
327 __sbit __at (0x9F) SM0;
328 __sbit __at (0x9E) SM1;
329 __sbit __at (0x9D) SM2;
330 __sbit __at (0x9B) TB8;
331 __sbit __at (0x99) TI;
334 __sbit __at (0xC0) CP_RL2;
335 __sbit __at (0xC3) EXEN2;
336 __sbit __at (0xC6) EXF2;
337 __sbit __at (0xC7) TF2;
338 __sbit __at (0xC2) TR2;
341 __sbit __at (0x89) IE0;
342 __sbit __at (0x8B) IE1;
343 __sbit __at (0x88) IT0;
344 __sbit __at (0x8A) IT1;
345 __sbit __at (0x8D) TF0;
346 __sbit __at (0x8F) TF1;
347 __sbit __at (0x8C) TR0;
348 __sbit __at (0x8E) TR1;
350 // Definition of the PAGE SFR
353 #define _pp0 PORT_PAGE=0 // PORT_PAGE postfix
354 #define _pp1 PORT_PAGE=1 // PORT_PAGE postfix
355 #define _pp2 PORT_PAGE=2 // PORT_PAGE postfix
356 #define _pp3 PORT_PAGE=3 // PORT_PAGE postfix
359 #define _ad0 ADC_PAGE=0 // ADC_PAGE postfix
360 #define _ad1 ADC_PAGE=1 // ADC_PAGE postfix
361 #define _ad2 ADC_PAGE=2 // ADC_PAGE postfix
362 #define _ad3 ADC_PAGE=3 // ADC_PAGE postfix
363 #define _ad4 ADC_PAGE=4 // ADC_PAGE postfix
364 #define _ad5 ADC_PAGE=5 // ADC_PAGE postfix
365 #define _ad6 ADC_PAGE=6 // ADC_PAGE postfix
368 #define _su0 SCU_PAGE=0 // SCU_PAGE postfix
369 #define _su1 SCU_PAGE=1 // SCU_PAGE postfix
370 #define _su2 SCU_PAGE=2 // SCU_PAGE postfix
373 #define _cc0 CCU_PAGE=0 // CCU_PAGE postfix
374 #define _cc1 CCU_PAGE=1 // CCU_PAGE postfix
375 #define _cc2 CCU_PAGE=2 // CCU_PAGE postfix
376 #define _cc3 CCU_PAGE=3 // CCU_PAGE postfix
379 #define _fl0 FLASH_PAGE=0 // FLASH_PAGE postfix
380 #define _fl1 FLASH_PAGE=1 // FLASH_PAGE postfix
381 #define _fl2 FLASH_PAGE=2 // FLASH_PAGE postfix
383 #define SST0 0x80 // Save SFR page to ST0
384 #define RST0 0xC0 // Restore SFR page from ST0
385 #define SST1 0x90 // Save SFR page to ST1
386 #define RST1 0xD0 // Restore SFR page from ST1
387 #define SST2 0xA0 // Save SFR page to ST2
388 #define RST2 0xE0 // Restore SFR page from ST2
389 #define SST3 0xB0 // Save SFR page to ST3
390 #define RST3 0xF0 // Restore SFR page from ST3
391 #define noSST 0x00 // Switch page without saving
393 #define SFR_PAGE(pg,op) pg+op