1 /*-------------------------------------------------------------------------
2 Register Declarations for NXP P89LPC924 and P89LPC925
3 (Based on datasheet Rev. 03
\97 15 December 2004)
5 Written By - Jesus Calvino-Fraga / jesusc at ece.ubc.ca (February 2007)
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2.1 of the License, or (at your option); any later version
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 In other words, you are welcome to use, share and improve this program
22 You are forbidden to forbid anyone else to use, share and improve
23 what you give them. Help stamp out software-hoarding!
24 -------------------------------------------------------------------------*/
26 #ifndef REG_P89LPC925_H
27 #define REG_P89LPC925_H
31 SFR(ACC, 0xE0); // Accumulator
41 SFR(ADCON1, 0x97); // A/D control register 1
51 SFR(ADINS, 0xA3); // A/D input select
57 SFR(ADMODA, 0xC0); // A/D mode register A
63 SFR(ADMODB, 0xA1); // A/D mode register B
70 SFR(AD1BH, 0xC4); // A/D_1 boundary high register
72 SFR(AD1BL, 0xBC); // A/D_1 boundary low register
74 SFR(AD1DAT0, 0xD5); // A/D_1 data register 0
76 SFR(AD1DAT1, 0xD6); // A/D_1 data register 1
78 SFR(AD1DAT2, 0xD7); // A/D_1 data register 2
80 SFR(AD1DAT3, 0xF5); // A/D_1 data register 3
82 SFR(AUXR1, 0xA2); // Auxiliary function register
90 SFR(B, 0xF0); // B register
100 SFR(BRGR0, 0xBE); // Baud rate generator rate LOW
102 SFR(BRGR1, 0xBF); // Baud rate generator rate HIGH
104 SFR(BRGCON, 0xBD); // Baud rate generator control
108 SFR(CMP1, 0xAC); // Comparator1 control register
116 SFR(CMP2, 0xAD); // Comparator2 control register
124 SFR(DIVM, 0x95); // CPU clock divide-by-M control
126 SFR(DPH, 0x83); // Data pointer HIGH
128 SFR(DPL, 0x82); // Data pointer LOW
130 SFR(FMADRH, 0xE7); // Program Flash address HIGH
132 SFR(FMADRL, 0xE6); // Program Flash address LOW
134 SFR(FMCON, 0xE4); // Program Flash control (Read)
141 SFR(FMCON, 0xE4); // Program Flash control (Write)
151 SFR(FMDATA, 0xE5); // Program Flash data
153 SFR(I2ADR, 0xDB); // I2C slave address register
163 SFR(I2CON, 0xD8); // I2C control register
169 SBIT(CRSEL, 0xD8, 0);
171 SFR(I2DAT, 0xDA); // I2C data register
173 SFR(I2SCLH, 0xDD); // Serial clock generator/SCL duty cycle register HIGH
175 SFR(I2SCLL, 0xDC); // Serial clock generator/SCL duty cycle register LOW
177 SFR(I2STAT, 0xD9); // I2C status register
184 SFR(IEN0, 0xA8); // Interrupt enable 0
186 SBIT(EWDRT, 0xA8, 6);
195 SFR(IEN1, 0xE8); // Interrupt enable 1
202 SFR(IP0, 0xB8); // Interrupt priority 0
203 SBIT(PWDRT, 0xB8, 6);
212 SFR(IP0H, 0xB7); // Interrupt priority 0 HIGH
222 SFR(IP1, 0xF8); // Interrupt priority 1
229 SFR(IP1H, 0xF7); // Interrupt priority 1 HIGH
236 SFR(KBCON, 0x94); // Keypad control register
237 #define PATN_SEL 0x02 //Pattern Matching Polarity selection
238 #define KBIF 0x01 // Keypad Interrupt Flag
240 SFR(KBMASK, 0x86); // Keypad interrupt register mask
242 SFR(KBPATN, 0x93); // Keypad pattern register
244 SFR(P0, 0x80); // Port 0
253 //P0 alternate pin functions
255 SBIT(CMP1b, 0x80, 6); //Should be CMP1 but there is SFR with that name
256 SBIT(CMPREF, 0x80, 5);
257 SBIT(CIN1A, 0x80, 4);
258 SBIT(CIN1B, 0x80, 3);
259 SBIT(CIN2A, 0x80, 2);
260 SBIT(CIN2B, 0x80, 1);
261 SBIT(CMP2b, 0x80, 0); //Should be CMP2 but there is SFR with that name
262 //More P0 alternate pin functions
272 SFR(P1, 0x90); // Port 1
281 //P1 alternate pin functions
291 SFR(P3, 0xB0); // Port 3
294 SBIT(XTAL1, 0xB0, 1);
295 SBIT(XTAL2, 0xB0, 0);
297 SFR(P0M1, 0x84); // Port0 output mode1
307 SFR(P0M2, 0x85); // Port0 output mode2
317 SFR(P1M1, 0x91); // Port1 output mode1
326 SFR(P1M2, 0x92); // Port1 output mode2
335 SFR(P3M1, 0xB1); // Port3 output mode1
339 SFR(P3M2, 0xB2); // Port3 output mode2
343 SFR(PCON, 0x87); // Power control register
353 SFR(PCONA, 0xB5); // Power control register A
360 SFR(PSW, 0xD0); // Program status word
370 SFR(PT0AD, 0xF6); // Port0 digital input disable
377 SFR(RSTSRC, 0xDF); // Reset source register
385 SFR(RTCCON, 0xD1); // Real-time clock control
392 SFR(RTCH, 0xD2); // Real-time clock register HIGH
394 SFR(RTCL, 0xD3); // Real-time clock register LOW
396 SFR(SADDR, 0xA9); // Serial port address register
398 SFR(SADEN, 0xB9); // Serial port address enable
400 SFR(SBUF, 0x99); // Serial Port data buffer register
402 SFR(SCON, 0x98); // Serial port control
413 SFR(SSTAT, 0xBA); // Serial port extended status register
423 SFR(SP, 0x81); // Stack pointer
425 SFR(TAMOD, 0x8F); // Timer0 and 1 auxiliary mode
429 SFR(TCON, 0x88); // Timer0 and 1 control
439 SFR(TH0, 0x8C); // Timer0 HIGH
441 SFR(TH1, 0x8D); // Timer 1 HIGH
443 SFR(TL0, 0x8A); // Timer 0 LOW
445 SFR(TL1, 0x8B); // Timer 1 LOW
447 SFR(TMOD, 0x89); // Timer0 and 1 mode
457 SFR(TRIM, 0x96); // Internal oscillator trim register
467 SFR(WDCON, 0xA7); // Watchdog control register
468 #define PRE2 0x80 //Watchdog Prescaler Tap Select bit 2
469 #define PRE1 0x40 //Watchdog Prescaler Tap Select bit 1
470 #define PRE0 0x20 //Watchdog Prescaler Tap Select bit 0
471 #define WDRUN 0x04 //Watchdog Run Control
472 #define WDTOF 0x02 //Watchdog Timer Time-Out Flag
473 #define WDCLK 0x01 //Watchdog input clock select
475 SFR(WDL, 0xC1); // Watchdog load
477 SFR(WFEED1, 0xC2); // Watchdog feed 1
479 SFR(WFEED2, 0xC3); // Watchdog feed 2
481 #endif /*REG_P89LPC925_H*/