1 /*-------------------------------------------------------------------------
\r
2 Register Declarations for NXP P89LPC924 and P89LPC925
\r
3 (Based on datasheet Rev. 03
\97 15 December 2004)
\r
5 Written By - Jesus Calvino-Fraga / jesusc at ece.ubc.ca (February 2007)
\r
7 This library is free software; you can redistribute it and/or
\r
8 modify it under the terms of the GNU Lesser General Public
\r
9 License as published by the Free Software Foundation; either
\r
10 version 2.1 of the License, or (at your option); any later version
\r
12 This library is distributed in the hope that it will be useful,
\r
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
\r
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
\r
15 Lesser General Public License for more details
\r
17 You should have received a copy of the GNU Lesser General Public
\r
18 License along with this library; if not, write to the Free Software
\r
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
\r
21 In other words, you are welcome to use, share and improve this program
\r
22 You are forbidden to forbid anyone else to use, share and improve
\r
23 what you give them. Help stamp out software-hoarding!
\r
24 -------------------------------------------------------------------------*/
\r
26 #ifndef REG_P89LPC925_H
\r
27 #define REG_P89LPC925_H
\r
29 #include <compiler_h>
\r
31 SFR(ACC*, 0xE0); // Accumulator
\r
32 SBIT(ACC_7, 0xE0, 7);
\r
33 SBIT(ACC_6, 0xE0, 6);
\r
34 SBIT(ACC_5, 0xE0, 5);
\r
35 SBIT(ACC_4, 0xE0, 4);
\r
36 SBIT(ACC_3, 0xE0, 3);
\r
37 SBIT(ACC_2, 0xE0, 2);
\r
38 SBIT(ACC_1, 0xE0, 1);
\r
39 SBIT(ACC_0, 0xE0, 0);
\r
41 SFR(ADCON1, 0x97); // A/D control register 1
\r
43 #define ENADCI1 0x40
\r
51 SFR(ADINS, 0xA3); // A/D input select
\r
57 SFR(ADMODA, 0xC0); // A/D mode register A
\r
63 SFR(ADMODB, 0xA1); // A/D mode register B
\r
70 SFR(AD1BH, 0xC4); // A/D_1 boundary high register
\r
72 SFR(AD1BL, 0xBC); // A/D_1 boundary low register
\r
74 SFR(AD1DAT0, 0xD5); // A/D_1 data register 0
\r
76 SFR(AD1DAT1, 0xD6); // A/D_1 data register 1
\r
78 SFR(AD1DAT2, 0xD7); // A/D_1 data register 2
\r
80 SFR(AD1DAT3, 0xF5); // A/D_1 data register 3
\r
82 SFR(AUXR1, 0xA2); // Auxiliary function register
\r
90 SFR(B*, 0xF0); // B register
\r
100 SFR(BRGR0, 0xBE); // Baud rate generator rate LOW
\r
102 SFR(BRGR1, 0xBF); // Baud rate generator rate HIGH
\r
104 SFR(BRGCON, 0xBD); // Baud rate generator control
\r
108 SFR(CMP1, 0xAC); // Comparator1 control register
\r
116 SFR(CMP2, 0xAD); // Comparator2 control register
\r
124 SFR(DIVM, 0x95); // CPU clock divide-by-M control
\r
126 SFR(DPH, 0x83); // Data pointer HIGH
\r
128 SFR(DPL, 0x82); // Data pointer LOW
\r
130 SFR(FMADRH, 0xE7); // Program Flash address HIGH
\r
132 SFR(FMADRL, 0xE6); // Program Flash address LOW
\r
134 SFR(FMCON, 0xE4); // Program Flash control (Read)
\r
141 SFR(FMCON, 0xE4); // Program Flash control (Write)
\r
142 #define FMCMD_7 0x80
\r
143 #define FMCMD_6 0x40
\r
144 #define FMCMD_5 0x20
\r
145 #define FMCMD_4 0x10
\r
146 #define FMCMD_3 0x08
\r
147 #define FMCMD_2 0x04
\r
148 #define FMCMD_1 0x02
\r
149 #define FMCMD_0 0x01
\r
151 SFR(FMDATA, 0xE5); // Program Flash data
\r
153 SFR(I2ADR, 0xDB); // I2C slave address register
\r
154 #define I2ADR_6 0x80
\r
155 #define I2ADR_5 0x40
\r
156 #define I2ADR_4 0x20
\r
157 #define I2ADR_3 0x10
\r
158 #define I2ADR_2 0x08
\r
159 #define I2ADR_1 0x04
\r
160 #define I2ADR_0 0x02
\r
163 SFR(I2CON*, 0xD8); // I2C control register
\r
164 SBIT(I2EN, 0xD8, 6);
\r
165 SBIT(STA, 0xD8, 5);
\r
166 SBIT(STO, 0xD8, 4);
\r
169 SBIT(CRSEL, 0xD8, 0);
\r
171 SFR(I2DAT, 0xDA); // I2C data register
\r
173 SFR(I2SCLH, 0xDD); // Serial clock generator/SCL duty cycle register HIGH
\r
175 SFR(I2SCLL, 0xDC); // Serial clock generator/SCL duty cycle register LOW
\r
177 SFR(I2STAT, 0xD9); // I2C status register
\r
184 SFR(IEN0*, 0xA8); // Interrupt enable 0
\r
186 SBIT(EWDRT, 0xA8, 6);
\r
187 SBIT(EBO, 0xA8, 5);
\r
189 SBIT(ESR, 0xA8, 4);
\r
190 SBIT(ET1, 0xA8, 3);
\r
191 SBIT(EX1, 0xA8, 2);
\r
192 SBIT(ET0, 0xA8, 1);
\r
193 SBIT(EX0, 0xA8, 0);
\r
195 SFR(IEN1*, 0xE8); // Interrupt enable 1
\r
196 SBIT(EAD, 0xE8, 7);
\r
197 SBIT(EST, 0xE8, 6);
\r
199 SBIT(EKBI, 0xE8, 1);
\r
200 SBIT(EI2C, 0xE8, 0);
\r
202 SFR(IP0*, 0xB8); // Interrupt priority 0
\r
203 SBIT(PWDRT, 0xB8, 6);
\r
204 SBIT(PBO, 0xB8, 5);
\r
206 SBIT(PSR, 0xB8, 4);
\r
207 SBIT(PT1, 0xB8, 3);
\r
208 SBIT(PX1, 0xB8, 2);
\r
209 SBIT(PT0, 0xB8, 1);
\r
210 SBIT(PX0, 0xB8, 0);
\r
212 SFR(IP0H, 0xB7); // Interrupt priority 0 HIGH
\r
213 #define PWDRTH 0x40
\r
222 SFR(IP1*, 0xF8); // Interrupt priority 1
\r
223 SBIT(PAD, 0xF8, 7);
\r
224 SBIT(PST, 0xF8, 6);
\r
226 SBIT(PKBI, 0xF8, 1);
\r
227 SBIT(PI2C, 0xF8, 0);
\r
229 SFR(IP1H, 0xF7); // Interrupt priority 1 HIGH
\r
236 SFR(KBCON, 0x94); // Keypad control register
\r
237 #define PATN_SEL 0x02 //Pattern Matching Polarity selection
\r
238 #define KBIF 0x01 // Keypad Interrupt Flag
\r
240 SFR(KBMASK, 0x86); // Keypad interrupt register mask
\r
242 SFR(KBPATN, 0x93); // Keypad pattern register
\r
244 SFR(P0*, 0x80); // Port 0
\r
245 SBIT(P0_7, 0x80, 7);
\r
246 SBIT(P0_6, 0x80, 6);
\r
247 SBIT(P0_5, 0x80, 5);
\r
248 SBIT(P0_4, 0x80, 4);
\r
249 SBIT(P0_3, 0x80, 3);
\r
250 SBIT(P0_2, 0x80, 2);
\r
251 SBIT(P0_1, 0x80, 1);
\r
252 SBIT(P0_0, 0x80, 0);
\r
253 //P0 alternate pin functions
\r
255 SBIT(CMP1, 0x80, 6);
\r
256 SBIT(CMPREF, 0x80, 5);
\r
257 SBIT(CIN1A, 0x80, 4);
\r
258 SBIT(CIN1B, 0x80, 3);
\r
259 SBIT(CIN2A, 0x80, 2);
\r
260 SBIT(CIN2B, 0x80, 1);
\r
261 SBIT(CMP2, 0x80, 0);
\r
262 //More P0 alternate pin functions
\r
263 SBIT(KB7, 0x80, 7);
\r
264 SBIT(KB6, 0x80, 6);
\r
265 SBIT(KB5, 0x80, 5);
\r
266 SBIT(KB4, 0x80, 4);
\r
267 SBIT(KB3, 0x80, 3);
\r
268 SBIT(KB2, 0x80, 2);
\r
269 SBIT(KB1, 0x80, 1);
\r
270 SBIT(KB0, 0x80, 0);
\r
272 SFR(P1*, 0x90); // Port 1
\r
273 SBIT(P1_5, 0x90, 5);
\r
274 SBIT(P1_4, 0x90, 4);
\r
275 SBIT(P1_3, 0x90, 3);
\r
276 SBIT(P1_2, 0x90, 2);
\r
277 SBIT(P1_1, 0x90, 1);
\r
278 SBIT(P1_0, 0x90, 0);
\r
279 //P1 alternate pin functions
\r
280 SBIT(RST, 0x90, 5);
\r
281 SBIT(INT1, 0x90, 4);
\r
282 SBIT(INT0, 0x90, 3);
\r
283 SBIT(SDA, 0x90, 3);
\r
285 SBIT(SCL, 0x90, 2);
\r
286 SBIT(RXD, 0x90, 1);
\r
287 SBIT(TXD, 0x90, 0);
\r
289 SFR(P3*, 0xB0); // Port 3
\r
290 SBIT(P3_1, 0xB0, 1);
\r
291 SBIT(P3_0, 0xB0, 0);
\r
292 SBIT(XTAL1, 0xB0, 1);
\r
293 SBIT(XTAL2, 0xB0, 0);
\r
295 SFR(P0M1, 0x84); // Port0 output mode1
\r
296 #define P0M1_7 0x80
\r
297 #define P0M1_6 0x40
\r
298 #define P0M1_5 0x20
\r
299 #define P0M1_4 0x10
\r
300 #define P0M1_3 0x08
\r
301 #define P0M1_2 0x04
\r
302 #define P0M1_1 0x02
\r
303 #define P0M1_0 0x01
\r
305 SFR(P0M2, 0x85); // Port0 output mode2
\r
306 #define P0M2_7 0x80
\r
307 #define P0M2_6 0x40
\r
308 #define P0M2_5 0x20
\r
309 #define P0M2_4 0x10
\r
310 #define P0M2_3 0x08
\r
311 #define P0M2_2 0x04
\r
312 #define P0M2_1 0x02
\r
313 #define P0M2_0 0x01
\r
315 SFR(P1M1, 0x91); // Port1 output mode1
\r
316 #define P1M1_7 0x80
\r
317 #define P1M1_6 0x40
\r
318 #define P1M1_4 0x10
\r
319 #define P1M1_3 0x08
\r
320 #define P1M1_2 0x04
\r
321 #define P1M1_1 0x02
\r
322 #define P1M1_0 0x01
\r
324 SFR(P1M2, 0x92); // Port1 output mode2
\r
325 #define P1M2_7 0x80
\r
326 #define P1M2_6 0x40
\r
327 #define P1M2_4 0x10
\r
328 #define P1M2_3 0x08
\r
329 #define P1M2_2 0x04
\r
330 #define P1M2_1 0x02
\r
331 #define P1M2_0 0x01
\r
333 SFR(P3M1, 0xB1); // Port3 output mode1
\r
334 #define P3M1_1 0x02
\r
335 #define P3M1_0 0x01
\r
337 SFR(P3M2, 0xB2); // Port3 output mode2
\r
338 #define P3M2_1 0x02
\r
339 #define P3M2_0 0x01
\r
341 SFR(PCON, 0x87); // Power control register
\r
351 SFR(PCONA, 0xB5); // Power control register A
\r
358 SFR(PSW*, 0xD0); // Program status word
\r
362 SBIT(RS1, 0xD0, 4);
\r
363 SBIT(RS0, 0xD0, 3);
\r
368 SFR(PT0AD, 0xF6); // Port0 digital input disable
\r
369 #define PT0AD_5 0x20
\r
370 #define PT0AD_4 0x10
\r
371 #define PT0AD_3 0x08
\r
372 #define PT0AD_2 0x04
\r
373 #define PT0AD_1 0x02
\r
375 SFR(RSTSRC, 0xDF); // Reset source register
\r
383 SFR(RTCCON, 0xD1); // Real-time clock control
\r
390 SFR(RTCH, 0xD2); // Real-time clock register HIGH
\r
392 SFR(RTCL, 0xD3); // Real-time clock register LOW
\r
394 SFR(SADDR, 0xA9); // Serial port address register
\r
396 SFR(SADEN, 0xB9); // Serial port address enable
\r
398 SFR(SBUF, 0x99); // Serial Port data buffer register
\r
400 SFR(SCON*, 0x98); // Serial port control
\r
402 SBIT(SM0, 0x98, 7);
\r
403 SBIT(SM1, 0x98, 6);
\r
404 SBIT(SM2, 0x98, 5);
\r
405 SBIT(REN, 0x98, 4);
\r
406 SBIT(TB8, 0x98, 3);
\r
407 SBIT(RB8, 0x98, 2);
\r
411 SFR(SSTAT, 0xBA); // Serial port extended status register
\r
415 #define DBISEL 0x10
\r
421 SFR(SP, 0x81); // Stack pointer
\r
423 SFR(TAMOD, 0x8F); // Timer0 and 1 auxiliary mode
\r
427 SFR(TCON*, 0x88); // Timer0 and 1 control
\r
428 SBIT(TF1, 0x88, 7);
\r
429 SBIT(TR1, 0x88, 6);
\r
430 SBIT(TF0, 0x88, 5);
\r
431 SBIT(TR0, 0x88, 4);
\r
432 SBIT(IE1, 0x88, 3);
\r
433 SBIT(IT1, 0x88, 2);
\r
434 SBIT(IE0, 0x88, 1);
\r
435 SBIT(IT0, 0x88, 0);
\r
437 SFR(TH0, 0x8C); // Timer0 HIGH
\r
439 SFR(TH1, 0x8D); // Timer 1 HIGH
\r
441 SFR(TL0, 0x8A); // Timer 0 LOW
\r
443 SFR(TL1, 0x8B); // Timer 1 LOW
\r
445 SFR(TMOD, 0x89); // Timer0 and 1 mode
\r
446 #define T1GATE 0x80
\r
450 #define T0GATE 0x08
\r
455 SFR(TRIM, 0x96); // Internal oscillator trim register
\r
458 #define TRIM_5 0x20
\r
459 #define TRIM_4 0x10
\r
460 #define TRIM_3 0x08
\r
461 #define TRIM_2 0x04
\r
462 #define TRIM_1 0x02
\r
463 #define TRIM_0 0x01
\r
465 SFR(WDCON, 0xA7); // Watchdog control register
\r
466 #define PRE2 0x80 //Watchdog Prescaler Tap Select bit 2
\r
467 #define PRE1 0x40 //Watchdog Prescaler Tap Select bit 1
\r
468 #define PRE0 0x20 //Watchdog Prescaler Tap Select bit 0
\r
469 #define WDRUN 0x04 //Watchdog Run Control
\r
470 #define WDTOF 0x02 //Watchdog Timer Time-Out Flag
\r
471 #define WDCLK 0x01 //Watchdog input clock select
\r
473 SFR(WDL, 0xC1); // Watchdog load
\r
475 SFR(WFEED1, 0xC2); // Watchdog feed 1
\r
477 SFR(WFEED2, 0xC3); // Watchdog feed 2
\r
479 #endif /*REG_P89LPC925_H*/
\r