1 /*------------------------------------------------------------------//--------
4 This header allows to use the microcontroler Philips P89LPC922
5 with the compiler SDCC.
7 Copyright (c) 2005 Omar Espinosa--e-mail: opiedrahita2003 AT yahoo.com.
9 This library is free software; you can redistribute it and/or
10 modify it under the terms of the GNU Lesser General Public
11 License as published by the Free Software Foundation; either
12 version 2.1 of the License, or (at your option) any later version.
14 This library is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 Lesser General Public License for more details.
19 You should have received a copy of the GNU Lesser General Public
20 License along with this library; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 Archivo encabezador para el ucontrolador Philips P89LPC922.
25 Derechos de copy (DC) 2005. OMAR ESPINOSA P. E-mail: opiedrahita2003 AT yahoo.com
27 //------------------------------------------------------------------//--//------*/
31 //* BYTE Registers *//
32 __sfr __at (0x80) P0 ;
33 __sfr __at (0x90) P1 ;
34 __sfr __at (0xB0) P3 ;
35 __sfr __at (0xD0) PSW ;
36 __sfr __at (0xE0) ACC ;
38 __sfr __at (0x81) SP ;
39 __sfr __at (0x82) DPL ;
40 __sfr __at (0x83) DPH ;
41 __sfr __at (0x87) PCON ;
42 __sfr __at (0x88) TCON ;
43 __sfr __at (0x89) TMOD ;
44 __sfr __at (0x8A) TL0 ;
45 __sfr __at (0x8B) TL1 ;
46 __sfr __at (0x8B) TH0 ;
47 __sfr __at (0x8D) TH1 ;
48 __sfr __at (0xA8) IEN0 ;
49 __sfr __at (0xB8) IP0 ;
50 __sfr __at (0x98) SCON ;
51 __sfr __at (0x99) SBUF ;
54 __sfr __at (0xA2) AUXR1 ;
55 __sfr __at (0xA9) SADDR ;
56 __sfr __at (0xB9) SADEN ;
57 __sfr __at (0xBE) BRGR0 ;
58 __sfr __at (0xBF) BRGR1 ;
59 __sfr __at (0xBD) BRGCON ;
60 __sfr __at (0xAC) CMP1 ;
61 __sfr __at (0xAD) CMP2 ;
62 __sfr __at (0x95) DIVM ;
63 __sfr __at (0xE7) FMADRH ;
64 __sfr __at (0xE6) FMADRL ;
65 __sfr __at (0xE4) FMCON ;
66 __sfr __at (0xE5) FMDATA ;
67 __sfr __at (0xDB) I2ADR ;
68 __sfr __at (0xD8) I2CON ;
69 __sfr __at (0xDA) I2DAT ;
70 __sfr __at (0xDD) I2SCLH ;
71 __sfr __at (0xDC) I2SCLL ;
72 __sfr __at (0xD9) I2STAT ;
73 __sfr __at (0xF8) IP1 ;
74 __sfr __at (0xF7) IP1H ;
75 __sfr __at (0x94) KBCON ;
76 __sfr __at (0x86) KBMASK ;
77 __sfr __at (0x93) KBPATN ;
78 __sfr __at (0x84) P0M1 ;
79 __sfr __at (0x85) P0M2 ;
80 __sfr __at (0x91) P1M1 ;
81 __sfr __at (0x92) P1M2 ;
82 __sfr __at (0xB1) P3M1 ;
83 __sfr __at (0xB2) P3M2 ;
84 __sfr __at (0xB5) PCONA ;
85 __sfr __at (0xF6) PT0AD ;
86 __sfr __at (0xDF) RSTSRC ;
87 __sfr __at (0xD1) RTCCON ;
88 __sfr __at (0xD2) RTCH ;
89 __sfr __at (0xD3) RTCL ;
90 __sfr __at (0xBA) SSTAT ;
91 __sfr __at (0x8F) TAMOD ;
92 __sfr __at (0x96) TRIM ;
93 __sfr __at (0xA7) WDCON ;
94 __sfr __at (0xC1) WDL ;
95 __sfr __at (0xC2) WFEED1 ;
96 __sfr __at (0xC3) WFEED2 ;
97 __sfr __at (0xB7) IP0H ;
98 __sfr __at (0xE8) IEN1 ;
102 __sbit __at (0xD0) PSW_0 ;
103 __sbit __at (0xD1) PSW_1 ;
104 __sbit __at (0xD2) PSW_2 ;
105 __sbit __at (0xD3) PSW_3 ;
106 __sbit __at (0xD4) PSW_4 ;
107 __sbit __at (0xD5) PSW_5 ;
108 __sbit __at (0xD6) PSW_6 ;
109 __sbit __at (0xD7) PSW_7 ;
121 __sbit __at (0x8F) TCON_7 ;
122 __sbit __at (0x8E) TCON_6 ;
123 __sbit __at (0x8D) TCON_5 ;
124 __sbit __at (0x8C) TCON_4 ;
125 __sbit __at (0x8B) TCON_3 ;
126 __sbit __at (0x8A) TCON_2 ;
127 __sbit __at (0x89) TCON_1 ;
128 __sbit __at (0x88) TCON_0 ;
140 __sbit __at (0xAF) IEN0_7 ;
141 __sbit __at (0xAE) IEN0_6 ;
142 __sbit __at (0xAD) IEN0_5 ;
143 __sbit __at (0xAC) IEN0_4 ;
144 __sbit __at (0xAB) IEN0_3 ;
145 __sbit __at (0xAA) IEN0_2 ;
146 __sbit __at (0xA9) IEN0_1 ;
147 __sbit __at (0xA8) IEN0_0 ;
152 #define ES IEN0_4 // alternatively "ESR"
160 __sbit __at (0xEA) IEN1_2 ;
161 __sbit __at (0xE9) IEN1_1 ;
162 __sbit __at (0xE8) IEN1_0 ;
169 __sbit __at (0xFE) IP1_6 ;
170 __sbit __at (0xFA) IP1_2 ;
171 __sbit __at (0xF9) IP1_1 ;
172 __sbit __at (0xF8) IP1_0 ;
180 __sbit __at (0xBE) IP0_6 ;
181 __sbit __at (0xBD) IP0_5 ;
182 __sbit __at (0xBC) IP0_4 ; // alternatively "PSR"
183 __sbit __at (0xBB) IP0_3 ;
184 __sbit __at (0xBA) IP0_2 ;
185 __sbit __at (0xB9) IP0_1 ;
186 __sbit __at (0xB8) IP0_0 ;
190 #define PS IP0_4 // alternatively "PSR"
198 __sbit __at (0x98) SCON_0 ;
199 __sbit __at (0x99) SCON_1 ;
200 __sbit __at (0x9A) SCON_2 ;
201 __sbit __at (0x9B) SCON_3 ;
202 __sbit __at (0x9C) SCON_4 ;
203 __sbit __at (0x9D) SCON_5 ;
204 __sbit __at (0x9E) SCON_6 ;
205 __sbit __at (0x9F) SCON_7 ;
207 #define SM0 SCON_7 // alternatively "FE"
218 __sbit __at (0xDE) I2CON_6 ;
219 __sbit __at (0xDD) I2CON_5 ;
220 __sbit __at (0xDC) I2CON_4 ;
221 __sbit __at (0xDB) I2CON_3 ;
222 __sbit __at (0xDA) I2CON_2 ;
223 __sbit __at (0xD8) I2CON_0 ;
230 #define CRSEL I2CON_0
233 __sbit __at (0x80) P0_0 ;
234 __sbit __at (0x81) P0_1 ;
235 __sbit __at (0x82) P0_2 ;
236 __sbit __at (0x83) P0_3 ;
237 __sbit __at (0x84) P0_4 ;
238 __sbit __at (0x85) P0_5 ;
239 __sbit __at (0x86) P0_6 ;
240 __sbit __at (0x87) P0_7 ;
242 #define KB7 P0_7 // alternatively "T1"
244 #define KB6 P0_6 // alternatively "CMP1"
251 #define KB0 P0_0 // alternatively "CMP2"
255 __sbit __at (0x90) P1_0 ;
256 __sbit __at (0x91) P1_1 ;
257 __sbit __at (0x92) P1_2 ;
258 __sbit __at (0x93) P1_3 ;
259 __sbit __at (0x94) P1_4 ;
260 __sbit __at (0x95) P1_5 ;
261 __sbit __at (0x96) P1_6 ;
262 __sbit __at (0x97) P1_7 ;
266 #define INT0 P1_3 // alternatively "SDA"
268 #define T0 P1_2 // alternatively "SCL"
274 __sbit __at (0xB0) P3_0 ;
275 __sbit __at (0xB1) P3_1 ;