1 /*-------------------------------------------------------------------------
2 Register Declarations for the SiLabs C8051T63x Processor Range
4 Copyright (C) 2008 - Steven Borley, steven.borley@partnerelectronics.com
6 This library is free software; you can redistribute it and/or
7 modify it under the terms of the GNU Lesser General Public
8 License as published by the Free Software Foundation; either
9 version 2.1 of the License, or (at your option) any later version.
11 This library is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 Lesser General Public License for more details.
16 You should have received a copy of the GNU Lesser General Public
17 License along with this library; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------*/
28 SFR( P0, 0x80 ) ; /* PORT 0 */
29 SFR( SP, 0x81 ) ; /* STACK POINTER */
30 SFR( DPL, 0x82 ) ; /* DATA POINTER - LOW BYTE */
31 SFR( DPH, 0x83 ) ; /* DATA POINTER - HIGH BYTE */
32 SFR( TOFFL, 0x85 ) ; /* TEMPERATURE SENSOR OFFSET - LOW BYTE */
33 SFR( TOFFH, 0x86 ) ; /* TEMPERATURE SENSOR OFFSET - HIGH BYTE */
34 SFR( PCON, 0x87 ) ; /* POWER CONTROL */
35 SFR( TCON, 0x88 ) ; /* TIMER CONTROL */
36 SFR( TMOD, 0x89 ) ; /* TIMER MODE */
37 SFR( TL0, 0x8A ) ; /* TIMER 0 - LOW BYTE */
38 SFR( TL1, 0x8B ) ; /* TIMER 1 - LOW BYTE */
39 SFR( TH0, 0x8C ) ; /* TIMER 0 - HIGH BYTE */
40 SFR( TH1, 0x8D ) ; /* TIMER 1 - HIGH BYTE */
41 SFR( CKCON, 0x8E ) ; /* CLOCK CONTROL */
42 SFR( PSCTL, 0x8F ) ; /* PROGRAM STORE R/W CONTROL */
43 SFR( P1, 0x90 ) ; /* PORT 1 */
44 SFR( TMR3CN, 0x91 ) ; /* TIMER 3 CONTROL */
45 SFR( TMR3RLL, 0x92 ) ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
46 SFR( TMR3RLH, 0x93 ) ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
47 SFR( TMR3L, 0x94 ) ; /* TIMER 3 - LOW BYTE */
48 SFR( TMR3H, 0x95 ) ; /* TIMER 3 - HIGH BYTE */
49 SFR( IDA0L, 0x96 ) ; /* CURRENT MODE DAC 0 - LOW BYTE */
50 SFR( IDA0H, 0x97 ) ; /* CURRENT MODE DAC 0 - HIGH BYTE */
51 SFR( SCON, 0x98 ) ; /* SERIAL PORT CONTROL */
52 SFR( SCON0, 0x98 ) ; /* SERIAL PORT CONTROL */
53 SFR( SBUF, 0x99 ) ; /* SERIAL PORT BUFFER */
54 SFR( SBUF0, 0x99 ) ; /* SERIAL PORT BUFFER */
55 SFR( CPT0CN, 0x9B ) ; /* COMPARATOR 0 CONTROL */
56 SFR( CPT0MD, 0x9D ) ; /* COMPARATOR 0 MODE SELECTION */
57 SFR( CPT0MX, 0x9F ) ; /* COMPARATOR 0 MUX SELECTION */
58 SFR( P2, 0xA0 ) ; /* PORT 2 */
59 SFR( SPI0CFG, 0xA1 ) ; /* SPI0 CONFIGURATION */
60 SFR( SPI0CKR, 0xA2 ) ; /* SPI0 CLOCK RATE CONTROL */
61 SFR( SPI0DAT, 0xA3 ) ; /* SPI0 DATA */
62 SFR( P0MDOUT, 0xA4 ) ; /* PORT 0 OUTPUT MODE CONFIGURATION */
63 SFR( P1MDOUT, 0xA5 ) ; /* PORT 1 OUTPUT MODE CONFIGURATION */
64 SFR( P2MDOUT, 0xA6 ) ; /* PORT 2 OUTPUT MODE CONFIGURATION */
65 SFR( IE, 0xA8 ) ; /* INTERRUPT ENABLE */
66 SFR( CLKSEL, 0xA9 ) ; /* SYSTEM CLOCK SELECT */
67 SFR( EMI0CN, 0xAA ) ; /* EXTERNAL MEMORY INTERFACE CONTROL */
68 SFR( _XPAGE, 0xAA ) ; /* XDATA/PDATA PAGE */
69 SFR( OSCXCN, 0xB1 ) ; /* EXTERNAL OSCILLATOR CONTROL */
70 SFR( OSCICN, 0xB2 ) ; /* INTERNAL OSCILLATOR CONTROL */
71 SFR( OSCICL, 0xB3 ) ; /* INTERNAL OSCILLATOR CALIBRATION */
72 SFR( IP, 0xB8 ) ; /* INTERRUPT PRIORITY */
73 SFR( IDA0CN, 0xB9 ) ; /* CURRENT MODE DAC 0 - CONTROL */
74 SFR( AMX0P, 0xBB ) ; /* ADC 0 MUX POSITIVE CHANNEL SELECTION */
75 SFR( ADC0CF, 0xBC ) ; /* ADC 0 CONFIGURATION */
76 SFR( ADC0L, 0xBD ) ; /* ADC 0 DATA WORD LSB */
77 SFR( ADC0H, 0xBE ) ; /* ADC 0 DATA WORD MSB */
78 SFR( SMB0CN, 0xC0 ) ; /* SMBUS CONTROL */
79 SFR( SMB0CF, 0xC1 ) ; /* SMBUS CONFIGURATION */
80 SFR( SMB0DAT, 0xC2 ) ; /* SMBUS DATA */
81 SFR( ADC0GTL, 0xC3 ) ; /* ADC 0 GREATER-THAN LOW BYTE */
82 SFR( ADC0GTH, 0xC4 ) ; /* ADC 0 GREATER-THAN HIGH BYTE */
83 SFR( ADC0LTL, 0xC5 ) ; /* ADC 0 LESS-THAN LOW BYTE */
84 SFR( ADC0LTH, 0xC6 ) ; /* ADC 0 LESS-THAN HIGH BYTE */
85 SFR( REG0CN, 0xC7 ) ; /* Voltage Regulator Control */
86 SFR( T2CON, 0xC8 ) ; /* TIMER 2 CONTROL */
87 SFR( TMR2CN, 0xC8 ) ; /* TIMER 2 CONTROL */
88 SFR( RCAP2L, 0xCA ) ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
89 SFR( TMR2RLL, 0xCA ) ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
90 SFR( RCAP2H, 0xCB ) ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
91 SFR( TMR2RLH, 0xCB ) ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
92 SFR( TL2, 0xCC ) ; /* TIMER 2 - LOW BYTE */
93 SFR( TMR2L, 0xCC ) ; /* TIMER 2 - LOW BYTE */
94 SFR( TH2, 0xCD ) ; /* TIMER 2 - HIGH BYTE */
95 SFR( TMR2H, 0xCD ) ; /* TIMER 2 - HIGH BYTE */
96 SFR( PSW, 0xD0 ) ; /* PROGRAM STATUS WORD */
97 SFR( REF0CN, 0xD1 ) ; /* VOLTAGE REFERENCE 0 CONTROL */
98 SFR( P0SKIP, 0xD4 ) ; /* PORT 0 SKIP */
99 SFR( P1SKIP, 0xD5 ) ; /* PORT 1 SKIP */
100 SFR( SMB0ADR, 0xD7 ) ; /* SMBUS SLAVE ADDRESS */
101 SFR( PCA0CN, 0xD8 ) ; /* PCA CONTROL */
102 SFR( PCA0MD, 0xD9 ) ; /* PCA MODE */
103 SFR( PCA0CPM0, 0xDA ) ; /* PCA MODULE 0 MODE REGISTER */
104 SFR( PCA0CPM1, 0xDB ) ; /* PCA MODULE 1 MODE REGISTER */
105 SFR( PCA0CPM2, 0xDC ) ; /* PCA MODULE 2 MODE REGISTER */
106 SFR( ACC, 0xE0 ) ; /* ACCUMULATOR */
107 SFR( XBR0, 0xE1 ) ; /* PORT MUX CONFIGURATION REGISTER 0 */
108 SFR( XBR1, 0xE2 ) ; /* PORT MUX CONFIGURATION REGISTER 1 */
109 SFR( OSCLCN, 0xE3 ) ; /* LOW-FREQUENCY OSCILLATOR CONTROL */
110 SFR( IT01CF, 0xE4 ) ; /* INT0/INT1 CONFIGURATION REGISTER */
111 SFR( INT01CF, 0xE4 ) ; /* INT0/INT1 CONFIGURATION REGISTER */
112 SFR( EIE1, 0xE6 ) ; /* EXTERNAL INTERRUPT ENABLE 1 */
113 SFR( SMB0ADM, 0xE7 ) ; /* SMBUS SLAVE ADDRESS MASK */
114 SFR( ADC0CN, 0xE8 ) ; /* ADC 0 CONTROL */
115 SFR( PCA0CPL1, 0xE9 ) ; /* PCA CAPTURE 1 LOW */
116 SFR( PCA0CPH1, 0xEA ) ; /* PCA CAPTURE 1 HIGH */
117 SFR( PCA0CPL2, 0xEB ) ; /* PCA CAPTURE 2 LOW */
118 SFR( PCA0CPH2, 0xEC ) ; /* PCA CAPTURE 2 HIGH */
119 SFR( P1MAT, 0xED ) ; /* PORT 1 MATCH REGISTER */
120 SFR( P1MASK, 0xEE ) ; /* PORT 1 MASK REGISTER */
121 SFR( RSTSRC, 0xEF ) ; /* RESET SOURCE */
122 SFR( B, 0xF0 ) ; /* B REGISTER */
123 SFR( P0MODE, 0xF1 ) ; /* PORT 0 INPUT MODE CONFIGURATION */
124 SFR( P0MDIN, 0xF1 ) ; /* PORT 0 INPUT MODE CONFIGURATION */
125 SFR( P1MODE, 0xF2 ) ; /* PORT 1 INPUT MODE CONFIGURATION */
126 SFR( P1MDIN, 0xF2 ) ; /* PORT 1 INPUT MODE CONFIGURATION */
127 SFR( EIP1, 0xF6 ) ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
128 SFR( PCA0PWM, 0xF7 ) ; /* PCA PWM CONFIGURATION */
129 SFR( SPI0CN, 0xF8 ) ; /* SPI0 CONTROL */
130 SFR( PCA0L, 0xF9 ) ; /* PCA COUNTER LOW */
131 SFR( PCA0H, 0xFA ) ; /* PCA COUNTER HIGH */
132 SFR( PCA0CPL0, 0xFB ) ; /* PCA CAPTURE 0 LOW */
133 SFR( PCA0CPH0, 0xFC ) ; /* PCA CAPTURE 0 HIGH */
134 SFR( P0MAT, 0xFD ) ; /* PORT 0 MATCH REGISTER */
135 SFR( P0MASK, 0xFE ) ; /* PORT 0 MASK REGISTER */
136 SFR( VDM0CN, 0xFF ) ; /* VDD MONITOR CONTROL */
139 /* WORD/DWORD Registers */
141 SFR16E( TOFF, 0x8685 ) ; /* TEMPERATURE SENSOR OFFSET WORD */
142 SFR16E( TMR0, 0x8C8A ) ; /* TIMER 0 COUNTER */
143 SFR16E( TMR1, 0x8D8B ) ; /* TIMER 1 COUNTER */
144 SFR16E( TMR2, 0xCDCC ) ; /* TIMER 2 COUNTER */
145 SFR16E( RCAP2, 0xCBCA ) ; /* TIMER 2 CAPTURE REGISTER WORD */
146 SFR16E( TMR2RL, 0xCBCA ) ; /* TIMER 2 CAPTURE REGISTER WORD */
147 SFR16E( TMR3, 0x9594 ) ; /* TIMER 3 COUNTER */
148 SFR16E( TMR3RL, 0x9392 ) ; /* TIMER 3 CAPTURE REGISTER WORD */
149 SFR16E( IDA0, 0x9796 ) ; /* CURRENT MODE DAC 0 DATA WORD */
150 SFR16E( ADC0, 0xBEBD ) ; /* ADC 0 DATA WORD */
151 SFR16E( ADC0GT, 0xC4C3 ) ; /* ADC 0 GREATER-THAN REGISTER WORD */
152 SFR16E( ADC0LT, 0xC6C5 ) ; /* ADC 0 LESS-THAN REGISTER WORD */
153 SFR16E( PCA0, 0xFAF9 ) ; /* PCA COUNTER */
154 SFR16E( PCA0CP0, 0xFCFB ) ; /* PCA CAPTURE 0 WORD */
155 SFR16E( PCA0CP1, 0xEAE9 ) ; /* PCA CAPTURE 1 WORD */
156 SFR16E( PCA0CP2, 0xECEB ) ; /* PCA CAPTURE 2 WORD */
162 SBIT( P0_0, 0x80, 0 ) ;
163 SBIT( P0_1, 0x80, 1 ) ;
164 SBIT( P0_2, 0x80, 2 ) ;
165 SBIT( P0_3, 0x80, 3 ) ;
166 SBIT( P0_4, 0x80, 4 ) ;
167 SBIT( P0_5, 0x80, 5 ) ;
168 SBIT( P0_6, 0x80, 6 ) ;
169 SBIT( P0_7, 0x80, 7 ) ;
172 SBIT( IT0, 0x88, 0 ) ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
173 SBIT( IE0, 0x88, 1 ) ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
174 SBIT( IT1, 0x88, 2 ) ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
175 SBIT( IE1, 0x88, 3 ) ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
176 SBIT( TR0, 0x88, 4 ) ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
177 SBIT( TF0, 0x88, 5 ) ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
178 SBIT( TR1, 0x88, 6 ) ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
179 SBIT( TF1, 0x88, 7 ) ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
182 SBIT( P1_0, 0x90, 0 ) ;
183 SBIT( P1_1, 0x90, 1 ) ;
184 SBIT( P1_2, 0x90, 2 ) ;
185 SBIT( P1_3, 0x90, 3 ) ;
186 SBIT( P1_4, 0x90, 4 ) ;
187 SBIT( P1_5, 0x90, 5 ) ;
188 SBIT( P1_6, 0x90, 6 ) ;
189 SBIT( P1_7, 0x90, 7 ) ;
192 SBIT( RI, 0x98, 0 ) ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
193 SBIT( RI0, 0x98, 0 ) ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
194 SBIT( TI, 0x98, 1 ) ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
195 SBIT( TI0, 0x98, 1 ) ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
196 SBIT( RB8, 0x98, 2 ) ; /* SCON.2 - RECEIVE BIT 8 */
197 SBIT( RB80, 0x98, 2 ) ; /* SCON.2 - RECEIVE BIT 8 */
198 SBIT( TB8, 0x98, 3 ) ; /* SCON.3 - TRANSMIT BIT 8 */
199 SBIT( TB80, 0x98, 3 ) ; /* SCON.3 - TRANSMIT BIT 8 */
200 SBIT( REN, 0x98, 4 ) ; /* SCON.4 - RECEIVE ENABLE */
201 SBIT( REN0, 0x98, 4 ) ; /* SCON.4 - RECEIVE ENABLE */
202 SBIT( SM2, 0x98, 5 ) ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
203 SBIT( MCE0, 0x98, 5 ) ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
204 SBIT( SM0, 0x98, 7 ) ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
205 SBIT( S0MODE, 0x98, 7 ) ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
208 SBIT( P2_0, 0xA0, 0 ) ;
209 SBIT( P2_1, 0xA0, 1 ) ;
210 SBIT( P2_2, 0xA0, 2 ) ;
211 SBIT( P2_3, 0xA0, 3 ) ;
212 SBIT( P2_4, 0xA0, 4 ) ;
213 SBIT( P2_5, 0xA0, 5 ) ;
214 SBIT( P2_6, 0xA0, 6 ) ;
215 SBIT( P2_7, 0xA0, 7 ) ;
218 SBIT( EX0, 0xA8, 0 ) ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
219 SBIT( ET0, 0xA8, 1 ) ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
220 SBIT( EX1, 0xA8, 2 ) ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
221 SBIT( ET1, 0xA8, 3 ) ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
222 SBIT( ES, 0xA8, 4 ) ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
223 SBIT( ES0, 0xA8, 4 ) ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
224 SBIT( ET2, 0xA8, 5 ) ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */
225 SBIT( ESPI0, 0xA8, 6 ) ; /* IE.6 - SPI0 INTERRUPT ENABLE */
226 SBIT( EA, 0xA8, 7 ) ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
229 SBIT( PX0, 0xB8, 0 ) ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
230 SBIT( PT0, 0xB8, 1 ) ; /* IP.1 - TIMER 0 PRIORITY */
231 SBIT( PX1, 0xB8, 2 ) ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
232 SBIT( PT1, 0xB8, 3 ) ; /* IP.3 - TIMER 1 PRIORITY */
233 SBIT( PS, 0xB8, 4 ) ; /* IP.4 - SERIAL PORT PRIORITY */
234 SBIT( PS0, 0xB8, 4 ) ; /* IP.4 - SERIAL PORT PRIORITY */
235 SBIT( PT2, 0xB8, 5 ) ; /* IP.5 - TIMER 2 PRIORITY */
236 SBIT( PSPI0, 0xB8, 6 ) ; /* IP.6 - SPI0 PRIORITY */
239 SBIT( SI, 0xC0, 0 ) ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */
240 SBIT( ACK, 0xC0, 1 ) ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */
241 SBIT( ARBLOST, 0xC0, 2 ) ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */
242 SBIT( ACKRQ, 0xC0, 3 ) ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */
243 SBIT( STO, 0xC0, 4 ) ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */
244 SBIT( STA, 0xC0, 5 ) ; /* SMB0CN.5 - SMBUS 0 START FLAG */
245 SBIT( TXMODE, 0xC0, 6 ) ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */
246 SBIT( MASTER, 0xC0, 7 ) ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */
249 SBIT( T2XCLK, 0xC8, 0 ) ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */
250 SBIT( TR2, 0xC8, 2 ) ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */
251 SBIT( T2SPLIT, 0xC8, 3 ) ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */
252 SBIT( TF2CEN, 0xC8, 5 ) ; /* TMR2CN.5 - TIMER 2 LOW-FREQ OSC CAPTURE ENABLE*/
253 SBIT( TF2LEN, 0xC8, 5 ) ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */
254 SBIT( TF2L, 0xC8, 6 ) ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */
255 SBIT( TF2, 0xC8, 7 ) ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */
256 SBIT( TF2H, 0xC8, 7 ) ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */
259 SBIT( PARITY, 0xD0, 0 ) ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
260 SBIT( F1, 0xD0, 1 ) ; /* PSW.1 - FLAG 1 */
261 SBIT( OV, 0xD0, 2 ) ; /* PSW.2 - OVERFLOW FLAG */
262 SBIT( RS0, 0xD0, 3 ) ; /* PSW.3 - REGISTER BANK SELECT 0 */
263 SBIT( RS1, 0xD0, 4 ) ; /* PSW.4 - REGISTER BANK SELECT 1 */
264 SBIT( F0, 0xD0, 5 ) ; /* PSW.5 - FLAG 0 */
265 SBIT( AC, 0xD0, 6 ) ; /* PSW.6 - AUXILIARY CARRY FLAG */
266 SBIT( CY, 0xD0, 7 ) ; /* PSW.7 - CARRY FLAG */
269 SBIT( CCF0, 0xD8, 0 ) ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */
270 SBIT( CCF1, 0xD8, 1 ) ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */
271 SBIT( CCF2, 0xD8, 2 ) ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */
272 SBIT( CR, 0xD8, 6 ) ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */
273 SBIT( CF, 0xD8, 7 ) ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */
276 SBIT( AD0CM0, 0xE8, 0 ) ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */
277 SBIT( AD0CM1, 0xE8, 1 ) ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */
278 SBIT( AD0CM2, 0xE8, 2 ) ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */
279 SBIT( AD0WINT, 0xE8, 3 ) ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */
280 SBIT( AD0BUSY, 0xE8, 4 ) ; /* ADC0CN.4 - ADC 0 BUSY FLAG */
281 SBIT( AD0INT, 0xE8, 5 ) ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */
282 SBIT( AD0TM, 0xE8, 6 ) ; /* ADC0CN.6 - ADC 0 TRACK MODE */
283 SBIT( AD0EN, 0xE8, 7 ) ; /* ADC0CN.7 - ADC 0 ENABLE */
286 SBIT( SPIEN, 0xF8, 0 ) ; /* SPI0CN.0 - SPI0 ENABLE */
287 SBIT( TXBMT, 0xF8, 1 ) ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */
288 SBIT( NSSMD0, 0xF8, 2 ) ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */
289 SBIT( NSSMD1, 0xF8, 3 ) ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */
290 SBIT( RXOVRN, 0xF8, 4 ) ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */
291 SBIT( MODF, 0xF8, 5 ) ; /* SPI0CN.5 - MODE FAULT FLAG */
292 SBIT( WCOL, 0xF8, 6 ) ; /* SPI0CN.6 - WRITE COLLISION FLAG */
293 SBIT( SPIF, 0xF8, 7 ) ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG */
296 /* Predefined SFR Bit Masks */
298 #define PCON_IDLE 0x01 /* PCON */
299 #define PCON_STOP 0x02 /* PCON */
300 #define T1M 0x08 /* CKCON */
301 #define PSWE 0x01 /* PSCTL */
302 #define PSEE 0x02 /* PSCTL */
303 #define ECP0 0x20 /* EIE1 */
304 #define PORSF 0x02 /* RSTSRC */
305 #define SWRSF 0x10 /* RSTSRC */
306 #define ECCF 0x01 /* PCA0CPMn */
307 #define PWM 0x02 /* PCA0CPMn */
308 #define TOG 0x04 /* PCA0CPMn */
309 #define MAT 0x08 /* PCA0CPMn */
310 #define CAPN 0x10 /* PCA0CPMn */
311 #define CAPP 0x20 /* PCA0CPMn */
312 #define ECOM 0x40 /* PCA0CPMn */
313 #define PWM16 0x80 /* PCA0CPMn */
314 #define CP0E 0x10 /* XBR0 */
315 #define CP0OEN 0x10 /* XBR0 */
316 #define CP0AE 0x20 /* XBR0 */
317 #define CP0AOEN 0x20 /* XBR0 */
321 #define INT_EXT0 0 /* External Interrupt 0 */
322 #define INT_TIMER0 1 /* Timer0 Overflow */
323 #define INT_EXT1 2 /* External Interrupt 1 */
324 #define INT_TIMER1 3 /* Timer1 Overflow */
325 #define INT_UART0 4 /* Serial Port 0 */
326 #define INT_TIMER2 5 /* Timer2 Overflow */
327 #define INT_SPI0 6 /* Serial Peripheral Interface 0 */
328 #define INT_SMBUS0 7 /* SMBus0 Interface */
329 #define INT_PMAT 8 /* Port match */
330 #define INT_ADC0_WINDOW 9 /* ADC0 Window Comparison */
331 #define INT_ADC0_EOC 10 /* ADC0 End Of Conversion */
332 #define INT_PCA0 11 /* PCA0 Peripheral */
333 #define INT_COMPARATOR0 12 /* Comparator0 */
335 #define INT_TIMER3 14 /* Timer3 Overflow */