1 /*-------------------------------------------------------------------------
2 Register Declarations for the SiLabs C8051T60x Processor Range
4 Copyright (C) 2008 - Steven Borley, steven.borley@partnerelectronics.com
6 This library is free software; you can redistribute it and/or
7 modify it under the terms of the GNU Lesser General Public
8 License as published by the Free Software Foundation; either
9 version 2.1 of the License, or (at your option) any later version.
11 This library is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 Lesser General Public License for more details.
16 You should have received a copy of the GNU Lesser General Public
17 License along with this library; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------*/
29 SFR( P0, 0x80 ) ; /* PORT 0 */
30 SFR( SP, 0x81 ) ; /* STACK POINTER */
31 SFR( DPL, 0x82 ) ; /* DATA POINTER - LOW BYTE */
32 SFR( DPH, 0x83 ) ; /* DATA POINTER - HIGH BYTE */
33 SFR( PCON, 0x87 ) ; /* POWER CONTROL */
34 SFR( TCON, 0x88 ) ; /* TIMER CONTROL */
35 SFR( TMOD, 0x89 ) ; /* TIMER MODE */
36 SFR( TL0, 0x8A ) ; /* TIMER 0 - LOW BYTE */
37 SFR( TL1, 0x8B ) ; /* TIMER 1 - LOW BYTE */
38 SFR( TH0, 0x8C ) ; /* TIMER 0 - HIGH BYTE */
39 SFR( TH1, 0x8D ) ; /* TIMER 1 - HIGH BYTE */
40 SFR( CKCON, 0x8E ) ; /* CLOCK CONTROL */
41 SFR( SCON, 0x98 ) ; /* SERIAL PORT CONTROL */
42 SFR( SCON0, 0x98 ) ; /* SERIAL PORT CONTROL */
43 SFR( SBUF, 0x99 ) ; /* SERIAL PORT BUFFER */
44 SFR( SBUF0, 0x99 ) ; /* SERIAL PORT BUFFER */
45 SFR( CPT0MD, 0x9D ) ; /* COMPARATOR 0 MODE SELECTION */
46 SFR( CPT0MX, 0x9F ) ; /* COMPARATOR 0 MUX SELECTION */
47 SFR( TOFFL, 0xA2 ) ; /* TEMPERATURE SENSOR OFFSET - LOW BYTE */
48 SFR( TOFFH, 0xA3 ) ; /* TEMPERATURE SENSOR OFFSET - HIGH BYTE */
49 SFR( P0MDOUT, 0xA4 ) ; /* PORT 0 OUTPUT MODE CONFIGURATION */
50 SFR( IE, 0xA8 ) ; /* INTERRUPT ENABLE */
51 SFR( OSCXCN, 0xB1 ) ; /* EXTERNAL OSCILLATOR CONTROL */
52 SFR( OSCICN, 0xB2 ) ; /* INTERNAL OSCILLATOR CONTROL */
53 SFR( OSCICL, 0xB3 ) ; /* INTERNAL OSCILLATOR CALIBRATION */
54 SFR( IP, 0xB8 ) ; /* INTERRUPT PRIORITY */
55 SFR( AMX0SL, 0xBB ) ; /* ADC 0 MUX CHANNEL SELECTION */
56 SFR( ADC0CF, 0xBC ) ; /* ADC 0 CONFIGURATION */
57 SFR( ADC0L, 0xBD ) ; /* ADC 0 DATA - LOW BYTE */
58 SFR( ADC0H, 0xBE ) ; /* ADC 0 DATA - HIGH BYTE */
59 SFR( SMB0CN, 0xC0 ) ; /* SMBUS CONTROL */
60 SFR( SMB0CF, 0xC1 ) ; /* SMBUS CONFIGURATION */
61 SFR( SMB0DAT, 0xC2 ) ; /* SMBUS DATA */
62 SFR( ADC0GTL, 0xC3 ) ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
63 SFR( ADC0GTH, 0xC4 ) ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
64 SFR( ADC0LTL, 0xC5 ) ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
65 SFR( ADC0LTH, 0xC6 ) ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
66 SFR( REG0CN, 0xC7 ) ; /* Voltage Regulator Control */
67 SFR( T2CON, 0xC8 ) ; /* TIMER 2 CONTROL */
68 SFR( TMR2CN, 0xC8 ) ; /* TIMER 2 CONTROL */
69 SFR( RCAP2L, 0xCA ) ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
70 SFR( TMR2RLL, 0xCA ) ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
71 SFR( RCAP2H, 0xCB ) ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
72 SFR( TMR2RLH, 0xCB ) ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
73 SFR( TL2, 0xCC ) ; /* TIMER 2 - LOW BYTE */
74 SFR( TMR2L, 0xCC ) ; /* TIMER 2 - LOW BYTE */
75 SFR( TH2, 0xCD ) ; /* TIMER 2 - HIGH BYTE */
76 SFR( TMR2H, 0xCD ) ; /* TIMER 2 - HIGH BYTE */
77 SFR( PSW, 0xD0 ) ; /* PROGRAM STATUS WORD */
78 SFR( REF0CN, 0xD1 ) ; /* VOLTAGE REFERENCE 0 CONTROL */
79 SFR( PCA0CN, 0xD8 ) ; /* PCA CONTROL */
80 SFR( PCA0MD, 0xD9 ) ; /* PCA MODE */
81 SFR( PCA0CPM0, 0xDA ) ; /* PCA MODULE 0 MODE REGISTER */
82 SFR( PCA0CPM1, 0xDB ) ; /* PCA MODULE 1 MODE REGISTER */
83 SFR( PCA0CPM2, 0xDC ) ; /* PCA MODULE 2 MODE REGISTER */
84 SFR( ACC, 0xE0 ) ; /* ACCUMULATOR */
85 SFR( PRT0MX, 0xE1 ) ; /* PORT MUX CONFIGURATION REGISTER 0 */
86 SFR( XBR0, 0xE1 ) ; /* PORT MUX CONFIGURATION REGISTER 0 */
87 SFR( PRT1MX, 0xE2 ) ; /* PORT MUX CONFIGURATION REGISTER 1 */
88 SFR( XBR1, 0xE2 ) ; /* PORT MUX CONFIGURATION REGISTER 1 */
89 SFR( PRT2MX, 0xE3 ) ; /* PORT MUX CONFIGURATION REGISTER 2 */
90 SFR( XBR2, 0xE3 ) ; /* PORT MUX CONFIGURATION REGISTER 2 */
91 SFR( IT01CF, 0xE4 ) ; /* INT0/INT1 CONFIGURATION REGISTER */
92 SFR( INT01CF, 0xE4 ) ; /* INT0/INT1 CONFIGURATION REGISTER */
93 SFR( EIE1, 0xE6 ) ; /* EXTERNAL INTERRUPT ENABLE 1 */
94 SFR( ADC0CN, 0xE8 ) ; /* ADC 0 CONTROL */
95 SFR( PCA0CPL1, 0xE9 ) ; /* PCA CAPTURE 1 LOW */
96 SFR( PCA0CPH1, 0xEA ) ; /* PCA CAPTURE 1 HIGH */
97 SFR( PCA0CPL2, 0xEB ) ; /* PCA CAPTURE 2 LOW */
98 SFR( PCA0CPH2, 0xEC ) ; /* PCA CAPTURE 2 HIGH */
99 SFR( RSTSRC, 0xEF ) ; /* RESET SOURCE */
100 SFR( B, 0xF0 ) ; /* B REGISTER */
101 SFR( P0MODE, 0xF1 ) ; /* PORT 0 INPUT MODE CONFIGURATION */
102 SFR( P0MDIN, 0xF1 ) ; /* PORT 0 INPUT MODE CONFIGURATION */
103 SFR( EIP1, 0xF6 ) ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
104 SFR( CPT0CN, 0xF8 ) ; /* COMPARATOR 0 CONTROL */
105 SFR( PCA0L, 0xF9 ) ; /* PCA COUNTER LOW */
106 SFR( PCA0H, 0xFA ) ; /* PCA COUNTER HIGH */
107 SFR( PCA0CPL0, 0xFB ) ; /* PCA CAPTURE 0 LOW */
108 SFR( PCA0CPH0, 0xFC ) ; /* PCA CAPTURE 0 HIGH */
111 /* WORD/DWORD Registers */
113 SFR16E( TMR0, 0x8C8A ) ; /* TIMER 0 COUNTER */
114 SFR16E( TMR1, 0x8D8B ) ; /* TIMER 1 COUNTER */
115 SFR16E( TOFF, 0xA3A2 ) ; /* TEMPERATURE SENSOR OFFSET WORD */
116 SFR16E( ADC0, 0xAEAD ) ; /* ADC0 DATA WORD */
117 SFR16E( ADC0GT, 0xC4C3 ) ; /* ADC 0 GREATER-THAN REGISTER WORD */
118 SFR16E( ADC0LT, 0xC6C5 ) ; /* ADC 0 LESS-THAN REGISTER WORD */
119 SFR16E( TMR2, 0xCDCC ) ; /* TIMER 2 COUNTER */
120 SFR16E( RCAP2, 0xCBCA ) ; /* TIMER 2 CAPTURE REGISTER WORD */
121 SFR16E( TMR2RL, 0xCBCA ) ; /* TIMER 2 CAPTURE REGISTER WORD */
122 SFR16E( PCA0, 0xFAF9 ) ; /* PCA COUNTER */
123 SFR16E( PCA0CP0, 0xFCFB ) ; /* PCA CAPTURE 0 WORD */
124 SFR16E( PCA0CP1, 0xEAE9 ) ; /* PCA CAPTURE 1 WORD */
125 SFR16E( PCA0CP2, 0xECEB ) ; /* PCA CAPTURE 2 WORD */
131 SBIT( P0_0, 0x80, 0 ) ;
132 SBIT( P0_1, 0x80, 1 ) ;
133 SBIT( P0_2, 0x80, 2 ) ;
134 SBIT( P0_3, 0x80, 3 ) ;
135 SBIT( P0_4, 0x80, 4 ) ;
136 SBIT( P0_5, 0x80, 5 ) ;
137 SBIT( P0_6, 0x80, 6 ) ;
138 SBIT( P0_7, 0x80, 7 ) ;
141 SBIT( IT0, 0x88, 0 ) ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
142 SBIT( IE0, 0x88, 1 ) ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
143 SBIT( IT1, 0x88, 2 ) ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
144 SBIT( IE1, 0x88, 3 ) ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
145 SBIT( TR0, 0x88, 4 ) ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
146 SBIT( TF0, 0x88, 5 ) ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
147 SBIT( TR1, 0x88, 6 ) ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
148 SBIT( TF1, 0x88, 7 ) ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
151 SBIT( RI, 0x98, 0 ) ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
152 SBIT( RI0, 0x98, 0 ) ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
153 SBIT( TI, 0x98, 1 ) ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
154 SBIT( TI0, 0x98, 1 ) ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
155 SBIT( RB8, 0x98, 2 ) ; /* SCON.2 - RECEIVE BIT 8 */
156 SBIT( RB80, 0x98, 2 ) ; /* SCON.2 - RECEIVE BIT 8 */
157 SBIT( TB8, 0x98, 3 ) ; /* SCON.3 - TRANSMIT BIT 8 */
158 SBIT( TB80, 0x98, 3 ) ; /* SCON.3 - TRANSMIT BIT 8 */
159 SBIT( REN, 0x98, 4 ) ; /* SCON.4 - RECEIVE ENABLE */
160 SBIT( REN0, 0x98, 4 ) ; /* SCON.4 - RECEIVE ENABLE */
161 SBIT( SM2, 0x98, 5 ) ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
162 SBIT( MCE0, 0x98, 5 ) ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
163 SBIT( SM0, 0x98, 7 ) ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
164 SBIT( S0MODE, 0x98, 7 ) ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
167 SBIT( EX0, 0xA8, 0 ) ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
168 SBIT( ET0, 0xA8, 1 ) ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
169 SBIT( EX1, 0xA8, 2 ) ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
170 SBIT( ET1, 0xA8, 3 ) ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
171 SBIT( ES, 0xA8, 4 ) ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
172 SBIT( ES0, 0xA8, 4 ) ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
173 SBIT( ET2, 0xA8, 5 ) ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */
174 SBIT( IEGF0, 0xA8, 6 ) ; /* IE.6 - GENERAL PURPOSE FLAG 0 */
175 SBIT( EA, 0xA8, 7 ) ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
178 SBIT( PX0, 0xB8, 0 ) ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
179 SBIT( PT0, 0xB8, 1 ) ; /* IP.1 - TIMER 0 PRIORITY */
180 SBIT( PX1, 0xB8, 2 ) ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
181 SBIT( PT1, 0xB8, 3 ) ; /* IP.3 - TIMER 1 PRIORITY */
182 SBIT( PS, 0xB8, 4 ) ; /* IP.4 - SERIAL PORT PRIORITY */
183 SBIT( PS0, 0xB8, 4 ) ; /* IP.4 - SERIAL PORT PRIORITY */
184 SBIT( PT2, 0xB8, 5 ) ; /* IP.5 - TIMER 2 PRIORITY */
187 SBIT( SI, 0xC0, 0 ) ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */
188 SBIT( ACK, 0xC0, 1 ) ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */
189 SBIT( ARBLOST, 0xC0, 2 ) ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */
190 SBIT( ACKRQ, 0xC0, 3 ) ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */
191 SBIT( STO, 0xC0, 4 ) ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */
192 SBIT( STA, 0xC0, 5 ) ; /* SMB0CN.5 - SMBUS 0 START FLAG */
193 SBIT( TXMODE, 0xC0, 6 ) ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */
194 SBIT( MASTER, 0xC0, 7 ) ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */
197 SBIT( T2XCLK, 0xC8, 0 ) ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */
198 SBIT( TR2, 0xC8, 2 ) ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */
199 SBIT( T2SPLIT, 0xC8, 3 ) ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */
200 SBIT( TF2LEN, 0xC8, 5 ) ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */
201 SBIT( TF2L, 0xC8, 6 ) ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */
202 SBIT( TF2, 0xC8, 7 ) ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */
203 SBIT( TF2H, 0xC8, 7 ) ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */
206 SBIT( PARITY, 0xD0, 0 ) ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
207 SBIT( F1, 0xD0, 1 ) ; /* PSW.1 - FLAG 1 */
208 SBIT( OV, 0xD0, 2 ) ; /* PSW.2 - OVERFLOW FLAG */
209 SBIT( RS0, 0xD0, 3 ) ; /* PSW.3 - REGISTER BANK SELECT 0 */
210 SBIT( RS1, 0xD0, 4 ) ; /* PSW.4 - REGISTER BANK SELECT 1 */
211 SBIT( F0, 0xD0, 5 ) ; /* PSW.5 - FLAG 0 */
212 SBIT( AC, 0xD0, 6 ) ; /* PSW.6 - AUXILIARY CARRY FLAG */
213 SBIT( CY, 0xD0, 7 ) ; /* PSW.7 - CARRY FLAG */
216 SBIT( CCF0, 0xD8, 0 ) ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */
217 SBIT( CCF1, 0xD8, 1 ) ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */
218 SBIT( CCF2, 0xD8, 2 ) ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */
219 SBIT( CR, 0xD8, 6 ) ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */
220 SBIT( CF, 0xD8, 7 ) ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */
223 SBIT( AD0CM0, 0xE8, 0 ) ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */
224 SBIT( AD0CM1, 0xE8, 1 ) ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */
225 SBIT( AD0CM2, 0xE8, 2 ) ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */
226 SBIT( AD0WINT, 0xE8, 3 ) ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */
227 SBIT( AD0BUSY, 0xE8, 4 ) ; /* ADC0CN.4 - ADC 0 BUSY FLAG */
228 SBIT( AD0INT, 0xE8, 5 ) ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */
229 SBIT( AD0TM, 0xE8, 6 ) ; /* ADC0CN.6 - ADC 0 TRACK MODE */
230 SBIT( AD0EN, 0xE8, 7 ) ; /* ADC0CN.7 - ADC 0 ENABLE */
233 SBIT( CP0HYN0, 0xF8, 0 ) ; /* CPT0CN.0 - Comp.0 Neg. Hysteresis Control Bit0*/
234 SBIT( CP0HYN1, 0xF8, 1 ) ; /* CPT0CN.1 - Comp.0 Neg. Hysteresis Control Bit1*/
235 SBIT( CP0HYP0, 0xF8, 2 ) ; /* CPT0CN.2 - Comp.0 Pos. Hysteresis Control Bit0*/
236 SBIT( CP0HYP1, 0xF8, 3 ) ; /* CPT0CN.3 - Comp.0 Pos. Hysteresis Control Bit1*/
237 SBIT( CP0FIF, 0xF8, 4 ) ; /* CPT0CN.4 - Comparator0 Falling-Edge Int. Flag */
238 SBIT( CP0RIF, 0xF8, 5 ) ; /* CPT0CN.5 - Comparator0 Rising-Edge Int. Flag */
239 SBIT( CP0OUT, 0xF8, 6 ) ; /* CPT0CN.6 - Comparator0 Output State Flag */
240 SBIT( CP0EN, 0xF8, 7 ) ; /* CPT0CN.7 - Comparator0 Enable Bit */
243 /* Predefined SFR Bit Masks */
245 #define PCON_IDLE 0x01 /* PCON */
246 #define PCON_STOP 0x02 /* PCON */
247 #define T1M 0x10 /* CKCON */
248 #define PSWE 0x01 /* PSCTL */
249 #define PSEE 0x02 /* PSCTL */
250 #define ECP0F 0x10 /* EIE1 */
251 #define ECP0R 0x20 /* EIE1 */
252 #define PORSF 0x02 /* RSTSRC */
253 #define SWRSF 0x10 /* RSTSRC */
254 #define ECCF 0x01 /* PCA0CPMn */
255 #define PWM 0x02 /* PCA0CPMn */
256 #define TOG 0x04 /* PCA0CPMn */
257 #define MAT 0x08 /* PCA0CPMn */
258 #define CAPN 0x10 /* PCA0CPMn */
259 #define CAPP 0x20 /* PCA0CPMn */
260 #define ECOM 0x40 /* PCA0CPMn */
261 #define PWM16 0x80 /* PCA0CPMn */
262 #define CP0E 0x10 /* XBR1 */
263 #define CP0OEN 0x10 /* XBR1 */
264 #define CP0AE 0x20 /* XBR1 */
265 #define CP0AOEN 0x20 /* XBR1 */
269 #define INT_EXT0 0 /* External Interrupt 0 */
270 #define INT_TIMER0 1 /* Timer0 Overflow */
271 #define INT_EXT1 2 /* External Interrupt 1 */
272 #define INT_TIMER1 3 /* Timer1 Overflow */
273 #define INT_UART0 4 /* Serial Port 0 */
274 #define INT_TIMER2 5 /* Timer2 Overflow */
275 #define INT_SMBUS0 6 /* SMBus0 Interface */
276 #define INT_ADC0_WINDOW 7 /* ADC0 Window Comparison */
277 #define INT_ADC0_EOC 8 /* ADC0 End Of Conversion */
278 #define INT_PCA0 9 /* PCA0 Peripheral */
279 #define INT_CP0F 10 /* Comparator0 falling edge */
280 #define INT_CP0R 11 /* Comparator1 rising edge */