1 /*-------------------------------------------------------------------------
2 Register Declarations for Analog Devices ADuC841/ADuC842/ADuC843
3 (Based on datasheet Rev 0, 11/2003 )
5 Written By - Jesus Calvino-Fraga / jesusc at ece.ubc.ca (March 2007)
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2.1 of the License, or (at your option); any later version
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 In other words, you are welcome to use, share and improve this program
22 You are forbidden to forbid anyone else to use, share and improve
23 what you give them. Help stamp out software-hoarding!
24 -------------------------------------------------------------------------*/
30 SFR(CFG841, 0xAF); // ADuC841 Configuration SFR.
31 SFR(CFG842, 0xAF); // ADuC842/ADuC843 Configuration SFR.
32 //For the two SFRs above these are the bits. Warning: some are different for
33 //the ADuC841 and ADuC842/ADuC843. Check the datasheet!
34 #define EPM2 0x10 // Flash/EE Controller and PWM Clock Frequency Configuration Bit 2.
35 #define EPM1 0x08 // Flash/EE Controller and PWM Clock Frequency Configuration Bit 1.
36 #define EPM0 0x04 // Flash/EE Controller and PWM Clock Frequency Configuration Bit 0.
37 #define EXSP 0x80 // Extended SP Enable.
38 #define PWPO 0x40 // PWM Pin Out Selection.
39 #define DBUF 0x20 // DAC Output Buffer.
40 #define EXTCLK 0x10 // Set by the user to 1 to select an external clock input on P3.4.
41 #define MSPI 0x02 // Set to 1 by the user to move the SPI functionality of.
42 #define XRAMEN 0x01 // XRAM Enable Bit.
44 SFR(SP, 0x81); // Stack Pointer.
45 SFR(SPH, 0xB7); // Stack pointer high.
47 SFR(DPL, 0x82); // Data Pointer Low.
48 SFR(DPH, 0x83); // Data Pointer High.
49 SFR(DPP, 0x84); // Data Pointer Page Byte.
50 SFR(DPCON, 0xA7); // Data Pointer Control SFR.
52 SFR(PCON, 0x87); // Power Control.
53 #define SMOD 0x80 //Double UART Baud Rate.
54 #define SERIPD 0x40 //I2C/SPI Power-Down Interrupt Enable.
55 #define INT0PD 0x20 //INT0 Power-Down Interrupt Enable.
56 #define ALEOFF 0x10 //Disable ALE Output.
57 #define GF1 0x08 //General-Purpose Flag Bit.
58 #define GF0 0x04 //General-Purpose Flag Bit.
59 #define PD 0x02 //Power-Down Mode Enable.
60 #define IDL 0x01 //Idle Mode Enable.
62 SFR(TCON, 0x88); // Timer/Counter Control.
63 SBIT(TF1, 0x88, 7); // Timer 1 overflow flag.
64 SBIT(TR1, 0x88, 6); // Timer 1 run control flag.
65 SBIT(TF0, 0x88, 5); // Timer 0 overflow flag.
66 SBIT(TR0, 0x88, 4); // Timer 0 run control flag.
67 SBIT(IE1, 0x88, 3); // Interrupt 1 flag.
68 SBIT(IT1, 0x88, 2); // Interrupt 1 type control bit.
69 SBIT(IE0, 0x88, 1); // Interrupt 0 flag.
70 SBIT(IT0, 0x88, 0); // Interrupt 0 type control bit.
72 SFR(TMOD, 0x89); // Timer/Counter Mode Control.
73 #define GATE1 0x80 // External enable for timer 1.
74 #define C_T1 0x40 // Timer or counter select for timer 1.
75 #define M1_1 0x20 // Operation mode bit 1 for timer 1.
76 #define M0_1 0x10 // Operation mode bit 0 for timer 1.
77 #define GATE0 0x08 // External enable for timer 0.
78 #define C_T0 0x04 // Timer or counter select for timer 0.
79 #define M1_0 0x02 // Operation mode bit 1 for timer 0.
80 #define M0_0 0x01 // Operation mode bit 0 for timer 0.
82 SFR(TL0, 0x8A); // Timer 0 LSB.
83 SFR(TL1, 0x8B); // Timer 1 LSB.
84 SFR(TH0, 0x8C); // Timer 0 MSB.
85 SFR(TH1, 0x8D); // Timer 1 MSB.
87 SFR(P0, 0x80); // Port 0
88 SBIT(P0_0, 0x80, 0); // Port 0 bit 0.
89 SBIT(P0_1, 0x80, 1); // Port 0 bit 1.
90 SBIT(P0_2, 0x80, 2); // Port 0 bit 2.
91 SBIT(P0_3, 0x80, 3); // Port 0 bit 3.
92 SBIT(P0_4, 0x80, 4); // Port 0 bit 4.
93 SBIT(P0_5, 0x80, 5); // Port 0 bit 5.
94 SBIT(P0_6, 0x80, 6); // Port 0 bit 6.
95 SBIT(P0_7, 0x80, 7); // Port 0 bit 7.
97 SFR(P1, 0x90); // Port 1
98 SBIT(P1_0, 0x90, 0); // Port 1 bit 0.
99 SBIT(P1_1, 0x90, 1); // Port 1 bit 1.
100 SBIT(P1_2, 0x90, 2); // Port 1 bit 2.
101 SBIT(P1_3, 0x90, 3); // Port 1 bit 3.
102 SBIT(P1_4, 0x90, 4); // Port 1 bit 4.
103 SBIT(P1_5, 0x90, 5); // Port 1 bit 5.
104 SBIT(P1_6, 0x90, 6); // Port 1 bit 6.
105 SBIT(P1_7, 0x90, 7); // Port 1 bit 7.
107 SBIT(T2EX, 0x90, 1); //Capture/reload trigger for Counter 2.
108 SBIT(T2, 0x90, 0); //Input to Timer/Counter 2.
110 SFR(P2, 0xA0); // Port 2
111 SBIT(P2_0, 0xA0, 0); // Port 2 bit 0.
112 SBIT(P2_1, 0xA0, 1); // Port 2 bit 1.
113 SBIT(P2_2, 0xA0, 2); // Port 2 bit 2.
114 SBIT(P2_3, 0xA0, 3); // Port 2 bit 3.
115 SBIT(P2_4, 0xA0, 4); // Port 2 bit 4.
116 SBIT(P2_5, 0xA0, 5); // Port 2 bit 5.
117 SBIT(P2_6, 0xA0, 6); // Port 2 bit 6.
118 SBIT(P2_7, 0xA0, 7); // Port 2 bit 7.
120 SFR(P3, 0xB0); // Port 3
121 SBIT(P3_0, 0xB0, 0); // Port 3 bit 0.
122 SBIT(P3_1, 0xB0, 1); // Port 3 bit 1.
123 SBIT(P3_2, 0xB0, 2); // Port 3 bit 2.
124 SBIT(P3_3, 0xB0, 3); // Port 3 bit 3.
125 SBIT(P3_4, 0xB0, 4); // Port 3 bit 4.
126 SBIT(P3_5, 0xB0, 5); // Port 3 bit 5.
127 SBIT(P3_6, 0xB0, 6); // Port 3 bit 6.
128 SBIT(P3_7, 0xB0, 7); // Port 3 bit 7.
139 SFR(I2CADD, 0x9B); // I2C Address Register 1.
140 SFR(I2CADD1, 0x91); // I2C Address Register 2.
141 SFR(I2CADD2, 0x92); // I2C Address Register 3.
142 SFR(I2CADD3, 0x93); // I2C Address Register 4.
143 SFR(I2CDAT, 0x9A); // I2C Data Register.
145 SFR(SCON, 0x98); // Serial Port Control.
146 SBIT(SM0, 0x98, 7); // Serial Port Mode Bit 0.
147 SBIT(SM1, 0x98, 6); // Serial Port Mode Bit 1.
148 SBIT(SM2, 0x98, 5); // Serial Port Mode Bit 2.
149 SBIT(REN, 0x98, 4); // Enables serial reception.
150 SBIT(TB8, 0x98, 3); // The 9th data bit that will be transmitted in Modes 2 and 3.
151 SBIT(RB8, 0x98, 2); // In Modes 2 and 3, the 9th data bit that was received.
152 SBIT(TI, 0x98, 1); // Transmit interrupt flag.
153 SBIT(RI, 0x98, 0); // Receive interrupt flag.
155 SFR(SBUF, 0x99); // Serial Data Buffer.
157 //For these two, you may want to check page 68 of the datasheet...
158 SFR(T3FD, 0x9D); // Fractional divider ratio.
159 SFR(T3CON, 0x9E); // T3CON is the baud rate control SFR, allowing Timer 3 to be
160 // used to set up the UART baud rate, and setting up the binary
162 #define T3BAUDEN 0x80 // T3 UART BAUD Enable.
163 #define DIV2 0x04 // Binary Divider Factor bit 3.
164 #define DIV1 0x02 // Binary Divider Factor bit 2.
165 #define DIV0 0x01 // Binary Divider Factor bit 1.
167 SFR(TIMECON, 0xA1); // TIC Control Register.
168 #define TFH 0x40 // Twenty-Four Hour Select Bit.
169 #define ITS1 0x20 // Interval Timebase Selection Bit 1.
170 #define ITS0 0x10 // Interval Timebase Selection Bit 1.
171 #define STI 0x08 // Single Time Interval Bit.
172 #define TII 0x04 // TIC Interrupt Bit.
173 #define TIEN 0x02 // Time Interval Enable Bit.
174 #define TCEN 0x01 // Time Clock Enable Bit.
176 SFR(HTHSEC, 0xA2); // Hundredths Seconds Time Register.
177 SFR(SEC, 0xA3); // Seconds Time Register.
178 SFR(MIN, 0xA4); // Minutes Time Register.
179 SFR(HOUR, 0xA5); // Hours Time Register.
180 SFR(INTVAL, 0xA6); // User Time Interval Select Register.
182 SFR(IE, 0xA8); // Interrupt Enable.
183 SBIT(EA, 0xA8, 7); // Global Interrupt Enable.
184 SBIT(EADC, 0xA8, 6); // ADC Interrupt Enable.
185 SBIT(ET2, 0xA8, 5); // Timer 2 Interrupt Enable.
186 SBIT(ES, 0xA8, 4); // Serial Interrupt Enable.
187 SBIT(ET1, 0xA8, 3); // Timer 1 Interrupt Enable.
188 SBIT(EX1, 0xA8, 2); // External 1 Interrupt Enable.
189 SBIT(ET0, 0xA8, 1); // Timer 0 Interrupt Enable.
190 SBIT(EX0, 0xA8, 0); // External 0 Interrupt Enable.
192 SFR(IEIP2, 0xA9); // Secondary Interrupt Enable Register
193 #define PTI 0x40 // Priority for time interval interrupt.
194 #define PPSM 0x20 // Priority for power supply monitor interrupt.
195 #define PSI2 0x10 // Priority for SPI/I2C interrupt. Same name as bit in IP???
196 #define ETI 0x04 // Enable time interval counter interrupts.
197 #define EPSMI 0x02 // Enable power supply monitor interrupts.
198 #define ESI 0x01 // Enable SPI or I2C serial port interrupts.
200 SFR(PWMCON, 0xAE); //PWM control.
201 #define SNGL 0x80 // Turns off PMW output at P2.6 or P3.4.
202 #define MD2 0x40 // PWM Mode Bit 2.
203 #define MD1 0x20 // PWM Mode Bit 2.
204 #define MD0 0x10 // PWM Mode Bit 2.
205 #define CDIV1 0x08 // PWM Clock Divider bit 1.
206 #define CDIV0 0x04 // PWM Clock Divider bit 1.
207 #define CSEL1 0x02 // PWM Clock Select bit 1. (Typo in datasheet???)
208 #define CSEL0 0x01 // PWM Clock Select bit 0.
210 SFR(PWM0L, 0xB1); // PWM 0 duty cycle low.
211 SFR(PWM0H, 0xB2); // PWM 0 duty cycle high.
212 SFR(PWM1L, 0xB3); // PWM 1 duty cycle low.
213 SFR(PWM1H, 0xB4); // PWM 1 duty cycle high.
215 SFR(IP, 0xB8); // Interrupt Priority Reg.
216 SBIT(PSI, 0xB8, 7); // Priority for SPI/I2C interrupt.
217 SBIT(PADC, 0xB8, 6); // ADC interrupt priority bit.
218 SBIT(PT2, 0xB8, 5); // Timer 2 interrupt priority bit.
219 SBIT(PS, 0xB8, 4); // Serial Port interrupt priority bit.
220 SBIT(PT1, 0xB8, 3); // Timer 1 interrupt priority bit.
221 SBIT(PX1, 0xB8, 2); // External interrupt 1 priority bit.
222 SBIT(PT0, 0xB8, 1); // Timer 0 interrupt priority bit.
223 SBIT(PX0, 0xB8, 0); // External interrupt 0 priority bit.
225 SFR(ECON, 0xB9); // Flash/EE Memory Control SFR.
226 SFR(EDATA1, 0xBC); // EE page data byte 1.
227 SFR(EDATA2, 0xBD); // EE page data byte 2.
228 SFR(EDATA3, 0xBE); // EE page data byte 3.
229 SFR(EDATA4, 0xBF); // EE page data byte 4.
230 SFR(EADRL, 0xC6); // EE address low.
231 SFR(EADRH, 0xC7); // EE address high.
233 SFR(WDCON, 0xC0); //Watchdog Timer Control Register.
234 SBIT(PRE3, 0xc0, 7); // Timeout period bit 4.
235 SBIT(PRE2, 0xc0, 6); // Timeout period bit 3.
236 SBIT(PRE1, 0xc0, 5); // Timeout period bit 2.
237 SBIT(PRE0, 0xc0, 4); // Timeout period bit 1.
238 SBIT(WDIR, 0xc0, 3); // Watchdog Interrupt Response Enable Bit.
239 SBIT(WDS, 0xc0, 2); // Watchdog Status Bit.
240 SBIT(WDE, 0xc0, 1); // Watchdog Enable Bit.
241 SBIT(WDWR, 0xc0, 0); // Watchdog Write Enable Bit.
243 SFR(CHIPID, 0xC2); // System Self-Identification? WARNING: No description in the datasheet.
245 SFR(T2CON, 0xC8); // Timer / Counter 2 Control.
246 SBIT(TF2, 0xC8, 7); // Timer 2 overflow flag.
247 SBIT(EXF2, 0xC8, 6); // Timer 2 external flag.
248 SBIT(RCLK, 0xC8, 5); // Receive clock flag.
249 SBIT(TCLK, 0xC8, 4); // Transmit clock flag.
250 SBIT(EXEN2, 0xC8, 3); // Timer 2 external enable flag.
251 SBIT(TR2, 0xC8, 2); // Start/stop control for timer 2.
252 SBIT(CNT2, 0xC8, 1); // Timer or coutner select.
253 SBIT(CAP2, 0xC8, 0); // Capture/reload flag.
255 SFR(RCAP2L, 0xCA); // Timer 2 Capture LSB.
256 SFR(RCAP2H, 0xCB); // Timer 2 Capture MSB.
257 SFR(TL2, 0xCC); // Timer 2 LSB.
258 SFR(TH2, 0xCD); // Timer 2 MSB.
260 SFR(PSW, 0xD0); // Program Status Word.
261 SBIT(CY, 0xD0, 7); // Carry Flag.
262 SBIT(AC, 0xD0, 6); // Auxiliary Carry Flag.
263 SBIT(F0, 0xD0, 5); // User-Defined Flag.
264 SBIT(RS1, 0xD0, 4); // Register Bank Select 1.
265 SBIT(RS0, 0xD0, 3); // Register Bank Select 0.
266 SBIT(OV, 0xD0, 2); // Overflow Flag.
267 SBIT(F1, 0xD0, 1); // User-Defined Flag.
268 SBIT(P, 0xD0, 0); // Parity Flag.
270 SFR(DMAL, 0xD2); // DMA mode address pointer low.
271 SFR(DMAH, 0xD3); // DMA mode address pointer high.
272 SFR(DMAP, 0xD4); // DMA mode address pointer page. (?)
273 SFR(PLLCON, 0xD7); // PLL Control Register.
275 SFR(PSMCON, 0xDF); // Power supply monitor.
276 #define CMPD 0x40 // DVDD Comparator Bit.
277 #define PSMI 0x20 // Power Supply Monitor Interrupt Bit.
278 #define TPD1 0x10 // DVDD Trip Point Selection Bit 2.
279 #define TPD0 0x08 // DVDD Trip Point Selection Bit 1.
280 #define PSMEN 0x01 // Power Supply Monitor Enable Bit.
282 SFR(ACC, 0xE0); // Accumulator
283 SBIT(ACC_0, 0xE0, 0); // Accumulator bit 0.
284 SBIT(ACC_1, 0xE0, 1); // Accumulator bit 1.
285 SBIT(ACC_2, 0xE0, 2); // Accumulator bit 2.
286 SBIT(ACC_3, 0xE0, 3); // Accumulator bit 3.
287 SBIT(ACC_4, 0xE0, 4); // Accumulator bit 4.
288 SBIT(ACC_5, 0xE0, 5); // Accumulator bit 5.
289 SBIT(ACC_6, 0xE0, 6); // Accumulator bit 6.
290 SBIT(ACC_7, 0xE0, 7); // Accumulator bit 7.
292 SFR(I2CCON, 0xE8); // I2C Control Register
294 SBIT(MDO, 0xE8, 7); // I2C Software Master Data Output Bit.
295 SBIT(MDE, 0xE8, 6); // I2C Software Master Data Output Enable Bit.
296 SBIT(MCO, 0xE8, 5); // I2C Software Master Clock Output Bit.
297 SBIT(MDI, 0xE8, 4); // I2C Software Master Data Input Bit.
299 SBIT(I2CSI, 0xE8, 7); // I2C Stop Interrupt Enable Bit.
300 SBIT(I2CGC, 0xE8, 6); // I2C General Call Status Bit.
301 SBIT(I2CID1, 0xE8, 5); // I2C Interrupt Decode Bit 2.
302 SBIT(I2CID0, 0xE8, 4); // I2C Interrupt Decode Bit 1.
303 SBIT(I2CM, 0xE8, 3); // I2C Master/Slave Mode Bit.
304 SBIT(I2CRS, 0xE8, 2); // I2C Reset Bit.
305 SBIT(I2CTX, 0xE8, 1); // I2C Direction Transfer Bit.
306 SBIT(I2CI, 0xE8, 0); // I2C Interrupt Bit.
308 SFR(B, 0xF0); // B Register
309 SBIT(B_0, 0xF0, 0); // Register B bit 0.
310 SBIT(B_1, 0xF0, 1); // Register B bit 1.
311 SBIT(B_2, 0xF0, 2); // Register B bit 2.
312 SBIT(B_3, 0xF0, 3); // Register B bit 3.
313 SBIT(B_4, 0xF0, 4); // Register B bit 4.
314 SBIT(B_5, 0xF0, 5); // Register B bit 5.
315 SBIT(B_6, 0xF0, 6); // Register B bit 6.
316 SBIT(B_7, 0xF0, 7); // Register B bit 7.
318 SFR(ADCCON1, 0xEF); //ADC Control SFR 1
319 //WARNING: bit 7 is named MD1 in the datasheet, but that name is already used.
320 #define MD 0x80 // The mode bit selects the active operating mode of the ADC.
321 #define EXT_REF 0x40 // Set by the user to select an external reference.
322 #define CK1 0x20 // The ADC clock divide bit 1.
323 #define CK0 0x10 // The ADC clock divide bit 0.
324 #define AQ1 0x08 // ADC acquisition select bit 1.
325 #define AQ0 0x04 // ADC acquisition select bit 0.
326 #define T2C 0x02 // The Timer 2 conversion bit.
327 #define EXC 0x01 // The external trigger enable bit.
329 SFR(ADCCON2, 0xD8); // ADC Control SFR 2.
330 SBIT(ADCI, 0xD8, 7); // ADC Interrupt Bit.
331 SBIT(DMA, 0xD8, 6); // DMA Mode Enable Bit.
332 SBIT(CCONV, 0xD8, 5); // Continuous Conversion Bit.
333 SBIT(SCONV, 0xD8, 4); // Single Conversion Bit.
334 SBIT(CS3, 0xD8, 3); // Channel Selection Bit 4.
335 SBIT(CS2, 0xD8, 2); // Channel Selection Bit 3.
336 SBIT(CS1, 0xD8, 1); // Channel Selection Bit 2.
337 SBIT(CS0, 0xD8, 0); // Channel Selection Bit 1.
339 SFR(ADCCON3, 0xF5); //ADC Control SFR 3
340 #define BUSY 0x80 // ADC Busy Status Bit.
341 #define AVGS1 0x20 // Number of Average Selection Bit 2.
342 #define AVGS0 0x10 // Number of Average Selection Bit 1.
343 #define TYPICAL 0x02 // Calibration Type Select Bit.
344 #define SCAL 0x01 // Start Calibration Cycle Bit.
346 SFR(ADCDATAL, 0xD9); // ADC Result byte low.
347 SFR(ADCDATAH, 0xDA); // ADC Result byte high. WARNING: bits 4 to 7 are the ADC channel!
348 SFR(ADCOFSL, 0xF1); // Offset calibration coefficient byte (low).
349 SFR(ADCOFSH, 0xF2); // Offset calibration coefficient byte (high).
350 SFR(ADCGAINL, 0xF3); // Gain calibration coefficient byte (low).
351 SFR(ADCGAINH, 0xF4); // Gain calibration coefficient byte (high).
353 SFR(SPIDAT, 0xF7); // SPI Data Register.
355 SFR(SPICON, 0xF8); // SPI Control Register.
356 SBIT(ISPI, 0xF8, 7); // SPI Interrupt Bit.
357 SBIT(WCOL, 0xF8, 6); // Write Collision Error Bit.
358 SBIT(SPE, 0xF8, 5); // SPI Interface Enable Bit.
359 SBIT(SPIM, 0xF8, 4); // SPI Master/Slave Mode Select Bit.
360 SBIT(CPOL, 0xF8, 3); // Clock Polarity Select Bit.
361 SBIT(CPHA, 0xF8, 2); // Clock Phase Select Bit.
362 SBIT(SPR1, 0xF8, 1); // SPI Bit Rate Select Bit 2.
363 SBIT(SPR0, 0xF8, 0); // SPI Bit Rate Select Bit 1.
365 SFR(DAC0L, 0xF9); // DAC0 Data Low Byte.
366 SFR(DAC0H, 0xFA); // DAC0 Data High Byte.
367 SFR(DAC1L, 0xFB); // DAC1 Data Low Byte.
368 SFR(DAC1H, 0xFC); // DAC1 Data High Byte.
369 SFR(DACCON, 0xFD); // DAC Control Register.
370 #define MODE 0x80 // 8/12 bit selection.
371 #define RNG1 0x40 // DAC1 Range Select Bit.
372 #define RNG0 0x20 // DAC0 Range Select Bit.
373 #define CLR1 0x10 // DAC1 Clear Bit.
374 #define CLR0 0x08 // DAC0 Clear Bit.
375 #define SYNC 0x04 // DAC0/1 Update Synchronization Bit.
376 #define PD1 0x02 // DAC1 Power-Down Bit.
377 #define PD0 0x01 // DAC0 Power-Down Bit.
379 #endif //REG_ADUC84X_H