1 /*-------------------------------------------------------------------------
2 Register Declarations for the DALLAS DS80C390 Processor
3 far from complete, e.g. no CAN
5 Written By - Johan Knol, johan.knol@iduna.nl
7 This program is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by the
9 Free Software Foundation; either version 2, or (at your option) any
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 In other words, you are welcome to use, share and improve this program.
22 You are forbidden to forbid anyone else to use, share and improve
23 what you give them. Help stamp out software-hoarding!
24 -------------------------------------------------------------------------*/
29 __sfr __at 0x80 P4; // ce3..ce0, a19..a16
30 __sfr __at 0x81 SP; // stack pointer
31 __sfr __at 0x82 DPL; // data pointer 0 lsb
32 __sfr __at 0x83 DPH; // data pointer 0 msb
33 __sfr __at 0x84 DPL1; // data pointer 1 lsb
34 __sfr __at 0x85 DPH1; // data pointer 1 msb
35 __sfr __at 0x86 DPS; // data pointer select
36 __sfr __at 0x87 PCON; // power control
37 __sfr __at 0x88 TCON; // timer/counter control
46 __sfr __at 0x89 TMOD; // timer mode control
47 __sfr __at 0x8a TL0; // timer 0 lsb
48 __sfr __at 0x8b TL1; // timer 1 msb
49 __sfr __at 0x8c TH0; // timer 0 msb
50 __sfr __at 0x8d TH1; // timer 1 msb
51 __sfr __at 0x8e CKCON; // clock control
54 __sbit __at 0x91 T2EX;
55 __sbit __at 0x92 RXD1;
56 __sbit __at 0x93 TXD1;
57 __sbit __at 0x94 INT2;
58 __sbit __at 0x95 INT3;
59 __sbit __at 0x96 INT4;
60 __sbit __at 0x97 INT5;
61 __sfr __at 0x91 EXIF; // external interrupt flag
62 __sfr __at 0x92 P4CNT;
63 __sfr __at 0x93 DPX; // extended datapointer 0
64 __sfr __at 0x95 DPX1; // extended datapointer 1
65 __sfr __at 0x98 SCON0; // serial 0 control
66 __sbit __at 0x98 RI_0;
67 __sbit __at 0x99 TI_0;
68 __sbit __at 0x9a RB8_0;
69 __sbit __at 0x9b TB8_0;
70 __sbit __at 0x9c REN_0;
71 __sbit __at 0x9d SM2_0;
72 __sbit __at 0x9e SM1_0;
73 __sbit __at 0x9f SM0_0;
74 __sbit __at 0x9f FE_0; // depending on SMOD0
75 __sfr __at 0x99 SBUF0; // serial 0 data buffer
76 __sfr __at 0x9b ESP; // extended stack pointer
77 __sfr __at 0x9c AP; // address page
78 __sfr __at 0x9d ACON; // address control
79 __sfr __at 0xa0 P2; // never mind the sbits
81 __sfr __at 0xa2 P5CNT;
82 __sfr __at 0xa8 IE; // interrupt enable
92 __sbit __at 0xb0 RXD0;
93 __sbit __at 0xb1 TXD0;
94 __sbit __at 0xb2 INT0;
95 __sbit __at 0xb3 INT1;
100 __sfr __at 0xb8 IP; // interupt priority
101 __sbit __at 0xb8 PX0; // external 0
102 __sbit __at 0xb9 PT0; // timer 0
103 __sbit __at 0xba PX1; // external 1
104 __sbit __at 0xbb PT1; // timer 1
105 __sbit __at 0xbc PS0; // serial port 0
106 __sbit __at 0xbd PT2; // timer 2
107 __sbit __at 0xbe PS1; // serial port 1
108 __sfr __at 0xc0 SCON1; // serial 1 control
109 __sbit __at 0xc0 RI_1;
110 __sbit __at 0xc1 TI_1;
111 __sbit __at 0xc2 RB8_1;
112 __sbit __at 0xc3 TB8_1;
113 __sbit __at 0xc4 REN_1;
114 __sbit __at 0xc5 SM2_1;
115 __sbit __at 0xc6 SM1_1;
116 __sbit __at 0xc7 SM0_1;
117 __sbit __at 0xc7 FE_1; // depending on SMOD0
118 __sfr __at 0xc1 SBUF1; // serial 1 data buffer
119 __sfr __at 0xc4 PMR; // power managment
120 __sfr __at 0xc6 MCON; // memory control register
121 __sfr __at 0xc7 TA; // timed access register
122 __sfr __at 0xc8 T2CON; // timer 2 control
123 __sbit __at 0xc8 CP_RL; // capture/reload
124 __sbit __at 0xc9 C_T; // count/timer
125 __sbit __at 0xca TR2; // stop/run
126 __sbit __at 0xcb EXEN2;
127 __sbit __at 0xcc TCLK;
128 __sbit __at 0xcd RCLK;
129 __sbit __at 0xce EXF2;
130 __sbit __at 0xcf TF2; // overflow flag
131 __sfr __at 0xc9 T2MOD; // timer 2 mode
132 __sfr __at 0xca RCAP2L; // timer 2 capture/reload
133 __sfr __at 0xca RTL2; // depends on CP_RL
134 __sfr __at 0xcb RCAP2H;
135 __sfr __at 0xcb RTH2;
136 __sfr __at 0xcc TL2; // timer 2 lsb
137 __sfr __at 0xcd TH2; // timer 2 msb
138 __sfr __at 0xd0 PSW; // program status word (byte actually)
139 __sbit __at 0xd0 P; // parity
140 __sbit __at 0xd1 F1; // user flag 1
141 __sbit __at 0xd2 OV; // overflow flag
142 __sbit __at 0xd3 RS0; // register select l
143 __sbit __at 0xd4 RS1; // register select h
144 __sbit __at 0xd5 F0; // user flag 0
145 __sbit __at 0xd6 AC; // auxiliary carry flag
146 __sbit __at 0xd7 CY; // carry flag
147 __sfr __at 0xd1 MCNT0; // arithmetic accellerator
148 __sfr __at 0xd2 MCNT1;
152 __sfr __at 0xd8 WDCON; // watch dog
153 __sbit __at 0xd8 RWT;
154 __sbit __at 0xd9 EWT;
155 __sbit __at 0xda WDRF;
156 __sbit __at 0xdb WDIF;
157 __sbit __at 0xdc PFI;
158 __sbit __at 0xdd EPFI;
159 __sbit __at 0xde POR;
160 __sbit __at 0xdf SMOD_1;
161 __sfr __at 0xe0 ACC; // accumulator
162 __sfr __at 0xe8 EIE; // extended interrupt enable
163 __sbit __at 0xe8 EX2;
164 __sbit __at 0xe9 EX3;
165 __sbit __at 0xea EX4;
166 __sbit __at 0xeb EX5;
167 __sbit __at 0xec EWDI;
168 __sbit __at 0xed C1IE;
169 __sbit __at 0xee C0IE;
170 __sbit __at 0xef CANBIE;
171 __sfr __at 0xea MXAX; // extended address register
172 __sfr __at 0xf0 B; // aux accumulator
173 __sfr __at 0xf8 EIP; // extended interrupt priority
174 __sbit __at 0xf8 PX2;
175 __sbit __at 0xf9 PX3;
176 __sbit __at 0xfa PX4;
177 __sbit __at 0xfb PX5;
178 __sbit __at 0xfc PWDI;
179 __sbit __at 0xfd C1IP;
180 __sbit __at 0xfe C0IP;
181 __sbit __at 0xff CANBIP;
183 /* WORD/DWORD Registers */
185 __sfr16 __at (0x8C8A) TMR0 ; /* TIMER 0 COUNTER */
186 __sfr16 __at (0x8D8B) TMR1 ; /* TIMER 1 COUNTER */
187 __sfr16 __at (0xCDCC) TMR2 ; /* TIMER 2 COUNTER */
188 __sfr16 __at (0xCBCA) RCAP2 ; /* TIMER 2 CAPTURE REGISTER WORD */
190 #endif /* DS80C390_H */