1 /*-------------------------------------------------------------------------
2 Register Declarations for ATMEL 89S8252 and 89LS8252 Processors
4 Written By - Dipl.-Ing. (FH) Michael Schmitt
5 mschmitt@mainz-online.de
6 michael.schmitt@t-online.de
10 Additional definitions Nov 23 1999
11 by Bernd Krueger-Knauber <bkk@infratec-plus.de>
13 based on reg51.h by Sandeep Dutta sandeep.dutta@usa.net
14 KEIL C compatible definitions are included
16 This program is free software; you can redistribute it and/or modify it
17 under the terms of the GNU General Public License as published by the
18 Free Software Foundation; either version 2, or (at your option) any
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the Free Software
28 Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 In other words, you are welcome to use, share and improve this program.
31 You are forbidden to forbid anyone else to use, share and improve
32 what you give them. Help stamp out software-hoarding!
33 -------------------------------------------------------------------------*/
38 /* BYTE addressable registers */
42 sfr at 0x82 DP0L ; /* as called by Atmel */
44 sfr at 0x83 DP0H ; /* as called by Atmel */
45 sfr at 0x84 DP1L ; /* at89S8252 specific register */
46 sfr at 0x85 DP1H ; /* at89S8252 specific register */
47 sfr at 0x86 SPDR ; /* at89S8252 specific register */
56 sfr at 0x96 WMCON ; /* at89S8252 specific register */
61 sfr at 0xAA SPSR ; /* at89S8252 specific register */
71 sfr at 0xD5 SPCR ; /* at89S8252 specific register */
77 /* BIT addressable registers */
111 /* P1 SPI portpins */
112 sbit at 0x94 SS; /* SPI: SS - Slave port select input */
113 sbit at 0x95 MOSI; /* SPI: MOSI - Master data output, slave data input */
114 sbit at 0x96 MISO; /* SPI: MISO - Master data input, slave data output */
115 sbit at 0x97 SCK; /* SPI: SCK - Master clock output, slave clock input */
175 sbit at 0xC8 T2CON_0 ;
176 sbit at 0xC9 T2CON_1 ;
177 sbit at 0xCA T2CON_2 ;
178 sbit at 0xCB T2CON_3 ;
179 sbit at 0xCC T2CON_4 ;
180 sbit at 0xCD T2CON_5 ;
181 sbit at 0xCE T2CON_6 ;
182 sbit at 0xCF T2CON_7 ;
184 sbit at 0xC8 CP_RL2 ;
204 sbit at 0xF0 BREG_F0 ;
205 sbit at 0xF1 BREG_F1 ;
206 sbit at 0xF2 BREG_F2 ;
207 sbit at 0xF3 BREG_F3 ;
208 sbit at 0xF4 BREG_F4 ;
209 sbit at 0xF5 BREG_F5 ;
210 sbit at 0xF6 BREG_F6 ;
211 sbit at 0xF7 BREG_F7 ;
214 /* BIT definitions for bits that are not directly accessible */
259 #define T0_GATE_ 0x08
263 #define T1_GATE_ 0x80
268 #define T0_MASK_ 0x0F
269 #define T1_MASK_ 0xF0
279 #define WMCON_WDTEN 0x01
280 #define WMCON_WDTRST 0x02
281 #define WMCON_DPS 0x04
282 #define WMCON_EEMEN 0x08
283 #define WMCON_EEMWE 0x10
284 #define WMCON_PS0 0x20
285 #define WMCON_PS1 0x40
286 #define WMCON_PS2 0x80
289 #define SPCR_SPR0 0x01
290 #define SPCR_SPR1 0x02
291 #define SPCR_CPHA 0x04
292 #define SPCR_CPOL 0x08
293 #define SPCR_MSTR 0x10
294 #define SPCR_DORD 0x20
295 #define SPCR_SPE 0x40
296 #define SPCR_SPIE 0x80
299 #define SPSR_WCOL 0x40
300 #define SPSR_SPIF 0x80
303 #define SPDR_SPD0 0x10
304 #define SPDR_SPD1 0x20
305 #define SPDR_SPD2 0x40
306 #define SPDR_SPD3 0x80
307 #define SPDR_SPD4 0x10
308 #define SPDR_SPD5 0x20
309 #define SPDR_SPD6 0x40
310 #define SPDR_SPD7 0x80
312 /* Interrupt numbers: address = (number * 8) + 3 */
313 #define IE0_VECTOR 0 /* 0x03 external interrupt 0 */
314 #define EX0_VECTOR 0 /* 0x03 external interrupt 0 */
315 #define TF0_VECTOR 1 /* 0x0b timer 0 */
316 #define IE1_VECTOR 2 /* 0x13 external interrupt 1 */
317 #define EX1_VECTOR 2 /* 0x13 external interrupt 1 */
318 #define TF1_VECTOR 3 /* 0x1b timer 1 */
319 #define SI0_VECTOR 4 /* 0x23 serial port 0 */
320 #define TF2_VECTOR 5 /* 0x2B timer 2 */
321 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
324 /* This is one of the addons comming from Bernd Krueger-Knauber */
326 /* ALE (0x8E) Bit Values */
327 sfr at 0x8E ALE; /* at89S8252 specific register */
329 /* Macro to enable and disable the toggling of the ALE-pin (EMV) */
331 /* Explanation : Orignal Intel 8051 Cores (Atmel has to use the */
332 /* Intel Core) have a festure that ALE is only active during */
333 /* MOVX or MOVC instruction. Otherwise the ALE-Pin is weakly */
334 /* pulled high. This can be used to force some external devices */
335 /* into stanby mode and reduced EMI noise */
337 #define ALE_OFF ALE = ALE | 0x01
338 #define ALE_ON ALE = ALE & 0xFE