1 /*-------------------------------------------------------------------------
2 Register Declarations for SIEMENS SAB 80515 Processor
4 Written By - Bela Torok
6 based on reg51.h by Sandeep Dutta sandeep.dutta@usa.net
8 modified 20. march 2000 by Michael.Schmitt@t-online.de
10 KEIL C compatible definitions are included
12 This program is free software; you can redistribute it and/or modify it
13 under the terms of the GNU General Public License as published by the
14 Free Software Foundation; either version 2, or (at your option) any
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 In other words, you are welcome to use, share and improve this program.
27 You are forbidden to forbid anyone else to use, share and improve
28 what you give them. Help stamp out software-hoarding!
29 -------------------------------------------------------------------------*/
34 /* BYTE addressable registers */
51 sfr at 0xA8 IEN0 ; /* as called by Siemens */
52 sfr at 0xA9 IP0 ; /* interrupt priority register - SAB80515 specific */
53 sfr at 0xAA SRELL ; // Baudrategenerator Reload Low Value
55 sfr at 0xB1 SYSCON ; // XRAM Controller Access Control SAB80C515A specific
56 sfr at 0xB8 IEN1 ; /* interrupt enable register - SAB80515 specific */
57 sfr at 0xB9 IP1 ; /* interrupt priority register as called by Siemens */
58 sfr at 0xBA SRELH ; // Baudrategenerator Reload HIGH Value
59 sfr at 0xC0 IRCON ; /* interrupt control register - SAB80515 specific */
60 sfr at 0xC1 CCEN ; /* compare/capture enable register */
61 sfr at 0xC2 CCL1 ; /* compare/capture register 1, low byte */
62 sfr at 0xC3 CCH1 ; /* compare/capture register 1, high byte */
63 sfr at 0xC4 CCL2 ; /* compare/capture register 2, low byte */
64 sfr at 0xC5 CCH2 ; /* compare/capture register 2, high byte */
65 sfr at 0xC6 CCL3 ; /* compare/capture register 3, low byte */
66 sfr at 0xC7 CCH3 ; /* compare/capture register 3, high byte */
68 sfr at 0xCA CRCL ; /* compare/reload/capture register, low byte */
69 sfr at 0xCB CRCH ; /* compare/reload/capture register, high byte */
73 //sfr at 0xD8 ADCON ; /* A/D-converter control register */
75 sfr at 0xD8 ADCON0 ; /* A/D-converter control register as called by Siemens */
76 sfr at 0xD8 ADCON1 ; /* A/D-converter control register as called by Siemens */
77 sfr at 0xD9 ADDATH ; /* A/D-converter data register High-Byte*/
78 sfr at 0xDA ADDATL ; /* A/D-converter data register High-Byte*/
80 //sfr at 0xD8 DAPR ; /* D/A-converter program register */
83 sfr at 0xE8 P4 ; /* Port 4 - SAB80515 specific */
85 sfr at 0xF8 P5 ; /* Port 5 - SAB80515 specific */
88 /* BIT addressable registers */
119 sbit at 0x90 INT3_CC0 ; /* P1 alternate functions - SAB80515 specific */
120 sbit at 0x91 INT4_CC1 ;
121 sbit at 0x92 INT5_CC2 ;
122 sbit at 0x93 INT6_CC3 ;
125 sbit at 0x96 CLKOUT ;
155 sbit at 0xAE WDT ; /* watchdog timer reset - SAB80515 specific */
158 sbit at 0xAF EAL ; /* EA as called by Siemens */
179 // IEN1 von MS geprueft
180 sbit at 0xB8 EADC ; /* A/D converter interrupt enable */
186 sbit at 0xBE SWDT ; /* watchdog timer start/reset */
187 sbit at 0xBF EXEN2 ; /* timer2 external reload interrupt enable */
189 // IRCON von MS geprueft
190 sbit at 0xC0 IADC ; /* A/D converter irq flag */
191 sbit at 0xC1 IEX2 ; /* external interrupt edge detect flag */
196 sbit at 0xC6 TF2 ; /* timer 2 owerflow flag */
197 sbit at 0xC7 EXF2 ; /* timer2 reload flag */
200 sbit at 0xC8 T2CON_0 ;
201 sbit at 0xC9 T2CON_1 ;
202 sbit at 0xCA T2CON_2 ;
203 sbit at 0xCB T2CON_3 ;
204 sbit at 0xCC T2CON_4 ;
205 sbit at 0xCD T2CON_5 ;
206 sbit at 0xCE T2CON_6 ;
207 sbit at 0xCF T2CON_7 ;
242 sbit at 0xA0 AREG_F0 ;
243 sbit at 0xA1 AREG_F1 ;
244 sbit at 0xA2 AREG_F2 ;
245 sbit at 0xA3 AREG_F3 ;
246 sbit at 0xA4 AREG_F4 ;
247 sbit at 0xA5 AREG_F5 ;
248 sbit at 0xA6 AREG_F6 ;
249 sbit at 0xA7 AREG_F7 ;
262 sbit at 0xF0 BREG_F0 ;
263 sbit at 0xF1 BREG_F1 ;
264 sbit at 0xF2 BREG_F2 ;
265 sbit at 0xF3 BREG_F3 ;
266 sbit at 0xF4 BREG_F4 ;
267 sbit at 0xF5 BREG_F5 ;
268 sbit at 0xF6 BREG_F6 ;
269 sbit at 0xF7 BREG_F7 ;
281 /* BIT definitions for bits that are not directly accessible */
326 #define T0_GATE_ 0x08
330 #define T1_GATE_ 0x80
335 #define T0_MASK_ 0x0F
336 #define T1_MASK_ 0xF0
346 #define WMCON_WDTEN 0x01
347 #define WMCON_WDTRST 0x02
348 #define WMCON_DPS 0x04
349 #define WMCON_EEMEN 0x08
350 #define WMCON_EEMWE 0x10
351 #define WMCON_PS0 0x20
352 #define WMCON_PS1 0x40
353 #define WMCON_PS2 0x80
356 #define SPCR_SPR0 0x01
357 #define SPCR_SPR1 0x02
358 #define SPCR_CPHA 0x04
359 #define SPCR_CPOL 0x08
360 #define SPCR_MSTR 0x10
361 #define SPCR_DORD 0x20
362 #define SPCR_SPE 0x40
363 #define SPCR_SPIE 0x80
366 #define SPSR_WCOL 0x40
367 #define SPSR_SPIF 0x80
370 #define SPDR_SPD0 0x10
371 #define SPDR_SPD1 0x20
372 #define SPDR_SPD2 0x40
373 #define SPDR_SPD3 0x80
374 #define SPDR_SPD4 0x10
375 #define SPDR_SPD5 0x20
376 #define SPDR_SPD6 0x40
377 #define SPDR_SPD7 0x80
380 #define XMAP0_BIT 0x01
381 #define XMAP1_BIT 0x02
382 #define RMAP_BIT 0x10
383 #define EALE_BIT 0x20
385 // ADCON0 bits von MS geprueft
386 #define ADCON0_MX0 0x01
387 #define ADCON0_MX1 0x02
388 #define ADCON0_MX2 0x04
389 #define ADCON0_ADM 0x08
390 #define ADCON0_BSY 0x10
391 #define ADCON0_ADEX 0x20
392 #define ADCON0_CLK 0x40
393 #define ADCON0_BD 0x80
395 // ADCON1 bits von MS geprueft
396 #define ADCON1_MX0 0x01
397 #define ADCON1_MX1 0x02
398 #define ADCON1_MX2 0x04
399 #define ADCON1_ADCL 0x80
401 /* Interrupt numbers: address = (number * 8) + 3 */
402 #define IE0_VECTOR 0 /* 0x03 external interrupt 0 */
403 #define TF0_VECTOR 1 /* 0x0b timer 0 */
404 #define IE1_VECTOR 2 /* 0x13 external interrupt 1 */
405 #define TF1_VECTOR 3 /* 0x1b timer 1 */
406 #define SI0_VECTOR 4 /* 0x23 serial port 0 */
407 #define TF2_VECTOR 5 /* 0x2B timer 2 */
408 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
410 #define IADC_VECTOR 8 /* 0x43 A/D converter interrupt */
411 #define IEX2_VECTOR 9 /* 0x4B external interrupt 2 */
412 #define IEX3_VECTOR 10 /* 0x53 external interrupt 3 */
413 #define IEX4_VECTOR 11 /* 0x5B external interrupt 4 */
414 #define IEX5_VECTOR 12 /* 0x63 external interrupt 5 */
415 #define IEX6_VECTOR 13 /* 0x6B external interrupt 6 */