1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /***************************************************************************
4 * Copyright (C) 2011 by Andreas Fritiofson *
5 * andreas.fritiofson@gmail.com *
6 ***************************************************************************/
14 * r0 - flash base (in), status (out)
15 * r1 - count (halfword-16bit)
25 #define STM32_FLASH_SR_OFFSET 0x0c /* offset of SR register from flash reg base */
31 ldr r6, [r2, #0] /* read wp */
32 cmp r6, #0 /* abort if wp == 0 */
34 ldr r5, [r2, #4] /* read rp */
35 cmp r5, r6 /* wait until rp != wp */
37 ldrh r6, [r5] /* "*target_address++ = *rp++" */
42 ldr r6, [r0, #STM32_FLASH_SR_OFFSET] /* wait until BSY flag is reset */
46 movs r7, #0x14 /* check the error bits */
49 cmp r5, r3 /* wrap rp at end of buffer */
54 str r5, [r2, #4] /* store rp */
55 subs r1, r1, #1 /* decrement halfword count */
57 beq exit /* loop if not done */
61 str r0, [r2, #4] /* set rp = 0 on error */
63 mov r0, r6 /* return status in r0 */