1 /* SPDX-License-Identifier: BSD-3-Clause */
3 /******************************************************************************
5 * Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/
7 ******************************************************************************/
9 #ifndef OPENOCD_LOADERS_FLASH_MSP432_MSP432P411X_H
10 #define OPENOCD_LOADERS_FLASH_MSP432_MSP432P411X_H
18 /* Available Peripherals */
19 #define __MCU_HAS_FLCTL_A__ /* Module FLCTL_A is available */
20 #define __MCU_HAS_SYSCTL_A__ /* Module SYSCTL_A is available */
22 /* Device and Peripheral Memory Map */
23 #define FLASH_BASE ((uint32_t)0x00000000) /* Flash memory address */
24 #define PERIPH_BASE ((uint32_t)0x40000000) /* Peripherals address */
25 #define CS_BASE (PERIPH_BASE + 0x00010400) /* Address of CS regs. */
26 #define PCM_BASE (PERIPH_BASE + 0x00010000) /* Address of PCM regs. */
27 #define RTC_C_BASE (PERIPH_BASE + 0x00004400) /* Address of RTC_C regs */
28 #define TLV_BASE ((uint32_t)0x00201000) /* Address of TLV regs. */
29 #define WDT_A_BASE (PERIPH_BASE + 0x00004800) /* Address of WDT_A regs */
30 #define BITBAND_PERI_BASE ((uint32_t)(0x42000000))
33 * Peripherals with 8-bit or 16-bit register access allow only 8-bit or
34 * 16-bit bit band access, so cast to 8 bit always
36 #define BITBAND_PERI(x, b) (*((volatile uint8_t *) (BITBAND_PERI_BASE + \
37 (((uint32_t)(uint32_t *)&(x)) - PERIPH_BASE)*32 + (b)*4)))
39 /* Register map for CLock Signal peripheral (CS) */
41 volatile uint32_t KEY; /* Key Register */
42 volatile uint32_t CTL0; /* Control 0 Register */
43 volatile uint32_t CTL1; /* Control 1 Register */
44 volatile uint32_t CTL2; /* Control 2 Register */
45 volatile uint32_t CTL3; /* Control 3 Register */
48 /* Register map for Power Control Module peripheral (PCM) */
50 volatile uint32_t CTL0; /* Control 0 Register */
51 volatile uint32_t CTL1; /* Control 1 Register */
52 volatile uint32_t IE; /* Interrupt Enable Register */
53 volatile uint32_t IFG; /* Interrupt Flag Register */
54 volatile uint32_t CLRIFG; /* Clear Interrupt Flag Register */
57 /* Register map for Real-Time Clock peripheral (RTC_C) */
59 volatile uint16_t CTL0; /* RTCCTL0 Register */
60 volatile uint16_t CTL13; /* RTCCTL13 Register */
61 volatile uint16_t OCAL; /* RTCOCAL Register */
62 volatile uint16_t TCMP; /* RTCTCMP Register */
63 volatile uint16_t PS0CTL; /* RTC Prescale Timer 0 Control Register */
64 volatile uint16_t PS1CTL; /* RTC Prescale Timer 1 Control Register */
65 volatile uint16_t PS; /* Real-Time Clock Prescale Timer Register */
66 volatile uint16_t IV; /* Real-Time Clock Interrupt Vector Register */
67 volatile uint16_t TIM0; /* RTCTIM0 Register Hexadecimal Format */
68 volatile uint16_t TIM1; /* Real-Time Clock Hour, Day of Week */
69 volatile uint16_t DATE; /* RTCDATE - Hexadecimal Format */
70 volatile uint16_t YEAR; /* RTCYEAR Register - Hexadecimal Format */
71 volatile uint16_t AMINHR; /* RTCMINHR - Hexadecimal Format */
72 volatile uint16_t ADOWDAY; /* RTCADOWDAY - Hexadecimal Format */
73 volatile uint16_t BIN2BCD; /* Binary-to-BCD Conversion Register */
74 volatile uint16_t BCD2BIN; /* BCD-to-Binary Conversion Register */
77 /* Register map for Watchdog Timer peripheral (WDT_A) */
79 uint16_t RESERVED0[6];
80 volatile uint16_t CTL; /* Watchdog Timer Control Register */
83 /* Peripheral Declarations */
84 #define CS ((struct cs *) CS_BASE)
85 #define PCM ((struct pcm *) PCM_BASE)
86 #define RTC_C ((struct rtc_c *) RTC_C_BASE)
87 #define WDT_A ((struct wdt_a *) WDT_A_BASE)
89 /* Peripheral Register Bit Definitions */
91 /* DCORSEL Bit Mask */
92 #define CS_CTL0_DCORSEL_MASK ((uint32_t)0x00070000)
93 /* Nominal DCO Frequency Range (MHz): 2 to 4 */
94 #define CS_CTL0_DCORSEL_1 ((uint32_t)0x00010000)
95 /* Nominal DCO Frequency Range (MHz): 16 to 32 */
96 #define CS_CTL0_DCORSEL_4 ((uint32_t)0x00040000)
97 /* CS control key value */
98 #define CS_KEY_VAL ((uint32_t)0x0000695A)
101 #define PCM_CTL0_AMR_MASK ((uint32_t)0x0000000F)
103 #define PCM_CTL0_LPMR_MASK ((uint32_t)0x000000F0)
104 /* LPM3.5. Core voltage setting 0. */
105 #define PCM_CTL0_LPMR_10 ((uint32_t)0x000000A0)
107 #define PCM_CTL0_LPMR_12 ((uint32_t)0x000000C0)
109 #define PCM_CTL0_CPM_OFS (8)
111 #define PCM_CTL0_CPM_MASK ((uint32_t)0x00003F00)
112 /* PCMKEY Bit Mask */
113 #define PCM_CTL0_KEY_MASK ((uint32_t)0xFFFF0000)
114 /* PMR_BUSY Bit Offset */
115 #define PCM_CTL1_PMR_BUSY_OFS (8)
117 /* RTCKEY Bit Offset */
118 #define RTC_C_CTL0_KEY_OFS (8)
119 /* RTCKEY Bit Mask */
120 #define RTC_C_CTL0_KEY_MASK ((uint16_t)0xFF00)
121 /* RTCHOLD Bit Offset */
122 #define RTC_C_CTL13_HOLD_OFS (6)
123 /* RTC_C Key Value for RTC_C write access */
124 #define RTC_C_KEY ((uint16_t)0xA500)
126 /* Watchdog timer hold */
127 #define WDT_A_CTL_HOLD ((uint16_t)0x0080)
128 /* WDT Key Value for WDT write access */
129 #define WDT_A_CTL_PW ((uint16_t)0x5A00)
131 /* Address of BSL API table */
132 #define BSL_API_TABLE_ADDR ((uint32_t)0x00202000)
138 #endif /* OPENOCD_LOADERS_FLASH_MSP432_MSP432P411X_H */