git.gag.com Git - fw/openocd/blob - contrib/loaders/flash/msp432/driverlib.h

   1 /* SPDX-License-Identifier: BSD-3-Clause */
   2
   3 /******************************************************************************
   4 *
   5 * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
   6 *
   7 ******************************************************************************/
   8
   9 #ifndef OPENOCD_LOADERS_FLASH_MSP432_DRIVERLIB_H
  10 #define OPENOCD_LOADERS_FLASH_MSP432_DRIVERLIB_H
  11
  12 #include <stdint.h>
  13 #include <stdbool.h>
  14
  15 #ifdef __cplusplus
  16 extern "C" {
  17 #endif
  18
  19 #if defined(__MSP432E4X__)
  20 #include "msp432e4x.h"
  21 #elif defined(__MSP432P401X__)
  22 #include "msp432p401x.h"
  23 #elif defined(__MSP432P411X__)
  24 #include "msp432p411x.h"
  25 #else
  26 #error "Failed to match a device specific include file"
  27 #endif
  28
  29 /* Structure type to access the System Control Block (SCB). */
  30 struct SCB_Type {
  31         volatile uint32_t CPUID;         /* CPUID Base Register */
  32         volatile uint32_t ICSR;          /* Interrupt Control and State Register */
  33         volatile uint32_t VTOR;          /* Vector Table Offset Register */
  34         volatile uint32_t AIRCR;         /* Application Interrupt and Reset Control */
  35         volatile uint32_t SCR;           /* System Control Register */
  36         volatile uint32_t CCR;           /* Configuration Control Register */
  37         volatile uint8_t  SHP[12U];      /* System Handlers Priority Registers */
  38         volatile uint32_t SHCSR;         /* System Handler Control and State */
  39         volatile uint32_t CFSR;          /* Configurable Fault Status Register */
  40         volatile uint32_t HFSR;          /* HardFault Status Register */
  41         volatile uint32_t DFSR;          /* Debug Fault Status Register */
  42         volatile uint32_t MMFAR;         /* MemManage Fault Address Register */
  43         volatile uint32_t BFAR;          /* BusFault Address Register */
  44         volatile uint32_t AFSR;          /* Auxiliary Fault Status Register */
  45         volatile uint32_t PFR[2U];       /* Processor Feature Register */
  46         volatile uint32_t DFR;           /* Debug Feature Register */
  47         volatile uint32_t ADR;           /* Auxiliary Feature Register */
  48         volatile uint32_t MMFR[4U];      /* Memory Model Feature Register */
  49         volatile uint32_t ISAR[5U];      /* Instruction Set Attributes Register */
  50                          uint32_t RESERVED0[5U];
  51         volatile uint32_t CPACR;         /* Coprocessor Access Control Register */
  52 };
  53
  54 /* SCB:SCR register bits */
  55 #define SCB_SCR_SLEEPDEEP_POS 2U
  56 #define SCB_SCR_SLEEPDEEP_MSK (1UL << SCB_SCR_SLEEPDEEP_POS)
  57
  58 /* Memory mapping of Core Hardware */
  59 #define SCS_BASE (0xE000E000UL)         /* System Control Space Base Address */
  60 #define SCB_BASE (SCS_BASE +  0x0D00UL) /* System Control Block Base Address */
  61 #define SCB ((struct SCB_Type *)SCB_BASE) /* SCB configuration struct */
  62
  63 /* Definitions of standard bits */
  64 #define BIT0   (uint16_t)(0x0001)
  65 #define BIT1   (uint16_t)(0x0002)
  66 #define BIT2   (uint16_t)(0x0004)
  67 #define BIT3   (uint16_t)(0x0008)
  68 #define BIT4   (uint16_t)(0x0010)
  69 #define BIT5   (uint16_t)(0x0020)
  70 #define BIT6   (uint16_t)(0x0040)
  71 #define BIT7   (uint16_t)(0x0080)
  72 #define BIT8   (uint16_t)(0x0100)
  73 #define BIT9   (uint16_t)(0x0200)
  74 #define BITA   (uint16_t)(0x0400)
  75 #define BITB   (uint16_t)(0x0800)
  76 #define BITC   (uint16_t)(0x1000)
  77 #define BITD   (uint16_t)(0x2000)
  78 #define BITE   (uint16_t)(0x4000)
  79 #define BITF   (uint16_t)(0x8000)
  80 #define BIT(x) ((uint16_t)1 << (x))
  81
  82 /* CPU Module prototypes */
  83 extern uint32_t cpu_cpsid(void);
  84 extern void cpu_wfi(void);
  85
  86 /* Clock Signal Module constants */
  87 #define CS_DCO_FREQUENCY_3  CS_CTL0_DCORSEL_1
  88 #define CS_DCO_FREQUENCY_24 CS_CTL0_DCORSEL_4
  89
  90 /* Power Control Module constants */
  91 #define PCM_KEY              0x695A0000
  92 #define PCM_AM_LDO_VCORE0    0x00
  93 #define PCM_AM_LDO_VCORE1    0x01
  94 #define PCM_AM_DCDC_VCORE0   0x04
  95 #define PCM_AM_DCDC_VCORE1   0x05
  96 #define PCM_AM_LF_VCORE0     0x08
  97 #define PCM_AM_LF_VCORE1     0x09
  98 #define PCM_LPM0_LDO_VCORE0  0x10
  99 #define PCM_LPM0_LDO_VCORE1  0x11
 100 #define PCM_LPM0_DCDC_VCORE0 0x14
 101 #define PCM_LPM0_DCDC_VCORE1 0x15
 102 #define PCM_LPM0_LF_VCORE0   0x18
 103 #define PCM_LPM0_LF_VCORE1   0x19
 104 #define PCM_LPM3             0x20
 105 #define PCM_LPM4             0x21
 106 #define PCM_LPM35_VCORE0     0xC0
 107 #define PCM_LPM45            0xA0
 108 #define PCM_VCORE0           0x00
 109 #define PCM_VCORE1           0x01
 110 #define PCM_VCORELPM3        0x02
 111 #define PCM_LDO_MODE         0x00
 112 #define PCM_DCDC_MODE        0x01
 113 #define PCM_LF_MODE          0x02
 114
 115 /* Power Control Module prototypes */
 116 extern bool pcm_set_core_voltage_level(uint_fast8_t voltage_level);
 117 extern uint8_t pcm_get_core_voltage_level(void);
 118 extern bool pcm_set_power_mode(uint_fast8_t power_mode);
 119 extern uint8_t pcm_get_power_mode(void);
 120 extern bool pcm_set_power_state(uint_fast8_t power_state);
 121 extern uint8_t pcm_get_power_state(void);
 122 extern bool pcm_shutdown_device(uint32_t shutdown_mode);
 123 extern bool pcm_goto_lpm0(void);
 124 extern bool pcm_goto_lpm3(void);
 125 extern bool pcm_goto_lpm4(void);
 126
 127 /* ROM API Function Pointers */
 128 #define ROM_API_TABLE         ((unsigned long *)0x02000800)
 129 #define ROM_FLASH_CTL_TABLE   ((unsigned long *)(ROM_API_TABLE[7]))
 130 #define ROM_PCM_TABLE         ((unsigned long *)(ROM_API_TABLE[13]))
 131 #define ROM_WDT_TABLE         ((unsigned long *)(ROM_API_TABLE[25]))
 132 #define ROM_SYS_CTL_A_TABLE   ((unsigned long *)(ROM_API_TABLE[26]))
 133 #define ROM_FLASH_CTL_A_TABLE ((unsigned long *)(ROM_API_TABLE[27]))
 134
 135 #if defined(__MSP432P401X__)
 136 #define ROM_FLASH_CTL_UNPROTECT_SECTOR \
 137         ((bool (*)(uint_fast8_t memory_space, \
 138                 uint32_t sector_mask))ROM_FLASH_CTL_TABLE[4])
 139 #endif
 140 #if defined(__MSP432P401X__)
 141 #define ROM_FLASH_CTL_PROTECT_SECTOR \
 142         ((bool (*)(uint_fast8_t memory_space, \
 143                 uint32_t sector_mask))ROM_FLASH_CTL_TABLE[5])
 144 #endif
 145 #if defined(__MSP432P401X__)
 146 #define ROM_FLASH_CTL_PERFORM_MASS_ERASE \
 147         ((bool (*)(void))ROM_FLASH_CTL_TABLE[8])
 148 #endif
 149 #if defined(__MSP432P401X__)
 150 #define ROM_FLASH_CTL_ERASE_SECTOR \
 151         ((bool (*)(uint32_t addr))ROM_FLASH_CTL_TABLE[9])
 152 #endif
 153 #if defined(__MSP432P401X__)
 154 #define ROM_FLASH_CTL_PROGRAM_MEMORY \
 155         ((bool (*)(void *src, void *dest, uint32_t length))ROM_FLASH_CTL_TABLE[10])
 156 #endif
 157 #if defined(__MSP432P401X__)
 158 #define ROM_FLASH_CTL_SET_WAIT_STATE \
 159         ((void (*)(uint32_t bank, uint32_t wait_state))ROM_FLASH_CTL_TABLE[21])
 160 #endif
 161 #if defined(__MSP432P401X__)
 162 #define ROM_FLASH_CTL_GET_WAIT_STATE \
 163         ((uint32_t (*)(uint32_t bank))ROM_FLASH_CTL_TABLE[22])
 164 #endif
 165 #if defined(__MSP432P401X__)
 166 #define ROM_PCM_SET_CORE_VOLTAGE_LEVEL \
 167         ((bool (*)(uint_fast8_t voltage_level))ROM_PCM_TABLE[0])
 168 #endif
 169 #if defined(__MSP432P401X__)
 170 #define ROM_PCM_GET_CORE_VOLTAGE_LEVEL \
 171         ((uint8_t (*)(void))ROM_PCM_TABLE[1])
 172 #endif
 173 #if defined(__MSP432P401X__)
 174 #define ROM_PCM_SET_POWER_STATE \
 175         ((bool (*)(uint_fast8_t power_state))ROM_PCM_TABLE[6])
 176 #endif
 177 #if defined(__MSP432P401X__)
 178 #define ROM_PCM_GET_POWER_STATE \
 179         ((uint8_t (*)(void))ROM_PCM_TABLE[8])
 180 #endif
 181 #if defined(__MSP432P401X__) || defined(__MSP432P411X__)
 182 #define ROM_WDT_A_HOLD_TIMER \
 183         ((void (*)(void))ROM_WDT_TABLE[0])
 184 #endif
 185 #if defined(__MSP432P411X__)
 186 #define ROM_SYS_CTL_A_GET_FLASH_SIZE \
 187         ((uint_least32_t (*)(void))ROM_SYS_CTL_A_TABLE[1])
 188 #endif
 189 #if defined(__MSP432P411X__)
 190 #define ROM_SYS_CTL_A_GET_INFO_FLASH_SIZE \
 191         ((uint_least32_t (*)(void))ROM_SYS_CTL_A_TABLE[18])
 192 #endif
 193 #if defined(__MSP432P411X__)
 194 #define ROM_FLASH_CTL_A_UNPROTECT_MEMORY \
 195         ((bool (*)(uint32_t start_addr, uint32_t end_addr))ROM_FLASH_CTL_A_TABLE[4])
 196 #endif
 197 #if defined(__MSP432P411X__)
 198 #define ROM_FLASH_CTL_A_PROTECT_MEMORY \
 199         ((bool (*)(uint32_t start_addr, uint32_t end_addr))ROM_FLASH_CTL_A_TABLE[5])
 200 #endif
 201 #if defined(__MSP432P411X__)
 202 #define ROM_FLASH_CTL_A_PERFORM_MASS_ERASE \
 203         ((bool (*)(void))ROM_FLASH_CTL_A_TABLE[8])
 204 #endif
 205 #if defined(__MSP432P411X__)
 206 #define ROM_FLASH_CTL_A_ERASE_SECTOR \
 207         ((bool (*)(uint32_t addr))ROM_FLASH_CTL_A_TABLE[9])
 208 #endif
 209 #if defined(__MSP432P411X__)
 210 #define ROM_FLASH_CTL_A_PROGRAM_MEMORY \
 211         ((bool (*)(void *src, void *dest, uint32_t length)) \
 212                 ROM_FLASH_CTL_A_TABLE[10])
 213 #endif
 214 #if defined(__MSP432P411X__)
 215 #define ROM_FLASH_CTL_A_SET_WAIT_STATE \
 216         ((void (*)(uint32_t bank, uint32_t wait_state))ROM_FLASH_CTL_A_TABLE[21])
 217 #endif
 218 #if defined(__MSP432P411X__)
 219 #define ROM_FLASH_CTL_A_GET_WAIT_STATE \
 220         ((uint32_t (*)(uint32_t bank))ROM_FLASH_CTL_A_TABLE[22])
 221 #endif
 222
 223 /* Map API functions to ROM or locally built functions */
 224 #ifdef ROM_FLASH_CTL_UNPROTECT_SECTOR
 225 #define MAP_FLASH_CTL_UNPROTECT_SECTOR ROM_FLASH_CTL_UNPROTECT_SECTOR
 226 #else
 227 #define MAP_FLASH_CTL_UNPROTECT_SECTOR flash_ctl_unprotect_sector
 228 #endif
 229 #ifdef ROM_FLASH_CTL_PROTECT_SECTOR
 230 #define MAP_FLASH_CTL_PROTECT_SECTOR ROM_FLASH_CTL_PROTECT_SECTOR
 231 #else
 232 #define MAP_FLASH_CTL_PROTECT_SECTOR flash_ctl_protect_sector
 233 #endif
 234 #ifdef ROM_FLASH_CTL_PERFORM_MASS_ERASE
 235 #define MAP_FLASH_CTL_PERFORM_MASS_ERASE ROM_FLASH_CTL_PERFORM_MASS_ERASE
 236 #else
 237 #define MAP_FLASH_CTL_PERFORM_MASS_ERASE flash_ctl_perform_mass_erase
 238 #endif
 239 #ifdef ROM_FLASH_CTL_ERASE_SECTOR
 240 #define MAP_FLASH_CTL_ERASE_SECTOR ROM_FLASH_CTL_ERASE_SECTOR
 241 #else
 242 #define MAP_FLASH_CTL_ERASE_SECTOR flash_ctl_erase_sector
 243 #endif
 244 #ifdef ROM_FLASH_CTL_PROGRAM_MEMORY
 245 #define MAP_FLASH_CTL_PROGRAM_MEMORY ROM_FLASH_CTL_PROGRAM_MEMORY
 246 #else
 247 #define MAP_FLASH_CTL_PROGRAM_MEMORY flash_ctl_program_memory
 248 #endif
 249 #ifdef ROM_FLASH_CTL_SET_WAIT_STATE
 250 #define MAP_FLASH_CTL_SET_WAIT_STATE ROM_FLASH_CTL_SET_WAIT_STATE
 251 #else
 252 #define MAP_FLASH_CTL_SET_WAIT_STATE flash_ctl_set_wait_state
 253 #endif
 254 #ifdef ROM_FLASH_CTL_GET_WAIT_STATE
 255 #define MAP_FLASH_CTL_GET_WAIT_STATE ROM_FLASH_CTL_GET_WAIT_STATE
 256 #else
 257 #define MAP_FLASH_CTL_GET_WAIT_STATE flash_ctl_get_wait_state
 258 #endif
 259 #ifdef ROM_PCM_SET_CORE_VOLTAGE_LEVEL
 260 #define MAP_PCM_SET_CORE_VOLTAGE_LEVEL ROM_PCM_SET_CORE_VOLTAGE_LEVEL
 261 #else
 262 #define MAP_PCM_SET_CORE_VOLTAGE_LEVEL pcm_set_core_voltage_level
 263 #endif
 264 #ifdef ROM_PCM_GET_CORE_VOLTAGE_LEVEL
 265 #define MAP_PCM_GET_CORE_VOLTAGE_LEVEL ROM_PCM_GET_CORE_VOLTAGE_LEVEL
 266 #else
 267 #define MAP_PCM_GET_CORE_VOLTAGE_LEVEL pcm_get_core_voltage_level
 268 #endif
 269 #ifdef ROM_PCM_SET_POWER_STATE
 270 #define MAP_PCM_SET_POWER_STATE ROM_PCM_SET_POWER_STATE
 271 #else
 272 #define MAP_PCM_SET_POWER_STATE pcm_set_power_state
 273 #endif
 274 #ifdef ROM_PCM_GET_POWER_STATE
 275 #define MAP_PCM_GET_POWER_STATE ROM_PCM_GET_POWER_STATE
 276 #else
 277 #define MAP_PCM_GET_POWER_STATE pcm_get_power_state
 278 #endif
 279 #ifdef ROM_WDT_A_HOLD_TIMER
 280 #define MAP_WDT_A_HOLD_TIMER ROM_WDT_A_HOLD_TIMER
 281 #else
 282 #define MAP_WDT_A_HOLD_TIMER wdt_a_hold_timer
 283 #endif
 284 #ifdef ROM_SYS_CTL_A_GET_FLASH_SIZE
 285 #define MAP_SYS_CTL_A_GET_FLASH_SIZE ROM_SYS_CTL_A_GET_FLASH_SIZE
 286 #else
 287 #define MAP_SYS_CTL_A_GET_FLASH_SIZE sys_ctl_a_get_flash_size
 288 #endif
 289 #ifdef ROM_SYS_CTL_A_GET_INFO_FLASH_SIZE
 290 #define MAP_SYS_CTL_A_GET_INFO_FLASH_SIZE ROM_SYS_CTL_A_GET_INFO_FLASH_SIZE
 291 #else
 292 #define MAP_SYS_CTL_A_GET_INFO_FLASH_SIZE sys_ctl_a_get_info_flash_size
 293 #endif
 294 #ifdef ROM_FLASH_CTL_A_UNPROTECT_MEMORY
 295 #define MAP_FLASH_CTL_A_UNPROTECT_MEMORY ROM_FLASH_CTL_A_UNPROTECT_MEMORY
 296 #else
 297 #define MAP_FLASH_CTL_A_UNPROTECT_MEMORY flash_ctl_a_unprotect_memory
 298 #endif
 299 #ifdef ROM_FLASH_CTL_A_PROTECT_MEMORY
 300 #define MAP_FLASH_CTL_A_PROTECT_MEMORY ROM_FLASH_CTL_A_PROTECT_MEMORY
 301 #else
 302 #define MAP_FLASH_CTL_A_PROTECT_MEMORY flash_ctl_a_protect_memory
 303 #endif
 304 #ifdef ROM_FLASH_CTL_A_PERFORM_MASS_ERASE
 305 #define MAP_FLASH_CTL_A_PERFORM_MASS_ERASE ROM_FLASH_CTL_A_PERFORM_MASS_ERASE
 306 #else
 307 #define MAP_FLASH_CTL_A_PERFORM_MASS_ERASE flash_ctl_a_perform_mass_erase
 308 #endif
 309 #ifdef ROM_FLASH_CTL_A_ERASE_SECTOR
 310 #define MAP_FLASH_CTL_A_ERASE_SECTOR ROM_FLASH_CTL_A_ERASE_SECTOR
 311 #else
 312 #define MAP_FLASH_CTL_A_ERASE_SECTOR flash_ctl_a_erase_sector
 313 #endif
 314 #ifdef ROM_FLASH_CTL_A_PROGRAM_MEMORY
 315 #define MAP_FLASH_CTL_A_PROGRAM_MEMORY ROM_FLASH_CTL_A_PROGRAM_MEMORY
 316 #else
 317 #define MAP_FLASH_CTL_A_PROGRAM_MEMORY flash_ctl_a_program_memory
 318 #endif
 319 #ifdef ROM_FLASH_CTL_A_SET_WAIT_STATE
 320 #define MAP_FLASH_CTL_A_SET_WAIT_STATE ROM_FLASH_CTL_A_SET_WAIT_STATE
 321 #else
 322 #define MAP_FLASH_CTL_A_SET_WAIT_STATE flash_ctl_a_set_wait_state
 323 #endif
 324 #ifdef ROM_FLASH_CTL_A_GET_WAIT_STATE
 325 #define MAP_FLASH_CTL_A_GET_WAIT_STATE ROM_FLASH_CTL_A_GET_WAIT_STATE
 326 #else
 327 #define MAP_FLASH_CTL_A_GET_WAIT_STATE flash_ctl_a_get_wait_state
 328 #endif
 329
 330 /* Real Time Clock Module prototypes */
 331 extern void rtc_c_hold_clock(void);
 332
 333 /* Watchdog Timer Module prototypes */
 334 extern void wdt_a_hold_timer(void);
 335
 336 #if defined(__MCU_HAS_FLCTL_A__)
 337 #define FLASH_A_BANK0                0x00
 338 #define FLASH_A_BANK1                0x01
 339 #define __INFO_FLASH_A_TECH_START__  0x00200000
 340 #define __INFO_FLASH_A_TECH_MIDDLE__ 0x00204000
 341 #endif
 342
 343 #if defined(__MCU_HAS_FLCTL__)
 344 #define FLASH_BANK0 0x00
 345 #define FLASH_BANK1 0x01
 346 #define FLASH_MAIN_MEMORY_SPACE_BANK0 0x01
 347 #define FLASH_MAIN_MEMORY_SPACE_BANK1 0x02
 348 #define FLASH_INFO_MEMORY_SPACE_BANK0 0x03
 349 #define FLASH_INFO_MEMORY_SPACE_BANK1 0x04
 350 #define FLASH_SECTOR0 FLCTL_BANK0_MAIN_WEPROT_PROT0
 351 #define FLASH_SECTOR1 FLCTL_BANK0_MAIN_WEPROT_PROT1
 352 #endif
 353
 354 #ifdef __cplusplus
 355 }
 356 #endif
 357
 358 #endif /* OPENOCD_LOADERS_FLASH_MSP432_DRIVERLIB_H */