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33 ******************************************************************************/
37 #include "driverlib.h"
40 * Wrapper function for the CPSID instruction.
41 * Returns the state of PRIMASK on entry.
43 uint32_t __attribute__((naked)) cpu_cpsid(void)
47 /* Read PRIMASK and disable interrupts. */
48 __asm(" mrs r0, PRIMASK\n"
54 * The return is handled in the inline assembly, but the compiler will
55 * still complain if there is not an explicit return here (despite the fact
56 * that this does not result in any code being produced because of the
62 /* Wrapper function for the CPUWFI instruction. */
63 void __attribute__((naked)) cpu_wfi(void)
65 /* Wait for the next interrupt. */
70 /* Power Control Module APIs */
73 static bool __pcm_set_core_voltage_level_advanced(uint_fast8_t voltage_level,
74 uint32_t time_out, bool blocking)
77 uint8_t current_voltage_level;
81 /* Getting current power mode and level */
82 power_mode = pcm_get_power_mode();
83 current_voltage_level = pcm_get_core_voltage_level();
85 bool_timeout = time_out > 0 ? true : false;
87 /* If we are already at the power mode they requested, return */
88 if (current_voltage_level == voltage_level)
91 while (current_voltage_level != voltage_level) {
93 reg_value = PCM->CTL0;
95 switch (pcm_get_power_state()) {
96 case PCM_AM_LF_VCORE1:
97 case PCM_AM_DCDC_VCORE1:
98 case PCM_AM_LDO_VCORE0:
99 PCM->CTL0 = (PCM_KEY | (PCM_AM_LDO_VCORE1)
100 | (reg_value & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK)));
102 case PCM_AM_LF_VCORE0:
103 case PCM_AM_DCDC_VCORE0:
104 case PCM_AM_LDO_VCORE1:
105 PCM->CTL0 = (PCM_KEY | (PCM_AM_LDO_VCORE0)
106 | (reg_value & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK)));
113 while (BITBAND_PERI(PCM->CTL1, PCM_CTL1_PMR_BUSY_OFS)) {
114 if (bool_timeout && !(--time_out))
120 current_voltage_level = pcm_get_core_voltage_level();
123 /* Changing the power mode if we are stuck in LDO mode */
124 if (power_mode != pcm_get_power_mode()) {
125 if (power_mode == PCM_DCDC_MODE)
126 return pcm_set_power_mode(PCM_DCDC_MODE);
128 return pcm_set_power_mode(PCM_LF_MODE);
134 bool pcm_set_core_voltage_level(uint_fast8_t voltage_level)
136 return __pcm_set_core_voltage_level_advanced(voltage_level, 0, true);
139 uint8_t pcm_get_power_mode(void)
141 uint8_t current_power_state;
143 current_power_state = pcm_get_power_state();
145 switch (current_power_state) {
146 case PCM_AM_LDO_VCORE0:
147 case PCM_AM_LDO_VCORE1:
148 case PCM_LPM0_LDO_VCORE0:
149 case PCM_LPM0_LDO_VCORE1:
152 case PCM_AM_DCDC_VCORE0:
153 case PCM_AM_DCDC_VCORE1:
154 case PCM_LPM0_DCDC_VCORE0:
155 case PCM_LPM0_DCDC_VCORE1:
156 return PCM_DCDC_MODE;
157 case PCM_LPM0_LF_VCORE0:
158 case PCM_LPM0_LF_VCORE1:
159 case PCM_AM_LF_VCORE1:
160 case PCM_AM_LF_VCORE0:
165 uint8_t pcm_get_core_voltage_level(void)
167 uint8_t current_power_state = pcm_get_power_state();
169 switch (current_power_state) {
170 case PCM_AM_LDO_VCORE0:
171 case PCM_AM_DCDC_VCORE0:
172 case PCM_AM_LF_VCORE0:
173 case PCM_LPM0_LDO_VCORE0:
174 case PCM_LPM0_DCDC_VCORE0:
175 case PCM_LPM0_LF_VCORE0:
178 case PCM_AM_LDO_VCORE1:
179 case PCM_AM_DCDC_VCORE1:
180 case PCM_AM_LF_VCORE1:
181 case PCM_LPM0_LDO_VCORE1:
182 case PCM_LPM0_DCDC_VCORE1:
183 case PCM_LPM0_LF_VCORE1:
186 return PCM_VCORELPM3;
190 static bool __pcm_set_power_mode_advanced(uint_fast8_t power_mode,
191 uint32_t time_out, bool blocking)
193 uint8_t current_power_mode;
194 uint8_t current_power_state;
198 /* Getting Current Power Mode */
199 current_power_mode = pcm_get_power_mode();
201 /* If the power mode being set it the same as the current mode, return */
202 if (power_mode == current_power_mode)
205 current_power_state = pcm_get_power_state();
207 bool_timeout = time_out > 0 ? true : false;
209 /* Go through the while loop while we haven't achieved the power mode */
210 while (current_power_mode != power_mode) {
212 reg_value = PCM->CTL0;
214 switch (current_power_state) {
215 case PCM_AM_DCDC_VCORE0:
216 case PCM_AM_LF_VCORE0:
217 PCM->CTL0 = (PCM_KEY | PCM_AM_LDO_VCORE0
218 | (reg_value & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK)));
220 case PCM_AM_LF_VCORE1:
221 case PCM_AM_DCDC_VCORE1:
222 PCM->CTL0 = (PCM_KEY | PCM_AM_LDO_VCORE1
223 | (reg_value & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK)));
225 case PCM_AM_LDO_VCORE1: {
226 if (power_mode == PCM_DCDC_MODE) {
227 PCM->CTL0 = (PCM_KEY | PCM_AM_DCDC_VCORE1
228 | (reg_value & ~(PCM_CTL0_KEY_MASK
229 | PCM_CTL0_AMR_MASK)));
230 } else if (power_mode == PCM_LF_MODE) {
231 PCM->CTL0 = (PCM_KEY | PCM_AM_LF_VCORE1
232 | (reg_value & ~(PCM_CTL0_KEY_MASK
233 | PCM_CTL0_AMR_MASK)));
238 case PCM_AM_LDO_VCORE0: {
239 if (power_mode == PCM_DCDC_MODE) {
240 PCM->CTL0 = (PCM_KEY | PCM_AM_DCDC_VCORE0
241 | (reg_value & ~(PCM_CTL0_KEY_MASK
242 | PCM_CTL0_AMR_MASK)));
243 } else if (power_mode == PCM_LF_MODE) {
244 PCM->CTL0 = (PCM_KEY | PCM_AM_LF_VCORE0
245 | (reg_value & ~(PCM_CTL0_KEY_MASK
246 | PCM_CTL0_AMR_MASK)));
256 while (BITBAND_PERI(PCM->CTL1, PCM_CTL1_PMR_BUSY_OFS)) {
257 if (bool_timeout && !(--time_out))
263 current_power_mode = pcm_get_power_mode();
264 current_power_state = pcm_get_power_state();
270 bool pcm_set_power_mode(uint_fast8_t power_mode)
272 return __pcm_set_power_mode_advanced(power_mode, 0, true);
275 static bool __pcm_set_power_state_advanced(uint_fast8_t power_state,
276 uint32_t timeout, bool blocking)
278 uint8_t current_power_state;
279 current_power_state = pcm_get_power_state();
281 if (current_power_state == power_state)
284 switch (power_state) {
285 case PCM_AM_LDO_VCORE0:
286 return __pcm_set_core_voltage_level_advanced(PCM_VCORE0, timeout,
287 blocking) && __pcm_set_power_mode_advanced(PCM_LDO_MODE,
289 case PCM_AM_LDO_VCORE1:
290 return __pcm_set_core_voltage_level_advanced(PCM_VCORE1, timeout,
291 blocking) && __pcm_set_power_mode_advanced(PCM_LDO_MODE,
293 case PCM_AM_DCDC_VCORE0:
294 return __pcm_set_core_voltage_level_advanced(PCM_VCORE0, timeout,
295 blocking) && __pcm_set_power_mode_advanced(PCM_DCDC_MODE,
297 case PCM_AM_DCDC_VCORE1:
298 return __pcm_set_core_voltage_level_advanced(PCM_VCORE1, timeout,
299 blocking) && __pcm_set_power_mode_advanced(PCM_DCDC_MODE,
301 case PCM_AM_LF_VCORE0:
302 return __pcm_set_core_voltage_level_advanced(PCM_VCORE0, timeout,
303 blocking) && __pcm_set_power_mode_advanced(PCM_LF_MODE,
305 case PCM_AM_LF_VCORE1:
306 return __pcm_set_core_voltage_level_advanced(PCM_VCORE1, timeout,
307 blocking) && __pcm_set_power_mode_advanced(PCM_LF_MODE,
309 case PCM_LPM0_LDO_VCORE0:
310 if (!__pcm_set_core_voltage_level_advanced(PCM_VCORE0, timeout,
311 blocking) || !__pcm_set_power_mode_advanced(PCM_LDO_MODE,
314 return pcm_goto_lpm0();
315 case PCM_LPM0_LDO_VCORE1:
316 if (!__pcm_set_core_voltage_level_advanced(PCM_VCORE1, timeout,
317 blocking) || !__pcm_set_power_mode_advanced(PCM_LDO_MODE,
320 return pcm_goto_lpm0();
321 case PCM_LPM0_DCDC_VCORE0:
322 if (!__pcm_set_core_voltage_level_advanced(PCM_VCORE0, timeout,
323 blocking) || !__pcm_set_power_mode_advanced(PCM_DCDC_MODE,
326 return pcm_goto_lpm0();
327 case PCM_LPM0_DCDC_VCORE1:
328 if (!__pcm_set_core_voltage_level_advanced(PCM_VCORE1, timeout,
329 blocking) || !__pcm_set_power_mode_advanced(PCM_DCDC_MODE,
332 return pcm_goto_lpm0();
333 case PCM_LPM0_LF_VCORE0:
334 if (!__pcm_set_core_voltage_level_advanced(PCM_VCORE0, timeout,
335 blocking) || !__pcm_set_power_mode_advanced(PCM_LF_MODE,
338 return pcm_goto_lpm0();
339 case PCM_LPM0_LF_VCORE1:
340 if (!__pcm_set_core_voltage_level_advanced(PCM_VCORE1, timeout,
341 blocking) || !__pcm_set_power_mode_advanced(PCM_LF_MODE,
344 return pcm_goto_lpm0();
346 return pcm_goto_lpm3();
348 return pcm_goto_lpm4();
350 return pcm_shutdown_device(PCM_LPM45);
351 case PCM_LPM35_VCORE0:
352 return pcm_shutdown_device(PCM_LPM35_VCORE0);
360 bool pcm_set_power_state(uint_fast8_t power_state)
362 return __pcm_set_power_state_advanced(power_state, 0, true);
365 bool pcm_shutdown_device(uint32_t shutdown_mode)
367 uint32_t shutdown_mode_bits = (shutdown_mode == PCM_LPM45) ?
368 PCM_CTL0_LPMR_12 : PCM_CTL0_LPMR_10;
370 /* If a power transition is occuring, return false */
371 if (BITBAND_PERI(PCM->CTL1, PCM_CTL1_PMR_BUSY_OFS))
374 /* Initiating the shutdown */
375 SCB->SCR |= SCB_SCR_SLEEPDEEP_MSK;
377 PCM->CTL0 = (PCM_KEY | shutdown_mode_bits
378 | (PCM->CTL0 & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_LPMR_MASK)));
385 bool pcm_goto_lpm4(void)
387 /* Disabling RTC_C and WDT_A */
391 /* LPM4 is just LPM3 with WDT_A/RTC_C disabled... */
392 return pcm_goto_lpm3();
395 bool pcm_goto_lpm0(void)
397 /* If we are in the middle of a state transition, return false */
398 if (BITBAND_PERI(PCM->CTL1, PCM_CTL1_PMR_BUSY_OFS))
401 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_MSK;
408 bool pcm_goto_lpm3(void)
410 uint_fast8_t current_power_state;
411 uint_fast8_t current_power_mode;
413 /* If we are in the middle of a state transition, return false */
414 if (BITBAND_PERI(PCM->CTL1, PCM_CTL1_PMR_BUSY_OFS))
417 /* If we are in the middle of a shutdown, return false */
418 if ((PCM->CTL0 & PCM_CTL0_LPMR_MASK) == PCM_CTL0_LPMR_10
419 || (PCM->CTL0 & PCM_CTL0_LPMR_MASK) == PCM_CTL0_LPMR_12)
422 current_power_mode = pcm_get_power_mode();
423 current_power_state = pcm_get_power_state();
425 if (current_power_mode == PCM_DCDC_MODE)
426 pcm_set_power_mode(PCM_LDO_MODE);
428 /* Clearing the SDR */
430 (PCM->CTL0 & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_LPMR_MASK)) | PCM_KEY;
432 /* Setting the sleep deep bit */
433 SCB->SCR |= SCB_SCR_SLEEPDEEP_MSK;
437 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_MSK;
439 return pcm_set_power_state(current_power_state);
442 uint8_t pcm_get_power_state(void)
444 return (PCM->CTL0 & PCM_CTL0_CPM_MASK) >> PCM_CTL0_CPM_OFS;
449 /* Real Time Clock APIs */
452 void rtc_c_hold_clock(void)
454 RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY;
455 BITBAND_PERI(RTC_C->CTL13, RTC_C_CTL13_HOLD_OFS) = 1;
456 BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0;
461 /* Watch Dog Timer APIs */
464 void wdt_a_hold_timer(void)
467 uint8_t new_wdt_status = (WDT_A->CTL | WDT_A_CTL_HOLD);
469 WDT_A->CTL = WDT_A_CTL_PW + new_wdt_status;