git.gag.com Git - fw/openocd/blob - contrib/loaders/flash/fpga/xilinx_bscan_spi.py

   1 #!/usr/bin/python3
   2 #
   3 #  Copyright (C) 2015 Robert Jordens <jordens@gmail.com>
   4 #
   5 #  This program is free software; you can redistribute it and/or modify
   6 #  it under the terms of the GNU General Public License as published by
   7 #  the Free Software Foundation; either version 2 of the License, or
   8 #  (at your option) any later version.
   9 #
  10 #  This program is distributed in the hope that it will be useful,
  11 #  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 #  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 #  GNU General Public License for more details.
  14 #
  15
  16 from migen.fhdl.std import *
  17 from mibuild.generic_platform import *
  18 from mibuild.xilinx import XilinxPlatform
  19 from mibuild.xilinx.vivado import XilinxVivadoToolchain
  20 from mibuild.xilinx.ise import XilinxISEToolchain
  21
  22
  23 """
  24 This migen script produces proxy bitstreams to allow programming SPI flashes
  25 behind FPGAs. JTAG signalling is connected directly to SPI signalling. CS_N is
  26 asserted when the JTAG IR contains the USER1 instruction and the state is
  27 SHIFT-DR.
  28
  29 Xilinx bscan cells sample TDO on falling TCK and forward it.
  30 MISO requires sampling on rising CLK and leads to one cycle of latency.
  31
  32 https://github.com/m-labs/migen
  33 """
  34
  35
  36 class Spartan3(Module):
  37     macro = "BSCAN_SPARTAN3"
  38
  39     def __init__(self, platform):
  40         self.clock_domains.cd_jtag = ClockDomain(reset_less=True)
  41         spi = platform.request("spiflash")
  42         shift = Signal()
  43         tdo = Signal()
  44         sel1 = Signal()
  45         self.comb += [
  46             self.cd_jtag.clk.eq(spi.clk),
  47             spi.cs_n.eq(~shift | ~sel1),
  48         ]
  49         self.sync.jtag += tdo.eq(spi.miso)
  50         self.specials += Instance(self.macro,
  51                                   o_DRCK1=spi.clk, o_SHIFT=shift,
  52                                   o_TDI=spi.mosi, i_TDO1=tdo, i_TDO2=0,
  53                                   o_SEL1=sel1)
  54
  55
  56 class Spartan3A(Spartan3):
  57     macro = "BSCAN_SPARTAN3A"
  58
  59
  60 class Spartan6(Module):
  61     def __init__(self, platform):
  62         self.clock_domains.cd_jtag = ClockDomain(reset_less=True)
  63         spi = platform.request("spiflash")
  64         shift = Signal()
  65         tdo = Signal()
  66         sel = Signal()
  67         self.comb += self.cd_jtag.clk.eq(spi.clk), spi.cs_n.eq(~shift | ~sel)
  68         self.sync.jtag += tdo.eq(spi.miso)
  69         self.specials += Instance("BSCAN_SPARTAN6", p_JTAG_CHAIN=1,
  70                                   o_TCK=spi.clk, o_SHIFT=shift, o_SEL=sel,
  71                                   o_TDI=spi.mosi, i_TDO=tdo)
  72
  73
  74 class Series7(Module):
  75     def __init__(self, platform):
  76         self.clock_domains.cd_jtag = ClockDomain(reset_less=True)
  77         spi = platform.request("spiflash")
  78         clk = Signal()
  79         shift = Signal()
  80         tdo = Signal()
  81         sel = Signal()
  82         self.comb += self.cd_jtag.clk.eq(clk), spi.cs_n.eq(~shift | ~sel)
  83         self.sync.jtag += tdo.eq(spi.miso)
  84         self.specials += Instance("BSCANE2", p_JTAG_CHAIN=1,
  85                                   o_SHIFT=shift, o_TCK=clk, o_SEL=sel,
  86                                   o_TDI=spi.mosi, i_TDO=tdo)
  87         self.specials += Instance("STARTUPE2", i_CLK=0, i_GSR=0, i_GTS=0,
  88                                   i_KEYCLEARB=0, i_PACK=1, i_USRCCLKO=clk,
  89                                   i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
  90
  91
  92 class XilinxBscanSpi(XilinxPlatform):
  93     pinouts = {
  94         # bitstreams are named by die, package does not matter, speed grade
  95         # should not matter.
  96         #                    cs_n, clk, mosi, miso, *pullups
  97         "xc3s100e": ("cp132",
  98             ["M2", "N12", "N2", "N8"],
  99             "LVCMOS33", Spartan3),
 100         "xc3s1200e": ("fg320",
 101             ["U3", "U16", "T4", "N10"],
 102             "LVCMOS33", Spartan3),
 103         "xc3s1400a": ("fg484",
 104             ["Y4", "AA20", "AB14", "AB20"],
 105             "LVCMOS33", Spartan3A),
 106         "xc3s1400an": ("fgg484",
 107             ["Y4", "AA20", "AB14", "AB20"],
 108             "LVCMOS33", Spartan3A),
 109         "xc3s1600e": ("fg320",
 110             ["U3", "U16", "T4", "N10"],
 111             "LVCMOS33", Spartan3),
 112         "xc3s200a": ("fg320",
 113             ["V3", "U16", "T11", "V16"],
 114             "LVCMOS33", Spartan3A),
 115         "xc3s200an": ("ftg256",
 116             ["T2", "R14", "P10", "T14"],
 117             "LVCMOS33", Spartan3A),
 118         "xc3s250e": ("cp132",
 119             ["M2", "N12", "N2", "N8"],
 120             "LVCMOS33", Spartan3),
 121         "xc3s400a": ("fg320",
 122             ["V3", "U16", "T11", "V16"],
 123             "LVCMOS33", Spartan3A),
 124         "xc3s400an": ("fgg400",
 125             ["Y2", "Y19", "W12", "W18"],
 126             "LVCMOS33", Spartan3A),
 127         "xc3s500e": ("cp132",
 128             ["M2", "N12", "N2", "N8"],
 129             "LVCMOS33", Spartan3),
 130         "xc3s50a": ("ft256",
 131             ["T2", "R14", "P10", "T14"],
 132             "LVCMOS33", Spartan3A),
 133         "xc3s50an": ("ftg256",
 134             ["T2", "R14", "P10", "T14"],
 135             "LVCMOS33", Spartan3A),
 136         "xc3s700a": ("fg400",
 137             ["Y2", "Y19", "W12", "W18"],
 138             "LVCMOS33", Spartan3A),
 139         "xc3s700an": ("fgg484",
 140             ["Y4", "AA20", "AB14", "AB20"],
 141             "LVCMOS33", Spartan3A),
 142         "xc3sd1800a": ("cs484",
 143             ["U7", "V17", "V13", "W17"],
 144             "LVCMOS33", Spartan3A),
 145         "xc3sd3400a": ("cs484",
 146             ["U7", "V17", "V13", "W17"],
 147             "LVCMOS33", Spartan3A),
 148
 149         "xc6slx100": ("csg484-2",
 150             ["AB5", "W17", "AB17", "Y17", "V13", "W13"],
 151             "LVCMOS33", Spartan6),
 152         "xc6slx100t": ("csg484-2",
 153             ["AB5", "W17", "AB17", "Y17", "V13", "W13"],
 154             "LVCMOS33", Spartan6),
 155         "xc6slx150": ("csg484-2",
 156             ["AB5", "W17", "AB17", "Y17", "V13", "W13"],
 157             "LVCMOS33", Spartan6),
 158         "xc6slx150t": ("csg484-2",
 159             ["AB5", "W17", "AB17", "Y17", "V13", "W13"],
 160             "LVCMOS33", Spartan6),
 161         "xc6slx16": ("cpg196-2",
 162             ["P2", "N13", "P11", "N11", "N10", "P10"],
 163             "LVCMOS33", Spartan6),
 164         "xc6slx25": ("csg324-2",
 165             ["V3", "R15", "T13", "R13", "T14", "V14"],
 166             "LVCMOS33", Spartan6),
 167         "xc6slx25t": ("csg324-2",
 168             ["V3", "R15", "T13", "R13", "T14", "V14"],
 169             "LVCMOS33", Spartan6),
 170         "xc6slx45": ("csg324-2",
 171             ["V3", "R15", "T13", "R13", "T14", "V14"],
 172             "LVCMOS33", Spartan6),
 173         "xc6slx45t": ("csg324-2",
 174             ["V3", "R15", "T13", "R13", "T14", "V14"],
 175             "LVCMOS33", Spartan6),
 176         "xc6slx4": ("cpg196-2",
 177             ["P2", "N13", "P11", "N11", "N10", "P10"],
 178             "LVCMOS33", Spartan6),
 179         "xc6slx4t": ("qg144-2",
 180             ["P38", "P70", "P64", "P65", "P62", "P61"],
 181             "LVCMOS33", Spartan6),
 182         "xc6slx75": ("csg484-2",
 183             ["AB5", "W17", "AB17", "Y17", "V13", "W13"],
 184             "LVCMOS33", Spartan6),
 185         "xc6slx75t": ("csg484-2",
 186             ["AB5", "W17", "AB17", "Y17", "V13", "W13"],
 187             "LVCMOS33", Spartan6),
 188         "xc6slx9": ("cpg196-2",
 189             ["P2", "N13", "P11", "N11", "N10", "P10"],
 190             "LVCMOS33", Spartan6),
 191         "xc6slx9t": ("qg144-2",
 192             ["P38", "P70", "P64", "P65", "P62", "P61"],
 193             "LVCMOS33", Spartan6),
 194
 195         "xc7a100t": ("csg324-1",
 196             ["L13", None, "K17", "K18", "L14", "M14"],
 197             "LVCMOS25", Series7),
 198         "xc7a15t": ("cpg236-1",
 199             ["K19", None, "D18", "D19", "G18", "F18"],
 200             "LVCMOS25", Series7),
 201         "xc7a200t": ("fbg484-1",
 202             ["T19", None, "P22", "R22", "P21", "R21"],
 203             "LVCMOS25", Series7),
 204         "xc7a35t": ("cpg236-1",
 205             ["K19", None, "D18", "D19", "G18", "F18"],
 206             "LVCMOS25", Series7),
 207         "xc7a50t": ("cpg236-1",
 208             ["K19", None, "D18", "D19", "G18", "F18"],
 209             "LVCMOS25", Series7),
 210         "xc7a75t": ("csg324-1",
 211             ["L13", None, "K17", "K18", "L14", "M14"],
 212             "LVCMOS25", Series7),
 213         "xc7k160t": ("fbg484-1",
 214             ["L16", None, "H18", "H19", "G18", "F19"],
 215             "LVCMOS25", Series7),
 216         "xc7k325t": ("fbg676-1",
 217             ["C23", None, "B24", "A25", "B22", "A22"],
 218             "LVCMOS25", Series7),
 219         "xc7k355t": ("ffg901-1",
 220             ["V26", None, "R30", "T30", "R28", "T28"],
 221             "LVCMOS25", Series7),
 222         "xc7k410t": ("fbg676-1",
 223             ["C23", None, "B24", "A25", "B22", "A22"],
 224             "LVCMOS25", Series7),
 225         "xc7k420t": ("ffg1156-1",
 226             ["V30", None, "AA33", "AA34", "Y33", "Y34"],
 227             "LVCMOS25", Series7),
 228         "xc7k480t": ("ffg1156-1",
 229             ["V30", None, "AA33", "AA34", "Y33", "Y34"],
 230             "LVCMOS25", Series7),
 231         "xc7k70t": ("fbg484-1",
 232             ["L16", None, "H18", "H19", "G18", "F19"],
 233             "LVCMOS25", Series7),
 234         "xc7v2000t": ("fhg1761-1",
 235             ["AL36", None, "AM36", "AN36", "AJ36", "AJ37"],
 236             "LVCMOS18", Series7),
 237         "xc7v585t": ("ffg1157-1",
 238             ["AL33", None, "AN33", "AN34", "AK34", "AL34"],
 239             "LVCMOS18", Series7),
 240         "xc7vh580t": ("flg1155-1",
 241             ["AL28", None, "AE28", "AF28", "AJ29", "AJ30"],
 242             "LVCMOS18", Series7),
 243         "xc7vh870t": ("flg1932-1",
 244             ["V32", None, "T33", "R33", "U31", "T31"],
 245             "LVCMOS18", Series7),
 246         "xc7vx1140t": ("flg1926-1",
 247             ["AK33", None, "AN34", "AN35", "AJ34", "AK34"],
 248             "LVCMOS18", Series7),
 249         "xc7vx330t": ("ffg1157-1",
 250             ["AL33", None, "AN33", "AN34", "AK34", "AL34"],
 251             "LVCMOS18", Series7),
 252         "xc7vx415t": ("ffg1157-1",
 253             ["AL33", None, "AN33", "AN34", "AK34", "AL34"],
 254             "LVCMOS18", Series7),
 255         "xc7vx485t": ("ffg1157-1",
 256             ["AL33", None, "AN33", "AN34", "AK34", "AL34"],
 257             "LVCMOS18", Series7),
 258         "xc7vx550t": ("ffg1158-1",
 259             ["C24", None, "A23", "A24", "B26", "A26"],
 260             "LVCMOS18", Series7),
 261         "xc7vx690t": ("ffg1157-1",
 262             ["AL33", None, "AN33", "AN34", "AK34", "AL34"],
 263             "LVCMOS18", Series7),
 264         "xc7vx980t": ("ffg1926-1",
 265             ["AK33", None, "AN34", "AN35", "AJ34", "AK34"],
 266             "LVCMOS18", Series7),
 267     }
 268
 269     def __init__(self, device, pins, std):
 270         cs_n, clk, mosi, miso = pins[:4]
 271         io = ["spiflash", 0,
 272               Subsignal("cs_n", Pins(cs_n)),
 273               Subsignal("mosi", Pins(mosi)),
 274               Subsignal("miso", Pins(miso), Misc("PULLUP")),
 275               IOStandard(std),
 276               ]
 277         if clk:
 278             io.append(Subsignal("clk", Pins(clk)))
 279         for i, p in enumerate(pins[4:]):
 280             io.append(Subsignal("pullup{}".format(i), Pins(p), Misc("PULLUP")))
 281
 282         XilinxPlatform.__init__(self, device, [io])
 283         if isinstance(self.toolchain, XilinxVivadoToolchain):
 284             self.toolchain.bitstream_commands.append(
 285                 "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]"
 286             )
 287         elif isinstance(self.toolchain, XilinxISEToolchain):
 288             self.toolchain.bitgen_opt += " -g compress"
 289
 290     @classmethod
 291     def make(cls, device, errors=False):
 292         pkg, pins, std, Top = cls.pinouts[device]
 293         platform = cls("{}-{}".format(device, pkg), pins, std)
 294         top = Top(platform)
 295         name = "bscan_spi_{}".format(device)
 296         dir = "build_{}".format(device)
 297         try:
 298             platform.build(top, build_name=name, build_dir=dir)
 299         except Exception as e:
 300             print("ERROR: build failed for {}: {}".format(device, e))
 301             if errors:
 302                 raise
 303
 304
 305 if __name__ == "__main__":
 306     import argparse
 307     import multiprocessing
 308     p = argparse.ArgumentParser(description="build bscan_spi bitstreams "
 309                                 "for openocd jtagspi flash driver")
 310     p.add_argument("device", nargs="*",
 311                    default=sorted(list(XilinxBscanSpi.pinouts)),
 312                    help="build for these devices (default: %(default)s)")
 313     p.add_argument("-p", "--parallel", default=1, type=int,
 314                    help="number of parallel builds (default: %(default)s)")
 315     args = p.parse_args()
 316     pool = multiprocessing.Pool(args.parallel)
 317     pool.map(XilinxBscanSpi.make, args.device, chunksize=1)