1 /***************************************************************************
2 * Copyright (C) 2011 by Andreas Fritiofson *
3 * andreas.fritiofson@gmail.com *
4 * Copyright (C) 2013 by Roman Dmitrienko *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
21 ***************************************************************************/
30 * r0 - flash base (in), status (out)
31 * r1 - count (word-32bit)
41 /* offsets of registers from flash reg base */
42 #define EFM32_MSC_WRITECTRL_OFFSET 0x008
43 #define EFM32_MSC_WRITECMD_OFFSET 0x00c
44 #define EFM32_MSC_ADDRB_OFFSET 0x010
45 #define EFM32_MSC_WDATA_OFFSET 0x018
46 #define EFM32_MSC_STATUS_OFFSET 0x01c
50 str r6, [r0, #EFM32_MSC_WRITECTRL_OFFSET]
53 ldr r6, [r2, #0] /* read wp */
54 cmp r6, #0 /* abort if wp == 0 */
56 ldr r5, [r2, #4] /* read rp */
57 cmp r5, r6 /* wait until rp != wp */
60 /* store address in MSC_ADDRB */
61 str r4, [r0, #EFM32_MSC_ADDRB_OFFSET]
64 str r6, [r0, #EFM32_MSC_WRITECMD_OFFSET]
65 /* check status for INVADDR and/or LOCKED */
66 ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET]
71 /* wait for WDATAREADY */
73 ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET]
78 /* load data to WDATA */
80 str r6, [r0, #EFM32_MSC_WDATA_OFFSET]
81 /* set WRITEONCE bit */
83 str r6, [r0, #EFM32_MSC_WRITECMD_OFFSET]
85 adds r5, #4 /* rp++ */
86 adds r4, #4 /* target_address++ */
88 /* wait until BUSY flag is reset */
90 ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET]
95 cmp r5, r3 /* wrap rp at end of buffer */
100 str r5, [r2, #4] /* store rp */
101 subs r1, r1, #1 /* decrement word count */
103 beq exit /* loop if not done */
107 str r0, [r2, #4] /* set rp = 0 on error */
109 mov r0, r6 /* return status in r0 */