1 /******************************************************************************
3 * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
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6 * modification, are permitted provided that the following conditions
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33 ******************************************************************************/
35 #ifndef OPENOCD_LOADERS_FLASH_CC26XX_HW_REGS_H
36 #define OPENOCD_LOADERS_FLASH_CC26XX_HW_REGS_H
38 /******************************************************************************
40 * Macros for direct hardware access.
42 * If using these macros the programmer should be aware of any limitations to
43 * the address accessed i.e. if it supports word and/or byte access.
45 ******************************************************************************/
46 /* Word (32 bit) access to address x */
47 /* Read example : my32BitVar = HWREG(base_addr + offset) ; */
48 /* Write example : HWREG(base_addr + offset) = my32BitVar ; */
49 #define HWREG(x) (*((volatile unsigned long *)(x)))
51 /* Half word (16 bit) access to address x */
52 /* Read example : my16BitVar = HWREGH(base_addr + offset) ; */
53 /* Write example : HWREGH(base_addr + offset) = my16BitVar ; */
54 #define HWREGH(x) (*((volatile unsigned short *)(x)))
56 /* Byte (8 bit) access to address x */
57 /* Read example : my8BitVar = HWREGB(base_addr + offset) ; */
58 /* Write example : HWREGB(base_addr + offset) = my8BitVar ; */
59 #define HWREGB(x) (*((volatile unsigned char *)(x)))
61 /******************************************************************************
63 * Macro for access to bit-band supported addresses via the bit-band region.
65 * Macro calculates the corresponding address to access in the bit-band region
66 * based on the actual address of the memory/register and the bit number.
68 * Do NOT use this macro to access the bit-band region directly!
70 ******************************************************************************/
71 /* Bit-band access to address x bit number b using word access (32 bit) */
72 #define HWREGBITW(x, b) \
73 HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
74 (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
76 /******************************************************************************
78 * Memory mapped components base address definitions
80 ******************************************************************************/
81 #define FLASH_BASE 0x40030000
82 #define FLASH_CFG_BASE 0x50000000
83 #define AON_PMCTL_BASE 0x40090000
85 /******************************************************************************
87 * This section defines the register offsets of FLASH component
89 ******************************************************************************/
91 /* FMC and Efuse Status */
92 #define FLASH_O_STAT 0x0000001C
95 #define FLASH_O_CFG 0x00000024
97 /* Flash Size Configuration */
98 #define FLASH_O_FLASH_SIZE 0x0000002C
101 #define FLASH_O_FWLOCK 0x0000003C
104 #define FLASH_O_FWFLAG 0x00000040
106 /* FMC Read Control */
107 #define FLASH_O_FRDCTL 0x00002000
109 /* FMC Bank Protection */
110 #define FLASH_O_FBPROT 0x00002030
112 /* FMC Bank Sector Enable */
113 #define FLASH_O_FBSE 0x00002034
115 /* FMC Module Access Control */
116 #define FLASH_O_FMAC 0x00002050
118 /* FMC Module Status */
119 #define FLASH_O_FMSTAT 0x00002054
122 #define FLASH_O_FLOCK 0x00002064
124 /* FMC VREADCT Trim */
125 #define FLASH_O_FVREADCT 0x00002080
127 /* FMC VHVCT1 Trim */
128 #define FLASH_O_FVHVCT1 0x00002084
130 /* FMC VHVCT2 Trim */
131 #define FLASH_O_FVHVCT2 0x00002088
134 #define FLASH_O_FVNVCT 0x00002090
137 #define FLASH_O_FVSLP 0x00002094
140 #define FLASH_O_FVWLCT 0x00002098
142 /* FMC Sequential Pump Information */
143 #define FLASH_O_FSEQPMP 0x000020A8
145 /* FMC FSM Command */
146 #define FLASH_O_FSM_CMD 0x0000220C
148 /* FMC FSM Program/Erase Operation Setup */
149 #define FLASH_O_FSM_PE_OSU 0x00002210
151 /* FMC FSM Voltage Status Setup */
152 #define FLASH_O_FSM_VSTAT 0x00002214
154 /* FMC FSM Program/Erase Verify Setup */
155 #define FLASH_O_FSM_PE_VSU 0x00002218
157 /* FMC FSM Compare Verify Setup */
158 #define FLASH_O_FSM_CMP_VSU 0x0000221C
160 /* FMC FSM EXECUTEZ to Valid Data */
161 #define FLASH_O_FSM_EX_VAL 0x00002220
163 /* FMC FSM Read Mode Hold */
164 #define FLASH_O_FSM_RD_H 0x00002224
166 /* FMC FSM Program Hold */
167 #define FLASH_O_FSM_P_OH 0x00002228
169 /* FMC FSM Erase Operation Hold */
170 #define FLASH_O_FSM_ERA_OH 0x0000222C
172 /* FMC FSM Program/Erase Verify Hold */
173 #define FLASH_O_FSM_PE_VH 0x00002234
175 /* FMC FSM Program Pulse Width */
176 #define FLASH_O_FSM_PRG_PW 0x00002240
178 /* FMC FSM Erase Pulse Width */
179 #define FLASH_O_FSM_ERA_PW 0x00002244
181 /* FMC FSM Maximum Programming Pulses */
182 #define FLASH_O_FSM_PRG_PUL 0x00002268
184 /* FMC FSM Maximum Erase Pulses */
185 #define FLASH_O_FSM_ERA_PUL 0x0000226C
187 /* FMC FSM EC Step Size */
188 #define FLASH_O_FSM_STEP_SIZE 0x00002270
190 /* FMC FSM EC Step Height */
191 #define FLASH_O_FSM_EC_STEP_HEIGHT 0x00002278
193 /* FMC FSM_ST_MACHINE */
194 #define FLASH_O_FSM_ST_MACHINE 0x0000227C
196 /* FMC FSM Register Write Enable */
197 #define FLASH_O_FSM_WR_ENA 0x00002288
199 /* FMC FSM Command Execute */
200 #define FLASH_O_FSM_EXECUTE 0x000022B4
202 /* FMC FSM Sector Erased 1 */
203 #define FLASH_O_FSM_SECTOR1 0x000022C0
205 /* FMC FSM Sector Erased 2 */
206 #define FLASH_O_FSM_SECTOR2 0x000022C4
208 /* FMC Flash Bank 0 Starting Address */
209 #define FLASH_O_FCFG_B0_START 0x00002410
211 /* FMC Flash Bank 0 Sector Size 0 */
212 #define FLASH_O_FCFG_B0_SSIZE0 0x00002430
214 /******************************************************************************
216 * Register: FLASH_O_STAT
218 ******************************************************************************/
219 /* Field: [2] SAMHOLD_DIS
221 * Status indicator of flash sample and hold sequencing logic. This bit will go
222 * to 1 some delay after CFG.DIS_IDLE is set to 1.
224 * 1: Sample and hold disabled and stable */
225 #define FLASH_STAT_SAMHOLD_DIS 0x00000004
229 * Fast version of the FMC FMSTAT.BUSY bit.
230 * This flag is valid immediately after the operation setting it (FMSTAT.BUSY
231 * is delayed some cycles)
234 #define FLASH_STAT_BUSY 0x00000002
236 /******************************************************************************
238 * Register: FLASH_O_CFG
240 ******************************************************************************/
241 /* Field: [8] STANDBY_MODE_SEL
243 * [Configured by boot firmware]
244 * STANDBY mode selection control. This bit, in conjunction with
245 * STANDBY_PW_SEL, determine which 1 of 4 sub-modes is selected for control of
246 * the behavior and timing of the STANDBY input to the pump.
248 * 0 : Legacy PG1 behavior is selected when STANDBY_PW_SEL = 00. This is
249 * referred to as sub-mode 1. When STANDBY_PW_SEL != 00, then sub-mode 2
250 * behavior is selected. STANDBY will be glitchy in these modes.
251 * 1 : STANDBY pulse-width counter modes selected. In these two modes (referred
252 * to as sub-mode 3 and sub-mode 4), the low time pulse width of the STANDBY
253 * signal to the pump, is controlled by a programmable timer. STANDBY will not
254 * be glitchy in these modes. */
255 #define FLASH_CFG_STANDBY_MODE_SEL_M 0x00000100
256 #define FLASH_CFG_STANDBY_MODE_SEL_S 8
258 /* Field: [7:6] STANDBY_PW_SEL
260 * [Configured by boot firmware]
261 * STANDBY pulse width counter selection control. These bits, in conjunction
262 * with STANDBY_MODE_SEL, determine which 1 of 4 sub-modes is selected for
263 * control of the behavior and timing of the STANDBY input to the pump.
265 * 00 : Legacy PG1 behavior is selected when STANDBY_MODE_SEL=0. Sub-mode 4 is
266 * selected when STANDBY_MODE_SEL=1. In sub-mode 4, STANDBY will be low for at
267 * least 9 pump clock cycles.
268 * 01 : Sub-mode 2 or 3 is selected, and STANDBY will be low for at least 9
270 * 10: Sub-mode 2 or 3 is selected, and STANDBY will be low for at least 5 pump
272 * 11: Sub-mode 2 or 3 is selected, and STANDBY will be low for at least 13
273 * pump clock cycles. */
274 #define FLASH_CFG_STANDBY_PW_SEL_M 0x000000C0
275 #define FLASH_CFG_STANDBY_PW_SEL_S 6
277 /* Field: [1] DIS_STANDBY
279 * [Configured by boot firmware]
280 * Disable standby functionality in read idle state */
281 #define FLASH_CFG_DIS_STANDBY 0x00000002
282 #define FLASH_CFG_DIS_STANDBY_BITN 1
283 #define FLASH_CFG_DIS_STANDBY_M 0x00000002
285 /* Field: [0] DIS_IDLE
287 * [Configured by boot firmware]
288 * Disable sample and hold functionality in read idle state */
289 #define FLASH_CFG_DIS_IDLE 0x00000001
290 #define FLASH_CFG_DIS_IDLE_M 0x00000001
291 #define FLASH_CFG_DIS_IDLE_S 0
293 /******************************************************************************
295 * Register: FLASH_O_FLASH_SIZE
297 ******************************************************************************/
298 /* Field: [7:0] SECTORS
300 * [Configured by boot firmware]
301 * Flash size. The number of flash sectors in the configured device. Read
302 * access to sectors equal to this number or higher will result in an error.
303 * The CCFG area is the sector (SECTORS - 1) Writing to this register is
304 * disabled by the CFG.CONFIGURED bit. */
305 #define FLASH_FLASH_SIZE_SECTORS_M 0x000000FF
306 #define FLASH_FLASH_SIZE_SECTORS_S 0
308 /******************************************************************************
310 * Register: FLASH_O_FRDCTL
312 ******************************************************************************/
313 /* Field: [11:8] RWAIT
315 * [Configured by boot firmware]
316 * FMC Wait State. This field determines the FLCLK period during FMC controlled
318 * - During power up/ power down / low power mode
319 * - During FSM operations like program, erase
320 * - During software interface mode (see FLOCK , FBSTROBES registers)
321 * FLCLK_period = HCLK_period X (RWAIT + 1),
322 * FSM state machine operations are usually twice this amount. This value
323 * should never be set less than 2. */
324 #define FLASH_FRDCTL_RWAIT_M 0x00000F00
325 #define FLASH_FRDCTL_RWAIT_S 8
327 /******************************************************************************
329 * Register: FLASH_O_FBPROT
331 ******************************************************************************/
332 /* Field: [0] PROTL1DIS
334 * Level 1 Protection Disable bit. Setting this bit disables protection from
335 * writing to the FBAC.OTPPROTDIS bits as well as the Sector Enable registers
336 * FBSE for all banks. Clearing this bit enables protection and disables write
337 * access to the FBAC.OTPPROTDIS register bits and FBSE register. */
338 #define FLASH_FBPROT_PROTL1DIS 0x00000001
340 /******************************************************************************
342 * Register: FLASH_O_FMSTAT
344 ******************************************************************************/
347 * Command Status. Once the FSM starts any failure will set this bit. When set,
348 * this bit informs the host that the program, erase, or validate sector
349 * command failed and the command was stopped. This bit is cleared by the
350 * Clear_Status command. For some errors, this will be the only indication of
351 * an FSM error because the cause does not fall within the other error bit
353 #define FLASH_FMSTAT_CSTAT 0x00000010
355 /******************************************************************************
357 * Register: FLASH_O_FVREADCT
359 ******************************************************************************/
360 /* Field: [3:0] VREADCT
362 * [Configured by boot firmware]
363 * These bits control the voltage level for the specified pump voltage of
364 * wordline power supply for read mode. */
365 #define FLASH_FVREADCT_VREADCT_M 0x0000000F
366 #define FLASH_FVREADCT_VREADCT_S 0
368 /******************************************************************************
370 * Register: FLASH_O_FVHVCT1
372 ******************************************************************************/
373 /* Field: [23:20] TRIM13_E
375 * [Configured by boot firmware]
376 * These bits control the voltage level for the specified pump voltage of high
377 * voltage supply input during erase operation. */
378 #define FLASH_FVHVCT1_TRIM13_E_M 0x00F00000
379 #define FLASH_FVHVCT1_TRIM13_E_S 20
381 /* Field: [19:16] VHVCT_E
383 * [Configured by boot firmware]
384 * These bits control the voltage level for the specified pump voltage of high
385 * voltage supply input during erase operation. */
386 #define FLASH_FVHVCT1_VHVCT_E_M 0x000F0000
387 #define FLASH_FVHVCT1_VHVCT_E_S 16
389 /* Field: [7:4] TRIM13_PV
391 * [Configured by boot firmware]
392 * These bits control the voltage level for the specified pump voltage of high
393 * voltage supply input during program verify operation. */
394 #define FLASH_FVHVCT1_TRIM13_PV_M 0x000000F0
395 #define FLASH_FVHVCT1_TRIM13_PV_S 4
397 /* Field: [3:0] VHVCT_PV
399 * [Configured by boot firmware]
400 * These bits control the voltage level for the specified pump voltage of high
401 * voltage supply input during program verify operation. */
402 #define FLASH_FVHVCT1_VHVCT_PV_M 0x0000000F
403 #define FLASH_FVHVCT1_VHVCT_PV_S 0
405 /******************************************************************************
407 * Register: FLASH_O_FVHVCT2
409 ******************************************************************************/
410 /* Field: [23:20] TRIM13_P
412 * [Configured by boot firmware]
413 * These bits control the voltage level for the specified pump voltage of high
414 * voltage supply input during program operation. */
415 #define FLASH_FVHVCT2_TRIM13_P_M 0x00F00000
416 #define FLASH_FVHVCT2_TRIM13_P_S 20
418 /* Field: [19:16] VHVCT_P
420 * [Configured by boot firmware]
421 * These bits control the voltage level for the specified pump voltage of high
422 * voltage supply input during program operation. */
423 #define FLASH_FVHVCT2_VHVCT_P_M 0x000F0000
424 #define FLASH_FVHVCT2_VHVCT_P_S 16
426 /******************************************************************************
428 * Register: FLASH_O_FVNVCT
430 ******************************************************************************/
431 /* Field: [12:8] VCG2P5CT
433 * [Configured by boot firmware]
434 * These bits control the voltage level for the VCG 2.5 CT pump voltage. */
435 #define FLASH_FVNVCT_VCG2P5CT_M 0x00001F00
436 #define FLASH_FVNVCT_VCG2P5CT_S 8
438 /******************************************************************************
440 * Register: FLASH_O_FVSLP
442 ******************************************************************************/
443 /* Field: [15:12] VSL_P
445 * [Configured by boot firmware]
446 * These bits control the voltage level for the specified pump voltage of high
447 * current power input during program operation. */
448 #define FLASH_FVSLP_VSL_P_M 0x0000F000
449 #define FLASH_FVSLP_VSL_P_S 12
451 /******************************************************************************
453 * Register: FLASH_O_FVWLCT
455 ******************************************************************************/
456 /* Field: [4:0] VWLCT_P
458 * [Configured by boot firmware]
459 * These bits control the voltage level for the specified pump voltage of
460 * wordline power supply during programming operations. */
461 #define FLASH_FVWLCT_VWLCT_P_M 0x0000001F
462 #define FLASH_FVWLCT_VWLCT_P_S 0
464 /******************************************************************************
466 * Register: FLASH_O_FSEQPMP
468 ******************************************************************************/
469 /* Field: [21:20] TRIM_1P7
471 * [Configured by boot firmware]
472 * This register goes directly to the pump's TRIM_1P7 port pins. */
473 #define FLASH_FSEQPMP_TRIM_1P7_M 0x00300000
474 #define FLASH_FSEQPMP_TRIM_1P7_S 20
476 /* Field: [14:12] VIN_AT_X
478 * This register controls to the pump's VIN_AT_XPX port pins with the following
481 * If VIN_BY_PASS=0 then pump VIN_AT_XPX is equal to VIN_AT_XIN input ports
482 * from the BATMON logic after clocking through synchronizers and the sequence
483 * checker FSM logic contained in the flash wrapper.
485 * If VIN_BY_PASS=1 and VIN_AT_X=???
487 * 0: then all pump VIN_AT_XPX signals are 0.
488 * 1: then pump VIN_AT_1P7 is set.
489 * 2: then pump VIN_AT_2P1 is also set.
490 * 3: then pump VIN_AT_2P4 is also set.
491 * 4-7: then pump VIN_AT_3P0 is also set (ie all VIN_AT_XPX signals are 1). */
492 #define FLASH_FSEQPMP_VIN_AT_X_M 0x00007000
493 #define FLASH_FSEQPMP_VIN_AT_X_S 12
495 /* Field: [8] VIN_BY_PASS
497 * [Configured by boot firmware]
499 * When this bit is a zero, the pump's VIN_AT_XPX ports comes from the FMC
500 * input port VIN_AT_XIN.
502 * When this bit is a one, the pump's VIN_AT_XPX ports comes from the VIN_AT_X
504 #define FLASH_FSEQPMP_VIN_BY_PASS 0x00000100
505 #define FLASH_FSEQPMP_VIN_BY_PASS_M 0x00000100
507 /******************************************************************************
509 * Register: FLASH_O_FSM_PE_OSU
511 ******************************************************************************/
512 /* Field: [15:8] PGM_OSU
514 * [Configured by boot firmware]
515 * Program Operation Setup time. This determines the flash clocks from the mode
516 * change to program, to the start of the program pulse. */
517 #define FLASH_FSM_PE_OSU_PGM_OSU_M 0x0000FF00
518 #define FLASH_FSM_PE_OSU_PGM_OSU_S 8
520 /* Field: [7:0] ERA_OSU
522 * [Configured by boot firmware]
523 * Erase Operation Setup time. This determines the flash clocks from the mode
524 * change to erase, to the start of the erase pulse. */
525 #define FLASH_FSM_PE_OSU_ERA_OSU_M 0x000000FF
526 #define FLASH_FSM_PE_OSU_ERA_OSU_S 0
528 /******************************************************************************
530 * Register: FLASH_O_FSM_VSTAT
532 ******************************************************************************/
533 /* Field: [15:12] VSTAT_CNT
535 * [Configured by boot firmware]
536 * Voltage Status Count. Gives the number of consecutive HCLK pulses that must
537 * be out of range before a voltage-out-of-range status error is given in
538 * FMSTAT.VOLSTAT. One pulse in range will reset the counter. This is mainly a
539 * glitch filter on the voltage status pump signal. */
540 #define FLASH_FSM_VSTAT_VSTAT_CNT_M 0x0000F000
541 #define FLASH_FSM_VSTAT_VSTAT_CNT_S 12
543 /******************************************************************************
545 * Register: FLASH_O_FSM_PE_VSU
547 ******************************************************************************/
548 /* Field: [15:8] PGM_VSU
550 * [Configured by boot firmware]
551 * Program Verify Setup time. This determines the flash clocks from the mode
552 * change to program verify, to the change of address and the beginning of the
553 * address setup time. */
554 #define FLASH_FSM_PE_VSU_PGM_VSU_M 0x0000FF00
555 #define FLASH_FSM_PE_VSU_PGM_VSU_S 8
557 /* Field: [7:0] ERA_VSU
559 * [Configured by boot firmware]
560 * Erase Verify Setup time. This determines the flash clocks from the mode
561 * change to erase verify, to the change of address and the beginning of the
562 * address setup time. */
563 #define FLASH_FSM_PE_VSU_ERA_VSU_M 0x000000FF
564 #define FLASH_FSM_PE_VSU_ERA_VSU_S 0
566 /******************************************************************************
568 * Register: FLASH_O_FSM_CMP_VSU
570 ******************************************************************************/
571 /* Field: [15:12] ADD_EXZ
573 * [Configured by boot firmware]
574 * Address to EXECUTEZ low setup time. This determines the flash clocks from
575 * the row address change to the time EXECUTEZ goes low. All operations use
577 #define FLASH_FSM_CMP_VSU_ADD_EXZ_M 0x0000F000
578 #define FLASH_FSM_CMP_VSU_ADD_EXZ_S 12
580 /******************************************************************************
582 * Register: FLASH_O_FSM_EX_VAL
584 ******************************************************************************/
585 /* Field: [15:8] REP_VSU
587 * [Configured by boot firmware]
588 * Repeat Verify action setup. If a program or erase operation advances to the
589 * program_verify or erase_verify then this special shorter mode transition
590 * time will be used in place of FSM_PE_VSU.PGM_VSU or FSM_PE_VSU.ERA_VSU
592 #define FLASH_FSM_EX_VAL_REP_VSU_M 0x0000FF00
593 #define FLASH_FSM_EX_VAL_REP_VSU_S 8
595 /* Field: [7:0] EXE_VALD
597 * [Configured by boot firmware]
598 * EXECUTEZ low to valid Data. Determines the number of Flash clock cycles from
599 * EXECUTEZ going low to the time the verify data can be read in the program
600 * verify mode. Erase and compact verify is always a constant value which is
601 * currently set at one flash clock. This value must be greater than 0. */
602 #define FLASH_FSM_EX_VAL_EXE_VALD_M 0x000000FF
603 #define FLASH_FSM_EX_VAL_EXE_VALD_S 0
605 /******************************************************************************
607 * Register: FLASH_O_FSM_RD_H
609 ******************************************************************************/
612 * [Configured by boot firmware]
613 * Read mode hold. This determines the number of flash clocks from the start of
614 * the Read mode at the end of the operations until the FSM clears the
615 * FMSTAT.BUSY. Writing a zero to this register will result in a value of 1.
616 * The reset value of this register is 0x3Ah before FMC version 3.0.10.0 and
617 * 0x5Ah after this version. */
618 #define FLASH_FSM_RD_H_RD_H_M 0x000000FF
619 #define FLASH_FSM_RD_H_RD_H_S 0
621 /******************************************************************************
623 * Register: FLASH_O_FSM_P_OH
625 ******************************************************************************/
626 /* Field: [15:8] PGM_OH
628 * [Configured by boot firmware]
629 * EXECUTEZ high to mode change. This value determines the flash clocks from
630 * the EXECUTEZ going high at the end of a program operation to the time the
631 * mode can change. This value must be greater than or equal to one. */
632 #define FLASH_FSM_P_OH_PGM_OH_M 0x0000FF00
633 #define FLASH_FSM_P_OH_PGM_OH_S 8
635 /******************************************************************************
637 * Register: FLASH_O_FSM_ERA_OH
639 ******************************************************************************/
640 /* Field: [15:0] ERA_OH
642 * [Configured by boot firmware]
643 * EXECUTEZ high to mode change. Determines the flash clocks from EXECUTEZ
644 * going high at the end of an erase operation to the time the mode can change.
645 * If a bank erase is happening, then this is the time to when the TEZ and TCR
646 * values for bank erase are released. The mode changes 10 flash clocks after
647 * they are released. This value must be greater than or equal to one. */
648 #define FLASH_FSM_ERA_OH_ERA_OH_M 0x0000FFFF
649 #define FLASH_FSM_ERA_OH_ERA_OH_S 0
651 /******************************************************************************
653 * Register: FLASH_O_FSM_PE_VH
655 ******************************************************************************/
656 /* Field: [15:8] PGM_VH
658 * [Configured by boot firmware]
659 * Program Verify Hold. This register determines the flash clocks from EXECUTEZ
660 * going high after a program verify to a mode change. This value must be
661 * greater than or equal to one */
662 #define FLASH_FSM_PE_VH_PGM_VH_M 0x0000FF00
663 #define FLASH_FSM_PE_VH_PGM_VH_S 8
665 /******************************************************************************
667 * Register: FLASH_O_FSM_PRG_PW
669 ******************************************************************************/
670 /* Field: [15:0] PROG_PUL_WIDTH
672 * [Configured by boot firmware]
673 * Program Pulse width.This register gives the number of flash clocks that the
674 * EXECUTEZ signal is low in a program operation. */
675 #define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_M 0x0000FFFF
676 #define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_S 0
678 /******************************************************************************
680 * Register: FLASH_O_FSM_ERA_PW
682 ******************************************************************************/
683 /* Field: [31:0] FSM_ERA_PW
685 * [Configured by boot firmware]
686 * Erase Pulse width. This register gives the number flash clocks that the
687 * EXECUTEZ signal is low in an erase operation. */
688 #define FLASH_FSM_ERA_PW_FSM_ERA_PW_M 0xFFFFFFFF
689 #define FLASH_FSM_ERA_PW_FSM_ERA_PW_S 0
691 /******************************************************************************
693 * Register: FLASH_O_FSM_PRG_PUL
695 ******************************************************************************/
696 /* Field: [19:16] BEG_EC_LEVEL
698 * [Configured by boot firmware]
699 * Beginning level for VHVCT. This determines the beginning level for VHVCT
700 * that is used during erase modes. The pump voltage control registers supply
701 * the other values that do not change during FSM operations. The reset value
702 * is the same as FVHVCT1.VHVCT_E. */
703 #define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_M 0x000F0000
704 #define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_S 16
706 /* Field: [11:0] MAX_PRG_PUL
708 * [Configured by boot firmware]
709 * Maximum Programming Pulses. This register contains the maximum number of
710 * programming pulses allowed at one address. If it takes any more than this
711 * amount during a programming operation then the FSM will exit with an error
712 * and with the program violation, FMSTAT.PGV set, and the general error set,
713 * FMSTAT.CSTAT. Setting FSM_ST_MACHINE.OVERRIDE to 0 will allow more than this
714 * maximum value to occur without an error. During pre-conditioning for an
715 * erase operation the FSM programs all the bits to zero. If the maximum number
716 * of programming pulses is reached for an address, the FSM will continue with
717 * the next address and set the FMSTAT.PCV and the general error FMSTAT.CSTAT.
718 * If the FSM_ST_MACHINE.PREC_STOP_EN is set then the FSM will stop with errors
719 * when more than the maximum number of pulses is needed. The
720 * FSM_ST_MACHINE.OVERRIDE bit will take priority over the
721 * FSM_ST_MACHINE.PREC_STOP_EN and continue doing pulses without setting the
722 * error bits. Suspend operations will count a pulse if the program operation
723 * began no matter how long the pulse lasted before is was suspended. Frequent
724 * suspend or auto-suspend operations could result in max_pulse count error. */
725 #define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_M 0x00000FFF
726 #define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_S 0
728 /******************************************************************************
730 * Register: FLASH_O_FSM_ERA_PUL
732 ******************************************************************************/
733 /* Field: [19:16] MAX_EC_LEVEL
735 * [Configured by boot firmware]
736 * Maximum VHVCT Level. This determines the maximum level for VHVCT that is
737 * used during erase modes. The FSM will stop advancing VHVCT once it counts up
738 * to the MAX_EC_LEVEL level from the beginning level. The MAX_EC_LEVEL +
739 * FSM_EC_STEP_HEIGHT.EC_STEP_HEIGHT must be less than 0x200. The reset value
740 * is the same as FVHVCT1.VHVCT_E. */
741 #define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_M 0x000F0000
742 #define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_S 16
744 /* Field: [11:0] MAX_ERA_PUL
746 * [Configured by boot firmware]
747 * Maximum Erase Pulses. This register contains the maximum number of erase
748 * pulses allowed at one address. If it takes any more than this amount the FSM
749 * will exit with an error and with both the FMSTAT.EV and FMSTAT.CSTAT bits
750 * set. Setting FSM_ST_MACHINE.OVERRIDE to 1 will allow more than this maximum
751 * value to occur without an error. Suspend operations will count a pulse if
752 * the erase operation began no matter how long the pulse lasted before is was
753 * suspended. Frequent suspend or auto-suspend operations could result in
754 * max_pulse count error. */
755 #define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_M 0x00000FFF
756 #define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_S 0
758 /******************************************************************************
760 * Register: FLASH_O_FSM_STEP_SIZE
762 ******************************************************************************/
763 /* Field: [24:16] EC_STEP_SIZE
765 * [Configured by boot firmware]
766 * VHVCT Step Size. This is the number of erase pulses that must be completed
767 * for each level before the FSM increments the FSM_PUL_CNTR.CUR_EC_LEVEL to
768 * the next higher level. Actual erase pulses per level equals (EC_STEP_SIZE
769 * +1). The stepping is only needed for the VHVCT voltage. */
770 #define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_M 0x01FF0000
771 #define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_S 16
773 /******************************************************************************
775 * Register: FLASH_O_FSM_EC_STEP_HEIGHT
777 ******************************************************************************/
778 /* Field: [3:0] EC_STEP_HEIGHT
780 * [Configured by boot firmware]
781 * Height of each EC step. This is the number of counts that the
782 * FSM_PUL_CNTR.CUR_EC_LEVEL will increment when going to a new level. Actual
783 * count size equals (EC_STEP_HEIGHT + 1). The stepping applies only to the
784 * VHVCT voltage. If adding the height to the FSM_PUL_CNTR.CUR_EC_LEVEL results
785 * in a value higher than the FSM_ERA_PUL.MAX_EC_LEVEL then the
786 * FSM_PUL_CNTR.CUR_EC_LEVEL will be lowered to the MAX LEVEL before it is used
787 * in the next erase pulse. */
788 #define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_M 0x0000000F
790 /******************************************************************************
792 * Register: FLASH_O_FSM_ST_MACHINE
794 ******************************************************************************/
795 /* Field: [23] DO_PRECOND
797 * [Configured by boot firmware]
798 * Do preconditioning. When this bit is a one, the FSM will precondition the
799 * sector or bank before doing an erase operation. When zero, the FSM will just
800 * begin with the erase verify and skip the preconditioning. */
801 #define FLASH_FSM_ST_MACHINE_DO_PRECOND 0x00800000
802 #define FLASH_FSM_ST_MACHINE_DO_PRECOND_M 0x00800000
803 #define FLASH_FSM_ST_MACHINE_DO_PRECOND_S 23
805 /* Field: [14] ONE_TIME_GOOD
807 * [Configured by boot firmware]
808 * One Time Good function. If this bit is a one then the 'One Time Good'
809 * function is enabled for all program operations. This includes operations
810 * inside the erase functions and other functions. When zero, this function is
811 * disabled for all modes. When doing the One Time Good function, the FSM will
812 * attempt to program a location with data. If a desired zero bit reads back
813 * from the flash one time as good then that bit is blocked from writing a zero
814 * to the flash array again for this address. When the address changes, all
815 * bits are unblocked. This prevents a bit from reading 0 in one programming
816 * pulse and then 1 in the next programming pulse. On the second time the bit
817 * would get a programming pulse even though it read 0 in an earlier read. If
818 * this bit is a zero then the zero bits will be masked for each program verify
819 * operation. It is recommended for this bit to be set to 1. */
820 #define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD 0x00004000
822 /******************************************************************************
824 * Register: FLASH_O_FCFG_B0_SSIZE0
826 ******************************************************************************/
827 /* Field: [3:0] B0_SECT_SIZE
829 * Size of sectors in Bank 0. Common sector size for all sectors in the bank in
830 * 1K bytes multiples.
832 * 0x1: 1K bytes(FLES)
834 * 0x4: 4K bytes (FLEE)
837 #define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_M 0x0000000F
838 #define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_S 0
840 /******************************************************************************
842 * This section defines the register offsets of FCFG1 component
844 ******************************************************************************/
846 /* Flash Erase and Program Setup Time */
847 #define FCFG1_O_FLASH_E_P 0x00000170
849 /* Flash Compaction, Execute, Program and Read */
850 #define FCFG1_O_FLASH_C_E_P_R 0x00000174
852 /* Flash Program, Read, and Program Verify */
853 #define FCFG1_O_FLASH_P_R_PV 0x00000178
855 /* Flash Erase Hold and Sequence */
856 #define FCFG1_O_FLASH_EH_SEQ 0x0000017C
858 /* Flash VHV Erase */
859 #define FCFG1_O_FLASH_VHV_E 0x00000180
861 /* Flash Program Pulse */
862 #define FCFG1_O_FLASH_PP 0x00000184
864 /* Flash Program and Erase Pulse */
865 #define FCFG1_O_FLASH_PROG_EP 0x00000188
867 /* Flash Erase Pulse Width */
868 #define FCFG1_O_FLASH_ERA_PW 0x0000018C
871 #define FCFG1_O_FLASH_VHV 0x00000190
873 /* Flash VHV Program Verify */
874 #define FCFG1_O_FLASH_VHV_PV 0x00000194
877 #define FCFG1_O_FLASH_V 0x00000198
879 /* Flash OTP Data 3 */
880 #define FCFG1_O_FLASH_OTP_DATA3 0x000002B0
882 /* Flash OTP Data 4 */
883 #define FCFG1_O_FLASH_OTP_DATA4 0x00000308
885 /******************************************************************************
887 * Register: FCFG1_O_FLASH_E_P
889 ******************************************************************************/
890 /* Field: [31:24] PSU
892 * Program setup time in cycles. Value will be written to
893 * FLASH:FSM_PE_OSU.PGM_OSU by the flash device driver when an erase/program
894 * operation is initiated. */
895 #define FCFG1_FLASH_E_P_PSU_M 0xFF000000
896 #define FCFG1_FLASH_E_P_PSU_S 24
898 /* Field: [23:16] ESU
900 * Erase setup time in cycles. Value will be written to
901 * FLASH:FSM_PE_OSU.ERA_OSU by the flash device driver when an erase/program
902 * operation is initiated. */
903 #define FCFG1_FLASH_E_P_ESU_M 0x00FF0000
904 #define FCFG1_FLASH_E_P_ESU_S 16
906 /* Field: [15:8] PVSU
908 * Program verify setup time in cycles. Value will be written to
909 * FLASH:FSM_PE_VSU.PGM_VSU by the flash device driver when an erase/program
910 * operation is initiated. */
911 #define FCFG1_FLASH_E_P_PVSU_M 0x0000FF00
912 #define FCFG1_FLASH_E_P_PVSU_S 8
916 * Erase verify setup time in cycles. Value will be written to
917 * FLASH:FSM_PE_VSU.ERA_VSU by the flash device driver when an erase/program
918 * operation is initiated. */
919 #define FCFG1_FLASH_E_P_EVSU_M 0x000000FF
920 #define FCFG1_FLASH_E_P_EVSU_S 0
922 /******************************************************************************
924 * Register: FCFG1_O_FLASH_C_E_P_R
926 ******************************************************************************/
927 /* Field: [31:24] RVSU
929 * Repeat verify setup time in cycles. Used for repeated verifies during
930 * program and erase. Value will be written to FLASH:FSM_EX_VAL.REP_VSU by the
931 * flash device driver when an erase/program operation is initiated. */
932 #define FCFG1_FLASH_C_E_P_R_RVSU_M 0xFF000000
933 #define FCFG1_FLASH_C_E_P_R_RVSU_S 24
935 /* Field: [23:16] PV_ACCESS
937 * Program verify EXECUTEZ->data valid time in half-microseconds. Value
938 * will be converted to number of FCLK cycles by by flash device driver and the
939 * converted value is written to FLASH:FSM_EX_VAL.EXE_VALD when an
940 * erase/program operation is initiated. */
941 #define FCFG1_FLASH_C_E_P_R_PV_ACCESS_M 0x00FF0000
942 #define FCFG1_FLASH_C_E_P_R_PV_ACCESS_S 16
944 /* Field: [15:12] A_EXEZ_SETUP
946 * Address->EXECUTEZ setup time in cycles. Value will be written to
947 * FLASH:FSM_CMP_VSU.ADD_EXZ by the flash device driver when an erase/program
948 * operation is initiated. */
949 #define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_M 0x0000F000
950 #define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_S 12
952 /******************************************************************************
954 * Register: FCFG1_O_FLASH_P_R_PV
956 ******************************************************************************/
959 * Program hold time in half-microseconds after SAFELV goes high. Value will be
960 * converted to number of FCLK cycles by the flash device driver and the
961 * converted value is written to FLASH:FSM_P_OH.PGM_OH when an erase/program
962 * operation is initiated. */
963 #define FCFG1_FLASH_P_R_PV_PH_M 0xFF000000
964 #define FCFG1_FLASH_P_R_PV_PH_S 24
968 * Read hold/mode transition time in cycles. Value will be written to the RD_H
969 * field bits[7:0] of the FSM_RD_H register in the flash module by the flash
970 * device driver when an erase/program operation is initiated. */
971 #define FCFG1_FLASH_P_R_PV_RH_M 0x00FF0000
972 #define FCFG1_FLASH_P_R_PV_RH_S 16
976 * Program verify hold time in half-microseconds after SAFELV goes high. Value
977 * will be converted to number of FCLK cycles by the flash device driver and
978 * the converted value is written to FLASH:FSM_PE_VH.PGM_VH when an
979 * erase/program operation is initiated. */
980 #define FCFG1_FLASH_P_R_PV_PVH_M 0x0000FF00
981 #define FCFG1_FLASH_P_R_PV_PVH_S 8
983 /******************************************************************************
985 * Register: FCFG1_O_FLASH_EH_SEQ
987 ******************************************************************************/
990 * Erase hold time in half-microseconds after SAFELV goes high. Value will be
991 * converted to number of FCLK cycles by the flash device driver and the
992 * converted value is written to FLASH:FSM_ERA_OH.ERA_OH when an erase/program
993 * operation is initiated. */
994 #define FCFG1_FLASH_EH_SEQ_EH_M 0xFF000000
995 #define FCFG1_FLASH_EH_SEQ_EH_S 24
997 /* Field: [15:12] VSTAT
999 * Max number of HCLK cycles allowed for pump brown-out. Value will be written
1000 * to FLASH:FSM_VSTAT.VSTAT_CNT when an erase/program operation is initiated. */
1001 #define FCFG1_FLASH_EH_SEQ_VSTAT_M 0x0000F000
1002 #define FCFG1_FLASH_EH_SEQ_VSTAT_S 12
1004 /******************************************************************************
1006 * Register: FCFG1_O_FLASH_VHV_E
1008 ******************************************************************************/
1009 /* Field: [31:16] VHV_E_START
1011 * Starting VHV-Erase CT for stairstep erase. Value will be written to
1012 * FLASH:FSM_PRG_PUL.BEG_EC_LEVEL when erase/program operation is initiated. */
1013 #define FCFG1_FLASH_VHV_E_VHV_E_START_M 0xFFFF0000
1014 #define FCFG1_FLASH_VHV_E_VHV_E_START_S 16
1016 /* Field: [15:0] VHV_E_STEP_HIGHT
1018 * Number of VHV CTs to step after each erase pulse (up to the max). The actual
1019 * FMC register value should be one less than this since the FMC starts
1020 * counting from zero. Value will be written to
1021 * FLASH:FSM_EC_STEP_HEIGHT.EC_STEP_HEIGHT when an erase/program operation is
1023 #define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_M 0x0000FFFF
1024 #define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_S 0
1026 /******************************************************************************
1028 * Register: FCFG1_O_FLASH_PP
1030 ******************************************************************************/
1031 /* Field: [15:0] MAX_PP
1033 * Max program pulse limit per program operation. Value will be written to
1034 * FLASH:FSM_PRG_PUL.MAX_PRG_PUL when an erase/program operation is initiated. */
1035 #define FCFG1_FLASH_PP_MAX_PP_M 0x0000FFFF
1036 #define FCFG1_FLASH_PP_MAX_PP_S 0
1038 /******************************************************************************
1040 * Register: FCFG1_O_FLASH_PROG_EP
1042 ******************************************************************************/
1043 /* Field: [31:16] MAX_EP
1045 * Max erase pulse limit per erase operation. Value will be written to
1046 * FLASH:FSM_ERA_PUL.MAX_ERA_PUL when an erase/program operation is initiated. */
1047 #define FCFG1_FLASH_PROG_EP_MAX_EP_M 0xFFFF0000
1048 #define FCFG1_FLASH_PROG_EP_MAX_EP_S 16
1050 /* Field: [15:0] PROGRAM_PW
1052 * Program pulse width in half-microseconds. Value will be converted to number
1053 * of FCLK cycles by the flash device driver and the converted value is written
1054 * to FLASH:FSM_PRG_PW.PROG_PUL_WIDTH when a erase/program operation is
1056 #define FCFG1_FLASH_PROG_EP_PROGRAM_PW_M 0x0000FFFF
1057 #define FCFG1_FLASH_PROG_EP_PROGRAM_PW_S 0
1059 /******************************************************************************
1061 * Register: FCFG1_O_FLASH_ERA_PW
1063 ******************************************************************************/
1064 /* Field: [31:0] ERASE_PW
1066 * Erase pulse width in half-microseconds. Value will be converted to number of
1067 * FCLK cycles by the flash device driver and the converted value is written to
1068 * FLASH:FSM_ERA_PW.FSM_ERA_PW when a erase/program operation is initiated. */
1069 #define FCFG1_FLASH_ERA_PW_ERASE_PW_M 0xFFFFFFFF
1070 #define FCFG1_FLASH_ERA_PW_ERASE_PW_S 0
1072 /******************************************************************************
1074 * Register: FCFG1_O_FLASH_VHV
1076 ******************************************************************************/
1077 /* Field: [27:24] TRIM13_P
1079 * Value will be written to FLASH:FVHVCT2.TRIM13_P by the flash device driver
1080 * when an erase/program operation is initiated. */
1081 #define FCFG1_FLASH_VHV_TRIM13_P_M 0x0F000000
1082 #define FCFG1_FLASH_VHV_TRIM13_P_S 24
1084 /* Field: [19:16] VHV_P
1086 * Value will be written to FLASH:FVHVCT2.VHVCT_P by the flash device driver
1087 * when an erase/program operation is initiated. */
1088 #define FCFG1_FLASH_VHV_VHV_P_M 0x000F0000
1089 #define FCFG1_FLASH_VHV_VHV_P_S 16
1091 /* Field: [11:8] TRIM13_E
1093 * Value will be written to FLASH:FVHVCT1.TRIM13_E by the flash device driver
1094 * when an erase/program operation is initiated. */
1095 #define FCFG1_FLASH_VHV_TRIM13_E_M 0x00000F00
1096 #define FCFG1_FLASH_VHV_TRIM13_E_S 8
1098 /* Field: [3:0] VHV_E
1100 * Value will be written to FLASH:FVHVCT1.VHVCT_E by the flash device driver
1101 * when an erase/program operation is initiated */
1102 #define FCFG1_FLASH_VHV_VHV_E_M 0x0000000F
1103 #define FCFG1_FLASH_VHV_VHV_E_S 0
1105 /******************************************************************************
1107 * Register: FCFG1_O_FLASH_VHV_PV
1109 ******************************************************************************/
1110 /* Field: [27:24] TRIM13_PV
1112 * Value will be written to FLASH:FVHVCT1.TRIM13_PV by the flash device driver
1113 * when an erase/program operation is initiated. */
1114 #define FCFG1_FLASH_VHV_PV_TRIM13_PV_M 0x0F000000
1115 #define FCFG1_FLASH_VHV_PV_TRIM13_PV_S 24
1117 /* Field: [19:16] VHV_PV
1119 * Value will be written to FLASH:FVHVCT1.VHVCT_PV by the flash device driver
1120 * when an erase/program operation is initiated. */
1121 #define FCFG1_FLASH_VHV_PV_VHV_PV_M 0x000F0000
1122 #define FCFG1_FLASH_VHV_PV_VHV_PV_S 16
1124 /* Field: [15:8] VCG2P5
1126 * Control gate voltage during read, read margin, and erase verify. Value will
1127 * be written to FLASH:FVNVCT.VCG2P5CT by the flash device driver when an
1128 * erase/program operation is initiated. */
1129 #define FCFG1_FLASH_VHV_PV_VCG2P5_M 0x0000FF00
1130 #define FCFG1_FLASH_VHV_PV_VCG2P5_S 8
1132 /******************************************************************************
1134 * Register: FCFG1_O_FLASH_V
1136 ******************************************************************************/
1137 /* Field: [31:24] VSL_P
1139 * Sourceline voltage applied to the selected block during programming. Value
1140 * will be written to FLASH:FVSLP.VSL_P by the flash device driver when an
1141 * erase/program operation is initiated. */
1142 #define FCFG1_FLASH_V_VSL_P_M 0xFF000000
1143 #define FCFG1_FLASH_V_VSL_P_S 24
1145 /* Field: [23:16] VWL_P
1147 * Wordline voltage applied to the selected half-row during programming. Value
1148 * will be written to FLASH:FVWLCT.VWLCT_P by the flash device driver when an
1149 * erase/program operation is initiated. */
1150 #define FCFG1_FLASH_V_VWL_P_M 0x00FF0000
1151 #define FCFG1_FLASH_V_VWL_P_S 16
1153 /* Field: [15:8] V_READ
1155 * Wordline voltage applied to the selected block during reads and verifies.
1156 * Value will be written to FLASH:FVREADCT.VREADCT by the flash device driver
1157 * when an erase/program operation is initiated. */
1158 #define FCFG1_FLASH_V_V_READ_M 0x0000FF00
1159 #define FCFG1_FLASH_V_V_READ_S 8
1161 /******************************************************************************
1163 * Register: FCFG1_O_FLASH_OTP_DATA3
1165 ******************************************************************************/
1166 /* Field: [31:23] EC_STEP_SIZE
1168 * Value will be written to FLASH:FSM_STEP_SIZE.EC_STEP_SIZE by the flash
1169 * device driver when a erase/program operation is initiated. */
1170 #define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_M 0xFF800000
1171 #define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_S 23
1173 /* Field: [22] DO_PRECOND
1175 * Value will be written to FLASH:FSM_ST_MACHINE.DO_PRECOND by the flash device
1176 * driver when a erase/program operation is initiated.
1178 * Note that during a Total Erase operation the flash bank will always be
1179 * erased with Precondition enabled independent of the value of this FCFG1 bit
1181 #define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_M 0x00400000
1182 #define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_S 22
1184 /* Field: [21:18] MAX_EC_LEVEL
1186 * Value will be written to FLASH:FSM_ERA_PUL.MAX_EC_LEVEL by the flash device
1187 * driver when a erase/program operation is initiated. */
1188 #define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_M 0x003C0000
1189 #define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_S 18
1191 /* Field: [17:16] TRIM_1P7
1193 * Value will be written to FLASH:FSEQPMP.TRIM_1P7 by the flash device driver
1194 * when a erase/program operation is initiated. */
1195 #define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_M 0x00030000
1196 #define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_S 16
1198 /******************************************************************************
1200 * Register: FCFG1_O_FLASH_OTP_DATA4
1202 ******************************************************************************/
1203 /* Field: [31] STANDBY_MODE_SEL_INT_WRT
1205 * If AON_PMCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to
1206 * FLASH:CFG.STANDBY_MODE_SEL by flash device driver FW when a flash write
1207 * operation is initiated. */
1208 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_M 0x80000000
1209 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_S 31
1211 /* Field: [30:29] STANDBY_PW_SEL_INT_WRT
1213 * If AON_PMCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to
1214 * FLASH:CFG.STANDBY_PW_SEL by flash device driver FW when a flash write
1215 * operation is initiated. */
1216 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_M 0x60000000
1217 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_S 29
1219 /* Field: [28] DIS_STANDBY_INT_WRT
1221 * If AON_PMCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to
1222 * FLASH:CFG.DIS_STANDBY by flash device driver FW when a flash write operation
1224 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_M 0x10000000
1226 /* Field: [27] DIS_IDLE_INT_WRT
1228 * If AON_PMCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to
1229 * FLASH:CFG.DIS_IDLE by flash device driver FW when a flash write operation is
1231 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_M 0x08000000
1232 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_S 27
1234 /* Field: [26:24] VIN_AT_X_INT_WRT
1236 * If AON_PMCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to
1237 * FLASH:FSEQPMP.VIN_AT_X by flash device driver FW when a flash write
1238 * operation is initiated. */
1239 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_M 0x07000000
1240 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_S 24
1242 /* Field: [23] STANDBY_MODE_SEL_EXT_WRT
1244 * If AON_PMCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to
1245 * FLASH:CFG.STANDBY_MODE_SEL by flash device driver FW when a flash write
1246 * operation is initiated. */
1247 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_M 0x00800000
1248 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_S 23
1250 /* Field: [22:21] STANDBY_PW_SEL_EXT_WRT
1252 * If AON_PMCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to
1253 * FLASH:CFG.STANDBY_PW_SEL by flash device driver FW when a flash write
1254 * operation is initiated. */
1255 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_M 0x00600000
1256 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_S 21
1258 /* Field: [20] DIS_STANDBY_EXT_WRT
1260 * If AON_PMCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to
1261 * FLASH:CFG.DIS_STANDBY by flash device driver FW when a flash write operation
1263 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_M 0x00100000
1265 /* Field: [19] DIS_IDLE_EXT_WRT
1267 * If AON_PMCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to
1268 * FLASH:CFG.DIS_IDLE by flash device driver FW when a flash write operation is
1270 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_M 0x00080000
1271 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_S 19
1273 /* Field: [18:16] VIN_AT_X_EXT_WRT
1275 * If AON_PMCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to
1276 * FLASH:FSEQPMP.VIN_AT_X by flash device driver FW when a flash write
1277 * operation is initiated. */
1278 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_M 0x00070000
1279 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_S 16
1281 /* Field: [15] STANDBY_MODE_SEL_INT_RD
1283 * If AON_PMCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to
1284 * FLASH:CFG.STANDBY_MODE_SEL both by boot FW while in safezone, and by flash
1285 * device driver FW after completion of a flash write operation. */
1286 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M 0x00008000
1287 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S 15
1289 /* Field: [14:13] STANDBY_PW_SEL_INT_RD
1291 * If AON_PMCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to
1292 * FLASH:CFG.STANDBY_PW_SEL both by boot FW while in safezone, and by flash
1293 * device driver FW after completion of a flash write operation. */
1294 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M 0x00006000
1295 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S 13
1297 /* Field: [12] DIS_STANDBY_INT_RD
1299 * If AON_PMCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to
1300 * FLASH:CFG.DIS_STANDBY both by boot FW while in safezone, and by flash device
1301 * driver FW after completion of a flash write operation. */
1302 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M 0x00001000
1304 /* Field: [11] DIS_IDLE_INT_RD
1306 * If AON_PMCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to
1307 * FLASH:CFG.DIS_IDLE both by boot FW while in safezone, and by flash device
1308 * driver FW after completion of a flash write operation. */
1309 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_M 0x00000800
1310 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_S 11
1312 /* Field: [10:8] VIN_AT_X_INT_RD
1314 * If AON_PMCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to
1315 * FLASH:FSEQPMP.VIN_AT_X both by boot FW while in safezone, and by flash
1316 * device driver FW after completion of a flash write operation. */
1317 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M 0x00000700
1318 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S 8
1320 /* Field: [7] STANDBY_MODE_SEL_EXT_RD
1322 * If AON_PMCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to
1323 * FLASH:CFG.STANDBY_MODE_SEL both by boot FW while in safezone, and by flash
1324 * device driver FW after completion of a flash write operation. */
1325 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M 0x00000080
1326 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S 7
1328 /* Field: [6:5] STANDBY_PW_SEL_EXT_RD
1330 * If AON_PMCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to
1331 * FLASH:CFG.STANDBY_PW_SEL both by boot FW while in safezone, and by flash
1332 * device driver FW after completion of a flash write operation. */
1333 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M 0x00000060
1334 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S 5
1336 /* Field: [4] DIS_STANDBY_EXT_RD
1338 * If AON_PMCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to
1339 * FLASH:CFG.DIS_STANDBY both by boot FW while in safezone, and by flash device
1340 * driver FW after completion of a flash write operation. */
1341 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M 0x00000010
1343 /* Field: [3] DIS_IDLE_EXT_RD
1345 * If AON_PMCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to
1346 * FLASH:CFG.DIS_IDLE both by boot FW while in safezone, and by flash device
1347 * driver FW after completion of a flash write operation. */
1348 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_M 0x00000008
1349 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_S 3
1351 /* Field: [2:0] VIN_AT_X_EXT_RD
1353 * If AON_PMCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to
1354 * FLASH:FSEQPMP.VIN_AT_X both by boot FW while in safezone, and by flash
1355 * device driver FW after completion of a flash write operation. */
1356 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M 0x00000007
1357 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S 0
1359 /******************************************************************************
1361 * This section defines the register offsets of AON_PMCTL component
1363 ******************************************************************************/
1365 /* Power Management Control */
1366 #if defined(DEVICE_CC26X2)
1367 /* Agama (CC26x2) specific definition */
1368 #define AON_PMCTL_O_PWRCTL 0x00000010
1369 #elif defined(DEVICE_CC26X0)
1370 /* Chameleon (CC26x0) specific definition */
1371 #define AON_PMCTL_O_PWRCTL 0x00000000
1374 /* Field: [1] EXT_REG_MODE
1376 * Status of source for VDDRsupply:
1378 * 0: DCDC or GLDO are generating VDDR
1379 * 1: DCDC and GLDO are bypassed and an external regulator supplies VDDR */
1380 #define AON_PMCTL_PWRCTL_EXT_REG_MODE 0x00000002
1382 #endif /* #ifndef OPENOCD_LOADERS_FLASH_CC26XX_HW_REGS_H */