1 /* SPDX-License-Identifier: BSD-3-Clause */
3 /******************************************************************************
5 * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
7 ******************************************************************************/
9 #ifndef OPENOCD_LOADERS_FLASH_CC26XX_HW_REGS_H
10 #define OPENOCD_LOADERS_FLASH_CC26XX_HW_REGS_H
12 /******************************************************************************
14 * Macros for direct hardware access.
16 * If using these macros the programmer should be aware of any limitations to
17 * the address accessed i.e. if it supports word and/or byte access.
19 ******************************************************************************/
20 /* Word (32 bit) access to address x */
21 /* Read example : my32BitVar = HWREG(base_addr + offset) ; */
22 /* Write example : HWREG(base_addr + offset) = my32BitVar ; */
23 #define HWREG(x) (*((volatile unsigned long *)(x)))
25 /* Half word (16 bit) access to address x */
26 /* Read example : my16BitVar = HWREGH(base_addr + offset) ; */
27 /* Write example : HWREGH(base_addr + offset) = my16BitVar ; */
28 #define HWREGH(x) (*((volatile unsigned short *)(x)))
30 /* Byte (8 bit) access to address x */
31 /* Read example : my8BitVar = HWREGB(base_addr + offset) ; */
32 /* Write example : HWREGB(base_addr + offset) = my8BitVar ; */
33 #define HWREGB(x) (*((volatile unsigned char *)(x)))
35 /******************************************************************************
37 * Macro for access to bit-band supported addresses via the bit-band region.
39 * Macro calculates the corresponding address to access in the bit-band region
40 * based on the actual address of the memory/register and the bit number.
42 * Do NOT use this macro to access the bit-band region directly!
44 ******************************************************************************/
45 /* Bit-band access to address x bit number b using word access (32 bit) */
46 #define HWREGBITW(x, b) \
47 HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
48 (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
50 /******************************************************************************
52 * Memory mapped components base address definitions
54 ******************************************************************************/
55 #define FLASH_BASE 0x40030000
56 #define FLASH_CFG_BASE 0x50000000
57 #define AON_PMCTL_BASE 0x40090000
59 /******************************************************************************
61 * This section defines the register offsets of FLASH component
63 ******************************************************************************/
65 /* FMC and Efuse Status */
66 #define FLASH_O_STAT 0x0000001C
69 #define FLASH_O_CFG 0x00000024
71 /* Flash Size Configuration */
72 #define FLASH_O_FLASH_SIZE 0x0000002C
75 #define FLASH_O_FWLOCK 0x0000003C
78 #define FLASH_O_FWFLAG 0x00000040
80 /* FMC Read Control */
81 #define FLASH_O_FRDCTL 0x00002000
83 /* FMC Bank Protection */
84 #define FLASH_O_FBPROT 0x00002030
86 /* FMC Bank Sector Enable */
87 #define FLASH_O_FBSE 0x00002034
89 /* FMC Module Access Control */
90 #define FLASH_O_FMAC 0x00002050
92 /* FMC Module Status */
93 #define FLASH_O_FMSTAT 0x00002054
96 #define FLASH_O_FLOCK 0x00002064
98 /* FMC VREADCT Trim */
99 #define FLASH_O_FVREADCT 0x00002080
101 /* FMC VHVCT1 Trim */
102 #define FLASH_O_FVHVCT1 0x00002084
104 /* FMC VHVCT2 Trim */
105 #define FLASH_O_FVHVCT2 0x00002088
108 #define FLASH_O_FVNVCT 0x00002090
111 #define FLASH_O_FVSLP 0x00002094
114 #define FLASH_O_FVWLCT 0x00002098
116 /* FMC Sequential Pump Information */
117 #define FLASH_O_FSEQPMP 0x000020A8
119 /* FMC FSM Command */
120 #define FLASH_O_FSM_CMD 0x0000220C
122 /* FMC FSM Program/Erase Operation Setup */
123 #define FLASH_O_FSM_PE_OSU 0x00002210
125 /* FMC FSM Voltage Status Setup */
126 #define FLASH_O_FSM_VSTAT 0x00002214
128 /* FMC FSM Program/Erase Verify Setup */
129 #define FLASH_O_FSM_PE_VSU 0x00002218
131 /* FMC FSM Compare Verify Setup */
132 #define FLASH_O_FSM_CMP_VSU 0x0000221C
134 /* FMC FSM EXECUTEZ to Valid Data */
135 #define FLASH_O_FSM_EX_VAL 0x00002220
137 /* FMC FSM Read Mode Hold */
138 #define FLASH_O_FSM_RD_H 0x00002224
140 /* FMC FSM Program Hold */
141 #define FLASH_O_FSM_P_OH 0x00002228
143 /* FMC FSM Erase Operation Hold */
144 #define FLASH_O_FSM_ERA_OH 0x0000222C
146 /* FMC FSM Program/Erase Verify Hold */
147 #define FLASH_O_FSM_PE_VH 0x00002234
149 /* FMC FSM Program Pulse Width */
150 #define FLASH_O_FSM_PRG_PW 0x00002240
152 /* FMC FSM Erase Pulse Width */
153 #define FLASH_O_FSM_ERA_PW 0x00002244
155 /* FMC FSM Maximum Programming Pulses */
156 #define FLASH_O_FSM_PRG_PUL 0x00002268
158 /* FMC FSM Maximum Erase Pulses */
159 #define FLASH_O_FSM_ERA_PUL 0x0000226C
161 /* FMC FSM EC Step Size */
162 #define FLASH_O_FSM_STEP_SIZE 0x00002270
164 /* FMC FSM EC Step Height */
165 #define FLASH_O_FSM_EC_STEP_HEIGHT 0x00002278
167 /* FMC FSM_ST_MACHINE */
168 #define FLASH_O_FSM_ST_MACHINE 0x0000227C
170 /* FMC FSM Register Write Enable */
171 #define FLASH_O_FSM_WR_ENA 0x00002288
173 /* FMC FSM Command Execute */
174 #define FLASH_O_FSM_EXECUTE 0x000022B4
176 /* FMC FSM Sector Erased 1 */
177 #define FLASH_O_FSM_SECTOR1 0x000022C0
179 /* FMC FSM Sector Erased 2 */
180 #define FLASH_O_FSM_SECTOR2 0x000022C4
182 /* FMC Flash Bank 0 Starting Address */
183 #define FLASH_O_FCFG_B0_START 0x00002410
185 /* FMC Flash Bank 0 Sector Size 0 */
186 #define FLASH_O_FCFG_B0_SSIZE0 0x00002430
188 /******************************************************************************
190 * Register: FLASH_O_STAT
192 ******************************************************************************/
193 /* Field: [2] SAMHOLD_DIS
195 * Status indicator of flash sample and hold sequencing logic. This bit will go
196 * to 1 some delay after CFG.DIS_IDLE is set to 1.
198 * 1: Sample and hold disabled and stable */
199 #define FLASH_STAT_SAMHOLD_DIS 0x00000004
203 * Fast version of the FMC FMSTAT.BUSY bit.
204 * This flag is valid immediately after the operation setting it (FMSTAT.BUSY
205 * is delayed some cycles)
208 #define FLASH_STAT_BUSY 0x00000002
210 /******************************************************************************
212 * Register: FLASH_O_CFG
214 ******************************************************************************/
215 /* Field: [8] STANDBY_MODE_SEL
217 * [Configured by boot firmware]
218 * STANDBY mode selection control. This bit, in conjunction with
219 * STANDBY_PW_SEL, determine which 1 of 4 sub-modes is selected for control of
220 * the behavior and timing of the STANDBY input to the pump.
222 * 0 : Legacy PG1 behavior is selected when STANDBY_PW_SEL = 00. This is
223 * referred to as sub-mode 1. When STANDBY_PW_SEL != 00, then sub-mode 2
224 * behavior is selected. STANDBY will be glitchy in these modes.
225 * 1 : STANDBY pulse-width counter modes selected. In these two modes (referred
226 * to as sub-mode 3 and sub-mode 4), the low time pulse width of the STANDBY
227 * signal to the pump, is controlled by a programmable timer. STANDBY will not
228 * be glitchy in these modes. */
229 #define FLASH_CFG_STANDBY_MODE_SEL_M 0x00000100
230 #define FLASH_CFG_STANDBY_MODE_SEL_S 8
232 /* Field: [7:6] STANDBY_PW_SEL
234 * [Configured by boot firmware]
235 * STANDBY pulse width counter selection control. These bits, in conjunction
236 * with STANDBY_MODE_SEL, determine which 1 of 4 sub-modes is selected for
237 * control of the behavior and timing of the STANDBY input to the pump.
239 * 00 : Legacy PG1 behavior is selected when STANDBY_MODE_SEL=0. Sub-mode 4 is
240 * selected when STANDBY_MODE_SEL=1. In sub-mode 4, STANDBY will be low for at
241 * least 9 pump clock cycles.
242 * 01 : Sub-mode 2 or 3 is selected, and STANDBY will be low for at least 9
244 * 10: Sub-mode 2 or 3 is selected, and STANDBY will be low for at least 5 pump
246 * 11: Sub-mode 2 or 3 is selected, and STANDBY will be low for at least 13
247 * pump clock cycles. */
248 #define FLASH_CFG_STANDBY_PW_SEL_M 0x000000C0
249 #define FLASH_CFG_STANDBY_PW_SEL_S 6
251 /* Field: [1] DIS_STANDBY
253 * [Configured by boot firmware]
254 * Disable standby functionality in read idle state */
255 #define FLASH_CFG_DIS_STANDBY 0x00000002
256 #define FLASH_CFG_DIS_STANDBY_BITN 1
257 #define FLASH_CFG_DIS_STANDBY_M 0x00000002
259 /* Field: [0] DIS_IDLE
261 * [Configured by boot firmware]
262 * Disable sample and hold functionality in read idle state */
263 #define FLASH_CFG_DIS_IDLE 0x00000001
264 #define FLASH_CFG_DIS_IDLE_M 0x00000001
265 #define FLASH_CFG_DIS_IDLE_S 0
267 /******************************************************************************
269 * Register: FLASH_O_FLASH_SIZE
271 ******************************************************************************/
272 /* Field: [7:0] SECTORS
274 * [Configured by boot firmware]
275 * Flash size. The number of flash sectors in the configured device. Read
276 * access to sectors equal to this number or higher will result in an error.
277 * The CCFG area is the sector (SECTORS - 1) Writing to this register is
278 * disabled by the CFG.CONFIGURED bit. */
279 #define FLASH_FLASH_SIZE_SECTORS_M 0x000000FF
280 #define FLASH_FLASH_SIZE_SECTORS_S 0
282 /******************************************************************************
284 * Register: FLASH_O_FRDCTL
286 ******************************************************************************/
287 /* Field: [11:8] RWAIT
289 * [Configured by boot firmware]
290 * FMC Wait State. This field determines the FLCLK period during FMC controlled
292 * - During power up/ power down / low power mode
293 * - During FSM operations like program, erase
294 * - During software interface mode (see FLOCK , FBSTROBES registers)
295 * FLCLK_period = HCLK_period X (RWAIT + 1),
296 * FSM state machine operations are usually twice this amount. This value
297 * should never be set less than 2. */
298 #define FLASH_FRDCTL_RWAIT_M 0x00000F00
299 #define FLASH_FRDCTL_RWAIT_S 8
301 /******************************************************************************
303 * Register: FLASH_O_FBPROT
305 ******************************************************************************/
306 /* Field: [0] PROTL1DIS
308 * Level 1 Protection Disable bit. Setting this bit disables protection from
309 * writing to the FBAC.OTPPROTDIS bits as well as the Sector Enable registers
310 * FBSE for all banks. Clearing this bit enables protection and disables write
311 * access to the FBAC.OTPPROTDIS register bits and FBSE register. */
312 #define FLASH_FBPROT_PROTL1DIS 0x00000001
314 /******************************************************************************
316 * Register: FLASH_O_FMSTAT
318 ******************************************************************************/
321 * Command Status. Once the FSM starts any failure will set this bit. When set,
322 * this bit informs the host that the program, erase, or validate sector
323 * command failed and the command was stopped. This bit is cleared by the
324 * Clear_Status command. For some errors, this will be the only indication of
325 * an FSM error because the cause does not fall within the other error bit
327 #define FLASH_FMSTAT_CSTAT 0x00000010
329 /******************************************************************************
331 * Register: FLASH_O_FVREADCT
333 ******************************************************************************/
334 /* Field: [3:0] VREADCT
336 * [Configured by boot firmware]
337 * These bits control the voltage level for the specified pump voltage of
338 * wordline power supply for read mode. */
339 #define FLASH_FVREADCT_VREADCT_M 0x0000000F
340 #define FLASH_FVREADCT_VREADCT_S 0
342 /******************************************************************************
344 * Register: FLASH_O_FVHVCT1
346 ******************************************************************************/
347 /* Field: [23:20] TRIM13_E
349 * [Configured by boot firmware]
350 * These bits control the voltage level for the specified pump voltage of high
351 * voltage supply input during erase operation. */
352 #define FLASH_FVHVCT1_TRIM13_E_M 0x00F00000
353 #define FLASH_FVHVCT1_TRIM13_E_S 20
355 /* Field: [19:16] VHVCT_E
357 * [Configured by boot firmware]
358 * These bits control the voltage level for the specified pump voltage of high
359 * voltage supply input during erase operation. */
360 #define FLASH_FVHVCT1_VHVCT_E_M 0x000F0000
361 #define FLASH_FVHVCT1_VHVCT_E_S 16
363 /* Field: [7:4] TRIM13_PV
365 * [Configured by boot firmware]
366 * These bits control the voltage level for the specified pump voltage of high
367 * voltage supply input during program verify operation. */
368 #define FLASH_FVHVCT1_TRIM13_PV_M 0x000000F0
369 #define FLASH_FVHVCT1_TRIM13_PV_S 4
371 /* Field: [3:0] VHVCT_PV
373 * [Configured by boot firmware]
374 * These bits control the voltage level for the specified pump voltage of high
375 * voltage supply input during program verify operation. */
376 #define FLASH_FVHVCT1_VHVCT_PV_M 0x0000000F
377 #define FLASH_FVHVCT1_VHVCT_PV_S 0
379 /******************************************************************************
381 * Register: FLASH_O_FVHVCT2
383 ******************************************************************************/
384 /* Field: [23:20] TRIM13_P
386 * [Configured by boot firmware]
387 * These bits control the voltage level for the specified pump voltage of high
388 * voltage supply input during program operation. */
389 #define FLASH_FVHVCT2_TRIM13_P_M 0x00F00000
390 #define FLASH_FVHVCT2_TRIM13_P_S 20
392 /* Field: [19:16] VHVCT_P
394 * [Configured by boot firmware]
395 * These bits control the voltage level for the specified pump voltage of high
396 * voltage supply input during program operation. */
397 #define FLASH_FVHVCT2_VHVCT_P_M 0x000F0000
398 #define FLASH_FVHVCT2_VHVCT_P_S 16
400 /******************************************************************************
402 * Register: FLASH_O_FVNVCT
404 ******************************************************************************/
405 /* Field: [12:8] VCG2P5CT
407 * [Configured by boot firmware]
408 * These bits control the voltage level for the VCG 2.5 CT pump voltage. */
409 #define FLASH_FVNVCT_VCG2P5CT_M 0x00001F00
410 #define FLASH_FVNVCT_VCG2P5CT_S 8
412 /******************************************************************************
414 * Register: FLASH_O_FVSLP
416 ******************************************************************************/
417 /* Field: [15:12] VSL_P
419 * [Configured by boot firmware]
420 * These bits control the voltage level for the specified pump voltage of high
421 * current power input during program operation. */
422 #define FLASH_FVSLP_VSL_P_M 0x0000F000
423 #define FLASH_FVSLP_VSL_P_S 12
425 /******************************************************************************
427 * Register: FLASH_O_FVWLCT
429 ******************************************************************************/
430 /* Field: [4:0] VWLCT_P
432 * [Configured by boot firmware]
433 * These bits control the voltage level for the specified pump voltage of
434 * wordline power supply during programming operations. */
435 #define FLASH_FVWLCT_VWLCT_P_M 0x0000001F
436 #define FLASH_FVWLCT_VWLCT_P_S 0
438 /******************************************************************************
440 * Register: FLASH_O_FSEQPMP
442 ******************************************************************************/
443 /* Field: [21:20] TRIM_1P7
445 * [Configured by boot firmware]
446 * This register goes directly to the pump's TRIM_1P7 port pins. */
447 #define FLASH_FSEQPMP_TRIM_1P7_M 0x00300000
448 #define FLASH_FSEQPMP_TRIM_1P7_S 20
450 /* Field: [14:12] VIN_AT_X
452 * This register controls to the pump's VIN_AT_XPX port pins with the following
455 * If VIN_BY_PASS=0 then pump VIN_AT_XPX is equal to VIN_AT_XIN input ports
456 * from the BATMON logic after clocking through synchronizers and the sequence
457 * checker FSM logic contained in the flash wrapper.
459 * If VIN_BY_PASS=1 and VIN_AT_X=???
461 * 0: then all pump VIN_AT_XPX signals are 0.
462 * 1: then pump VIN_AT_1P7 is set.
463 * 2: then pump VIN_AT_2P1 is also set.
464 * 3: then pump VIN_AT_2P4 is also set.
465 * 4-7: then pump VIN_AT_3P0 is also set (ie all VIN_AT_XPX signals are 1). */
466 #define FLASH_FSEQPMP_VIN_AT_X_M 0x00007000
467 #define FLASH_FSEQPMP_VIN_AT_X_S 12
469 /* Field: [8] VIN_BY_PASS
471 * [Configured by boot firmware]
473 * When this bit is a zero, the pump's VIN_AT_XPX ports comes from the FMC
474 * input port VIN_AT_XIN.
476 * When this bit is a one, the pump's VIN_AT_XPX ports comes from the VIN_AT_X
478 #define FLASH_FSEQPMP_VIN_BY_PASS 0x00000100
479 #define FLASH_FSEQPMP_VIN_BY_PASS_M 0x00000100
481 /******************************************************************************
483 * Register: FLASH_O_FSM_PE_OSU
485 ******************************************************************************/
486 /* Field: [15:8] PGM_OSU
488 * [Configured by boot firmware]
489 * Program Operation Setup time. This determines the flash clocks from the mode
490 * change to program, to the start of the program pulse. */
491 #define FLASH_FSM_PE_OSU_PGM_OSU_M 0x0000FF00
492 #define FLASH_FSM_PE_OSU_PGM_OSU_S 8
494 /* Field: [7:0] ERA_OSU
496 * [Configured by boot firmware]
497 * Erase Operation Setup time. This determines the flash clocks from the mode
498 * change to erase, to the start of the erase pulse. */
499 #define FLASH_FSM_PE_OSU_ERA_OSU_M 0x000000FF
500 #define FLASH_FSM_PE_OSU_ERA_OSU_S 0
502 /******************************************************************************
504 * Register: FLASH_O_FSM_VSTAT
506 ******************************************************************************/
507 /* Field: [15:12] VSTAT_CNT
509 * [Configured by boot firmware]
510 * Voltage Status Count. Gives the number of consecutive HCLK pulses that must
511 * be out of range before a voltage-out-of-range status error is given in
512 * FMSTAT.VOLSTAT. One pulse in range will reset the counter. This is mainly a
513 * glitch filter on the voltage status pump signal. */
514 #define FLASH_FSM_VSTAT_VSTAT_CNT_M 0x0000F000
515 #define FLASH_FSM_VSTAT_VSTAT_CNT_S 12
517 /******************************************************************************
519 * Register: FLASH_O_FSM_PE_VSU
521 ******************************************************************************/
522 /* Field: [15:8] PGM_VSU
524 * [Configured by boot firmware]
525 * Program Verify Setup time. This determines the flash clocks from the mode
526 * change to program verify, to the change of address and the beginning of the
527 * address setup time. */
528 #define FLASH_FSM_PE_VSU_PGM_VSU_M 0x0000FF00
529 #define FLASH_FSM_PE_VSU_PGM_VSU_S 8
531 /* Field: [7:0] ERA_VSU
533 * [Configured by boot firmware]
534 * Erase Verify Setup time. This determines the flash clocks from the mode
535 * change to erase verify, to the change of address and the beginning of the
536 * address setup time. */
537 #define FLASH_FSM_PE_VSU_ERA_VSU_M 0x000000FF
538 #define FLASH_FSM_PE_VSU_ERA_VSU_S 0
540 /******************************************************************************
542 * Register: FLASH_O_FSM_CMP_VSU
544 ******************************************************************************/
545 /* Field: [15:12] ADD_EXZ
547 * [Configured by boot firmware]
548 * Address to EXECUTEZ low setup time. This determines the flash clocks from
549 * the row address change to the time EXECUTEZ goes low. All operations use
551 #define FLASH_FSM_CMP_VSU_ADD_EXZ_M 0x0000F000
552 #define FLASH_FSM_CMP_VSU_ADD_EXZ_S 12
554 /******************************************************************************
556 * Register: FLASH_O_FSM_EX_VAL
558 ******************************************************************************/
559 /* Field: [15:8] REP_VSU
561 * [Configured by boot firmware]
562 * Repeat Verify action setup. If a program or erase operation advances to the
563 * program_verify or erase_verify then this special shorter mode transition
564 * time will be used in place of FSM_PE_VSU.PGM_VSU or FSM_PE_VSU.ERA_VSU
566 #define FLASH_FSM_EX_VAL_REP_VSU_M 0x0000FF00
567 #define FLASH_FSM_EX_VAL_REP_VSU_S 8
569 /* Field: [7:0] EXE_VALD
571 * [Configured by boot firmware]
572 * EXECUTEZ low to valid Data. Determines the number of Flash clock cycles from
573 * EXECUTEZ going low to the time the verify data can be read in the program
574 * verify mode. Erase and compact verify is always a constant value which is
575 * currently set at one flash clock. This value must be greater than 0. */
576 #define FLASH_FSM_EX_VAL_EXE_VALD_M 0x000000FF
577 #define FLASH_FSM_EX_VAL_EXE_VALD_S 0
579 /******************************************************************************
581 * Register: FLASH_O_FSM_RD_H
583 ******************************************************************************/
586 * [Configured by boot firmware]
587 * Read mode hold. This determines the number of flash clocks from the start of
588 * the Read mode at the end of the operations until the FSM clears the
589 * FMSTAT.BUSY. Writing a zero to this register will result in a value of 1.
590 * The reset value of this register is 0x3Ah before FMC version 3.0.10.0 and
591 * 0x5Ah after this version. */
592 #define FLASH_FSM_RD_H_RD_H_M 0x000000FF
593 #define FLASH_FSM_RD_H_RD_H_S 0
595 /******************************************************************************
597 * Register: FLASH_O_FSM_P_OH
599 ******************************************************************************/
600 /* Field: [15:8] PGM_OH
602 * [Configured by boot firmware]
603 * EXECUTEZ high to mode change. This value determines the flash clocks from
604 * the EXECUTEZ going high at the end of a program operation to the time the
605 * mode can change. This value must be greater than or equal to one. */
606 #define FLASH_FSM_P_OH_PGM_OH_M 0x0000FF00
607 #define FLASH_FSM_P_OH_PGM_OH_S 8
609 /******************************************************************************
611 * Register: FLASH_O_FSM_ERA_OH
613 ******************************************************************************/
614 /* Field: [15:0] ERA_OH
616 * [Configured by boot firmware]
617 * EXECUTEZ high to mode change. Determines the flash clocks from EXECUTEZ
618 * going high at the end of an erase operation to the time the mode can change.
619 * If a bank erase is happening, then this is the time to when the TEZ and TCR
620 * values for bank erase are released. The mode changes 10 flash clocks after
621 * they are released. This value must be greater than or equal to one. */
622 #define FLASH_FSM_ERA_OH_ERA_OH_M 0x0000FFFF
623 #define FLASH_FSM_ERA_OH_ERA_OH_S 0
625 /******************************************************************************
627 * Register: FLASH_O_FSM_PE_VH
629 ******************************************************************************/
630 /* Field: [15:8] PGM_VH
632 * [Configured by boot firmware]
633 * Program Verify Hold. This register determines the flash clocks from EXECUTEZ
634 * going high after a program verify to a mode change. This value must be
635 * greater than or equal to one */
636 #define FLASH_FSM_PE_VH_PGM_VH_M 0x0000FF00
637 #define FLASH_FSM_PE_VH_PGM_VH_S 8
639 /******************************************************************************
641 * Register: FLASH_O_FSM_PRG_PW
643 ******************************************************************************/
644 /* Field: [15:0] PROG_PUL_WIDTH
646 * [Configured by boot firmware]
647 * Program Pulse width.This register gives the number of flash clocks that the
648 * EXECUTEZ signal is low in a program operation. */
649 #define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_M 0x0000FFFF
650 #define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_S 0
652 /******************************************************************************
654 * Register: FLASH_O_FSM_ERA_PW
656 ******************************************************************************/
657 /* Field: [31:0] FSM_ERA_PW
659 * [Configured by boot firmware]
660 * Erase Pulse width. This register gives the number flash clocks that the
661 * EXECUTEZ signal is low in an erase operation. */
662 #define FLASH_FSM_ERA_PW_FSM_ERA_PW_M 0xFFFFFFFF
663 #define FLASH_FSM_ERA_PW_FSM_ERA_PW_S 0
665 /******************************************************************************
667 * Register: FLASH_O_FSM_PRG_PUL
669 ******************************************************************************/
670 /* Field: [19:16] BEG_EC_LEVEL
672 * [Configured by boot firmware]
673 * Beginning level for VHVCT. This determines the beginning level for VHVCT
674 * that is used during erase modes. The pump voltage control registers supply
675 * the other values that do not change during FSM operations. The reset value
676 * is the same as FVHVCT1.VHVCT_E. */
677 #define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_M 0x000F0000
678 #define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_S 16
680 /* Field: [11:0] MAX_PRG_PUL
682 * [Configured by boot firmware]
683 * Maximum Programming Pulses. This register contains the maximum number of
684 * programming pulses allowed at one address. If it takes any more than this
685 * amount during a programming operation then the FSM will exit with an error
686 * and with the program violation, FMSTAT.PGV set, and the general error set,
687 * FMSTAT.CSTAT. Setting FSM_ST_MACHINE.OVERRIDE to 0 will allow more than this
688 * maximum value to occur without an error. During pre-conditioning for an
689 * erase operation the FSM programs all the bits to zero. If the maximum number
690 * of programming pulses is reached for an address, the FSM will continue with
691 * the next address and set the FMSTAT.PCV and the general error FMSTAT.CSTAT.
692 * If the FSM_ST_MACHINE.PREC_STOP_EN is set then the FSM will stop with errors
693 * when more than the maximum number of pulses is needed. The
694 * FSM_ST_MACHINE.OVERRIDE bit will take priority over the
695 * FSM_ST_MACHINE.PREC_STOP_EN and continue doing pulses without setting the
696 * error bits. Suspend operations will count a pulse if the program operation
697 * began no matter how long the pulse lasted before is was suspended. Frequent
698 * suspend or auto-suspend operations could result in max_pulse count error. */
699 #define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_M 0x00000FFF
700 #define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_S 0
702 /******************************************************************************
704 * Register: FLASH_O_FSM_ERA_PUL
706 ******************************************************************************/
707 /* Field: [19:16] MAX_EC_LEVEL
709 * [Configured by boot firmware]
710 * Maximum VHVCT Level. This determines the maximum level for VHVCT that is
711 * used during erase modes. The FSM will stop advancing VHVCT once it counts up
712 * to the MAX_EC_LEVEL level from the beginning level. The MAX_EC_LEVEL +
713 * FSM_EC_STEP_HEIGHT.EC_STEP_HEIGHT must be less than 0x200. The reset value
714 * is the same as FVHVCT1.VHVCT_E. */
715 #define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_M 0x000F0000
716 #define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_S 16
718 /* Field: [11:0] MAX_ERA_PUL
720 * [Configured by boot firmware]
721 * Maximum Erase Pulses. This register contains the maximum number of erase
722 * pulses allowed at one address. If it takes any more than this amount the FSM
723 * will exit with an error and with both the FMSTAT.EV and FMSTAT.CSTAT bits
724 * set. Setting FSM_ST_MACHINE.OVERRIDE to 1 will allow more than this maximum
725 * value to occur without an error. Suspend operations will count a pulse if
726 * the erase operation began no matter how long the pulse lasted before is was
727 * suspended. Frequent suspend or auto-suspend operations could result in
728 * max_pulse count error. */
729 #define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_M 0x00000FFF
730 #define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_S 0
732 /******************************************************************************
734 * Register: FLASH_O_FSM_STEP_SIZE
736 ******************************************************************************/
737 /* Field: [24:16] EC_STEP_SIZE
739 * [Configured by boot firmware]
740 * VHVCT Step Size. This is the number of erase pulses that must be completed
741 * for each level before the FSM increments the FSM_PUL_CNTR.CUR_EC_LEVEL to
742 * the next higher level. Actual erase pulses per level equals (EC_STEP_SIZE
743 * +1). The stepping is only needed for the VHVCT voltage. */
744 #define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_M 0x01FF0000
745 #define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_S 16
747 /******************************************************************************
749 * Register: FLASH_O_FSM_EC_STEP_HEIGHT
751 ******************************************************************************/
752 /* Field: [3:0] EC_STEP_HEIGHT
754 * [Configured by boot firmware]
755 * Height of each EC step. This is the number of counts that the
756 * FSM_PUL_CNTR.CUR_EC_LEVEL will increment when going to a new level. Actual
757 * count size equals (EC_STEP_HEIGHT + 1). The stepping applies only to the
758 * VHVCT voltage. If adding the height to the FSM_PUL_CNTR.CUR_EC_LEVEL results
759 * in a value higher than the FSM_ERA_PUL.MAX_EC_LEVEL then the
760 * FSM_PUL_CNTR.CUR_EC_LEVEL will be lowered to the MAX LEVEL before it is used
761 * in the next erase pulse. */
762 #define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_M 0x0000000F
764 /******************************************************************************
766 * Register: FLASH_O_FSM_ST_MACHINE
768 ******************************************************************************/
769 /* Field: [23] DO_PRECOND
771 * [Configured by boot firmware]
772 * Do preconditioning. When this bit is a one, the FSM will precondition the
773 * sector or bank before doing an erase operation. When zero, the FSM will just
774 * begin with the erase verify and skip the preconditioning. */
775 #define FLASH_FSM_ST_MACHINE_DO_PRECOND 0x00800000
776 #define FLASH_FSM_ST_MACHINE_DO_PRECOND_M 0x00800000
777 #define FLASH_FSM_ST_MACHINE_DO_PRECOND_S 23
779 /* Field: [14] ONE_TIME_GOOD
781 * [Configured by boot firmware]
782 * One Time Good function. If this bit is a one then the 'One Time Good'
783 * function is enabled for all program operations. This includes operations
784 * inside the erase functions and other functions. When zero, this function is
785 * disabled for all modes. When doing the One Time Good function, the FSM will
786 * attempt to program a location with data. If a desired zero bit reads back
787 * from the flash one time as good then that bit is blocked from writing a zero
788 * to the flash array again for this address. When the address changes, all
789 * bits are unblocked. This prevents a bit from reading 0 in one programming
790 * pulse and then 1 in the next programming pulse. On the second time the bit
791 * would get a programming pulse even though it read 0 in an earlier read. If
792 * this bit is a zero then the zero bits will be masked for each program verify
793 * operation. It is recommended for this bit to be set to 1. */
794 #define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD 0x00004000
796 /******************************************************************************
798 * Register: FLASH_O_FCFG_B0_SSIZE0
800 ******************************************************************************/
801 /* Field: [3:0] B0_SECT_SIZE
803 * Size of sectors in Bank 0. Common sector size for all sectors in the bank in
804 * 1K bytes multiples.
806 * 0x1: 1K bytes(FLES)
808 * 0x4: 4K bytes (FLEE)
811 #define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_M 0x0000000F
812 #define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_S 0
814 /******************************************************************************
816 * This section defines the register offsets of FCFG1 component
818 ******************************************************************************/
820 /* Flash Erase and Program Setup Time */
821 #define FCFG1_O_FLASH_E_P 0x00000170
823 /* Flash Compaction, Execute, Program and Read */
824 #define FCFG1_O_FLASH_C_E_P_R 0x00000174
826 /* Flash Program, Read, and Program Verify */
827 #define FCFG1_O_FLASH_P_R_PV 0x00000178
829 /* Flash Erase Hold and Sequence */
830 #define FCFG1_O_FLASH_EH_SEQ 0x0000017C
832 /* Flash VHV Erase */
833 #define FCFG1_O_FLASH_VHV_E 0x00000180
835 /* Flash Program Pulse */
836 #define FCFG1_O_FLASH_PP 0x00000184
838 /* Flash Program and Erase Pulse */
839 #define FCFG1_O_FLASH_PROG_EP 0x00000188
841 /* Flash Erase Pulse Width */
842 #define FCFG1_O_FLASH_ERA_PW 0x0000018C
845 #define FCFG1_O_FLASH_VHV 0x00000190
847 /* Flash VHV Program Verify */
848 #define FCFG1_O_FLASH_VHV_PV 0x00000194
851 #define FCFG1_O_FLASH_V 0x00000198
853 /* Flash OTP Data 3 */
854 #define FCFG1_O_FLASH_OTP_DATA3 0x000002B0
856 /* Flash OTP Data 4 */
857 #define FCFG1_O_FLASH_OTP_DATA4 0x00000308
859 /******************************************************************************
861 * Register: FCFG1_O_FLASH_E_P
863 ******************************************************************************/
864 /* Field: [31:24] PSU
866 * Program setup time in cycles. Value will be written to
867 * FLASH:FSM_PE_OSU.PGM_OSU by the flash device driver when an erase/program
868 * operation is initiated. */
869 #define FCFG1_FLASH_E_P_PSU_M 0xFF000000
870 #define FCFG1_FLASH_E_P_PSU_S 24
872 /* Field: [23:16] ESU
874 * Erase setup time in cycles. Value will be written to
875 * FLASH:FSM_PE_OSU.ERA_OSU by the flash device driver when an erase/program
876 * operation is initiated. */
877 #define FCFG1_FLASH_E_P_ESU_M 0x00FF0000
878 #define FCFG1_FLASH_E_P_ESU_S 16
880 /* Field: [15:8] PVSU
882 * Program verify setup time in cycles. Value will be written to
883 * FLASH:FSM_PE_VSU.PGM_VSU by the flash device driver when an erase/program
884 * operation is initiated. */
885 #define FCFG1_FLASH_E_P_PVSU_M 0x0000FF00
886 #define FCFG1_FLASH_E_P_PVSU_S 8
890 * Erase verify setup time in cycles. Value will be written to
891 * FLASH:FSM_PE_VSU.ERA_VSU by the flash device driver when an erase/program
892 * operation is initiated. */
893 #define FCFG1_FLASH_E_P_EVSU_M 0x000000FF
894 #define FCFG1_FLASH_E_P_EVSU_S 0
896 /******************************************************************************
898 * Register: FCFG1_O_FLASH_C_E_P_R
900 ******************************************************************************/
901 /* Field: [31:24] RVSU
903 * Repeat verify setup time in cycles. Used for repeated verifies during
904 * program and erase. Value will be written to FLASH:FSM_EX_VAL.REP_VSU by the
905 * flash device driver when an erase/program operation is initiated. */
906 #define FCFG1_FLASH_C_E_P_R_RVSU_M 0xFF000000
907 #define FCFG1_FLASH_C_E_P_R_RVSU_S 24
909 /* Field: [23:16] PV_ACCESS
911 * Program verify EXECUTEZ->data valid time in half-microseconds. Value
912 * will be converted to number of FCLK cycles by by flash device driver and the
913 * converted value is written to FLASH:FSM_EX_VAL.EXE_VALD when an
914 * erase/program operation is initiated. */
915 #define FCFG1_FLASH_C_E_P_R_PV_ACCESS_M 0x00FF0000
916 #define FCFG1_FLASH_C_E_P_R_PV_ACCESS_S 16
918 /* Field: [15:12] A_EXEZ_SETUP
920 * Address->EXECUTEZ setup time in cycles. Value will be written to
921 * FLASH:FSM_CMP_VSU.ADD_EXZ by the flash device driver when an erase/program
922 * operation is initiated. */
923 #define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_M 0x0000F000
924 #define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_S 12
926 /******************************************************************************
928 * Register: FCFG1_O_FLASH_P_R_PV
930 ******************************************************************************/
933 * Program hold time in half-microseconds after SAFELV goes high. Value will be
934 * converted to number of FCLK cycles by the flash device driver and the
935 * converted value is written to FLASH:FSM_P_OH.PGM_OH when an erase/program
936 * operation is initiated. */
937 #define FCFG1_FLASH_P_R_PV_PH_M 0xFF000000
938 #define FCFG1_FLASH_P_R_PV_PH_S 24
942 * Read hold/mode transition time in cycles. Value will be written to the RD_H
943 * field bits[7:0] of the FSM_RD_H register in the flash module by the flash
944 * device driver when an erase/program operation is initiated. */
945 #define FCFG1_FLASH_P_R_PV_RH_M 0x00FF0000
946 #define FCFG1_FLASH_P_R_PV_RH_S 16
950 * Program verify hold time in half-microseconds after SAFELV goes high. Value
951 * will be converted to number of FCLK cycles by the flash device driver and
952 * the converted value is written to FLASH:FSM_PE_VH.PGM_VH when an
953 * erase/program operation is initiated. */
954 #define FCFG1_FLASH_P_R_PV_PVH_M 0x0000FF00
955 #define FCFG1_FLASH_P_R_PV_PVH_S 8
957 /******************************************************************************
959 * Register: FCFG1_O_FLASH_EH_SEQ
961 ******************************************************************************/
964 * Erase hold time in half-microseconds after SAFELV goes high. Value will be
965 * converted to number of FCLK cycles by the flash device driver and the
966 * converted value is written to FLASH:FSM_ERA_OH.ERA_OH when an erase/program
967 * operation is initiated. */
968 #define FCFG1_FLASH_EH_SEQ_EH_M 0xFF000000
969 #define FCFG1_FLASH_EH_SEQ_EH_S 24
971 /* Field: [15:12] VSTAT
973 * Max number of HCLK cycles allowed for pump brown-out. Value will be written
974 * to FLASH:FSM_VSTAT.VSTAT_CNT when an erase/program operation is initiated. */
975 #define FCFG1_FLASH_EH_SEQ_VSTAT_M 0x0000F000
976 #define FCFG1_FLASH_EH_SEQ_VSTAT_S 12
978 /******************************************************************************
980 * Register: FCFG1_O_FLASH_VHV_E
982 ******************************************************************************/
983 /* Field: [31:16] VHV_E_START
985 * Starting VHV-Erase CT for stairstep erase. Value will be written to
986 * FLASH:FSM_PRG_PUL.BEG_EC_LEVEL when erase/program operation is initiated. */
987 #define FCFG1_FLASH_VHV_E_VHV_E_START_M 0xFFFF0000
988 #define FCFG1_FLASH_VHV_E_VHV_E_START_S 16
990 /* Field: [15:0] VHV_E_STEP_HIGHT
992 * Number of VHV CTs to step after each erase pulse (up to the max). The actual
993 * FMC register value should be one less than this since the FMC starts
994 * counting from zero. Value will be written to
995 * FLASH:FSM_EC_STEP_HEIGHT.EC_STEP_HEIGHT when an erase/program operation is
997 #define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_M 0x0000FFFF
998 #define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_S 0
1000 /******************************************************************************
1002 * Register: FCFG1_O_FLASH_PP
1004 ******************************************************************************/
1005 /* Field: [15:0] MAX_PP
1007 * Max program pulse limit per program operation. Value will be written to
1008 * FLASH:FSM_PRG_PUL.MAX_PRG_PUL when an erase/program operation is initiated. */
1009 #define FCFG1_FLASH_PP_MAX_PP_M 0x0000FFFF
1010 #define FCFG1_FLASH_PP_MAX_PP_S 0
1012 /******************************************************************************
1014 * Register: FCFG1_O_FLASH_PROG_EP
1016 ******************************************************************************/
1017 /* Field: [31:16] MAX_EP
1019 * Max erase pulse limit per erase operation. Value will be written to
1020 * FLASH:FSM_ERA_PUL.MAX_ERA_PUL when an erase/program operation is initiated. */
1021 #define FCFG1_FLASH_PROG_EP_MAX_EP_M 0xFFFF0000
1022 #define FCFG1_FLASH_PROG_EP_MAX_EP_S 16
1024 /* Field: [15:0] PROGRAM_PW
1026 * Program pulse width in half-microseconds. Value will be converted to number
1027 * of FCLK cycles by the flash device driver and the converted value is written
1028 * to FLASH:FSM_PRG_PW.PROG_PUL_WIDTH when a erase/program operation is
1030 #define FCFG1_FLASH_PROG_EP_PROGRAM_PW_M 0x0000FFFF
1031 #define FCFG1_FLASH_PROG_EP_PROGRAM_PW_S 0
1033 /******************************************************************************
1035 * Register: FCFG1_O_FLASH_ERA_PW
1037 ******************************************************************************/
1038 /* Field: [31:0] ERASE_PW
1040 * Erase pulse width in half-microseconds. Value will be converted to number of
1041 * FCLK cycles by the flash device driver and the converted value is written to
1042 * FLASH:FSM_ERA_PW.FSM_ERA_PW when a erase/program operation is initiated. */
1043 #define FCFG1_FLASH_ERA_PW_ERASE_PW_M 0xFFFFFFFF
1044 #define FCFG1_FLASH_ERA_PW_ERASE_PW_S 0
1046 /******************************************************************************
1048 * Register: FCFG1_O_FLASH_VHV
1050 ******************************************************************************/
1051 /* Field: [27:24] TRIM13_P
1053 * Value will be written to FLASH:FVHVCT2.TRIM13_P by the flash device driver
1054 * when an erase/program operation is initiated. */
1055 #define FCFG1_FLASH_VHV_TRIM13_P_M 0x0F000000
1056 #define FCFG1_FLASH_VHV_TRIM13_P_S 24
1058 /* Field: [19:16] VHV_P
1060 * Value will be written to FLASH:FVHVCT2.VHVCT_P by the flash device driver
1061 * when an erase/program operation is initiated. */
1062 #define FCFG1_FLASH_VHV_VHV_P_M 0x000F0000
1063 #define FCFG1_FLASH_VHV_VHV_P_S 16
1065 /* Field: [11:8] TRIM13_E
1067 * Value will be written to FLASH:FVHVCT1.TRIM13_E by the flash device driver
1068 * when an erase/program operation is initiated. */
1069 #define FCFG1_FLASH_VHV_TRIM13_E_M 0x00000F00
1070 #define FCFG1_FLASH_VHV_TRIM13_E_S 8
1072 /* Field: [3:0] VHV_E
1074 * Value will be written to FLASH:FVHVCT1.VHVCT_E by the flash device driver
1075 * when an erase/program operation is initiated */
1076 #define FCFG1_FLASH_VHV_VHV_E_M 0x0000000F
1077 #define FCFG1_FLASH_VHV_VHV_E_S 0
1079 /******************************************************************************
1081 * Register: FCFG1_O_FLASH_VHV_PV
1083 ******************************************************************************/
1084 /* Field: [27:24] TRIM13_PV
1086 * Value will be written to FLASH:FVHVCT1.TRIM13_PV by the flash device driver
1087 * when an erase/program operation is initiated. */
1088 #define FCFG1_FLASH_VHV_PV_TRIM13_PV_M 0x0F000000
1089 #define FCFG1_FLASH_VHV_PV_TRIM13_PV_S 24
1091 /* Field: [19:16] VHV_PV
1093 * Value will be written to FLASH:FVHVCT1.VHVCT_PV by the flash device driver
1094 * when an erase/program operation is initiated. */
1095 #define FCFG1_FLASH_VHV_PV_VHV_PV_M 0x000F0000
1096 #define FCFG1_FLASH_VHV_PV_VHV_PV_S 16
1098 /* Field: [15:8] VCG2P5
1100 * Control gate voltage during read, read margin, and erase verify. Value will
1101 * be written to FLASH:FVNVCT.VCG2P5CT by the flash device driver when an
1102 * erase/program operation is initiated. */
1103 #define FCFG1_FLASH_VHV_PV_VCG2P5_M 0x0000FF00
1104 #define FCFG1_FLASH_VHV_PV_VCG2P5_S 8
1106 /******************************************************************************
1108 * Register: FCFG1_O_FLASH_V
1110 ******************************************************************************/
1111 /* Field: [31:24] VSL_P
1113 * Sourceline voltage applied to the selected block during programming. Value
1114 * will be written to FLASH:FVSLP.VSL_P by the flash device driver when an
1115 * erase/program operation is initiated. */
1116 #define FCFG1_FLASH_V_VSL_P_M 0xFF000000
1117 #define FCFG1_FLASH_V_VSL_P_S 24
1119 /* Field: [23:16] VWL_P
1121 * Wordline voltage applied to the selected half-row during programming. Value
1122 * will be written to FLASH:FVWLCT.VWLCT_P by the flash device driver when an
1123 * erase/program operation is initiated. */
1124 #define FCFG1_FLASH_V_VWL_P_M 0x00FF0000
1125 #define FCFG1_FLASH_V_VWL_P_S 16
1127 /* Field: [15:8] V_READ
1129 * Wordline voltage applied to the selected block during reads and verifies.
1130 * Value will be written to FLASH:FVREADCT.VREADCT by the flash device driver
1131 * when an erase/program operation is initiated. */
1132 #define FCFG1_FLASH_V_V_READ_M 0x0000FF00
1133 #define FCFG1_FLASH_V_V_READ_S 8
1135 /******************************************************************************
1137 * Register: FCFG1_O_FLASH_OTP_DATA3
1139 ******************************************************************************/
1140 /* Field: [31:23] EC_STEP_SIZE
1142 * Value will be written to FLASH:FSM_STEP_SIZE.EC_STEP_SIZE by the flash
1143 * device driver when a erase/program operation is initiated. */
1144 #define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_M 0xFF800000
1145 #define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_S 23
1147 /* Field: [22] DO_PRECOND
1149 * Value will be written to FLASH:FSM_ST_MACHINE.DO_PRECOND by the flash device
1150 * driver when a erase/program operation is initiated.
1152 * Note that during a Total Erase operation the flash bank will always be
1153 * erased with Precondition enabled independent of the value of this FCFG1 bit
1155 #define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_M 0x00400000
1156 #define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_S 22
1158 /* Field: [21:18] MAX_EC_LEVEL
1160 * Value will be written to FLASH:FSM_ERA_PUL.MAX_EC_LEVEL by the flash device
1161 * driver when a erase/program operation is initiated. */
1162 #define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_M 0x003C0000
1163 #define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_S 18
1165 /* Field: [17:16] TRIM_1P7
1167 * Value will be written to FLASH:FSEQPMP.TRIM_1P7 by the flash device driver
1168 * when a erase/program operation is initiated. */
1169 #define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_M 0x00030000
1170 #define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_S 16
1172 /******************************************************************************
1174 * Register: FCFG1_O_FLASH_OTP_DATA4
1176 ******************************************************************************/
1177 /* Field: [31] STANDBY_MODE_SEL_INT_WRT
1179 * If AON_PMCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to
1180 * FLASH:CFG.STANDBY_MODE_SEL by flash device driver FW when a flash write
1181 * operation is initiated. */
1182 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_M 0x80000000
1183 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_S 31
1185 /* Field: [30:29] STANDBY_PW_SEL_INT_WRT
1187 * If AON_PMCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to
1188 * FLASH:CFG.STANDBY_PW_SEL by flash device driver FW when a flash write
1189 * operation is initiated. */
1190 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_M 0x60000000
1191 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_S 29
1193 /* Field: [28] DIS_STANDBY_INT_WRT
1195 * If AON_PMCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to
1196 * FLASH:CFG.DIS_STANDBY by flash device driver FW when a flash write operation
1198 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_M 0x10000000
1200 /* Field: [27] DIS_IDLE_INT_WRT
1202 * If AON_PMCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to
1203 * FLASH:CFG.DIS_IDLE by flash device driver FW when a flash write operation is
1205 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_M 0x08000000
1206 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_S 27
1208 /* Field: [26:24] VIN_AT_X_INT_WRT
1210 * If AON_PMCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to
1211 * FLASH:FSEQPMP.VIN_AT_X by flash device driver FW when a flash write
1212 * operation is initiated. */
1213 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_M 0x07000000
1214 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_S 24
1216 /* Field: [23] STANDBY_MODE_SEL_EXT_WRT
1218 * If AON_PMCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to
1219 * FLASH:CFG.STANDBY_MODE_SEL by flash device driver FW when a flash write
1220 * operation is initiated. */
1221 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_M 0x00800000
1222 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_S 23
1224 /* Field: [22:21] STANDBY_PW_SEL_EXT_WRT
1226 * If AON_PMCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to
1227 * FLASH:CFG.STANDBY_PW_SEL by flash device driver FW when a flash write
1228 * operation is initiated. */
1229 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_M 0x00600000
1230 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_S 21
1232 /* Field: [20] DIS_STANDBY_EXT_WRT
1234 * If AON_PMCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to
1235 * FLASH:CFG.DIS_STANDBY by flash device driver FW when a flash write operation
1237 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_M 0x00100000
1239 /* Field: [19] DIS_IDLE_EXT_WRT
1241 * If AON_PMCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to
1242 * FLASH:CFG.DIS_IDLE by flash device driver FW when a flash write operation is
1244 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_M 0x00080000
1245 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_S 19
1247 /* Field: [18:16] VIN_AT_X_EXT_WRT
1249 * If AON_PMCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to
1250 * FLASH:FSEQPMP.VIN_AT_X by flash device driver FW when a flash write
1251 * operation is initiated. */
1252 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_M 0x00070000
1253 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_S 16
1255 /* Field: [15] STANDBY_MODE_SEL_INT_RD
1257 * If AON_PMCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to
1258 * FLASH:CFG.STANDBY_MODE_SEL both by boot FW while in safezone, and by flash
1259 * device driver FW after completion of a flash write operation. */
1260 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M 0x00008000
1261 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S 15
1263 /* Field: [14:13] STANDBY_PW_SEL_INT_RD
1265 * If AON_PMCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to
1266 * FLASH:CFG.STANDBY_PW_SEL both by boot FW while in safezone, and by flash
1267 * device driver FW after completion of a flash write operation. */
1268 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M 0x00006000
1269 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S 13
1271 /* Field: [12] DIS_STANDBY_INT_RD
1273 * If AON_PMCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to
1274 * FLASH:CFG.DIS_STANDBY both by boot FW while in safezone, and by flash device
1275 * driver FW after completion of a flash write operation. */
1276 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M 0x00001000
1278 /* Field: [11] DIS_IDLE_INT_RD
1280 * If AON_PMCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to
1281 * FLASH:CFG.DIS_IDLE both by boot FW while in safezone, and by flash device
1282 * driver FW after completion of a flash write operation. */
1283 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_M 0x00000800
1284 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_S 11
1286 /* Field: [10:8] VIN_AT_X_INT_RD
1288 * If AON_PMCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to
1289 * FLASH:FSEQPMP.VIN_AT_X both by boot FW while in safezone, and by flash
1290 * device driver FW after completion of a flash write operation. */
1291 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M 0x00000700
1292 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S 8
1294 /* Field: [7] STANDBY_MODE_SEL_EXT_RD
1296 * If AON_PMCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to
1297 * FLASH:CFG.STANDBY_MODE_SEL both by boot FW while in safezone, and by flash
1298 * device driver FW after completion of a flash write operation. */
1299 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M 0x00000080
1300 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S 7
1302 /* Field: [6:5] STANDBY_PW_SEL_EXT_RD
1304 * If AON_PMCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to
1305 * FLASH:CFG.STANDBY_PW_SEL both by boot FW while in safezone, and by flash
1306 * device driver FW after completion of a flash write operation. */
1307 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M 0x00000060
1308 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S 5
1310 /* Field: [4] DIS_STANDBY_EXT_RD
1312 * If AON_PMCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to
1313 * FLASH:CFG.DIS_STANDBY both by boot FW while in safezone, and by flash device
1314 * driver FW after completion of a flash write operation. */
1315 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M 0x00000010
1317 /* Field: [3] DIS_IDLE_EXT_RD
1319 * If AON_PMCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to
1320 * FLASH:CFG.DIS_IDLE both by boot FW while in safezone, and by flash device
1321 * driver FW after completion of a flash write operation. */
1322 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_M 0x00000008
1323 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_S 3
1325 /* Field: [2:0] VIN_AT_X_EXT_RD
1327 * If AON_PMCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to
1328 * FLASH:FSEQPMP.VIN_AT_X both by boot FW while in safezone, and by flash
1329 * device driver FW after completion of a flash write operation. */
1330 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M 0x00000007
1331 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S 0
1333 /******************************************************************************
1335 * This section defines the register offsets of AON_PMCTL component
1337 ******************************************************************************/
1339 /* Power Management Control */
1340 #if defined(DEVICE_CC26X2)
1341 /* Agama (CC26x2) specific definition */
1342 #define AON_PMCTL_O_PWRCTL 0x00000010
1343 #elif defined(DEVICE_CC26X0)
1344 /* Chameleon (CC26x0) specific definition */
1345 #define AON_PMCTL_O_PWRCTL 0x00000000
1348 /* Field: [1] EXT_REG_MODE
1350 * Status of source for VDDRsupply:
1352 * 0: DCDC or GLDO are generating VDDR
1353 * 1: DCDC and GLDO are bypassed and an external regulator supplies VDDR */
1354 #define AON_PMCTL_PWRCTL_EXT_REG_MODE 0x00000002
1356 #endif /* #ifndef OPENOCD_LOADERS_FLASH_CC26XX_HW_REGS_H */