1 /* SPDX-License-Identifier: BSD-3-Clause */
3 /******************************************************************************
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
7 ******************************************************************************/
13 /******************************************************************************
15 * Defines for accesses to the security control in the customer configuration
16 * area in flash top sector.
18 ******************************************************************************/
19 #define CCFG_OFFSET_SECURITY CCFG_O_BL_CONFIG
20 #define CCFG_SIZE_SECURITY 0x00000014
22 /******************************************************************************
24 * Default values for security control in customer configuration area in flash
27 ******************************************************************************/
28 const uint8_t g_ccfg_default_sec[] = {
29 0xFF, 0xFF, 0xFF, 0xC5,
30 0xFF, 0xFF, 0xFF, 0xFF,
31 0xC5, 0xFF, 0xFF, 0xFF,
32 0xC5, 0xC5, 0xC5, 0xFF,
33 0xC5, 0xC5, 0xC5, 0xFF
36 typedef uint32_t (*flash_prg_pntr_t) (uint8_t *, uint32_t, uint32_t);
37 typedef uint32_t (*flash_sector_erase_pntr_t) (uint32_t);
39 /******************************************************************************
41 * Function prototypes for static functions
43 ******************************************************************************/
44 static void issue_fsm_command(flash_state_command_t command);
45 static void enable_sectors_for_write(void);
46 static uint32_t scale_cycle_values(uint32_t specified_timing,
47 uint32_t scale_value);
48 static void set_write_mode(void);
49 static void trim_for_write(void);
50 static void set_read_mode(void);
52 /******************************************************************************
54 * Erase a flash sector
56 ******************************************************************************/
57 uint32_t flash_sector_erase(uint32_t sector_address)
59 uint32_t error_return;
60 flash_sector_erase_pntr_t func_pntr;
62 /* Call ROM function */
63 func_pntr = (uint32_t (*)(uint32_t))(ROM_API_FLASH_TABLE[5]);
64 error_return = func_pntr(sector_address);
66 /* Enable standby because ROM function might have disabled it */
67 HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN) = 0;
69 /* Return status of operation. */
73 /******************************************************************************
75 * Erase all unprotected sectors in the flash main bank
77 ******************************************************************************/
78 uint32_t flash_bank_erase(bool force_precondition)
80 uint32_t error_return;
81 uint32_t sector_address;
84 /* Enable all sectors for erase. */
85 enable_sectors_for_write();
87 /* Clear the Status register. */
88 issue_fsm_command(FAPI_CLEAR_STATUS);
90 /* Enable erase of all sectors and enable precondition if required. */
91 reg_val = HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE);
92 HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE;
93 HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0x00000000;
94 HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0x00000000;
95 if (force_precondition)
96 HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |=
97 FLASH_FSM_ST_MACHINE_DO_PRECOND;
98 HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE;
100 /* Issue the bank erase command to the FSM. */
101 issue_fsm_command(FAPI_ERASE_BANK);
103 /* Wait for erase to finish. */
104 while (flash_check_fsm_for_ready() == FAPI_STATUS_FSM_BUSY)
108 error_return = flash_check_fsm_for_error();
110 /* Disable sectors for erase. */
111 flash_disable_sectors_for_write();
113 /* Set configured precondition mode since it may have been forced on. */
114 if (!(reg_val & FLASH_FSM_ST_MACHINE_DO_PRECOND)) {
115 HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE;
116 HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &=
117 ~FLASH_FSM_ST_MACHINE_DO_PRECOND;
118 HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE;
121 /* Program security data to default values in the customer configuration */
122 /* area within the flash top sector if erase was successful. */
123 if (error_return == FAPI_STATUS_SUCCESS) {
124 sector_address = FLASHMEM_BASE + flash_size_get() -
125 flash_sector_size_get();
126 error_return = flash_program((uint8_t *)g_ccfg_default_sec,
127 (sector_address + CCFG_OFFSET_SECURITY),
131 /* Return status of operation. */
135 /******************************************************************************
137 * Programs unprotected main bank flash sectors
139 ******************************************************************************/
140 uint32_t flash_program(uint8_t *data_buffer, uint32_t address, uint32_t count)
142 uint32_t error_return;
143 flash_prg_pntr_t func_pntr;
145 /* Call ROM function */
146 func_pntr = (uint32_t (*)(uint8_t *, uint32_t, uint32_t))
147 (ROM_API_FLASH_TABLE[6]);
148 error_return = func_pntr(data_buffer, address, count);
150 /* Enable standby because ROM function might have disabled it */
151 HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN) = 0;
153 /* Return status of operation. */
157 /******************************************************************************
159 * Disables all sectors for erase and programming on the active bank
161 ******************************************************************************/
162 void flash_disable_sectors_for_write(void)
164 /* Configure flash back to read mode */
167 /* Disable Level 1 Protection. */
168 HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS;
170 /* Disable all sectors for erase and programming. */
171 HWREG(FLASH_BASE + FLASH_O_FBSE) = 0x0000;
173 /* Enable Level 1 Protection. */
174 HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0;
176 /* Protect sectors from sector erase. */
177 HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE;
178 HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0xFFFFFFFF;
179 HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0xFFFFFFFF;
180 HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE;
183 /******************************************************************************
185 * Issues a command to the Flash State Machine.
187 ******************************************************************************/
188 static void issue_fsm_command(flash_state_command_t command)
190 /* Enable write to FSM register. */
191 HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE;
193 /* Issue FSM command. */
194 HWREG(FLASH_BASE + FLASH_O_FSM_CMD) = command;
196 /* Start command execute. */
197 HWREG(FLASH_BASE + FLASH_O_FSM_EXECUTE) = FLASH_CMD_EXEC;
199 /* Disable write to FSM register. */
200 HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE;
203 /******************************************************************************
205 * Enables all sectors for erase and programming on the active bank.
207 * This function disables the idle reading power reduction mode, selects the
208 * flash bank and enables all sectors for erase and programming on the active
210 * Sectors may be protected from programming depending on the value of the
211 * FLASH_O_FSM_BSLPx registers.
212 * Sectors may be protected from erase depending on the value of the
213 * FLASH_O_FSM_BSLEx registers. Additional sector erase protection is set by
214 * the FLASH_O_FSM_SECTOR1 register.
216 ******************************************************************************/
217 static void enable_sectors_for_write(void)
219 /* Trim flash module for program/erase operation. */
222 /* Configure flash to write mode */
225 /* Select flash bank. */
226 HWREG(FLASH_BASE + FLASH_O_FMAC) = 0x00;
228 /* Disable Level 1 Protection. */
229 HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS;
231 /* Enable all sectors for erase and programming. */
232 HWREG(FLASH_BASE + FLASH_O_FBSE) = 0xFFFF;
234 /* Enable Level 1 Protection */
235 HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0;
238 /******************************************************************************
240 * Trims the Flash Bank and Flash Pump for program/erase functionality
242 * This trimming will make it possible to perform erase and program operations
243 * of the flash. Trim values are loaded from factory configuration area
244 * (referred to as FCGF1). The trimming done by this function is valid until
245 * reset of the flash module.
247 * Some registers shall be written with a value that is a number of FCLK
248 * cycles. The trim values controlling these registers have a value of
249 * number of half us. FCLK = SysClk / ((RWAIT+1) x 2).
251 ******************************************************************************/
252 static void trim_for_write(void)
259 /* Return if flash is already trimmed for program/erase operations. */
260 if (HWREG(FLASH_BASE + FLASH_O_FWFLAG) & FW_WRT_TRIMMED)
263 /* Configure the FSM registers */
265 /* Enable access to the FSM registers. */
266 HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE;
268 /* Determine the scaling value to be used on timing related trim values. */
269 /* The value is based on the flash module clock frequency and RWAIT */
270 rwait = (HWREG(FLASH_BASE + FLASH_O_FRDCTL) &
271 FLASH_FRDCTL_RWAIT_M) >> FLASH_FRDCTL_RWAIT_S;
272 fclk_scale = (16 * FLASH_MODULE_CLK_FREQ) / (rwait + 1);
274 /* Configure Program pulse width bits 15:0. */
275 /* (FCFG1 offset 0x188 bits 15:0). */
276 value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_PROG_EP) &
277 FCFG1_FLASH_PROG_EP_PROGRAM_PW_M) >>
278 FCFG1_FLASH_PROG_EP_PROGRAM_PW_S;
280 value = scale_cycle_values(value, fclk_scale);
282 HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PW) =
283 (HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PW) &
284 ~FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_M) |
285 ((value << FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_S) &
286 FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_M);
288 /* Configure Erase pulse width bits 31:0. */
289 /* (FCFG1 offset 0x18C bits 31:0). */
290 value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_ERA_PW) &
291 FCFG1_FLASH_ERA_PW_ERASE_PW_M) >>
292 FCFG1_FLASH_ERA_PW_ERASE_PW_S;
294 value = scale_cycle_values(value, fclk_scale);
296 HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PW) =
297 (HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PW) &
298 ~FLASH_FSM_ERA_PW_FSM_ERA_PW_M) |
299 ((value << FLASH_FSM_ERA_PW_FSM_ERA_PW_S) &
300 FLASH_FSM_ERA_PW_FSM_ERA_PW_M);
302 /* Configure no of flash clock cycles from EXECUTEZ going low to the the
303 verify data can be read in the program verify mode bits 7:0. */
304 /* (FCFG1 offset 0x174 bits 23:16). */
305 value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_C_E_P_R) &
306 FCFG1_FLASH_C_E_P_R_PV_ACCESS_M) >>
307 FCFG1_FLASH_C_E_P_R_PV_ACCESS_S;
309 value = scale_cycle_values(value, fclk_scale);
311 HWREG(FLASH_BASE + FLASH_O_FSM_EX_VAL) =
312 (HWREG(FLASH_BASE + FLASH_O_FSM_EX_VAL) &
313 ~FLASH_FSM_EX_VAL_EXE_VALD_M) |
314 ((value << FLASH_FSM_EX_VAL_EXE_VALD_S) &
315 FLASH_FSM_EX_VAL_EXE_VALD_M);
317 /* Configure the number of flash clocks from the start of the Read mode at
318 the end of the operations until the FSM clears the BUSY bit in FMSTAT. */
319 /* (FCFG1 offset 0x178 bits 23:16). */
320 value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_P_R_PV) &
321 FCFG1_FLASH_P_R_PV_RH_M) >>
322 FCFG1_FLASH_P_R_PV_RH_S;
324 HWREG(FLASH_BASE + FLASH_O_FSM_RD_H) =
325 (HWREG(FLASH_BASE + FLASH_O_FSM_RD_H) &
326 ~FLASH_FSM_RD_H_RD_H_M) |
327 ((value << FLASH_FSM_RD_H_RD_H_S) &
328 FLASH_FSM_RD_H_RD_H_M);
330 /* Configure Program hold time */
331 /* (FCFG1 offset 0x178 bits 31:24). */
332 value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_P_R_PV) &
333 FCFG1_FLASH_P_R_PV_PH_M) >>
334 FCFG1_FLASH_P_R_PV_PH_S;
336 value = scale_cycle_values(value, fclk_scale);
338 HWREG(FLASH_BASE + FLASH_O_FSM_P_OH) =
339 (HWREG(FLASH_BASE + FLASH_O_FSM_P_OH) &
340 ~FLASH_FSM_P_OH_PGM_OH_M) |
341 ((value << FLASH_FSM_P_OH_PGM_OH_S) &
342 FLASH_FSM_P_OH_PGM_OH_M);
344 /* Configure Erase hold time */
345 /* (FCFG1 offset 0x17C bits 31:24). */
346 value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_EH_SEQ) &
347 FCFG1_FLASH_EH_SEQ_EH_M) >>
348 FCFG1_FLASH_EH_SEQ_EH_S;
350 value = scale_cycle_values(value, fclk_scale);
352 HWREG(FLASH_BASE + FLASH_O_FSM_ERA_OH) =
353 (HWREG(FLASH_BASE + FLASH_O_FSM_ERA_OH) &
354 ~FLASH_FSM_ERA_OH_ERA_OH_M) |
355 ((value << FLASH_FSM_ERA_OH_ERA_OH_S) &
356 FLASH_FSM_ERA_OH_ERA_OH_M);
358 /* Configure Program verify row switch time */
359 /* (FCFG1 offset0x178 bits 15:8). */
360 value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_P_R_PV) &
361 FCFG1_FLASH_P_R_PV_PVH_M) >>
362 FCFG1_FLASH_P_R_PV_PVH_S;
364 value = scale_cycle_values(value, fclk_scale);
366 HWREG(FLASH_BASE + FLASH_O_FSM_PE_VH) =
367 (HWREG(FLASH_BASE + FLASH_O_FSM_PE_VH) &
368 ~FLASH_FSM_PE_VH_PGM_VH_M) |
369 ((value << FLASH_FSM_PE_VH_PGM_VH_S) &
370 FLASH_FSM_PE_VH_PGM_VH_M);
372 /* Configure Program Operation Setup time */
373 /* (FCFG1 offset 0x170 bits 31:24). */
374 value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_E_P) &
375 FCFG1_FLASH_E_P_PSU_M) >>
376 FCFG1_FLASH_E_P_PSU_S;
378 HWREG(FLASH_BASE + FLASH_O_FSM_PE_OSU) =
379 (HWREG(FLASH_BASE + FLASH_O_FSM_PE_OSU) &
380 ~FLASH_FSM_PE_OSU_PGM_OSU_M) |
381 ((value << FLASH_FSM_PE_OSU_PGM_OSU_S) &
382 FLASH_FSM_PE_OSU_PGM_OSU_M);
384 /* Configure Erase Operation Setup time */
385 /* (FCGF1 offset 0x170 bits 23:16). */
386 value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_E_P) &
387 FCFG1_FLASH_E_P_ESU_M) >>
388 FCFG1_FLASH_E_P_ESU_S;
390 HWREG(FLASH_BASE + FLASH_O_FSM_PE_OSU) =
391 (HWREG(FLASH_BASE + FLASH_O_FSM_PE_OSU) &
392 ~FLASH_FSM_PE_OSU_ERA_OSU_M) |
393 ((value << FLASH_FSM_PE_OSU_ERA_OSU_S) &
394 FLASH_FSM_PE_OSU_ERA_OSU_M);
396 /* Confgure Program Verify Setup time */
397 /* (FCFG1 offset 0x170 bits 15:8). */
398 value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_E_P) &
399 FCFG1_FLASH_E_P_PVSU_M) >>
400 FCFG1_FLASH_E_P_PVSU_S;
402 HWREG(FLASH_BASE + FLASH_O_FSM_PE_VSU) =
403 (HWREG(FLASH_BASE + FLASH_O_FSM_PE_VSU) &
404 ~FLASH_FSM_PE_VSU_PGM_VSU_M) |
405 ((value << FLASH_FSM_PE_VSU_PGM_VSU_S) &
406 FLASH_FSM_PE_VSU_PGM_VSU_M);
408 /* Configure Erase Verify Setup time */
409 /* (FCFG1 offset 0x170 bits 7:0). */
410 value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_E_P) &
411 FCFG1_FLASH_E_P_EVSU_M) >>
412 FCFG1_FLASH_E_P_EVSU_S;
414 HWREG(FLASH_BASE + FLASH_O_FSM_PE_VSU) =
415 (HWREG(FLASH_BASE + FLASH_O_FSM_PE_VSU) &
416 ~FLASH_FSM_PE_VSU_ERA_VSU_M) |
417 ((value << FLASH_FSM_PE_VSU_ERA_VSU_S) &
418 FLASH_FSM_PE_VSU_ERA_VSU_M);
420 /* Configure Addr to EXECUTEZ low setup time */
421 /* (FCFG1 offset 0x174 bits 15:12). */
422 value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_C_E_P_R) &
423 FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_M) >>
424 FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_S;
426 HWREG(FLASH_BASE + FLASH_O_FSM_CMP_VSU) =
427 (HWREG(FLASH_BASE + FLASH_O_FSM_CMP_VSU) &
428 ~FLASH_FSM_CMP_VSU_ADD_EXZ_M) |
429 ((value << FLASH_FSM_CMP_VSU_ADD_EXZ_S) &
430 FLASH_FSM_CMP_VSU_ADD_EXZ_M);
432 /* Configure Voltage Status Count */
433 /* (FCFG1 offset 0x17C bits 15:12). */
434 value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_EH_SEQ) &
435 FCFG1_FLASH_EH_SEQ_VSTAT_M) >>
436 FCFG1_FLASH_EH_SEQ_VSTAT_S;
438 HWREG(FLASH_BASE + FLASH_O_FSM_VSTAT) =
439 (HWREG(FLASH_BASE + FLASH_O_FSM_VSTAT) &
440 ~FLASH_FSM_VSTAT_VSTAT_CNT_M) |
441 ((value << FLASH_FSM_VSTAT_VSTAT_CNT_S) &
442 FLASH_FSM_VSTAT_VSTAT_CNT_M);
444 /* Configure Repeat Verify action setup */
445 /* (FCFG1 offset 0x174 bits 31:24). */
446 value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_C_E_P_R) &
447 FCFG1_FLASH_C_E_P_R_RVSU_M) >>
448 FCFG1_FLASH_C_E_P_R_RVSU_S;
450 HWREG(FLASH_BASE + FLASH_O_FSM_EX_VAL) =
451 (HWREG(FLASH_BASE + FLASH_O_FSM_EX_VAL) &
452 ~FLASH_FSM_EX_VAL_REP_VSU_M) |
453 ((value << FLASH_FSM_EX_VAL_REP_VSU_S) &
454 FLASH_FSM_EX_VAL_REP_VSU_M);
456 /* Configure Maximum Programming Pulses */
457 /* (FCFG1 offset 0x184 bits 15:0). */
458 value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_PP) &
459 FCFG1_FLASH_PP_MAX_PP_M) >>
460 FCFG1_FLASH_PP_MAX_PP_S;
462 HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PUL) =
463 (HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PUL) &
464 ~FLASH_FSM_PRG_PUL_MAX_PRG_PUL_M) |
465 ((value << FLASH_FSM_PRG_PUL_MAX_PRG_PUL_S) &
466 FLASH_FSM_PRG_PUL_MAX_PRG_PUL_M);
468 /* Configure Beginning level for VHVCT used during erase modes */
469 /* (FCFG1 offset 0x180 bits 31:16). */
470 value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_VHV_E) &
471 FCFG1_FLASH_VHV_E_VHV_E_START_M) >>
472 FCFG1_FLASH_VHV_E_VHV_E_START_S;
474 HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PUL) =
475 (HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PUL) &
476 ~FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_M) |
477 ((value << FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_S) &
478 FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_M);
480 /* Configure Maximum EC Level */
481 /* (FCFG1 offset 0x2B0 bits 21:18). */
482 value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA3) &
483 FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_M) >>
484 FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_S;
486 HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PUL) =
487 (HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PUL) &
488 ~FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_M) |
489 ((value << FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_S) &
490 FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_M);
492 /* Configure Maximum Erase Pulses */
493 /* (FCFG1 offset 0x188 bits 31:16). */
494 value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_PROG_EP) &
495 FCFG1_FLASH_PROG_EP_MAX_EP_M) >>
496 FCFG1_FLASH_PROG_EP_MAX_EP_S;
498 HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PUL) =
499 (HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PUL) &
500 ~FLASH_FSM_ERA_PUL_MAX_ERA_PUL_M) |
501 ((value << FLASH_FSM_ERA_PUL_MAX_ERA_PUL_S) &
502 FLASH_FSM_ERA_PUL_MAX_ERA_PUL_M);
504 /* Configure the VHVCT Step Size. This is the number of erase pulses that
505 must be completed for each level before the FSM increments the
506 CUR_EC_LEVEL to the next higher level. Actual erase pulses per level
507 equals (EC_STEP_SIZE +1). The stepping is only needed for the VHVCT
509 /* (FCFG1 offset 0x2B0 bits 31:23). */
510 value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA3) &
511 FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_M) >>
512 FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_S;
514 HWREG(FLASH_BASE + FLASH_O_FSM_STEP_SIZE) =
515 (HWREG(FLASH_BASE + FLASH_O_FSM_STEP_SIZE) &
516 ~FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_M) |
517 ((value << FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_S) &
518 FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_M);
520 /* Configure the hight of each EC step. This is the number of counts that
521 the CUR_EC_LEVEL will increment when going to a new level. Actual count
522 size equals (EC_STEP_HEIGHT + 1). The stepping applies only to the VHVCT
524 The read trim value is decremented by 1 before written to the register
525 since actual counts equals (register value + 1). */
526 /* (FCFG1 offset 0x180 bits 15:0). */
527 value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_VHV_E) &
528 FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_M) >>
529 FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_S;
531 HWREG(FLASH_BASE + FLASH_O_FSM_EC_STEP_HEIGHT) = ((value - 1) &
532 FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_M);
534 /* Configure Precondition used in erase operations */
535 /* (FCFG1 offset 0x2B0 bit 22). */
536 value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA3) &
537 FCFG1_FLASH_OTP_DATA3_DO_PRECOND_M) >>
538 FCFG1_FLASH_OTP_DATA3_DO_PRECOND_S;
540 HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) =
541 (HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &
542 ~FLASH_FSM_ST_MACHINE_DO_PRECOND_M) |
543 ((value << FLASH_FSM_ST_MACHINE_DO_PRECOND_S) &
544 FLASH_FSM_ST_MACHINE_DO_PRECOND_M);
546 /* Enable the recommended Good Time function. */
547 HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |=
548 FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD;
550 /* Disable write access to FSM registers. */
551 HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE;
553 /* Configure the voltage registers */
555 /* Unlock voltage registers (0x2080 - 0x2098). */
556 HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA;
558 /* Configure voltage level for the specified pump voltage of high
559 voltage supply input during erase operation VHVCT_E and TRIM13_E */
560 /* (FCFG1 offset 0x190 bits[3:0] and bits[11:8]). */
561 temp_val = HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_VHV);
563 value = ((temp_val & FCFG1_FLASH_VHV_TRIM13_E_M)>>
564 FCFG1_FLASH_VHV_TRIM13_E_S) << FLASH_FVHVCT1_TRIM13_E_S;
565 value |= ((temp_val & FCFG1_FLASH_VHV_VHV_E_M)>>
566 FCFG1_FLASH_VHV_VHV_E_S) << FLASH_FVHVCT1_VHVCT_E_S;
568 HWREG(FLASH_BASE + FLASH_O_FVHVCT1) = (HWREG(FLASH_BASE + FLASH_O_FVHVCT1) &
569 ~(FLASH_FVHVCT1_TRIM13_E_M | FLASH_FVHVCT1_VHVCT_E_M)) | value;
571 /* Configure voltage level for the specified pump voltage of high voltage
572 supply input during program verify operation VHVCT_PV and TRIM13_PV */
573 /* (OTP offset 0x194 bits[19:16] and bits[27:24]). */
574 temp_val = HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_VHV_PV);
576 value = ((temp_val & FCFG1_FLASH_VHV_PV_TRIM13_PV_M) >>
577 FCFG1_FLASH_VHV_PV_TRIM13_PV_S) << FLASH_FVHVCT1_TRIM13_PV_S;
578 value |= ((temp_val & FCFG1_FLASH_VHV_PV_VHV_PV_M) >>
579 FCFG1_FLASH_VHV_PV_VHV_PV_S) << FLASH_FVHVCT1_VHVCT_PV_S;
581 HWREG(FLASH_BASE + FLASH_O_FVHVCT1) = (HWREG(FLASH_BASE + FLASH_O_FVHVCT1) &
582 ~(FLASH_FVHVCT1_TRIM13_PV_M | FLASH_FVHVCT1_VHVCT_PV_M)) | value;
584 /* Configure voltage level for the specified pump voltage of high voltage
585 supply input during program operation VHVCT_P and TRIM13_P */
586 /* (FCFG1 offset 0x190 bits[19:16] and bits[27:24]). */
587 temp_val = HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_VHV);
589 value = ((temp_val & FCFG1_FLASH_VHV_TRIM13_P_M) >>
590 FCFG1_FLASH_VHV_TRIM13_P_S) << FLASH_FVHVCT2_TRIM13_P_S;
591 value |= ((temp_val & FCFG1_FLASH_VHV_VHV_P_M) >>
592 FCFG1_FLASH_VHV_VHV_P_S) << FLASH_FVHVCT2_VHVCT_P_S;
594 HWREG(FLASH_BASE + FLASH_O_FVHVCT2) = (HWREG(FLASH_BASE + FLASH_O_FVHVCT2) &
595 ~(FLASH_FVHVCT2_TRIM13_P_M | FLASH_FVHVCT2_VHVCT_P_M)) | value;
597 /* Configure voltage level for the specified pump voltage of wordline power
598 supply for read mode */
599 /* (FCFG1 offset 0x198 Bits 15:8). */
600 value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_V) &
601 FCFG1_FLASH_V_V_READ_M) >> FCFG1_FLASH_V_V_READ_S;
603 HWREG(FLASH_BASE + FLASH_O_FVREADCT) =
604 (HWREG(FLASH_BASE + FLASH_O_FVREADCT) &
605 ~FLASH_FVREADCT_VREADCT_M) |
606 ((value << FLASH_FVREADCT_VREADCT_S) &
607 FLASH_FVREADCT_VREADCT_M);
609 /* Configure the voltage level for the VCG 2.5 CT pump voltage */
610 /* (FCFG1 offset 0x194 bits 15:8). */
611 value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_VHV_PV) &
612 FCFG1_FLASH_VHV_PV_VCG2P5_M) >>
613 FCFG1_FLASH_VHV_PV_VCG2P5_S;
615 HWREG(FLASH_BASE + FLASH_O_FVNVCT) =
616 (HWREG(FLASH_BASE + FLASH_O_FVNVCT) &
617 ~FLASH_FVNVCT_VCG2P5CT_M) |
618 ((value << FLASH_FVNVCT_VCG2P5CT_S) &
619 FLASH_FVNVCT_VCG2P5CT_M);
621 /* Configure the voltage level for the specified pump voltage of high
622 current power input during program operation */
623 /* (FCFG1 offset 0x198 bits 31:24). */
624 value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_V) &
625 FCFG1_FLASH_V_VSL_P_M) >>
626 FCFG1_FLASH_V_VSL_P_S;
628 HWREG(FLASH_BASE + FLASH_O_FVSLP) =
629 (HWREG(FLASH_BASE + FLASH_O_FVSLP) &
630 ~FLASH_FVSLP_VSL_P_M) |
631 ((value << FLASH_FVSLP_VSL_P_S) &
632 FLASH_FVSLP_VSL_P_M);
634 /* Configure the voltage level for the specified pump voltage of wordline
635 power supply during programming operations */
636 /* (OTP offset 0x198 bits 23:16). */
637 value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_V) &
638 FCFG1_FLASH_V_VWL_P_M) >>
639 FCFG1_FLASH_V_VWL_P_S;
641 HWREG(FLASH_BASE + FLASH_O_FVWLCT) =
642 (HWREG(FLASH_BASE + FLASH_O_FVWLCT) &
643 ~FLASH_FVWLCT_VWLCT_P_M) |
644 ((value << FLASH_FVWLCT_VWLCT_P_S) &
645 FLASH_FVWLCT_VWLCT_P_M);
647 /* Configure the pump's TRIM_1P7 port pins. */
648 /* (FCFG1 offset 0x2B0 bits 17:16). */
649 value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA3) &
650 FCFG1_FLASH_OTP_DATA3_TRIM_1P7_M) >>
651 FCFG1_FLASH_OTP_DATA3_TRIM_1P7_S;
653 HWREG(FLASH_BASE + FLASH_O_FSEQPMP) =
654 (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) &
655 ~FLASH_FSEQPMP_TRIM_1P7_M) |
656 ((value << FLASH_FSEQPMP_TRIM_1P7_S) &
657 FLASH_FSEQPMP_TRIM_1P7_M);
659 /* Lock the voltage registers. */
660 HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA;
662 /* Set trimmed flag. */
663 HWREG(FLASH_BASE + FLASH_O_FWLOCK) = 5;
664 HWREG(FLASH_BASE + FLASH_O_FWFLAG) |= FW_WRT_TRIMMED;
665 HWREG(FLASH_BASE + FLASH_O_FWLOCK) = 0;
668 /******************************************************************************
670 * Used to scale the TI OTP values based on the FClk scaling value.
672 ******************************************************************************/
673 static uint32_t scale_cycle_values(uint32_t specified_timing,
674 uint32_t scale_value)
676 uint32_t scaled_value = (specified_timing * scale_value) >> 6;
680 /******************************************************************************
682 * Used to set flash in read mode.
684 * Flash is configured with values loaded from OTP dependent on the current
687 ******************************************************************************/
688 static void set_read_mode(void)
693 /* Configure the STANDBY_MODE_SEL, STANDBY_PW_SEL, DIS_STANDBY, DIS_IDLE,
694 VIN_AT_X and VIN_BY_PASS for read mode */
695 if (HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) &
696 AON_PMCTL_PWRCTL_EXT_REG_MODE) {
698 /* Select trim values for external regulator mode:
699 Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 7)
700 Configure STANDBY_PW_SEL (OTP offset 0x308 bit 6:5)
701 Must be done while the register bit field CONFIG.DIS_STANDBY = 1 */
702 HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY;
705 HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4);
707 value = ((trim_value &
708 FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M) >>
709 FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S) <<
710 FLASH_CFG_STANDBY_MODE_SEL_S;
712 value |= ((trim_value &
713 FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M) >>
714 FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S) <<
715 FLASH_CFG_STANDBY_PW_SEL_S;
717 /* Configure DIS_STANDBY (OTP offset 0x308 bit 4).
718 Configure DIS_IDLE (OTP offset 0x308 bit 3). */
719 value |= ((trim_value &
720 (FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M |
721 FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_M)) >>
722 FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_S) <<
723 FLASH_CFG_DIS_IDLE_S;
725 HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) &
726 ~(FLASH_CFG_STANDBY_MODE_SEL_M | FLASH_CFG_STANDBY_PW_SEL_M |
727 FLASH_CFG_DIS_STANDBY_M | FLASH_CFG_DIS_IDLE_M)) | value;
729 /* Check if sample and hold functionality is disabled. */
730 if (HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE) {
731 /* Wait for disabled sample and hold functionality to be stable. */
732 while (!(HWREG(FLASH_BASE+FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS))
736 /* Configure VIN_AT_X (OTP offset 0x308 bits 2:0) */
737 value = ((trim_value &
738 FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M) >>
739 FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S) <<
740 FLASH_FSEQPMP_VIN_AT_X_S;
742 /* Configure VIN_BY_PASS which is dependent on the VIN_AT_X value.
743 If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise
744 VIN_BY_PASS should be 1 */
745 if (((value & FLASH_FSEQPMP_VIN_AT_X_M) >>
746 FLASH_FSEQPMP_VIN_AT_X_S) != 0x7)
747 value |= FLASH_FSEQPMP_VIN_BY_PASS;
749 HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA;
750 HWREG(FLASH_BASE + FLASH_O_FSEQPMP) =
751 (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) &
752 ~(FLASH_FSEQPMP_VIN_BY_PASS_M |
753 FLASH_FSEQPMP_VIN_AT_X_M)) | value;
754 HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA;
757 /* Select trim values for internal regulator mode:
758 Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 15)
759 COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 14:13)
760 Must be done while the register bit field CONFIG.DIS_STANDBY = 1 */
761 HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY;
764 HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4);
766 value = ((trim_value &
767 FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M) >>
768 FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S) <<
769 FLASH_CFG_STANDBY_MODE_SEL_S;
771 value |= ((trim_value &
772 FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M) >>
773 FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S) <<
774 FLASH_CFG_STANDBY_PW_SEL_S;
776 /* Configure DIS_STANDBY (OTP offset 0x308 bit 12).
777 Configure DIS_IDLE (OTP offset 0x308 bit 11). */
778 value |= ((trim_value &
779 (FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M |
780 FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_M)) >>
781 FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_S) <<
782 FLASH_CFG_DIS_IDLE_S;
784 HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) &
785 ~(FLASH_CFG_STANDBY_MODE_SEL_M | FLASH_CFG_STANDBY_PW_SEL_M |
786 FLASH_CFG_DIS_STANDBY_M | FLASH_CFG_DIS_IDLE_M)) | value;
788 /* Check if sample and hold functionality is disabled. */
789 if (HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE) {
790 /* Wait for disabled sample and hold functionality to be stable. */
791 while (!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS))
795 /* Configure VIN_AT_X (OTP offset 0x308 bits 10:8) */
796 value = (((trim_value &
797 FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M) >>
798 FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S) <<
799 FLASH_FSEQPMP_VIN_AT_X_S);
801 /* Configure VIN_BY_PASS which is dependent on the VIN_AT_X value.
802 If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise
803 VIN_BY_PASS should be 1 */
804 if (((value & FLASH_FSEQPMP_VIN_AT_X_M) >>
805 FLASH_FSEQPMP_VIN_AT_X_S) != 0x7)
806 value |= FLASH_FSEQPMP_VIN_BY_PASS;
808 HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA;
809 HWREG(FLASH_BASE + FLASH_O_FSEQPMP) =
810 (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) &
811 ~(FLASH_FSEQPMP_VIN_BY_PASS_M |
812 FLASH_FSEQPMP_VIN_AT_X_M)) | value;
813 HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA;
817 /******************************************************************************
819 * Used to set flash in write mode.
821 * Flash is configured with values loaded from OTP dependent on the current
824 ******************************************************************************/
825 static void set_write_mode(void)
830 /* Configure the STANDBY_MODE_SEL, STANDBY_PW_SEL, DIS_STANDBY, DIS_IDLE,
831 VIN_AT_X and VIN_BY_PASS for program/erase mode */
832 if (HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) &
833 AON_PMCTL_PWRCTL_EXT_REG_MODE) {
835 /* Select trim values for external regulator mode:
836 Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 23)
837 Configure STANDBY_PW_SEL (OTP offset 0x308 bit 22:21)
838 Must be done while the register bit field CONFIG.DIS_STANDBY = 1 */
839 HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY;
842 HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4);
844 value = ((trim_value &
845 FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_M) >>
846 FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_S) <<
847 FLASH_CFG_STANDBY_MODE_SEL_S;
849 value |= ((trim_value &
850 FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_M) >>
851 FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_S) <<
852 FLASH_CFG_STANDBY_PW_SEL_S;
854 /* Configure DIS_STANDBY (OTP offset 0x308 bit 20).
855 Configure DIS_IDLE (OTP offset 0x308 bit 19). */
856 value |= ((trim_value &
857 (FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_M |
858 FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_M)) >>
859 FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_S) <<
860 FLASH_CFG_DIS_IDLE_S;
862 HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) &
863 ~(FLASH_CFG_STANDBY_MODE_SEL_M | FLASH_CFG_STANDBY_PW_SEL_M |
864 FLASH_CFG_DIS_STANDBY_M | FLASH_CFG_DIS_IDLE_M)) | value;
866 /* Check if sample and hold functionality is disabled. */
867 if (HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE) {
868 /* Wait for disabled sample and hold functionality to be stable. */
869 while (!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS))
873 /* Configure VIN_AT_X (OTP offset 0x308 bits 18:16) */
874 value = ((trim_value &
875 FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_M) >>
876 FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_S) <<
877 FLASH_FSEQPMP_VIN_AT_X_S;
879 /* Configure VIN_BY_PASS which is dependent on the VIN_AT_X value.
880 If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise
881 VIN_BY_PASS should be 1 */
882 if (((value & FLASH_FSEQPMP_VIN_AT_X_M) >>
883 FLASH_FSEQPMP_VIN_AT_X_S) != 0x7)
884 value |= FLASH_FSEQPMP_VIN_BY_PASS;
886 HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA;
887 HWREG(FLASH_BASE + FLASH_O_FSEQPMP) =
888 (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) &
889 ~(FLASH_FSEQPMP_VIN_BY_PASS_M |
890 FLASH_FSEQPMP_VIN_AT_X_M)) | value;
891 HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA;
893 /* Select trim values for internal regulator mode:
894 Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 31)
895 COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 30:29)
896 Must be done while the register bit field CONFIG.DIS_STANDBY = 1 */
897 HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY;
900 HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4);
902 value = ((trim_value &
903 FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_M) >>
904 FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_S) <<
905 FLASH_CFG_STANDBY_MODE_SEL_S;
907 value |= ((trim_value &
908 FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_M) >>
909 FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_S) <<
910 FLASH_CFG_STANDBY_PW_SEL_S;
912 /* Configure DIS_STANDBY (OTP offset 0x308 bit 28).
913 Configure DIS_IDLE (OTP offset 0x308 bit 27). */
914 value |= ((trim_value &
915 (FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_M |
916 FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_M)) >>
917 FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_S) <<
918 FLASH_CFG_DIS_IDLE_S;
920 HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) &
921 ~(FLASH_CFG_STANDBY_MODE_SEL_M | FLASH_CFG_STANDBY_PW_SEL_M |
922 FLASH_CFG_DIS_STANDBY_M | FLASH_CFG_DIS_IDLE_M)) | value;
924 /* Check if sample and hold functionality is disabled. */
925 if (HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE) {
926 /* Wait for disabled sample and hold functionality to be stable. */
927 while (!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS))
931 /* Configure VIN_AT_X (OTP offset 0x308 bits 26:24) */
932 value = ((trim_value &
933 FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_M) >>
934 FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_S) <<
935 FLASH_FSEQPMP_VIN_AT_X_S;
937 /* Configure VIN_BY_PASS which is dependent on the VIN_AT_X value.
938 If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise
939 VIN_BY_PASS should be 1 */
940 if (((value & FLASH_FSEQPMP_VIN_AT_X_M) >>
941 FLASH_FSEQPMP_VIN_AT_X_S) != 0x7)
942 value |= FLASH_FSEQPMP_VIN_BY_PASS;
944 HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA;
945 HWREG(FLASH_BASE + FLASH_O_FSEQPMP) =
946 (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) &
947 ~(FLASH_FSEQPMP_VIN_BY_PASS_M |
948 FLASH_FSEQPMP_VIN_AT_X_M)) | value;
949 HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA;