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   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Copyright (C) 2005, 2007 by Dominic Rath                              *
   5  *   Dominic.Rath@gmx.de                                                   *
   6  *   Copyright (C) 2010 Spencer Oliver                                     *
   7  *   spen@spen-soft.co.uk                                                  *
   8  ***************************************************************************/
   9
  10         .text
  11         .syntax unified
  12         .arch armv7-m
  13         .thumb
  14         .thumb_func
  15
  16         .align 2
  17
  18 /* input parameters - */
  19 /*      R0 = source address */
  20 /*      R1 = destination address */
  21 /*      R2 = number of writes */
  22 /*      R3 = flash write command */
  23 /*      R4 = constant to mask DQ7 bits */
  24 /* output parameters - */
  25 /*      R5 = 0x80 ok 0x00 bad */
  26 /* temp registers - */
  27 /*      R6 = value read from flash to test status */
  28 /*      R7 = holding register */
  29 /* unlock registers - */
  30 /*  R8 = unlock1_addr */
  31 /*  R9 = unlock1_cmd */
  32 /*  R10 = unlock2_addr */
  33 /*  R11 = unlock2_cmd */
  34
  35 code:
  36         ldrh    r5, [r0], #2
  37         strh    r9, [r8]
  38         strh    r11, [r10]
  39         strh    r3, [r8]
  40         strh    r5, [r1]
  41         nop
  42 busy:
  43         ldrh    r6, [r1]
  44         eor             r7, r5, r6
  45         ands    r7, r4, r7
  46         bne             busy
  47         subs    r2, r2, #1      /* 0x1 */
  48         beq             success
  49         add             r1, r1, #2      /* 0x2 */
  50         b               code
  51
  52 success:
  53         mov             r5, #128        /* 0x80 */
  54         b               done
  55
  56 done:
  57         bkpt #0
  58
  59         .end