2 * Copyright © 2022 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
16 #include <ao_dma_samd21.h>
18 static uint8_t ao_spi_mutex[SAMD21_NUM_SERCOM];
19 static uint16_t ao_spi_pin_config[SAMD21_NUM_SERCOM];
24 struct ao_spi_samd21_info {
25 struct samd21_sercom *sercom;
28 static const struct ao_spi_samd21_info ao_spi_samd21_info[SAMD21_NUM_SERCOM] = {
30 .sercom = &samd21_sercom0,
33 .sercom = &samd21_sercom1,
36 .sercom = &samd21_sercom2,
39 .sercom = &samd21_sercom3,
42 .sercom = &samd21_sercom4,
45 .sercom = &samd21_sercom5,
49 static uint8_t spi_dev_null;
53 static uint8_t ao_spi_done[SAMD21_NUM_SERCOM];
56 _ao_spi_recv_dma_done(uint8_t dma_id, void *closure)
58 uint8_t id = (uint8_t) (uintptr_t) closure;
62 ao_wakeup(&ao_spi_done[id]);
65 static inline uint32_t
66 dma_chctrlb(uint8_t id, bool tx)
70 /* No complicated actions needed */
71 chctrlb |= SAMD21_DMAC_CHCTRLB_CMD_NOACT << SAMD21_DMAC_CHCTRLB_CMD;
73 /* Trigger after each byte transferred */
74 chctrlb |= SAMD21_DMAC_CHCTRLB_TRIGACT_BEAT << SAMD21_DMAC_CHCTRLB_TRIGACT;
76 /* Set the trigger source */
78 chctrlb |= SAMD21_DMAC_CHCTRLB_TRIGSRC_SERCOM_TX(id) << SAMD21_DMAC_CHCTRLB_TRIGSRC;
80 chctrlb |= SAMD21_DMAC_CHCTRLB_TRIGSRC_SERCOM_RX(id) << SAMD21_DMAC_CHCTRLB_TRIGSRC;
82 /* RX has priority over TX so that we don't drop incoming bytes */
84 chctrlb |= SAMD21_DMAC_CHCTRLB_LVL_LVL0 << SAMD21_DMAC_CHCTRLB_LVL;
86 chctrlb |= SAMD21_DMAC_CHCTRLB_LVL_LVL3 << SAMD21_DMAC_CHCTRLB_LVL;
88 /* No events needed */
89 chctrlb |= 0UL << SAMD21_DMAC_CHCTRLB_EVOE;
90 chctrlb |= 0UL << SAMD21_DMAC_CHCTRLB_EVIE;
92 /* And no actions either */
93 chctrlb |= SAMD21_DMAC_CHCTRLB_EVACT_NOACT << SAMD21_DMAC_CHCTRLB_EVACT;
98 static inline uint16_t
99 dma_btctrl(bool step, bool tx)
103 /* Always step by 1 */
104 btctrl |= SAMD21_DMAC_DESC_BTCTRL_STEPSIZE_X1 << SAMD21_DMAC_DESC_BTCTRL_STEPSIZE;
106 /* Step the source if transmit, otherwise step the dest */
108 btctrl |= SAMD21_DMAC_DESC_BTCTRL_STEPSEL_SRC << SAMD21_DMAC_DESC_BTCTRL_STEPSEL;
110 btctrl |= SAMD21_DMAC_DESC_BTCTRL_STEPSEL_DST << SAMD21_DMAC_DESC_BTCTRL_STEPSEL;
112 /* Set the increment if stepping */
115 btctrl |= 1UL << SAMD21_DMAC_DESC_BTCTRL_SRCINC;
117 btctrl |= 0UL << SAMD21_DMAC_DESC_BTCTRL_SRCINC;
118 btctrl |= 0UL << SAMD21_DMAC_DESC_BTCTRL_DSTINC;
120 btctrl |= 0UL << SAMD21_DMAC_DESC_BTCTRL_SRCINC;
122 btctrl |= 1UL << SAMD21_DMAC_DESC_BTCTRL_DSTINC;
124 btctrl |= 0UL << SAMD21_DMAC_DESC_BTCTRL_DSTINC;
127 /* byte at a time please */
128 btctrl |= SAMD21_DMAC_DESC_BTCTRL_BEATSIZE_BYTE << SAMD21_DMAC_DESC_BTCTRL_BEATSIZE;
131 * Watch for interrupts on RX -- we need to wait for the last byte to get received
132 * to know the SPI bus is idle
135 btctrl |= SAMD21_DMAC_DESC_BTCTRL_BLOCKACT_NOACT << SAMD21_DMAC_DESC_BTCTRL_BLOCKACT;
137 btctrl |= SAMD21_DMAC_DESC_BTCTRL_BLOCKACT_INT << SAMD21_DMAC_DESC_BTCTRL_BLOCKACT;
139 /* don't need any events */
140 btctrl |= SAMD21_DMAC_DESC_BTCTRL_EVOSEL_DISABLE << SAMD21_DMAC_DESC_BTCTRL_EVOSEL;
142 /* And make the descriptor valid */
143 btctrl |= 1UL << SAMD21_DMAC_DESC_BTCTRL_VALID;
149 spi_run(const void *out, void *in, uint16_t len, uint16_t spi_index, bool step_out, bool step_in)
151 const uint8_t *o = out;
153 uint8_t id = AO_SPI_INDEX(spi_index);
154 struct samd21_sercom *sercom = ao_spi_samd21_info[id].sercom;
156 ao_arch_block_interrupts();
160 * Stepped addresses to the DMA engine point past the end of
168 /* read any stuck data */
171 _ao_dma_start_transfer(AO_SERCOM_INPUT_DMA_ID(id),
172 (void *) &sercom->data,
175 dma_chctrlb(id, false),
176 dma_btctrl(step_in, false),
178 _ao_spi_recv_dma_done,
179 (void *) (uintptr_t) id
182 _ao_dma_start_transfer(AO_SERCOM_OUTPUT_DMA_ID(id),
184 (void *) &sercom->data,
186 dma_chctrlb(id, true),
187 dma_btctrl(step_out, true),
192 while (ao_spi_done[id] == 0)
193 ao_sleep(&ao_spi_done[id]);
195 _ao_dma_done_transfer(AO_SERCOM_OUTPUT_DMA_ID(id));
196 _ao_dma_done_transfer(AO_SERCOM_INPUT_DMA_ID(id));
197 ao_arch_release_interrupts();
203 spi_run(const void *out, void *in, uint16_t len, uint16_t spi_index, bool step_out, bool step_in)
205 uint8_t id = AO_SPI_INDEX(spi_index);
206 struct samd21_sercom *sercom = ao_spi_samd21_info[id].sercom;
207 const uint8_t *o = out;
215 while ((sercom->intflag & (1 << SAMD21_SERCOM_INTFLAG_RXC)) == 0)
217 *i = (uint8_t) sercom->data;
219 printf("\t%02x\n", *i);
231 ao_spi_send(const void *block, uint16_t len, uint16_t spi_index)
233 spi_run(block, &spi_dev_null, len, spi_index, true, false);
237 ao_spi_send_fixed(uint8_t data, uint16_t len, uint16_t spi_index)
239 spi_run(&data, &spi_dev_null, len, spi_index, false, false);
243 ao_spi_recv(void *block, uint16_t len, uint16_t spi_index)
246 spi_run(&spi_dev_null, block, len, spi_index, false, true);
251 ao_spi_duplex(const void *out, void *in, uint16_t len, uint16_t spi_index)
253 spi_run(out, in, len, spi_index, true, true);
257 ao_spi_disable_pin_config(uint16_t spi_pin_config)
259 switch (spi_pin_config) {
261 case AO_SPI_PIN_CONFIG(AO_SPI_0_PA08_PA09_PA10):
262 samd21_port_pmux_clr(&samd21_port_a, 8); /* MOSI */
263 samd21_port_pmux_clr(&samd21_port_a, 9); /* SCLK */
264 samd21_port_pmux_clr(&samd21_port_a, 10); /* MISO */
266 case AO_SPI_PIN_CONFIG(AO_SPI_0_PA04_PA05_PA06):
267 samd21_port_pmux_clr(&samd21_port_a, 4); /* MOSI */
268 samd21_port_pmux_clr(&samd21_port_a, 5); /* SCLK */
269 samd21_port_pmux_clr(&samd21_port_a, 6); /* MISO */
273 case AO_SPI_PIN_CONFIG(AO_SPI_3_PA22_PA23_PA20):
274 samd21_port_pmux_clr(&samd21_port_a, 22); /* MOSI */
275 samd21_port_pmux_clr(&samd21_port_a, 23); /* SCLK */
276 samd21_port_pmux_clr(&samd21_port_a, 20); /* MISO */
280 case AO_SPI_PIN_CONFIG(AO_SPI_4_PB10_PB11_PA12):
281 samd21_port_pmux_clr(&samd21_port_b, 10); /* MOSI */
282 samd21_port_pmux_clr(&samd21_port_b, 11); /* SCLK */
283 samd21_port_pmux_clr(&samd21_port_a, 12); /* MISO */
287 case AO_SPI_PIN_CONFIG(AO_SPI_5_PB22_PB23_PB03):
288 samd21_port_pmux_clr(&samd21_port_b, 22); /* MOSI */
289 samd21_port_pmux_clr(&samd21_port_b, 23); /* SCLK */
290 samd21_port_pmux_clr(&samd21_port_b, 3); /* MISO */
299 ao_spi_enable_pin_config(uint16_t spi_pin_config)
301 switch (spi_pin_config) {
303 case AO_SPI_PIN_CONFIG(AO_SPI_0_PA08_PA09_PA10):
304 ao_enable_output(&samd21_port_a, 8, 1);
305 ao_enable_output(&samd21_port_a, 9, 1);
306 ao_enable_input(&samd21_port_a, 10, AO_MODE_PULL_NONE);
308 samd21_port_pmux_set(&samd21_port_a, 8, SAMD21_PORT_PMUX_FUNC_C); /* MOSI */
309 samd21_port_pmux_set(&samd21_port_a, 9, SAMD21_PORT_PMUX_FUNC_C); /* SCLK */
310 samd21_port_pmux_set(&samd21_port_a, 10, SAMD21_PORT_PMUX_FUNC_C); /* MISO */
312 case AO_SPI_PIN_CONFIG(AO_SPI_0_PA04_PA05_PA06):
313 ao_enable_output(&samd21_port_a, 4, 1);
314 ao_enable_output(&samd21_port_a, 5, 1);
315 ao_enable_input(&samd21_port_a, 6, AO_MODE_PULL_NONE);
317 samd21_port_pmux_set(&samd21_port_a, 4, SAMD21_PORT_PMUX_FUNC_D); /* MOSI */
318 samd21_port_pmux_set(&samd21_port_a, 5, SAMD21_PORT_PMUX_FUNC_D); /* SCLK */
319 samd21_port_pmux_set(&samd21_port_a, 6, SAMD21_PORT_PMUX_FUNC_D); /* MISO */
323 case AO_SPI_PIN_CONFIG(AO_SPI_3_PA22_PA23_PA20):
324 ao_enable_output(&samd21_port_a, 22, 1);
325 ao_enable_output(&samd21_port_a, 23, 1);
326 ao_enable_input(&samd21_port_a, 20, AO_MODE_PULL_NONE);
328 samd21_port_pmux_set(&samd21_port_a, 22, SAMD21_PORT_PMUX_FUNC_C); /* MOSI */
329 samd21_port_pmux_set(&samd21_port_a, 23, SAMD21_PORT_PMUX_FUNC_C); /* SCLK */
330 samd21_port_pmux_set(&samd21_port_a, 20, SAMD21_PORT_PMUX_FUNC_D); /* MISO */
334 case AO_SPI_PIN_CONFIG(AO_SPI_4_PB10_PB11_PA12):
335 ao_enable_output(&samd21_port_b, 10, 1);
336 ao_enable_output(&samd21_port_b, 11, 1);
337 ao_enable_input(&samd21_port_a, 12, AO_MODE_PULL_NONE);
339 samd21_port_pmux_set(&samd21_port_b, 10, SAMD21_PORT_PMUX_FUNC_D); /* MOSI */
340 samd21_port_pmux_set(&samd21_port_b, 11, SAMD21_PORT_PMUX_FUNC_D); /* SCLK */
341 samd21_port_pmux_set(&samd21_port_a, 12, SAMD21_PORT_PMUX_FUNC_D); /* MISO */
345 case AO_SPI_PIN_CONFIG(AO_SPI_5_PB22_PB23_PB03):
346 ao_enable_output(&samd21_port_b, 22, 1);
347 ao_enable_output(&samd21_port_b, 23, 1);
348 ao_enable_input(&samd21_port_b, 3, AO_MODE_PULL_NONE);
350 samd21_port_pmux_set(&samd21_port_b, 22, SAMD21_PORT_PMUX_FUNC_D); /* 5.2 MOSI */
351 samd21_port_pmux_set(&samd21_port_b, 23, SAMD21_PORT_PMUX_FUNC_D); /* 5.3 SCLK */
352 samd21_port_pmux_set(&samd21_port_b, 3, SAMD21_PORT_PMUX_FUNC_D); /* 5.1 MISO */
356 ao_panic(AO_PANIC_SPI);
362 ao_spi_config(uint16_t spi_index, uint32_t baud)
364 uint16_t spi_pin_config = AO_SPI_PIN_CONFIG(spi_index);
365 uint8_t id = AO_SPI_INDEX(spi_index);
366 struct samd21_sercom *sercom = ao_spi_samd21_info[id].sercom;
368 if (spi_pin_config != ao_spi_pin_config[id]) {
369 ao_spi_disable_pin_config(ao_spi_pin_config[id]);
370 ao_spi_enable_pin_config(spi_pin_config);
371 ao_spi_pin_config[id] = spi_pin_config;
374 sercom->baud = (uint16_t) baud;
377 uint32_t ctrla = sercom->ctrla;
378 ctrla &= ~((1UL << SAMD21_SERCOM_CTRLA_CPOL) |
379 (1UL << SAMD21_SERCOM_CTRLA_CPHA) |
380 (SAMD21_SERCOM_CTRLA_DOPO_MASK << SAMD21_SERCOM_CTRLA_DOPO) |
381 (SAMD21_SERCOM_CTRLA_DIPO_MASK << SAMD21_SERCOM_CTRLA_DIPO));
382 ctrla |= ((AO_SPI_CPOL(spi_index) << SAMD21_SERCOM_CTRLA_CPOL) |
383 (AO_SPI_CPHA(spi_index) << SAMD21_SERCOM_CTRLA_CPHA) |
384 (AO_SPI_DOPO(spi_index) << SAMD21_SERCOM_CTRLA_DOPO) |
385 (AO_SPI_DIPO(spi_index) << SAMD21_SERCOM_CTRLA_DIPO));
387 /* finish setup and enable the hardware */
388 ctrla |= (1 << SAMD21_SERCOM_CTRLA_ENABLE);
391 printf("ctrla %08lx\n", ctrla);
394 sercom->ctrla = ctrla;
396 while (sercom->syncbusy & (1 << SAMD21_SERCOM_SYNCBUSY_ENABLE))
401 ao_spi_get(uint16_t spi_index, uint32_t speed)
403 uint8_t id = AO_SPI_INDEX(spi_index);
405 ao_mutex_get(&ao_spi_mutex[id]);
406 ao_spi_config(spi_index, speed);
410 ao_spi_put(uint16_t spi_index)
412 uint8_t id = AO_SPI_INDEX(spi_index);
413 struct samd21_sercom *sercom = ao_spi_samd21_info[id].sercom;
415 sercom->ctrla &= ~(1UL << SAMD21_SERCOM_CTRLA_ENABLE);
416 while (sercom->syncbusy & (1 << SAMD21_SERCOM_SYNCBUSY_ENABLE))
418 ao_mutex_put(&ao_spi_mutex[id]);
422 ao_spi_init_sercom(uint8_t id)
424 struct samd21_sercom *sercom = ao_spi_samd21_info[id].sercom;
426 /* Send a clock along */
427 samd21_gclk_clkctrl(0, SAMD21_GCLK_CLKCTRL_ID_SERCOM0_CORE + id);
429 samd21_nvic_set_enable(SAMD21_NVIC_ISR_SERCOM0_POS + id);
430 samd21_nvic_set_priority(SAMD21_NVIC_ISR_SERCOM0_POS + id, 4);
433 samd21_pm.apbcmask |= (1 << (SAMD21_PM_APBCMASK_SERCOM0 + id));
436 sercom->ctrla = (1 << SAMD21_SERCOM_CTRLA_SWRST);
438 while ((sercom->ctrla & (1 << SAMD21_SERCOM_CTRLA_SWRST)) ||
439 (sercom->syncbusy & (1 << SAMD21_SERCOM_SYNCBUSY_SWRST)))
443 sercom->ctrla = ((SAMD21_SERCOM_CTRLA_DORD_MSB << SAMD21_SERCOM_CTRLA_DORD) |
444 (0 << SAMD21_SERCOM_CTRLA_CPOL) |
445 (0 << SAMD21_SERCOM_CTRLA_CPHA) |
446 (0 << SAMD21_SERCOM_CTRLA_FORM) |
447 (2 << SAMD21_SERCOM_CTRLA_DIPO) |
448 (0 << SAMD21_SERCOM_CTRLA_DOPO) |
449 (0 << SAMD21_SERCOM_CTRLA_IBON) |
450 (0 << SAMD21_SERCOM_CTRLA_RUNSTDBY) |
451 (SAMD21_SERCOM_CTRLA_MODE_SPI_HOST << SAMD21_SERCOM_CTRLA_MODE) |
452 (0 << SAMD21_SERCOM_CTRLA_ENABLE) |
453 (0 << SAMD21_SERCOM_CTRLA_SWRST));
455 sercom->ctrlb = ((1 << SAMD21_SERCOM_CTRLB_RXEN) |
456 (0 << SAMD21_SERCOM_CTRLB_AMODE) |
457 (0 << SAMD21_SERCOM_CTRLB_MSSEN) |
458 (0 << SAMD21_SERCOM_CTRLB_SSDE) |
459 (0 << SAMD21_SERCOM_CTRLB_PLOADEN) |
460 (SAMD21_SERCOM_CTRLB_CHSIZE_8 << SAMD21_SERCOM_CTRLB_CHSIZE));
462 ao_spi_pin_config[id] = 0xffff;
469 ao_spi_init_sercom(0);
472 ao_spi_init_sercom(1);
475 ao_spi_init_sercom(2);
478 ao_spi_init_sercom(3);
481 ao_spi_init_sercom(4);
484 ao_spi_init_sercom(5);