2 * Copyright © 2008 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
22 * Test ADC in DMA mode
31 # define SLEEP_USB_EN (1 << 7)
32 # define SLEEP_XOSC_STB (1 << 6)
35 #define PERCFG_T1CFG_ALT_1 (0 << 6)
36 #define PERCFG_T1CFG_ALT_2 (1 << 6)
38 #define PERCFG_T3CFG_ALT_1 (0 << 5)
39 #define PERCFG_T3CFG_ALT_2 (1 << 5)
41 #define PERCFG_T4CFG_ALT_1 (0 << 4)
42 #define PERCFG_T4CFG_ALT_2 (1 << 4)
44 #define PERCFG_U1CFG_ALT_1 (0 << 1)
45 #define PERCFG_U1CFG_ALT_2 (1 << 1)
47 #define PERCFG_U0CFG_ALT_1 (0 << 0)
48 #define PERCFG_U0CFG_ALT_2 (1 << 0)
85 sfr at 0xE8 IRCON2; /* CPU Interrupt Flag 5 */
87 sbit at 0xE8 USBIF; /* USB interrupt flag (shared with Port2) */
88 sbit at 0xE8 P2IF; /* Port2 interrupt flag (shared with USB) */
89 sbit at 0xE9 UTX0IF; /* USART0 TX interrupt flag */
90 sbit at 0xEA UTX1IF; /* USART1 TX interrupt flag (shared with I2S TX) */
91 sbit at 0xEA I2STXIF; /* I2S TX interrupt flag (shared with USART1 TX) */
92 sbit at 0xEB P1IF; /* Port1 interrupt flag */
93 sbit at 0xEC WDTIF; /* Watchdog timer interrupt flag */
95 # define UxCSR_MODE_UART (1 << 7)
96 # define UxCSR_MODE_SPI (0 << 7)
97 # define UxCSR_RE (1 << 6)
98 # define UxCSR_SLAVE (1 << 5)
99 # define UxCSR_MASTER (0 << 5)
100 # define UxCSR_FE (1 << 4)
101 # define UxCSR_ERR (1 << 3)
102 # define UxCSR_RX_BYTE (1 << 2)
103 # define UxCSR_TX_BYTE (1 << 1)
104 # define UxCSR_ACTIVE (1 << 0)
109 # define UxUCR_FLUSH (1 << 7)
110 # define UxUCR_FLOW_DISABLE (0 << 6)
111 # define UxUCR_FLOW_ENABLE (1 << 6)
112 # define UxUCR_D9_EVEN_PARITY (0 << 5)
113 # define UxUCR_D9_ODD_PARITY (1 << 5)
114 # define UxUCR_BIT9_8_BITS (0 << 4)
115 # define UxUCR_BIT9_9_BITS (1 << 4)
116 # define UxUCR_PARITY_DISABLE (0 << 3)
117 # define UxUCR_PARITY_ENABLE (1 << 3)
118 # define UxUCR_SPB_1_STOP_BIT (0 << 2)
119 # define UxUCR_SPB_2_STOP_BITS (1 << 2)
120 # define UxUCR_STOP_LOW (0 << 1)
121 # define UxUCR_STOP_HIGH (1 << 1)
122 # define UxUCR_START_LOW (0 << 0)
123 # define UxUCR_START_HIGH (1 << 0)
128 # define UxGCR_CPOL_NEGATIVE (0 << 7)
129 # define UxGCR_CPOL_POSITIVE (1 << 7)
130 # define UxGCR_CPHA_FIRST_EDGE (0 << 6)
131 # define UxGCR_CPHA_SECOND_EDGE (1 << 6)
132 # define UxGCR_ORDER_LSB (0 << 5)
133 # define UxGCR_ORDER_MSB (1 << 5)
134 # define UxGCR_BAUD_E_MASK (0x1f)
135 # define UxGCR_BAUD_E_SHIFT 0
145 # define DMA_LEN_HIGH_VLEN_MASK (7 << 5)
146 # define DMA_LEN_HIGH_VLEN_LEN (0 << 5)
147 # define DMA_LEN_HIGH_VLEN_PLUS_1 (1 << 5)
148 # define DMA_LEN_HIGH_VLEN (2 << 5)
149 # define DMA_LEN_HIGH_VLEN_PLUS_2 (3 << 5)
150 # define DMA_LEN_HIGH_VLEN_PLUS_3 (4 << 5)
151 # define DMA_LEN_HIGH_MASK (0x1f)
153 # define DMA_CFG0_WORDSIZE_8 (0 << 7)
154 # define DMA_CFG0_WORDSIZE_16 (1 << 7)
155 # define DMA_CFG0_TMODE_MASK (3 << 5)
156 # define DMA_CFG0_TMODE_SINGLE (0 << 5)
157 # define DMA_CFG0_TMODE_BLOCK (1 << 5)
158 # define DMA_CFG0_TMODE_REPEATED_SINGLE (2 << 5)
159 # define DMA_CFG0_TMODE_REPEATED_BLOCK (3 << 5)
164 # define DMA_CFG0_TRIGGER_NONE 0
165 # define DMA_CFG0_TRIGGER_PREV 1
166 # define DMA_CFG0_TRIGGER_T1_CH0 2
167 # define DMA_CFG0_TRIGGER_T1_CH1 3
168 # define DMA_CFG0_TRIGGER_T1_CH2 4
169 # define DMA_CFG0_TRIGGER_T2_OVFL 6
170 # define DMA_CFG0_TRIGGER_T3_CH0 7
171 # define DMA_CFG0_TRIGGER_T3_CH1 8
172 # define DMA_CFG0_TRIGGER_T4_CH0 9
173 # define DMA_CFG0_TRIGGER_T4_CH1 10
174 # define DMA_CFG0_TRIGGER_IOC_0 12
175 # define DMA_CFG0_TRIGGER_IOC_1 13
176 # define DMA_CFG0_TRIGGER_URX0 14
177 # define DMA_CFG0_TRIGGER_UTX0 15
178 # define DMA_CFG0_TRIGGER_URX1 16
179 # define DMA_CFG0_TRIGGER_UTX1 17
180 # define DMA_CFG0_TRIGGER_FLASH 18
181 # define DMA_CFG0_TRIGGER_RADIO 19
182 # define DMA_CFG0_TRIGGER_ADC_CHALL 20
183 # define DMA_CFG0_TRIGGER_ADC_CH0 21
184 # define DMA_CFG0_TRIGGER_ADC_CH1 22
185 # define DMA_CFG0_TRIGGER_ADC_CH2 23
186 # define DMA_CFG0_TRIGGER_ADC_CH3 24
187 # define DMA_CFG0_TRIGGER_ADC_CH4 25
188 # define DMA_CFG0_TRIGGER_ADC_CH5 26
189 # define DMA_CFG0_TRIGGER_ADC_CH6 27
190 # define DMA_CFG0_TRIGGER_I2SRX 27
191 # define DMA_CFG0_TRIGGER_ADC_CH7 28
192 # define DMA_CFG0_TRIGGER_I2STX 28
193 # define DMA_CFG0_TRIGGER_ENC_DW 29
194 # define DMA_CFG0_TRIGGER_DNC_UP 30
196 # define DMA_CFG1_SRCINC_MASK (3 << 6)
197 # define DMA_CFG1_SRCINC_0 (0 << 6)
198 # define DMA_CFG1_SRCINC_1 (1 << 6)
199 # define DMA_CFG1_SRCINC_2 (2 << 6)
200 # define DMA_CFG1_SRCINC_MINUS_1 (3 << 6)
202 # define DMA_CFG1_DESTINC_MASK (3 << 4)
203 # define DMA_CFG1_DESTINC_0 (0 << 4)
204 # define DMA_CFG1_DESTINC_1 (1 << 4)
205 # define DMA_CFG1_DESTINC_2 (2 << 4)
206 # define DMA_CFG1_DESTINC_MINUS_1 (3 << 4)
208 # define DMA_CFG1_IRQMASK (1 << 3)
209 # define DMA_CFG1_M8 (1 << 2)
211 # define DMA_CFG1_PRIORITY_MASK (3 << 0)
212 # define DMA_CFG1_PRIORITY_LOW (0 << 0)
213 # define DMA_CFG1_PRIORITY_NORMAL (1 << 0)
214 # define DMA_CFG1_PRIORITY_HIGH (2 << 0)
217 * DMAARM - DMA Channel Arm
222 # define DMAARM_ABORT (1 << 7)
223 # define DMAARM_DMAARM4 (1 << 4)
224 # define DMAARM_DMAARM3 (1 << 3)
225 # define DMAARM_DMAARM2 (1 << 2)
226 # define DMAARM_DMAARM1 (1 << 1)
227 # define DMAARM_DMAARM0 (1 << 0)
230 * DMAREQ - DMA Channel Start Request and Status
235 # define DMAREQ_DMAREQ4 (1 << 4)
236 # define DMAREQ_DMAREQ3 (1 << 3)
237 # define DMAREQ_DMAREQ2 (1 << 2)
238 # define DMAREQ_DMAREQ1 (1 << 1)
239 # define DMAREQ_DMAREQ0 (1 << 0)
242 * DMA configuration 0 address
245 sfr at 0xD5 DMA0CFGH;
246 sfr at 0xD4 DMA0CFGL;
249 * DMA configuration 1-4 address
252 sfr at 0xD3 DMA1CFGH;
253 sfr at 0xD2 DMA1CFGL;
256 * DMAIRQ - DMA Interrupt Flag
261 # define DMAIRQ_DMAIF4 (1 << 4)
262 # define DMAIRQ_DMAIF3 (1 << 3)
263 # define DMAIRQ_DMAIF2 (1 << 2)
264 # define DMAIRQ_DMAIF1 (1 << 1)
265 # define DMAIRQ_DMAIF0 (1 << 0)
267 struct cc_dma_channel {
279 * ADC Data register, low and high
283 __xdata __at (0xDFBA) volatile uint16_t ADCXDATA;
286 * ADC Control Register 1
290 # define ADCCON1_EOC (1 << 7) /* conversion complete */
291 # define ADCCON1_ST (1 << 6) /* start conversion */
293 # define ADCCON1_STSEL_MASK (3 << 4) /* start select */
294 # define ADCCON1_STSEL_EXTERNAL (0 << 4) /* P2_0 pin triggers */
295 # define ADCCON1_STSEL_FULLSPEED (1 << 4) /* full speed, no waiting */
296 # define ADCCON1_STSEL_TIMER1 (2 << 4) /* timer 1 channel 0 */
297 # define ADCCON1_STSEL_START (3 << 4) /* set start bit */
299 # define ADCCON1_RCTRL_MASK (3 << 2) /* random number control */
300 # define ADCCON1_RCTRL_COMPLETE (0 << 2) /* operation completed */
301 # define ADCCON1_RCTRL_CLOCK_LFSR (1 << 2) /* Clock the LFSR once */
304 * ADC Control Register 2
308 # define ADCCON2_SREF_MASK (3 << 6) /* reference voltage */
309 # define ADCCON2_SREF_1_25V (0 << 6) /* internal 1.25V */
310 # define ADCCON2_SREF_EXTERNAL (1 << 6) /* external on AIN7 cc1110 */
311 # define ADCCON2_SREF_VDD (2 << 6) /* VDD on the AVDD pin */
312 # define ADCCON2_SREF_EXTERNAL_DIFF (3 << 6) /* external on AIN6-7 cc1110 */
314 # define ADCCON2_SDIV_MASK (3 << 4) /* decimation rate */
315 # define ADCCON2_SDIV_64 (0 << 4) /* 7 bits */
316 # define ADCCON2_SDIV_128 (1 << 4) /* 9 bits */
317 # define ADCCON2_SDIV_256 (2 << 4) /* 10 bits */
318 # define ADCCON2_SDIV_512 (3 << 4) /* 12 bits */
320 # define ADCCON2_SCH_MASK (0xf << 0) /* Sequence channel select */
321 # define ADCCON2_SCH_SHIFT 0
322 # define ADCCON2_SCH_AIN0 (0 << 0)
323 # define ADCCON2_SCH_AIN1 (1 << 0)
324 # define ADCCON2_SCH_AIN2 (2 << 0)
325 # define ADCCON2_SCH_AIN3 (3 << 0)
326 # define ADCCON2_SCH_AIN4 (4 << 0)
327 # define ADCCON2_SCH_AIN5 (5 << 0)
328 # define ADCCON2_SCH_AIN6 (6 << 0)
329 # define ADCCON2_SCH_AIN7 (7 << 0)
330 # define ADCCON2_SCH_AIN0_AIN1 (8 << 0)
331 # define ADCCON2_SCH_AIN2_AIN3 (9 << 0)
332 # define ADCCON2_SCH_AIN4_AIN5 (0xa << 0)
333 # define ADCCON2_SCH_AIN6_AIN7 (0xb << 0)
334 # define ADCCON2_SCH_GND (0xc << 0)
335 # define ADCCON2_SCH_VREF (0xd << 0)
336 # define ADCCON2_SCH_TEMP (0xe << 0)
337 # define ADCCON2_SCH_VDD_3 (0xf << 0)
341 * ADC Control Register 3
346 # define ADCCON3_EREF_MASK (3 << 6) /* extra conversion reference */
347 # define ADCCON3_EREF_1_25 (0 << 6) /* internal 1.25V */
348 # define ADCCON3_EREF_EXTERNAL (1 << 6) /* external AIN7 cc1110 */
349 # define ADCCON3_EREF_VDD (2 << 6) /* VDD on the AVDD pin */
350 # define ADCCON3_EREF_EXTERNAL_DIFF (3 << 6) /* external AIN6-7 cc1110 */
351 # define ADCCON2_EDIV_MASK (3 << 4) /* extral decimation */
352 # define ADCCON2_EDIV_64 (0 << 4) /* 7 bits */
353 # define ADCCON2_EDIV_128 (1 << 4) /* 9 bits */
354 # define ADCCON2_EDIV_256 (2 << 4) /* 10 bits */
355 # define ADCCON2_EDIV_512 (3 << 4) /* 12 bits */
356 # define ADCCON3_ECH_MASK (0xf << 0) /* Sequence channel select */
357 # define ADCCON3_ECH_SHIFT 0
358 # define ADCCON3_ECH_AIN0 (0 << 0)
359 # define ADCCON3_ECH_AIN1 (1 << 0)
360 # define ADCCON3_ECH_AIN2 (2 << 0)
361 # define ADCCON3_ECH_AIN3 (3 << 0)
362 # define ADCCON3_ECH_AIN4 (4 << 0)
363 # define ADCCON3_ECH_AIN5 (5 << 0)
364 # define ADCCON3_ECH_AIN6 (6 << 0)
365 # define ADCCON3_ECH_AIN7 (7 << 0)
366 # define ADCCON3_ECH_AIN0_AIN1 (8 << 0)
367 # define ADCCON3_ECH_AIN2_AIN3 (9 << 0)
368 # define ADCCON3_ECH_AIN4_AIN5 (0xa << 0)
369 # define ADCCON3_ECH_AIN6_AIN7 (0xb << 0)
370 # define ADCCON3_ECH_GND (0xc << 0)
371 # define ADCCON3_ECH_VREF (0xd << 0)
372 # define ADCCON3_ECH_TEMP (0xe << 0)
373 # define ADCCON3_ECH_VDD_3 (0xf << 0)
377 #define nop() _asm nop _endasm;
380 delay (unsigned char n)
393 debug_byte(uint8_t byte)
397 for (s = 0; s < 8; s++) {
404 struct cc_dma_channel __xdata dma_config;
408 /* The DMA engine writes to XDATA in MSB order */
414 struct dma_xdata16 adc_output[ADC_LEN];
416 #define DMA_XDATA16(a,n) ((uint16_t) ((a)[n].high << 8) | (uint16_t) (a[n].low))
418 #define ADDRH(a) (((uint16_t) (a)) >> 8)
419 #define ADDRL(a) (((uint16_t) (a)))
424 dma_config.cfg0 = (DMA_CFG0_WORDSIZE_16 |
425 DMA_CFG0_TMODE_REPEATED_SINGLE |
426 DMA_CFG0_TRIGGER_ADC_CHALL);
427 dma_config.cfg1 = (DMA_CFG1_SRCINC_0 |
429 DMA_CFG1_PRIORITY_NORMAL);
431 dma_config.src_high = ADDRH(&ADCXDATA);
432 dma_config.src_low = ADDRL(&ADCXDATA);
433 dma_config.dst_high = ADDRH(adc_output);
434 dma_config.dst_low = ADDRL(adc_output);
435 dma_config.len_high = 0;
436 dma_config.len_low = ADC_LEN;
437 DMA0CFGH = ADDRH(&dma_config);
438 DMA0CFGL = ADDRL(&dma_config);
439 ADCCFG = ((1 << 0) | /* acceleration */
440 (1 << 1) | /* pressure */
441 (1 << 2) | /* temperature */
442 (1 << 3) | /* battery voltage */
443 (1 << 4) | /* drogue sense */
444 (1 << 5)); /* main sense */
446 ADCCON1 = (ADCCON1_STSEL_START); /* ST bit triggers */
447 ADCCON2 = (ADCCON2_SREF_VDD | /* reference voltage is VDD */
448 ADCCON2_SDIV_512 | /* 12 bit ADC results */
449 ADCCON2_SCH_AIN5); /* sample all 6 inputs */
457 ADCCON1 |= ADCCON1_ST;
458 while ((DMAIRQ & 1) == 0)
463 * This version uses the USART in UART mode
470 * Configure the peripheral pin choices
471 * for both of the serial ports
473 * Note that telemetrum will use U1CFG_ALT_2
474 * but that overlaps with SPI ALT_2, so until
475 * we can test that this works, we'll set this
478 PERCFG = (PERCFG_U1CFG_ALT_2 |
482 * Make the UART pins controlled by the UART
485 P1SEL |= ((1 << 6) | (1 << 7));
488 * UART mode with the receiver enabled
490 U1CSR = (UxCSR_MODE_UART |
493 * Pick a 38.4kbaud rate
496 U1GCR = 10 << UxGCR_BAUD_E_SHIFT; /* 38400 */
497 // U1GCR = 3 << UxGCR_BAUD_E_SHIFT; /* 300 */
499 * Reasonable serial parameters
501 U1UCR = (UxUCR_FLUSH |
503 UxUCR_D9_ODD_PARITY |
505 UxUCR_PARITY_DISABLE |
506 UxUCR_SPB_2_STOP_BITS |
512 usart_out_byte(uint8_t byte)
521 usart_out_string(uint8_t *string)
525 while (b = *string++)
531 uint8_t __xdata num_buffer[NUM_LEN];
532 uint8_t __xdata * __xdata num_ptr;
535 usart_out_number(uint16_t v)
538 num_ptr = num_buffer + NUM_LEN;
541 *--num_ptr = '0' + v % 10;
544 while (num_ptr != num_buffer)
546 usart_out_string(num_buffer);
549 #define ADC(n) DMA_XDATA16(adc_output,n)
555 while (!(SLEEP & SLEEP_XOSC_STB))
563 usart_out_string("accel: ");
564 usart_out_number(ADC(0));
565 usart_out_string(" pres: ");
566 usart_out_number(ADC(1));
567 usart_out_string(" temp: ");
568 usart_out_number(ADC(2));
569 usart_out_string(" batt: ");
570 usart_out_number(ADC(3));
571 usart_out_string(" drogue: ");
572 usart_out_number(ADC(4));
573 usart_out_string(" main: ");
574 usart_out_number(ADC(5));
575 usart_out_string("\r\n");