From: Bdale Garbee <bdale@gag.com>
Date: Fri, 5 Nov 2010 04:48:36 +0000 (-0600)
Subject: enabling outline layer causes bogus drc errors, so leave it off
X-Git-Tag: fab-v0.1~12
X-Git-Url: https://git.gag.com/?p=hw%2Ftelenano;a=commitdiff_plain;h=2d861ce0cb46ce6e514870de3e30d1f799480a0a

enabling outline layer causes bogus drc errors, so leave it off
---

diff --git a/telenano.pcb b/telenano.pcb
index badbf27..dae41ef 100644
--- a/telenano.pcb
+++ b/telenano.pcb
@@ -1,5 +1,5 @@
 # release: pcb 20091103
-# date:    Thu Nov  4 16:46:09 2010
+# date:    Thu Nov  4 22:48:21 2010
 # user:    bdale (Bdale Garbee,KB0G)
 # host:    rover
 
@@ -1510,10 +1510,6 @@ Layer(2 "bottom")
 )
 Layer(3 "outline")
 (
-	Line[0 0 100000 0 1000 2000 ""]
-	Line[100000 0 100000 50000 1000 2000 ""]
-	Line[100000 50000 0 50000 1000 2000 ""]
-	Line[0 50000 0 0 1000 2000 ""]
 )
 Layer(4 "silk")
 (