From eb932d0e0e462cf906ee08472899350c5b619b3f Mon Sep 17 00:00:00 2001 From: Bdale Garbee Date: Wed, 25 Nov 2015 17:07:23 -0700 Subject: [PATCH] reduce pcb workspace size to board outline again, make version 2.0 --- telemega.pcb | 4 ++-- telemega.sch | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/telemega.pcb b/telemega.pcb index 7e5cf31..6443994 100644 --- a/telemega.pcb +++ b/telemega.pcb @@ -3,7 +3,7 @@ # To read pcb files, the pcb version (or the git source date) must be >= the file version FileVersion[20091103] -PCB["TeleMega" 3250.00mil 1500.00mil] +PCB["TeleMega" 3250.00mil 1250.00mil] Grid[100.000000 0.0000 0.0000 0] PolyArea[200000000.000000] @@ -4015,7 +4015,7 @@ Layer(6 "silk") Line[444.00mil 137.00mil 444.00mil 160.00mil 10.00mil 20.00mil "clearline"] Line[344.00mil 137.00mil 444.00mil 137.00mil 10.00mil 20.00mil "clearline"] Line[344.00mil 160.00mil 344.00mil 137.00mil 10.00mil 20.00mil "clearline"] - Text[2212.00mil 1178.00mil 0 200 "TeleMega v1.1" "clearline,onsolder"] + Text[2212.00mil 1178.00mil 0 200 "TeleMega v2.0" "clearline,onsolder"] Text[77.0250mm 1005.20mil 3 100 "` 2015 Bdale Garbee KB0G" "onsolder"] Text[1415.00mil 297.00mil 0 100 "companion" "clearline,onsolder"] Text[396.00mil 1238.00mil 3 150 "switch" "clearline,onsolder"] diff --git a/telemega.sch b/telemega.sch index 816418a..5f43eae 100644 --- a/telemega.sch +++ b/telemega.sch @@ -153,7 +153,7 @@ Tolerate up to N 68000 43600 67900 43600 4 N 67900 43600 67900 44000 4 T 82400 40400 9 10 1 0 0 0 1 -1.1 +2.0 T 80000 40400 9 10 1 0 0 0 1 1 T 80600 40400 9 10 1 0 0 0 1 -- 2.30.2