From: Bdale Garbee Date: Wed, 29 Feb 2012 21:39:46 +0000 (-0700) Subject: bring work area down to match board outline, add outline, move some silk X-Git-Tag: fab-v0.1~17 X-Git-Url: https://git.gag.com/?p=hw%2Ftelemega;a=commitdiff_plain;h=9f53344301a5f8257d39693c4f55f1633dc32446 bring work area down to match board outline, add outline, move some silk --- diff --git a/megametrum.pcb b/megametrum.pcb index 4a1315a..a16712f 100644 --- a/megametrum.pcb +++ b/megametrum.pcb @@ -3,15 +3,15 @@ # To read pcb files, the pcb version (or the git source date) must be >= the file version FileVersion[20070407] -PCB["TeleMetrum" 325000 150000] +PCB["TeleMetrum" 325000 125000] Grid[100.0 0 0 0] -Cursor[3000 34000 0.000000] +Cursor[3600 41100 0.000000] PolyArea[200000000.000000] Thermal[0.500000] DRC[600 1000 600 500 1500 700] Flags("nameonpcb,clearnew,snappin,liveroute") -Groups("1,c:4,s:2:3") +Groups("1,c:4,s:2:3:5") Styles["Signal,1000,3100,1500,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"] Symbol[' ' 1800] @@ -1444,7 +1444,7 @@ Element["" "0402" "R14" "100k" 56200 37900 -12250 -3550 0 100 ""] ) -Element["" "MPU6000" "U12" "MPU-6000" 49500 110900 4100 15500 2 100 ""] +Element["" "MPU6000" "U12" "MPU-6000" 49500 110900 4400 3200 2 100 ""] ( Pad[4920 6849 4920 8897 1102 866 1654 "GND" "18" "edge2"] Pad[4920 -8898 4920 -6850 1102 866 1654 "CLKIN" "1" ""] @@ -1516,7 +1516,7 @@ Element["" "0402" "C600" "100nF" 191700 98974 -750 -3150 3 105 ""] ) -Element["" "LPCC16" "U9" "unknown" 76900 110926 -13600 15448 1 100 ""] +Element["" "LPCC16" "U9" "unknown" 76900 110926 10800 10448 1 100 ""] ( Pad[4723 -2952 5314 -2952 1181 787 1575 "SETC" "12" "square,edge2"] Pad[-5315 -2952 -4724 -2952 1181 787 1575 "SCL" "1" "square"] @@ -1610,7 +1610,7 @@ Element["" "0402" "C10" "0.1uF" 242900 87900 9350 -3728 3 100 ""] ) -Element["" "0402" "C301" "0.1uF" 30300 118074 -2850 -4450 3 100 ""] +Element["" "0402" "C301" "0.1uF" 30300 118074 -1450 -5850 3 100 ""] ( Pad[-393 -1574 393 -1574 1968 2000 2568 "1" "1" "square"] Pad[-393 1574 393 1574 1968 2000 2568 "2" "2" "square"] @@ -2079,14 +2079,14 @@ Element["" "ABM3B" "X2" "8mhz" 213827 113923 -2798 4950 0 100 ""] ) -Element["" "0402" "C303" "10nF" 61900 115474 -3150 15702 1 100 ""] +Element["" "0402" "C303" "10nF" 61900 115474 -1050 -3498 1 100 ""] ( Pad[-393 1574 393 1574 1968 2000 2568 "1" "1" "square"] Pad[-393 -1574 393 -1574 1968 2000 2568 "2" "2" "square"] ) -Element["" "0402" "C21" "4.7uF" 85300 114474 2150 3750 3 100 ""] +Element["" "0402" "C21" "4.7uF" 85300 114474 3850 -4150 3 100 ""] ( Pad[-393 1574 393 1574 1968 2000 2568 "1" "1" "square"] Pad[-393 -1574 393 -1574 1968 2000 2568 "2" "2" "square"] @@ -3565,7 +3565,7 @@ Layer(4 "bottom") Line[86100 119500 86100 107000 1000 2000 "clearline"] Line[162500 114200 162500 120800 1000 2000 "clearline"] Line[162500 120800 159800 123500 1000 2000 "clearline"] - Line[159800 123500 39200 123500 1000 2000 "clearline"] + Line[159800 123500 39200 123500 1000 2000 "clearline,selected"] Line[39200 123500 38200 122500 1000 2000 "clearline"] Line[38200 122500 38200 117700 1000 2000 "clearline"] Line[99250 73150 99250 81850 1000 2000 "clearline"] @@ -3683,7 +3683,19 @@ Layer(4 "bottom") [324000 1000] [324000 124000] [1000 124000] ) ) -Layer(5 "silk") +Layer(5 "outline") +( + Attribute("PCB::skip-drc" "1") + Line[0 0 89000 0 1000 2000 "lock"] + Line[89000 0 89000 2600 1000 2000 "lock"] + Line[89000 2600 139000 2600 1000 2000 "lock"] + Line[139000 2600 139000 0 1000 2000 "lock"] + Line[139000 0 325000 0 1000 2000 "lock"] + Line[325000 0 325000 125000 1000 2000 "lock"] + Line[325000 125000 0 125000 1000 2000 "lock"] + Line[0 125000 0 0 1000 2000 "lock"] +) +Layer(6 "silk") ( Line[24400 90000 31700 97200 1000 2000 "clearline"] Line[34300 20100 34300 17800 1000 2000 "clearline"] @@ -3719,7 +3731,7 @@ Layer(5 "silk") [201553 28812] [216006 28812] [208047 36229] [196486 73403] ) ) -Layer(6 "silk") +Layer(7 "silk") ( ) NetList()