From: Bdale Garbee Date: Mon, 27 Feb 2012 18:32:01 +0000 (-0700) Subject: fixes incorporated from Keith's STM32L151 pin by pin review X-Git-Tag: fab-v0.1~21 X-Git-Url: https://git.gag.com/?p=hw%2Ftelemega;a=commitdiff_plain;h=88e2dda6f32d487e08bbaddbcb36fc175e10af94 fixes incorporated from Keith's STM32L151 pin by pin review --- diff --git a/Datasheets/microchip/mcp130t.pdf b/Datasheets/microchip/mcp130t.pdf new file mode 100644 index 0000000..ec7c5f2 Binary files /dev/null and b/Datasheets/microchip/mcp130t.pdf differ diff --git a/Datasheets/tdk/PS Series Rev2008.pdf b/Datasheets/tdk/PS Series Rev2008.pdf new file mode 100644 index 0000000..aef101c Binary files /dev/null and b/Datasheets/tdk/PS Series Rev2008.pdf differ diff --git a/megametrum.pcb b/megametrum.pcb index 867b00d..69b4360 100644 --- a/megametrum.pcb +++ b/megametrum.pcb @@ -6,7 +6,7 @@ FileVersion[20070407] PCB["TeleMetrum" 325000 125000] Grid[100.0 0 0 0] -Cursor[1200 21900 0.000000] +Cursor[5900 44500 0.000000] PolyArea[200000000.000000] Thermal[0.500000] DRC[600 1000 600 500 1500 700] @@ -878,7 +878,6 @@ Via[24200 62500 3100 2000 0 1500 "" "thermal(1S)"] Via[38300 96600 3100 2000 0 1500 "" "thermal(2S)"] Via[212200 19800 3100 2000 0 1500 "" "thermal(1S)"] Via[220200 12300 3100 2000 0 1500 "" "thermal(2S)"] -Via[206100 24800 3100 2000 0 1500 "" ""] Via[209000 27700 3100 2000 0 1500 "" ""] Via[219800 40900 3100 2000 0 1500 "" "thermal(1S)"] Via[219800 36400 3100 2000 0 1500 "" "thermal(2S)"] @@ -902,7 +901,7 @@ Via[161300 37000 3100 2000 0 1500 "" "thermal(1S)"] Via[158500 74300 3100 2000 0 1500 "" ""] Via[152600 112900 3100 2000 0 1500 "" ""] Via[196800 55300 3100 2000 0 1500 "" ""] -Via[196800 27200 3100 2000 0 1500 "" ""] +Via[196800 21700 3100 2000 0 1500 "" ""] Via[274100 2600 3100 2000 0 1500 "" ""] Via[85300 22200 3100 2000 0 1500 "" ""] Via[74400 30500 3100 2000 0 1500 "" ""] @@ -914,7 +913,7 @@ Via[111400 89600 3100 2000 0 1500 "" ""] Via[285200 50000 3100 2000 0 1500 "" ""] Via[291500 50000 3100 2000 0 1500 "" ""] Via[199700 52300 3100 2000 0 1500 "" ""] -Via[203000 48900 3100 2000 0 1500 "" ""] +Via[199900 43400 3100 2000 0 1500 "" ""] Via[29500 108100 3100 2000 0 1500 "" "thermal(1S)"] Via[38200 117700 3100 2000 0 1500 "" ""] Via[41100 120600 3100 2000 0 1500 "" "thermal(2S)"] @@ -934,7 +933,7 @@ Via[57000 11900 3100 2000 0 1500 "" ""] Via[134900 34700 3100 2000 0 1500 "" ""] Via[62700 7300 3100 2000 0 1500 "" ""] Via[131400 29300 3100 2000 0 1500 "" ""] -Via[185900 39100 3100 2000 0 1500 "" ""] +Via[206000 47000 3100 2000 0 1500 "" ""] Via[94000 15400 3100 2000 0 1500 "" ""] Via[2900 63700 3100 2000 0 1500 "" "thermal(1S)"] Via[81800 24300 3100 2000 0 1500 "" ""] @@ -945,8 +944,6 @@ Via[248460 101101 3100 2000 0 1500 "" "thermal(1S,3S)"] Via[224600 19900 3100 2000 0 1500 "" ""] Via[230500 28300 3100 2000 0 1500 "" ""] Via[275700 106500 3100 2000 0 1500 "" ""] -Via[200700 36700 3100 2000 0 1500 "" ""] -Via[214200 32500 3100 2000 0 1500 "" ""] Via[219700 73300 3100 2000 0 1500 "" ""] Via[151200 34800 3100 2000 0 1500 "" ""] Via[26400 122200 3100 2000 0 1500 "" ""] @@ -993,6 +990,10 @@ Via[155400 89400 3100 2000 0 1500 "" "thermal(2S)"] Via[179100 88800 3100 2000 0 1500 "" "thermal(2S)"] Via[192600 83900 3100 2000 0 1500 "" ""] Via[196700 83500 3100 2000 0 1500 "" ""] +Via[199700 27100 3100 2000 0 1500 "" ""] +Via[205900 24600 3100 2000 0 1500 "" ""] +Via[185600 38900 3100 2000 0 1500 "" ""] +Via[206000 40900 3100 2000 0 1500 "" ""] Element["lock" "hole-M3" "H2" "unknown" 12500 12500 -3700 -3300 0 100 ""] ( @@ -1192,116 +1193,6 @@ Element["" "SO8" "Q1" "FDS9926A" 74300 35500 -93300 9000 2 100 ""] ) -Element["" "lqfp100" "U7" "STM32L151" 183000 62500 3300 -6600 2 100 ""] -( - Pad[23621 28739 23621 32282 1181 787 1811 "PA2/USART2_TX/ADC_IN2/TIM2_CH3/TIM9_CH1" "25" "square,edge2"] - Pad[23621 -32283 23621 -28740 1181 787 1811 "PB12/SPI2_NSS/I2C2_SMBA/USART3_CKI/ADC_IN18/TIM10_CH1" "51" "square"] - Pad[-32283 23621 -28740 23621 1181 787 1811 "VDD3" "100" "square"] - Pad[28739 23621 32282 23621 1181 787 1811 "PA3/USART2_RX/ADC_IN3/TIM2_CH4/TIM9_CH2" "26" "square,edge2"] - Pad[21653 28739 21653 32282 1181 787 1811 "PA1/USART2_RTS/ADC_IN1/TIM2_CH2" "24" "square,edge2"] - Pad[21653 -32283 21653 -28740 1181 787 1811 "PB13/SPI2_SCK/USART3_CTS/ADC_IN19/TIM9_CH1" "52" "square"] - Pad[-32283 21653 -28740 21653 1181 787 1811 "VSS3" "99" "square"] - Pad[28739 21653 32282 21653 1181 787 1811 "VSS4" "27" "square,edge2"] - Pad[19684 28739 19684 32282 1181 787 1811 "PA0/WKUP1/USART2_CTS/ADC_IN0/TIM2_CH1_ETR" "23" "square,edge2"] - Pad[19684 -32283 19684 -28740 1181 787 1811 "PB14/SPI2_MISO/USART3_RTS/ADC_IN20/TIM9_CH2" "53" "square"] - Pad[-32283 19684 -28740 19684 1181 787 1811 "PE1/TIM11_CH1" "98" "square"] - Pad[28739 19684 32282 19684 1181 787 1811 "VDD4" "28" "square,edge2"] - Pad[17716 28739 17716 32282 1181 787 1811 "VDDA" "22" "square,edge2"] - Pad[17716 -32283 17716 -28740 1181 787 1811 "PB15/SPI2_MOSI/ADC_IN21/TIM11_CH1/RTC_50_60HZ" "54" "square"] - Pad[-32283 17716 -28740 17716 1181 787 1811 "PE0/TIM4_ETR/TIM10_CH1" "97" "square"] - Pad[28739 17716 32282 17716 1181 787 1811 "PA4/SPI1_NSS/USART2_CK/ADC_IN4/DAC_OUT1" "29" "square,edge2"] - Pad[15747 28739 15747 32282 1181 787 1811 "VREF+" "21" "square,edge2"] - Pad[15747 -32283 15747 -28740 1181 787 1811 "PD8/USART3_TX" "55" "square"] - Pad[-32283 15747 -28740 15747 1181 787 1811 "PB9/TIM4_CH4/I2C1_SDA/TIM11_CH1" "96" "square"] - Pad[28739 15747 32282 15747 1181 787 1811 "PA5/SPI1_SCK/ADC_IN5/DAC_OUT2/TIM2_CH1_ETR" "30" "square,edge2"] - Pad[13779 28739 13779 32282 1181 787 1811 "VREF-" "20" "square,edge2"] - Pad[13779 -32283 13779 -28740 1181 787 1811 "PD9/USART3_RX" "56" "square"] - Pad[-32283 13779 -28740 13779 1181 787 1811 "PB8/TIM4_CH3/I2C1_SCL/TIM10_CH1" "95" "square"] - Pad[28739 13779 32282 13779 1181 787 1811 "PA6/SPI1_MISO_ADC_IN6/TIM3_CH1/TIM10_CH1" "31" "square,edge2"] - Pad[11810 28739 11810 32282 1181 787 1811 "VSSA" "19" "square,edge2"] - Pad[11810 -32283 11810 -28740 1181 787 1811 "PD10/USART3_CK" "57" "square"] - Pad[-32283 11810 -28740 11810 1181 787 1811 "BOOT0" "94" "square"] - Pad[28739 11810 32282 11810 1181 787 1811 "PA7/SPI1_MOSI/ADC_IN7/TIM3_CH2/TIM11_CH1" "32" "square,edge2"] - Pad[9842 28739 9842 32282 1181 787 1811 "PC3/ADC_IN13" "18" "square,edge2"] - Pad[9842 -32283 9842 -28740 1181 787 1811 "PD11/USART3_CTS" "58" "square"] - Pad[-32283 9842 -28740 9842 1181 787 1811 "PB7/I2C1_SDA/TIM4_CH2/USART1_RX/PVD_IN" "93" "square"] - Pad[28739 9842 32282 9842 1181 787 1811 "PC4/ADC_IN14" "33" "square,edge2"] - Pad[7873 28739 7873 32282 1181 787 1811 "PC2/ADC_IN12" "17" "square,edge2"] - Pad[7873 -32283 7873 -28740 1181 787 1811 "PD12/TIM4_CH/USART3_RTS" "59" "square"] - Pad[-32283 7873 -28740 7873 1181 787 1811 "PB6/I2C1_SCL/TIM4_CH1/USART1_TX" "92" "square"] - Pad[28739 7873 32282 7873 1181 787 1811 "PC5/ADC_IN15" "34" "square,edge2"] - Pad[5905 28739 5905 32282 1181 787 1811 "PC1/ADC_IN11" "16" "square,edge2"] - Pad[5905 -32283 5905 -28740 1181 787 1811 "PD13/TIM4_CH2" "60" "square"] - Pad[-32283 5905 -28740 5905 1181 787 1811 "PB5/I2C1_SMBA/TIM3_CH2/SPI1_MOSI" "91" "square"] - Pad[28739 5905 32282 5905 1181 787 1811 "PB0/ADC_IN8/TIM3_CH3/VREF_OUT" "35" "square,edge2"] - Pad[3936 28739 3936 32282 1181 787 1811 "PC0/ADC_IN10" "15" "square,edge2"] - Pad[3936 -32283 3936 -28740 1181 787 1811 "PD14_TIM4_CH3" "61" "square"] - Pad[-32283 3936 -28740 3936 1181 787 1811 "PB4/JNTRSTSPI1_MISO/TIM3_CH1" "90" "square"] - Pad[28739 3936 32282 3936 1181 787 1811 "PB1/ADC_IN9/TIM3_CH4/VREF_OUT" "36" "square,edge2"] - Pad[1968 28739 1968 32282 1181 787 1811 "NRST" "14" "square,edge2"] - Pad[1968 -32283 1968 -28740 1181 787 1811 "PC15/TIM4_CH4" "62" "square"] - Pad[-32283 1968 -28740 1968 1181 787 1811 "PB3/JTDO/TIM2_CH2/TRACESWO/SPI1_SCK" "89" "square"] - Pad[28739 1968 32282 1968 1181 787 1811 "PB2/BOOT1" "37" "square,edge2"] - Pad[0 28739 0 32282 1181 787 1811 "PH1/OSC_OUT" "13" "square,edge2"] - Pad[0 -32283 0 -28740 1181 787 1811 "PC6/TIM3_CH1" "63" "square"] - Pad[-32283 0 -28740 0 1181 787 1811 "PD7/USART2_CK/TIM9_CH2" "88" "square"] - Pad[28739 0 32282 0 1181 787 1811 "PE7/ADC_IN22" "38" "square,edge2"] - Pad[-1969 28739 -1969 32282 1181 787 1811 "PH0/OSC_IN" "12" "square,edge2"] - Pad[-1969 -32283 -1969 -28740 1181 787 1811 "PC7/TIM3_CH2" "64" "square"] - Pad[-32283 -1969 -28740 -1969 1181 787 1811 "PD6/USART2_RX" "87" "square"] - Pad[28739 -1969 32282 -1969 1181 787 1811 "PE8/ADC_IN23" "39" "square,edge2"] - Pad[-3937 28739 -3937 32282 1181 787 1811 "VDD5" "11" "square,edge2"] - Pad[-3937 -32283 -3937 -28740 1181 787 1811 "PC8/TIM3_CH3" "65" "square"] - Pad[-32283 -3937 -28740 -3937 1181 787 1811 "PD5/USART2_TX" "86" "square"] - Pad[28739 -3937 32282 -3937 1181 787 1811 "PE9/ADC_IN24/TIM2_CH1_ETR" "40" "square,edge2"] - Pad[-5906 28739 -5906 32282 1181 787 1811 "VSS5" "10" "square,edge2"] - Pad[-5906 -32283 -5906 -28740 1181 787 1811 "PC9/TIM3_CH4" "66" "square"] - Pad[-32283 -5906 -28740 -5906 1181 787 1811 "PD4_USART2_RTS/SPI2_MOSI" "85" "square"] - Pad[28739 -5906 32282 -5906 1181 787 1811 "PE10/ADC_IN25/TIM2_CH2" "41" "square,edge2"] - Pad[-7874 28739 -7874 32282 1181 787 1811 "PC15/OSC32_OUT" "9" "square,edge2"] - Pad[-7874 -32283 -7874 -28740 1181 787 1811 "PA8/USART1_CK/MCO" "67" "square"] - Pad[-32283 -7874 -28740 -7874 1181 787 1811 "PD3/USART2_CTS/SPI2_MISO" "84" "square"] - Pad[28739 -7874 32282 -7874 1181 787 1811 "PE11/TIM2_CH3" "42" "square,edge2"] - Pad[-9843 28739 -9843 32282 1181 787 1811 "PC14/OSC32_IN" "8" "square,edge2"] - Pad[-9843 -32283 -9843 -28740 1181 787 1811 "PA9/USART1_TX" "68" "square"] - Pad[-32283 -9843 -28740 -9843 1181 787 1811 "PD2/TIM3_ETR" "83" "square"] - Pad[28739 -9843 32282 -9843 1181 787 1811 "PE12/TIM2_CH4/SPI1_NSS" "43" "square,edge2"] - Pad[-11811 28739 -11811 32282 1181 787 1811 "PC13/RTC_AF1/WKUP2" "7" "square,edge2"] - Pad[-11811 -32283 -11811 -28740 1181 787 1811 "PA10/USART1_RX" "69" "square"] - Pad[-32283 -11811 -28740 -11811 1181 787 1811 "PD1/SPI2_SCK" "82" "square"] - Pad[28739 -11811 32282 -11811 1181 787 1811 "PE13/SPI1_SCK" "44" "square,edge2"] - Pad[-13780 28739 -13780 32282 1181 787 1811 "VLCD" "6" "square,edge2"] - Pad[-13780 -32283 -13780 -28740 1181 787 1811 "PA11/USART1_CTS/USBDM/SPI1_MISO" "70" "square"] - Pad[-32283 -13780 -28740 -13780 1181 787 1811 "PD0/SPI2_NSS/TIM9_CH1" "81" "square"] - Pad[28739 -13780 32282 -13780 1181 787 1811 "PE14/SPI1_MISO" "45" "square,edge2"] - Pad[-15748 28739 -15748 32282 1181 787 1811 "PE6/TRACED3/WKUP3/TIM9_CH2" "5" "square,edge2"] - Pad[-15748 -32283 -15748 -28740 1181 787 1811 "PA12/USART1_RTS/USBDP/SPI1_MOSI" "71" "square"] - Pad[-32283 -15748 -28740 -15748 1181 787 1811 "PC12/USART3_CK" "80" "square"] - Pad[28739 -15748 32282 -15748 1181 787 1811 "PE15/SPI1_MOSI" "46" "square,edge2"] - Pad[-17717 28739 -17717 32282 1181 787 1811 "PE5/TRACED2/TIM9_CH1" "4" "square,edge2"] - Pad[-17717 -32283 -17717 -28740 1181 787 1811 "PA13/JTMS/SWDIO" "72" "square"] - Pad[-32283 -17717 -28740 -17717 1181 787 1811 "PC11/USART3_RX" "79" "square"] - Pad[28739 -17717 32282 -17717 1181 787 1811 "PB10/I2C2_SCL/USART3_TX/TIM2_CH3" "47" "square,edge2"] - Pad[-19685 28739 -19685 32282 1181 787 1811 "PE4/TRACED1/TIM3_CH2" "3" "square,edge2"] - Pad[-19685 -32283 -19685 -28740 1181 787 1811 "PH2/I2C2_SMBA" "73" "square"] - Pad[-32283 -19685 -28740 -19685 1181 787 1811 "PC10/USART3_TX" "78" "square"] - Pad[28739 -19685 32282 -19685 1181 787 1811 "PB11/I2C2_SDA/USART3_RX/TIM2_CH4" "48" "square,edge2"] - Pad[-21654 28739 -21654 32282 1181 787 1811 "PE3/TRACED0/TIM3_CH1" "2" "square,edge2"] - Pad[-21654 -32283 -21654 -28740 1181 787 1811 "VSS2" "74" "square"] - Pad[-32283 -21654 -28740 -21654 1181 787 1811 "PA15/JTDI/TIM2_CH1_ETR/SPI1_NSS" "77" "square"] - Pad[28739 -21654 32282 -21654 1181 787 1811 "VSS1" "49" "square,edge2"] - Pad[-23622 28739 -23622 32282 1181 787 1811 "PE2/TRACECK/TIM3_ETR" "1" "square,edge2"] - Pad[-23622 -32283 -23622 -28740 1181 787 1811 "VDD2" "75" "square"] - Pad[-32283 -23622 -28740 -23622 1181 787 1811 "PA14/JTCK/SWCLK" "76" "square"] - Pad[28739 -23622 32282 -23622 1181 787 1811 "VDD1" "50" "square,edge2"] - ElementLine [27558 -27559 27558 27558 1000] - ElementLine [-27559 -27559 27558 -27559 1000] - ElementLine [-27559 -27559 -27559 27558 1000] - ElementLine [-27559 27558 27558 27558 1000] - ElementArc [-28740 28739 500 500 180 360 1000] - - ) - Element["" "MS5607" "U4" "MS5607" 73700 11600 11139 -3011 0 100 ""] ( Pad[7381 3345 7381 5314 2362 2559 2962 "SCLK" "8" "square,edge2"] @@ -1719,7 +1610,7 @@ Element["" "0402" "R26" "27k" 226400 79326 3150 3472 3 100 ""] ) -Element["" "0402" "R25" "10k" 224426 73300 3350 -3050 0 100 ""] +Element["" "0402" "R25" "15k" 224426 73300 3350 -3050 0 100 ""] ( Pad[1574 -393 1574 393 1968 2000 2568 "1" "1" "square"] Pad[-1574 -393 -1574 393 1968 2000 2568 "2" "2" "square"] @@ -2218,89 +2109,89 @@ Element["" "0402" "C20" "0.22uF" 81426 119500 -3450 3250 2 100 ""] Element["" "TI-QFN32" "U6" "CC1120" 278300 91500 0 0 0 100 ""] ( - Pin[-5196 -5196 2900 2500 0 1500 "pin33" "33" "via,thermal(1S,3S)"] - Pin[0 -5196 2900 2500 0 1500 "pin33" "33" "via,thermal(1S,3S)"] - Pin[5197 -5196 2900 2500 0 1500 "pin33" "33" "via,thermal(1S,3S)"] - Pin[-5196 0 2900 2500 0 1500 "pin33" "33" "via,thermal(1S,3S)"] - Pin[0 0 2900 2500 0 1500 "pin33" "33" "via,thermal(1S,3S)"] - Pin[5197 0 2900 2500 0 1500 "pin33" "33" "via,thermal(1S,3S)"] - Pin[-5196 5197 2900 2500 0 1500 "pin33" "33" "via,thermal(1S,3S)"] - Pin[0 5197 2900 2500 0 1500 "pin33" "33" "via,thermal(1S,3S)"] - Pin[5197 5197 2900 2500 0 1500 "pin33" "33" "via,thermal(1S,3S)"] - Pad[0 0 0 0 14567 0 0 "pin33" "33" "square,nopaste"] - Pad[-5196 -5196 -5196 -5196 2598 0 0 "pin33" "33" "square,nopaste"] - Pad[-2597 -5196 -2597 -5196 2598 0 2598 "pin33" "33" "square,nopaste"] - Pad[-2597 -5196 -2597 -5196 1500 0 2598 "pin33" "33" "square"] - Pad[0 -5196 0 -5196 2598 0 0 "pin33" "33" "square,nopaste"] - Pad[2598 -5196 2598 -5196 2598 0 2598 "pin33" "33" "square,edge2,nopaste"] - Pad[2598 -5196 2598 -5196 1500 0 2598 "pin33" "33" "square,edge2"] - Pad[5197 -5196 5197 -5196 2598 0 0 "pin33" "33" "square,edge2,nopaste"] - Pad[-5196 -2597 -5196 -2597 2598 0 2598 "pin33" "33" "square,nopaste"] - Pad[-5196 -2597 -5196 -2597 1500 0 2598 "pin33" "33" "square"] - Pad[-2597 -2597 -2597 -2597 2598 0 2598 "pin33" "33" "square,nopaste"] - Pad[-2597 -2597 -2597 -2597 1500 0 2598 "pin33" "33" "square"] - Pad[0 -2597 0 -2597 2598 0 2598 "pin33" "33" "square,nopaste"] - Pad[0 -2597 0 -2597 1500 0 2598 "pin33" "33" "square"] - Pad[2598 -2597 2598 -2597 2598 0 2598 "pin33" "33" "square,edge2,nopaste"] - Pad[2598 -2597 2598 -2597 1500 0 2598 "pin33" "33" "square,edge2"] - Pad[5197 -2597 5197 -2597 2598 0 2598 "pin33" "33" "square,edge2,nopaste"] - Pad[5197 -2597 5197 -2597 1500 0 2598 "pin33" "33" "square,edge2"] - Pad[-5196 0 -5196 0 2598 0 0 "pin33" "33" "square,nopaste"] - Pad[-2597 0 -2597 0 2598 0 2598 "pin33" "33" "square,nopaste"] - Pad[-2597 0 -2597 0 1500 0 2598 "pin33" "33" "square"] - Pad[0 0 0 0 2598 0 0 "pin33" "33" "square,nopaste"] - Pad[2598 0 2598 0 2598 0 2598 "pin33" "33" "square,edge2,nopaste"] - Pad[2598 0 2598 0 1500 0 2598 "pin33" "33" "square,edge2"] - Pad[5197 0 5197 0 2598 0 0 "pin33" "33" "square,edge2,nopaste"] - Pad[-5196 2598 -5196 2598 2598 0 2598 "pin33" "33" "square,nopaste"] - Pad[-5196 2598 -5196 2598 1500 0 2598 "pin33" "33" "square"] - Pad[-2597 2598 -2597 2598 2598 0 2598 "pin33" "33" "square,nopaste"] - Pad[-2597 2598 -2597 2598 1500 0 2598 "pin33" "33" "square"] - Pad[0 2598 0 2598 2598 0 2598 "pin33" "33" "square,nopaste"] - Pad[0 2598 0 2598 1500 0 2598 "pin33" "33" "square"] - Pad[2598 2598 2598 2598 2598 0 2598 "pin33" "33" "square,edge2,nopaste"] - Pad[2598 2598 2598 2598 1500 0 2598 "pin33" "33" "square,edge2"] - Pad[5197 2598 5197 2598 2598 0 2598 "pin33" "33" "square,edge2,nopaste"] - Pad[5197 2598 5197 2598 1500 0 2598 "pin33" "33" "square,edge2"] - Pad[-5196 5197 -5196 5197 2598 0 0 "pin33" "33" "square,nopaste"] - Pad[-2597 5197 -2597 5197 2598 0 2598 "pin33" "33" "square,nopaste"] - Pad[-2597 5197 -2597 5197 1500 0 2598 "pin33" "33" "square"] - Pad[0 5197 0 5197 2598 0 0 "pin33" "33" "square,nopaste"] - Pad[2598 5197 2598 5197 2598 0 2598 "pin33" "33" "square,edge2,nopaste"] - Pad[2598 5197 2598 5197 1500 0 2598 "pin33" "33" "square,edge2"] - Pad[5197 5197 5197 5197 2598 0 0 "pin33" "33" "square,edge2,nopaste"] - Pad[-6889 -10865 -6889 -8621 1102 866 1654 "pin24" "24" ""] - Pad[-6889 8622 -6889 10866 1102 866 1654 "pin1" "1" "edge2"] - Pad[8622 -6889 10866 -6889 1102 866 1654 "pin16" "16" "edge2"] - Pad[-10865 -6889 -8621 -6889 1102 866 1654 "pin25" "25" ""] - Pad[-4920 -10865 -4920 -8621 1102 866 1654 "pin23" "23" ""] - Pad[-4920 8622 -4920 10866 1102 866 1654 "pin2" "2" "edge2"] - Pad[8622 -4920 10866 -4920 1102 866 1654 "pin15" "15" "edge2"] - Pad[-10865 -4920 -8621 -4920 1102 866 1654 "pin26" "26" ""] - Pad[-2952 -10865 -2952 -8621 1102 866 1654 "pin22" "22" ""] - Pad[-2952 8622 -2952 10866 1102 866 1654 "pin3" "3" "edge2"] - Pad[8622 -2952 10866 -2952 1102 866 1654 "pin14" "14" "edge2"] - Pad[-10865 -2952 -8621 -2952 1102 866 1654 "pin27" "27" ""] - Pad[-983 -10865 -983 -8621 1102 866 1654 "pin21" "21" ""] - Pad[-983 8622 -983 10866 1102 866 1654 "pin4" "4" "edge2"] - Pad[8622 -983 10866 -983 1102 866 1654 "pin13" "13" "edge2"] - Pad[-10865 -983 -8621 -983 1102 866 1654 "pin28" "28" ""] - Pad[984 -10865 984 -8621 1102 866 1654 "pin20" "20" ""] - Pad[984 8622 984 10866 1102 866 1654 "pin5" "5" "edge2"] - Pad[8622 984 10866 984 1102 866 1654 "pin12" "12" "edge2"] - Pad[-10865 984 -8621 984 1102 866 1654 "pin29" "29" ""] - Pad[2953 -10865 2953 -8621 1102 866 1654 "pin19" "19" ""] - Pad[2953 8622 2953 10866 1102 866 1654 "pin6" "6" "edge2"] - Pad[8622 2953 10866 2953 1102 866 1654 "pin11" "11" "edge2"] - Pad[-10865 2953 -8621 2953 1102 866 1654 "pin30" "30" ""] - Pad[4921 -10865 4921 -8621 1102 866 1654 "pin18" "18" ""] - Pad[4921 8622 4921 10866 1102 866 1654 "pin7" "7" "edge2"] - Pad[8622 4921 10866 4921 1102 866 1654 "pin10" "10" "edge2"] - Pad[-10865 4921 -8621 4921 1102 866 1654 "pin31" "31" ""] - Pad[6890 -10865 6890 -8621 1102 866 1654 "pin17" "17" ""] - Pad[6890 8622 6890 10866 1102 866 1654 "pin8" "8" "edge2"] - Pad[8622 6890 10866 6890 1102 866 1654 "pin9" "9" "edge2"] - Pad[-10865 6890 -8621 6890 1102 866 1654 "pin32" "32" ""] + Pin[-5196 -5196 2900 2500 0 1500 "GND" "33" "via,thermal(1S,3S)"] + Pin[0 -5196 2900 2500 0 1500 "GND" "33" "via,thermal(1S,3S)"] + Pin[5197 -5196 2900 2500 0 1500 "GND" "33" "via,thermal(1S,3S)"] + Pin[-5196 0 2900 2500 0 1500 "GND" "33" "via,thermal(1S,3S)"] + Pin[0 0 2900 2500 0 1500 "GND" "33" "via,thermal(1S,3S)"] + Pin[5197 0 2900 2500 0 1500 "GND" "33" "via,thermal(1S,3S)"] + Pin[-5196 5197 2900 2500 0 1500 "GND" "33" "via,thermal(1S,3S)"] + Pin[0 5197 2900 2500 0 1500 "GND" "33" "via,thermal(1S,3S)"] + Pin[5197 5197 2900 2500 0 1500 "GND" "33" "via,thermal(1S,3S)"] + Pad[0 0 0 0 14567 0 0 "GND" "33" "square,nopaste"] + Pad[-5196 -5196 -5196 -5196 2598 0 0 "GND" "33" "square,nopaste"] + Pad[-2597 -5196 -2597 -5196 2598 0 2598 "GND" "33" "square,nopaste"] + Pad[-2597 -5196 -2597 -5196 1500 0 2598 "GND" "33" "square"] + Pad[0 -5196 0 -5196 2598 0 0 "GND" "33" "square,nopaste"] + Pad[2598 -5196 2598 -5196 2598 0 2598 "GND" "33" "square,edge2,nopaste"] + Pad[2598 -5196 2598 -5196 1500 0 2598 "GND" "33" "square,edge2"] + Pad[5197 -5196 5197 -5196 2598 0 0 "GND" "33" "square,edge2,nopaste"] + Pad[-5196 -2597 -5196 -2597 2598 0 2598 "GND" "33" "square,nopaste"] + Pad[-5196 -2597 -5196 -2597 1500 0 2598 "GND" "33" "square"] + Pad[-2597 -2597 -2597 -2597 2598 0 2598 "GND" "33" "square,nopaste"] + Pad[-2597 -2597 -2597 -2597 1500 0 2598 "GND" "33" "square"] + Pad[0 -2597 0 -2597 2598 0 2598 "GND" "33" "square,nopaste"] + Pad[0 -2597 0 -2597 1500 0 2598 "GND" "33" "square"] + Pad[2598 -2597 2598 -2597 2598 0 2598 "GND" "33" "square,edge2,nopaste"] + Pad[2598 -2597 2598 -2597 1500 0 2598 "GND" "33" "square,edge2"] + Pad[5197 -2597 5197 -2597 2598 0 2598 "GND" "33" "square,edge2,nopaste"] + Pad[5197 -2597 5197 -2597 1500 0 2598 "GND" "33" "square,edge2"] + Pad[-5196 0 -5196 0 2598 0 0 "GND" "33" "square,nopaste"] + Pad[-2597 0 -2597 0 2598 0 2598 "GND" "33" "square,nopaste"] + Pad[-2597 0 -2597 0 1500 0 2598 "GND" "33" "square"] + Pad[0 0 0 0 2598 0 0 "GND" "33" "square,nopaste"] + Pad[2598 0 2598 0 2598 0 2598 "GND" "33" "square,edge2,nopaste"] + Pad[2598 0 2598 0 1500 0 2598 "GND" "33" "square,edge2"] + Pad[5197 0 5197 0 2598 0 0 "GND" "33" "square,edge2,nopaste"] + Pad[-5196 2598 -5196 2598 2598 0 2598 "GND" "33" "square,nopaste"] + Pad[-5196 2598 -5196 2598 1500 0 2598 "GND" "33" "square"] + Pad[-2597 2598 -2597 2598 2598 0 2598 "GND" "33" "square,nopaste"] + Pad[-2597 2598 -2597 2598 1500 0 2598 "GND" "33" "square"] + Pad[0 2598 0 2598 2598 0 2598 "GND" "33" "square,nopaste"] + Pad[0 2598 0 2598 1500 0 2598 "GND" "33" "square"] + Pad[2598 2598 2598 2598 2598 0 2598 "GND" "33" "square,edge2,nopaste"] + Pad[2598 2598 2598 2598 1500 0 2598 "GND" "33" "square,edge2"] + Pad[5197 2598 5197 2598 2598 0 2598 "GND" "33" "square,edge2,nopaste"] + Pad[5197 2598 5197 2598 1500 0 2598 "GND" "33" "square,edge2"] + Pad[-5196 5197 -5196 5197 2598 0 0 "GND" "33" "square,nopaste"] + Pad[-2597 5197 -2597 5197 2598 0 2598 "GND" "33" "square,nopaste"] + Pad[-2597 5197 -2597 5197 1500 0 2598 "GND" "33" "square"] + Pad[0 5197 0 5197 2598 0 0 "GND" "33" "square,nopaste"] + Pad[2598 5197 2598 5197 2598 0 2598 "GND" "33" "square,edge2,nopaste"] + Pad[2598 5197 2598 5197 1500 0 2598 "GND" "33" "square,edge2"] + Pad[5197 5197 5197 5197 2598 0 0 "GND" "33" "square,edge2,nopaste"] + Pad[-6889 -10865 -6889 -8621 1102 866 1654 "LPF1" "24" ""] + Pad[-6889 8622 -6889 10866 1102 866 1654 "VDD_GUARD" "1" "edge2"] + Pad[8622 -6889 10866 -6889 1102 866 1654 "NC" "16" "edge2"] + Pad[-10865 -6889 -8621 -6889 1102 866 1654 "AVDD_PFD_CHP" "25" ""] + Pad[-4920 -10865 -4920 -8621 1102 866 1654 "LPF0" "23" ""] + Pad[-4920 8622 -4920 10866 1102 866 1654 "RESET_N" "2" "edge2"] + Pad[8622 -4920 10866 -4920 1102 866 1654 "AVDD_RF" "15" "edge2"] + Pad[-10865 -4920 -8621 -4920 1102 866 1654 "DCPL_PFD_CHP" "26" ""] + Pad[-2952 -10865 -2952 -8621 1102 866 1654 "AVDD_SYNTH1" "22" ""] + Pad[-2952 8622 -2952 10866 1102 866 1654 "GPIO3" "3" "edge2"] + Pad[8622 -2952 10866 -2952 1102 866 1654 "RBIAS" "14" "edge2"] + Pad[-10865 -2952 -8621 -2952 1102 866 1654 "AVDD_SYNTH2" "27" ""] + Pad[-983 -10865 -983 -8621 1102 866 1654 "DCPL_VCO" "21" ""] + Pad[-983 8622 -983 10866 1102 866 1654 "GPIO2" "4" "edge2"] + Pad[8622 -983 10866 -983 1102 866 1654 "AVDD_IF" "13" "edge2"] + Pad[-10865 -983 -8621 -983 1102 866 1654 "AVDD_XOSC" "28" ""] + Pad[984 -10865 984 -8621 1102 866 1654 "LNA_N" "20" ""] + Pad[984 8622 984 10866 1102 866 1654 "DVDD" "5" "edge2"] + Pad[8622 984 10866 984 1102 866 1654 "DVDD" "12" "edge2"] + Pad[-10865 984 -8621 984 1102 866 1654 "DCPL_XOSC" "29" ""] + Pad[2953 -10865 2953 -8621 1102 866 1654 "LNA_P" "19" ""] + Pad[2953 8622 2953 10866 1102 866 1654 "DCPL" "6" "edge2"] + Pad[8622 2953 10866 2953 1102 866 1654 "CS_N" "11" "edge2"] + Pad[-10865 2953 -8621 2953 1102 866 1654 "XOSC_Q1" "30" ""] + Pad[4921 -10865 4921 -8621 1102 866 1654 "TRX_SW" "18" ""] + Pad[4921 8622 4921 10866 1102 866 1654 "SI" "7" "edge2"] + Pad[8622 4921 10866 4921 1102 866 1654 "GPIO0" "10" "edge2"] + Pad[-10865 4921 -8621 4921 1102 866 1654 "XOSC_Q2" "31" ""] + Pad[6890 -10865 6890 -8621 1102 866 1654 "PA" "17" ""] + Pad[6890 8622 6890 10866 1102 866 1654 "SCLK" "8" "edge2"] + Pad[8622 6890 10866 6890 1102 866 1654 "SO/GPIO1" "9" "edge2"] + Pad[-10865 6890 -8621 6890 1102 866 1654 "EXT_XOSC" "32" ""] ElementArc [-10235 10236 500 500 0 360 1000] ) @@ -2339,6 +2230,123 @@ Element["onsolder" "TDK_PS12" "U8" "TDK_PS12" 135500 62542 8100 -3316 1 100 "aut Pin[0 -9843 7874 3937 8661 2756 "2" "2" ""] ElementArc [0 0 24016 24016 90 360 394] + ) + +Element["" "0402" "R29" "1.5k" 149674 29600 -4572 -7350 0 100 ""] +( + Pad[1574 -393 1574 393 1968 2000 2568 "1" "1" "square"] + Pad[-1574 -393 -1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["" "lqfp100" "U7" "STM32L151" 183000 62500 3300 -6600 2 100 ""] +( + Pad[23621 28739 23621 32282 1181 787 1811 "PA2/USART2_TX/ADC_IN2/TIM2_CH3/TIM9_CH1" "25" "square,edge2"] + Pad[23621 -32283 23621 -28740 1181 787 1811 "PB12/SPI2_NSS/I2C2_SMBA/USART3_CKI/ADC_IN18/TIM10_CH1" "51" "square"] + Pad[-32283 23621 -28740 23621 1181 787 1811 "VDD3" "100" "square"] + Pad[28739 23621 32282 23621 1181 787 1811 "PA3/USART2_RX/ADC_IN3/TIM2_CH4/TIM9_CH2" "26" "square,edge2"] + Pad[21653 28739 21653 32282 1181 787 1811 "PA1/USART2_RTS/ADC_IN1/TIM2_CH2" "24" "square,edge2"] + Pad[21653 -32283 21653 -28740 1181 787 1811 "PB13/SPI2_SCK/USART3_CTS/ADC_IN19/TIM9_CH1" "52" "square"] + Pad[-32283 21653 -28740 21653 1181 787 1811 "VSS3" "99" "square"] + Pad[28739 21653 32282 21653 1181 787 1811 "VSS4" "27" "square,edge2"] + Pad[19684 28739 19684 32282 1181 787 1811 "PA0/WKUP1/USART2_CTS/ADC_IN0/TIM2_CH1_ETR" "23" "square,edge2"] + Pad[19684 -32283 19684 -28740 1181 787 1811 "PB14/SPI2_MISO/USART3_RTS/ADC_IN20/TIM9_CH2" "53" "square"] + Pad[-32283 19684 -28740 19684 1181 787 1811 "PE1/TIM11_CH1" "98" "square"] + Pad[28739 19684 32282 19684 1181 787 1811 "VDD4" "28" "square,edge2"] + Pad[17716 28739 17716 32282 1181 787 1811 "VDDA" "22" "square,edge2"] + Pad[17716 -32283 17716 -28740 1181 787 1811 "PB15/SPI2_MOSI/ADC_IN21/TIM11_CH1/RTC_50_60HZ" "54" "square"] + Pad[-32283 17716 -28740 17716 1181 787 1811 "PE0/TIM4_ETR/TIM10_CH1" "97" "square"] + Pad[28739 17716 32282 17716 1181 787 1811 "PA4/SPI1_NSS/USART2_CK/ADC_IN4/DAC_OUT1" "29" "square,edge2"] + Pad[15747 28739 15747 32282 1181 787 1811 "VREF+" "21" "square,edge2"] + Pad[15747 -32283 15747 -28740 1181 787 1811 "PD8/USART3_TX" "55" "square"] + Pad[-32283 15747 -28740 15747 1181 787 1811 "PB9/TIM4_CH4/I2C1_SDA/TIM11_CH1" "96" "square"] + Pad[28739 15747 32282 15747 1181 787 1811 "PA5/SPI1_SCK/ADC_IN5/DAC_OUT2/TIM2_CH1_ETR" "30" "square,edge2"] + Pad[13779 28739 13779 32282 1181 787 1811 "VREF-" "20" "square,edge2"] + Pad[13779 -32283 13779 -28740 1181 787 1811 "PD9/USART3_RX" "56" "square"] + Pad[-32283 13779 -28740 13779 1181 787 1811 "PB8/TIM4_CH3/I2C1_SCL/TIM10_CH1" "95" "square"] + Pad[28739 13779 32282 13779 1181 787 1811 "PA6/SPI1_MISO_ADC_IN6/TIM3_CH1/TIM10_CH1" "31" "square,edge2"] + Pad[11810 28739 11810 32282 1181 787 1811 "VSSA" "19" "square,edge2"] + Pad[11810 -32283 11810 -28740 1181 787 1811 "PD10/USART3_CK" "57" "square"] + Pad[-32283 11810 -28740 11810 1181 787 1811 "BOOT0" "94" "square"] + Pad[28739 11810 32282 11810 1181 787 1811 "PA7/SPI1_MOSI/ADC_IN7/TIM3_CH2/TIM11_CH1" "32" "square,edge2"] + Pad[9842 28739 9842 32282 1181 787 1811 "PC3/ADC_IN13" "18" "square,edge2"] + Pad[9842 -32283 9842 -28740 1181 787 1811 "PD11/USART3_CTS" "58" "square"] + Pad[-32283 9842 -28740 9842 1181 787 1811 "PB7/I2C1_SDA/TIM4_CH2/USART1_RX/PVD_IN" "93" "square"] + Pad[28739 9842 32282 9842 1181 787 1811 "PC4/ADC_IN14" "33" "square,edge2"] + Pad[7873 28739 7873 32282 1181 787 1811 "PC2/ADC_IN12" "17" "square,edge2"] + Pad[7873 -32283 7873 -28740 1181 787 1811 "PD12/TIM4_CH1/USART3_RTS" "59" "square"] + Pad[-32283 7873 -28740 7873 1181 787 1811 "PB6/I2C1_SCL/TIM4_CH1/USART1_TX" "92" "square"] + Pad[28739 7873 32282 7873 1181 787 1811 "PC5/ADC_IN15" "34" "square,edge2"] + Pad[5905 28739 5905 32282 1181 787 1811 "PC1/ADC_IN11" "16" "square,edge2"] + Pad[5905 -32283 5905 -28740 1181 787 1811 "PD13/TIM4_CH2" "60" "square"] + Pad[-32283 5905 -28740 5905 1181 787 1811 "PB5/I2C1_SMBA/TIM3_CH2/SPI1_MOSI" "91" "square"] + Pad[28739 5905 32282 5905 1181 787 1811 "PB0/ADC_IN8/TIM3_CH3/VREF_OUT" "35" "square,edge2"] + Pad[3936 28739 3936 32282 1181 787 1811 "PC0/ADC_IN10" "15" "square,edge2"] + Pad[3936 -32283 3936 -28740 1181 787 1811 "PD14_TIM4_CH3" "61" "square"] + Pad[-32283 3936 -28740 3936 1181 787 1811 "PB4/JNTRSTSPI1_MISO/TIM3_CH1" "90" "square"] + Pad[28739 3936 32282 3936 1181 787 1811 "PB1/ADC_IN9/TIM3_CH4/VREF_OUT" "36" "square,edge2"] + Pad[1968 28739 1968 32282 1181 787 1811 "NRST" "14" "square,edge2"] + Pad[1968 -32283 1968 -28740 1181 787 1811 "PD15/TIM4_CH4" "62" "square"] + Pad[-32283 1968 -28740 1968 1181 787 1811 "PB3/JTDO/TIM2_CH2/TRACESWO/SPI1_SCK" "89" "square"] + Pad[28739 1968 32282 1968 1181 787 1811 "PB2/BOOT1" "37" "square,edge2"] + Pad[0 28739 0 32282 1181 787 1811 "PH1/OSC_OUT" "13" "square,edge2"] + Pad[0 -32283 0 -28740 1181 787 1811 "PC6/TIM3_CH1" "63" "square"] + Pad[-32283 0 -28740 0 1181 787 1811 "PD7/USART2_CK/TIM9_CH2" "88" "square"] + Pad[28739 0 32282 0 1181 787 1811 "PE7/ADC_IN22" "38" "square,edge2"] + Pad[-1969 28739 -1969 32282 1181 787 1811 "PH0/OSC_IN" "12" "square,edge2"] + Pad[-1969 -32283 -1969 -28740 1181 787 1811 "PC7/TIM3_CH2" "64" "square"] + Pad[-32283 -1969 -28740 -1969 1181 787 1811 "PD6/USART2_RX" "87" "square"] + Pad[28739 -1969 32282 -1969 1181 787 1811 "PE8/ADC_IN23" "39" "square,edge2"] + Pad[-3937 28739 -3937 32282 1181 787 1811 "VDD5" "11" "square,edge2"] + Pad[-3937 -32283 -3937 -28740 1181 787 1811 "PC8/TIM3_CH3" "65" "square"] + Pad[-32283 -3937 -28740 -3937 1181 787 1811 "PD5/USART2_TX" "86" "square"] + Pad[28739 -3937 32282 -3937 1181 787 1811 "PE9/ADC_IN24/TIM2_CH1_ETR" "40" "square,edge2"] + Pad[-5906 28739 -5906 32282 1181 787 1811 "VSS5" "10" "square,edge2"] + Pad[-5906 -32283 -5906 -28740 1181 787 1811 "PC9/TIM3_CH4" "66" "square"] + Pad[-32283 -5906 -28740 -5906 1181 787 1811 "PD4_USART2_RTS/SPI2_MOSI" "85" "square"] + Pad[28739 -5906 32282 -5906 1181 787 1811 "PE10/ADC_IN25/TIM2_CH2" "41" "square,edge2"] + Pad[-7874 28739 -7874 32282 1181 787 1811 "PC15/OSC32_OUT" "9" "square,edge2"] + Pad[-7874 -32283 -7874 -28740 1181 787 1811 "PA8/USART1_CK/MCO" "67" "square"] + Pad[-32283 -7874 -28740 -7874 1181 787 1811 "PD3/USART2_CTS/SPI2_MISO" "84" "square"] + Pad[28739 -7874 32282 -7874 1181 787 1811 "PE11/TIM2_CH3" "42" "square,edge2"] + Pad[-9843 28739 -9843 32282 1181 787 1811 "PC14/OSC32_IN" "8" "square,edge2"] + Pad[-9843 -32283 -9843 -28740 1181 787 1811 "PA9/USART1_TX" "68" "square"] + Pad[-32283 -9843 -28740 -9843 1181 787 1811 "PD2/TIM3_ETR" "83" "square"] + Pad[28739 -9843 32282 -9843 1181 787 1811 "PE12/TIM2_CH4/SPI1_NSS" "43" "square,edge2"] + Pad[-11811 28739 -11811 32282 1181 787 1811 "PC13/RTC_AF1/WKUP2" "7" "square,edge2"] + Pad[-11811 -32283 -11811 -28740 1181 787 1811 "PA10/USART1_RX" "69" "square"] + Pad[-32283 -11811 -28740 -11811 1181 787 1811 "PD1/SPI2_SCK" "82" "square"] + Pad[28739 -11811 32282 -11811 1181 787 1811 "PE13/SPI1_SCK" "44" "square,edge2"] + Pad[-13780 28739 -13780 32282 1181 787 1811 "VLCD" "6" "square,edge2"] + Pad[-13780 -32283 -13780 -28740 1181 787 1811 "PA11/USART1_CTS/USBDM/SPI1_MISO" "70" "square"] + Pad[-32283 -13780 -28740 -13780 1181 787 1811 "PD0/SPI2_NSS/TIM9_CH1" "81" "square"] + Pad[28739 -13780 32282 -13780 1181 787 1811 "PE14/SPI1_MISO" "45" "square,edge2"] + Pad[-15748 28739 -15748 32282 1181 787 1811 "PE6/TRACED3/WKUP3/TIM9_CH2" "5" "square,edge2"] + Pad[-15748 -32283 -15748 -28740 1181 787 1811 "PA12/USART1_RTS/USBDP/SPI1_MOSI" "71" "square"] + Pad[-32283 -15748 -28740 -15748 1181 787 1811 "PC12/USART3_CK" "80" "square"] + Pad[28739 -15748 32282 -15748 1181 787 1811 "PE15/SPI1_MOSI" "46" "square,edge2"] + Pad[-17717 28739 -17717 32282 1181 787 1811 "PE5/TRACED2/TIM9_CH1" "4" "square,edge2"] + Pad[-17717 -32283 -17717 -28740 1181 787 1811 "PA13/JTMS/SWDIO" "72" "square"] + Pad[-32283 -17717 -28740 -17717 1181 787 1811 "PC11/USART3_RX" "79" "square"] + Pad[28739 -17717 32282 -17717 1181 787 1811 "PB10/I2C2_SCL/USART3_TX/TIM2_CH3" "47" "square,edge2"] + Pad[-19685 28739 -19685 32282 1181 787 1811 "PE4/TRACED1/TIM3_CH2" "3" "square,edge2"] + Pad[-19685 -32283 -19685 -28740 1181 787 1811 "PH2/I2C2_SMBA" "73" "square"] + Pad[-32283 -19685 -28740 -19685 1181 787 1811 "PC10/USART3_TX" "78" "square"] + Pad[28739 -19685 32282 -19685 1181 787 1811 "PB11/I2C2_SDA/USART3_RX/TIM2_CH4" "48" "square,edge2"] + Pad[-21654 28739 -21654 32282 1181 787 1811 "PE3/TRACED0/TIM3_CH1" "2" "square,edge2"] + Pad[-21654 -32283 -21654 -28740 1181 787 1811 "VSS2" "74" "square"] + Pad[-32283 -21654 -28740 -21654 1181 787 1811 "PA15/JTDI/TIM2_CH1_ETR/SPI1_NSS" "77" "square"] + Pad[28739 -21654 32282 -21654 1181 787 1811 "VSS1" "49" "square,edge2"] + Pad[-23622 28739 -23622 32282 1181 787 1811 "PE2/TRACECK/TIM3_ETR" "1" "square,edge2"] + Pad[-23622 -32283 -23622 -28740 1181 787 1811 "VDD2" "75" "square"] + Pad[-32283 -23622 -28740 -23622 1181 787 1811 "PA14/JTCK/SWCLK" "76" "square"] + Pad[28739 -23622 32282 -23622 1181 787 1811 "VDD1" "50" "square,edge2"] + ElementLine [27558 -27559 27558 27558 1000] + ElementLine [-27559 -27559 27558 -27559 1000] + ElementLine [-27559 -27559 -27559 27558 1000] + ElementLine [-27559 27558 27558 27558 1000] + ElementArc [-28740 28739 500 500 180 360 1000] + ) Layer(1 "top") ( @@ -2640,7 +2648,6 @@ Layer(1 "top") Line[24200 66000 24200 62500 1000 2000 "clearline"] Line[38300 96600 35400 96600 2500 2000 "clearline"] Line[35400 96600 35300 96500 2500 2000 "clearline"] - Line[200716 31988 200716 11984 1000 2000 "clearline"] Line[200716 11984 202800 9900 1000 2000 "clearline"] Line[202800 9900 206322 9900 1000 2000 "clearline"] Line[206322 9900 206420 9801 1000 2000 "clearline"] @@ -2650,8 +2657,6 @@ Layer(1 "top") Line[217700 14800 227699 4801 1000 2000 "clearline"] Line[233978 9801 222699 9801 1000 2000 "clearline"] Line[222699 9801 220200 12300 1000 2000 "clearline"] - Line[202684 31988 202684 28116 1000 2000 "clearline"] - Line[202684 28116 206000 24800 1000 2000 "clearline"] Line[204653 31988 204653 28747 1000 2000 "clearline"] Line[204653 28747 205700 27700 1000 2000 "clearline"] Line[213510 40846 219446 40846 1000 2000 "clearline"] @@ -2785,8 +2790,8 @@ Layer(1 "top") Line[19100 49700 18100 48700 1000 2000 "clearline"] Line[206420 4801 201199 4801 1000 2000 "clearline"] Line[201199 4801 198600 7400 1000 2000 "clearline"] - Line[198600 7400 198600 25400 1000 2000 "clearline"] - Line[198600 25400 196800 27200 1000 2000 "clearline"] + Line[198600 7400 198600 19400 1000 2000 "clearline"] + Line[198600 19400 196700 21700 1000 2000 "clearline"] Line[172500 7500 178000 2000 1000 2000 "clearline"] Line[178000 2000 211400 2000 1000 2000 "clearline"] Line[211400 2000 212600 3200 1000 2000 "clearline"] @@ -2850,7 +2855,6 @@ Layer(1 "top") Line[291500 45444 291447 45391 1000 2000 "clearline"] Line[152488 54626 196126 54626 1000 2000 "clearline"] Line[196126 54626 196800 55300 1000 2000 "clearline"] - Line[202900 48800 203000 48900 1000 2000 "clearline"] Line[226400 76279 226400 77752 1000 2000 "clearline"] Line[41626 111883 32817 111883 1000 2000 "clearline"] Line[32817 111883 32700 112000 1000 2000 "clearline"] @@ -2965,7 +2969,6 @@ Layer(1 "top") Line[142800 55300 146100 58600 1000 2000 "clearline"] Line[146100 58600 152452 58600 1000 2000 "clearline"] Line[152452 58600 152488 58563 1000 2000 "clearline"] - Line[186100 39300 185900 39100 1000 2000 "clearline"] Line[2900 73252 2900 70248 1000 2000 "clearline"] Line[2900 67100 2900 63700 1000 2000 "clearline"] Line[134950 39450 134950 34750 1000 2000 "clearline"] @@ -3001,8 +3004,6 @@ Layer(1 "top") Line[257100 105600 256100 106600 1000 2000 "clearline"] Line[256100 106600 254400 106600 1000 2000 "clearline"] Line[254400 106600 254400 106600 1000 2000 "clearline"] - Line[206100 24800 219700 24800 1000 2000 "clearline"] - Line[219700 24800 224700 19800 1000 2000 "clearline"] Line[224700 19800 233978 19800 1000 2000 "clearline"] Line[213510 70373 227573 70373 1000 2000 "clearline"] Line[227573 70373 233800 76600 1000 2000 "clearline"] @@ -3024,10 +3025,6 @@ Layer(1 "top") Line[235900 68800 223600 56500 1000 2000 "clearline"] Line[223600 56500 223600 35900 1000 2000 "clearline"] Line[223600 35900 220200 32500 1000 2000 "clearline"] - Line[220200 32500 214200 32500 1000 2000 "clearline"] - Line[214200 32500 214100 32400 1000 2000 "clearline"] - Line[200700 36700 200700 32004 1000 2000 "clearline"] - Line[200700 32004 200716 31988 1000 2000 "clearline"] Line[225700 27700 225700 55600 1000 2000 "clearline"] Line[225700 55600 238200 68100 1000 2000 "clearline"] Line[238200 68100 238200 114000 1000 2000 "clearline"] @@ -3049,7 +3046,6 @@ Layer(1 "top") Line[177500 104700 177300 104500 1000 2000 "clearline"] Line[29200 54600 29200 34500 1000 2000 "clearline"] Line[29200 34500 28100 33400 1000 2000 "clearline"] - Line[197500 43400 203000 48900 1000 2000 "clearline"] Line[192600 45200 199700 52300 1000 2000 "clearline"] Line[152488 50689 177789 50689 1000 2000 "clearline"] Line[177789 50689 177800 50700 1000 2000 "clearline"] @@ -3078,12 +3074,6 @@ Layer(1 "top") Line[216383 44783 218800 47200 1000 2000 "clearline"] Line[218800 47200 218800 56400 1000 2000 "clearline"] Line[152488 60531 121600 60600 1000 2000 "clearline"] - Line[213510 50689 209811 50689 1000 2000 "clearline"] - Line[209811 50689 207900 52600 1000 2000 "clearline"] - Line[207900 52600 207900 58000 1000 2000 "clearline"] - Line[207900 58000 205500 60400 1000 2000 "clearline"] - Line[205500 60400 167300 60400 1000 2000 "clearline"] - Line[167300 60400 167200 60500 1000 2000 "clearline"] Line[102300 28800 108200 28800 1000 2000 "clearline"] Line[108100 28800 108900 28000 1000 2000 "clearline"] Line[108850 28050 108900 24792 1000 2000 "clearline"] @@ -3094,13 +3084,6 @@ Layer(1 "top") Line[89900 22500 91400 24000 1000 2000 "clearline"] Line[91400 24000 103900 24000 1000 2000 "clearline"] Line[103900 24000 105000 25100 1000 2000 "clearline"] - Line[213510 48720 208580 48720 1000 2000 "clearline"] - Line[208580 48720 205400 51900 1000 2000 "clearline"] - Line[205400 51900 205400 55000 1000 2000 "clearline"] - Line[205400 55000 202000 58400 1000 2000 "clearline"] - Line[202000 58400 172800 58400 1000 2000 "clearline"] - Line[172800 58400 172200 57800 1000 2000 "clearline"] - Line[172200 57800 160200 57800 1000 2000 "clearline"] Line[160200 57800 160100 57900 1000 2000 "clearline"] Line[152488 78247 149853 78247 1000 2000 "clearline"] Line[149853 78247 146500 81600 1000 2000 "clearline"] @@ -3136,16 +3119,12 @@ Layer(1 "top") Line[213490 86100 213510 86121 1000 2000 "clearline"] Line[53100 41200 49300 45000 1000 2000 "clearline"] Line[49300 45000 49300 82200 1000 2000 "clearline"] - Line[213510 46752 207152 46752 1000 2000 "clearline"] - Line[207152 46752 201000 40600 1000 2000 "clearline"] - Line[201000 40600 187400 40600 1000 2000 "clearline"] - Line[187400 40600 186000 39200 1000 2000 "clearline"] Line[152488 44783 156800 44800 1000 2000 "clearline"] Line[157083 44783 157500 45200 1000 2000 "clearline"] Line[157450 45150 192600 45200 1000 2000 "clearline"] Line[152488 42815 157915 42815 1000 2000 "clearline"] Line[157915 42815 158500 43400 1000 2000 "clearline"] - Line[158500 43400 197500 43400 1000 2000 "clearline"] + Line[158500 43400 199900 43400 1000 2000 "clearline"] Line[181700 64500 202000 64500 1000 2000 "clearline"] Line[155400 89400 155400 86100 1000 2000 "clearline"] Line[152488 86121 155379 86121 1000 2000 "clearline"] @@ -3180,6 +3159,42 @@ Layer(1 "top") Line[174200 84200 169200 89200 1000 2000 "clearline"] Line[169200 89200 169200 92990 1000 2000 "clearline"] Line[169200 92990 169220 93010 1000 2000 "clearline"] + Line[148100 29600 148100 26600 1000 2000 "clearline"] + Line[151248 29600 156000 29600 1000 2000 "clearline"] + Line[202684 23584 200800 21700 1000 2000 "clearline"] + Line[200800 21700 200800 11900 1000 2000 "clearline"] + Line[202684 23584 202684 36384 1000 2000 "clearline"] + Line[202684 36384 203400 37100 1000 2000 "clearline"] + Line[203400 37100 208500 37100 1000 2000 "clearline"] + Line[208500 37100 213100 32500 1000 2000 "clearline"] + Line[220200 32500 213100 32500 1000 2000 "clearline"] + Line[200716 31988 200716 27216 1000 2000 "clearline"] + Line[200716 27216 199900 26400 1000 2000 "clearline"] + Line[199900 26400 186400 26400 1000 2000 "clearline"] + Line[186400 26400 177500 17500 1000 2000 "clearline"] + Line[205900 24600 219900 24600 1000 2000 "clearline"] + Line[219900 24600 224600 19900 1000 2000 "clearline"] + Line[213510 50689 209811 50689 1000 2000 "clearline"] + Line[209811 50689 207900 52600 1000 2000 "clearline"] + Line[207900 52600 207900 58000 1000 2000 "clearline"] + Line[207900 58000 205500 60400 1000 2000 "clearline"] + Line[205500 60400 167300 60400 1000 2000 "clearline"] + Line[167300 60400 167200 60500 1000 2000 "clearline"] + Line[213510 46752 210152 46752 1000 2000 "clearline"] + Line[210152 46752 207700 44300 1000 2000 "clearline"] + Line[207700 44300 204700 44300 1000 2000 "clearline"] + Line[204700 44300 203000 46000 1000 2000 "clearline"] + Line[203000 46000 203000 53400 1000 2000 "clearline"] + Line[203000 53400 198200 58200 1000 2000 "clearline"] + Line[198200 58200 171000 58200 1000 2000 "clearline"] + Line[171000 58200 169700 56900 1000 2000 "clearline"] + Line[169700 56900 161100 56900 1000 2000 "clearline"] + Line[161100 56900 160150 57850 1000 2000 "clearline"] + Line[213510 48720 207720 48720 1000 2000 "clearline"] + Line[207720 48720 206000 47000 1000 2000 "clearline"] + Line[185600 38900 200400 38900 1000 2000 "clearline"] + Line[200400 38900 202400 40900 1000 2000 "clearline"] + Line[202400 40900 206000 40900 1000 2000 "clearline"] Polygon("") ( [308000 1000] [324000 1000] [324000 55500] [308000 55500] @@ -3271,7 +3286,7 @@ Layer(3 "power plane") Line[252500 53700 248700 49900 1000 2000 "clearline"] Line[248700 49900 204800 49900 1000 2000 "clearline"] Line[204900 49900 204000 49900 1000 2000 "clearline"] - Line[204000 49900 203000 48900 1000 2000 "clearline"] + Line[204000 49900 199900 43400 1000 2000 "clearline"] Line[85300 22200 85300 16000 1000 2000 "clearline"] Line[85400 15900 88900 12400 1000 2000 "clearline"] Line[94000 15400 134800 15400 1000 2000 "clearline"] @@ -3285,16 +3300,12 @@ Layer(3 "power plane") Line[149700 10300 88300 10300 1000 2000 "clearline"] Line[81800 16700 88200 10300 1000 2000 "clearline"] Line[81800 24300 81800 16700 1000 2000 "clearline"] - Line[177500 17500 183000 23000 1000 2000 "clearline"] - Line[183000 23000 204300 23000 1000 2000 "clearline"] - Line[204300 23000 206100 24800 1000 2000 "clearline"] Line[209000 27700 209000 17800 1000 2000 "clearline"] Line[209000 17800 196300 5100 1000 2000 "clearline"] Line[196300 5100 184900 5100 1000 2000 "clearline"] Line[184900 5100 182500 7500 1000 2000 "clearline"] Line[224600 19900 230500 28300 1000 2000 "clearline"] Line[275700 122400 275700 106600 1000 2000 "clearline"] - Line[200700 36700 214200 32500 1000 2000 "clearline"] Line[181700 64500 151400 34900 1000 2000 "clearline"] Line[26400 122200 28100 122200 1000 2000 "clearline"] Line[28100 122200 29300 123400 1000 2000 "clearline"] @@ -3375,6 +3386,8 @@ Layer(3 "power plane") Line[205350 80850 206500 82000 1000 2000 "clearline"] Line[206500 82000 208200 82000 1000 2000 "clearline"] Line[208200 82000 208300 81900 1000 2000 "clearline"] + Line[205900 24600 200000 26600 1000 2000 "clearline"] + Line[206000 40900 206000 47000 1000 2000 "clearline"] Polygon("clearpoly,lock") ( [29000 44000] [110000 44000] [110000 81000] [29000 81000] @@ -3409,7 +3422,7 @@ Layer(4 "bottom") Line[167600 117400 167500 117500 1000 2000 "clearline"] Line[174100 37700 174100 105900 1000 2000 "clearline"] Line[174100 105900 172500 107500 1000 2000 "clearline"] - Line[196900 55200 196800 27200 1000 2000 "clearline"] + Line[196900 55200 196800 21700 1000 2000 "clearline"] Line[61600 68800 94900 68800 1000 2000 "clearline"] Line[94900 68800 99300 73200 1000 2000 "clearline"] Line[86100 119500 86100 107000 1000 2000 "clearline"] @@ -3575,6 +3588,7 @@ NetList() Connect("J20-6") Connect("L5-2") Connect("L600-1") + Connect("R29-1") Connect("R171-1") Connect("U1-5") Connect("U3-9") @@ -3906,27 +3920,27 @@ NetList() ( Connect("U3-8") Connect("U4-6") - Connect("U7-46") + Connect("U7-45") ) Net("mi2" "(unknown)") ( Connect("J9-4") Connect("U5-2") Connect("U6-9") - Connect("U7-54") + Connect("U7-53") ) Net("mo1" "(unknown)") ( Connect("U3-11") Connect("U4-7") - Connect("U7-45") + Connect("U7-46") ) Net("mo2" "(unknown)") ( Connect("J9-3") Connect("U5-5") Connect("U6-7") - Connect("U7-53") + Connect("U7-54") ) Net("reset_n" "(unknown)") ( @@ -4260,6 +4274,7 @@ NetList() Net("usbdp" "(unknown)") ( Connect("J5-3") + Connect("R29-2") Connect("U7-71") ) Net("v_batt" "(unknown)") diff --git a/megametrum.sch b/megametrum.sch index 651d357..2885b32 100644 --- a/megametrum.sch +++ b/megametrum.sch @@ -1,8 +1,8 @@ v 20110115 2 C 40000 40000 0 0 0 title-E-bdale.sym -N 54200 61600 53400 61600 4 +N 53200 61600 52400 61600 4 { -T 53700 61700 5 10 1 1 0 0 1 +T 52700 61700 5 10 1 1 0 0 1 netname=v_usb } N 56500 43600 53400 43600 4 @@ -81,7 +81,7 @@ N 81700 47400 81600 47400 4 N 81600 47400 81600 47300 4 T 80900 49800 9 10 1 0 0 0 1 70CM Antenna -C 53500 59700 1 0 1 gnd.sym +C 52500 59700 1 0 1 gnd.sym T 78400 41900 9 30 1 0 0 0 1 MegaMetrum C 41900 59700 1 0 0 3.3V-plus.sym @@ -170,11 +170,11 @@ device=RESISTOR T 63200 48800 5 10 1 1 180 0 1 refdes=R25 T 62800 48300 5 10 1 1 0 0 1 -value=10k +value=15k T 62700 48100 5 10 0 0 0 0 1 footprint=0402 T 62700 48100 5 10 0 0 0 0 1 -vendor_part_number=RMCF1/16S10K1%RCT-ND +vendor_part_number=311-15KJRCT-ND T 62700 48100 5 10 0 0 0 0 1 vendor=digikey T 62700 48100 5 10 0 1 0 0 1 @@ -211,7 +211,7 @@ netname=v_lipo C 62500 46700 1 0 0 gnd.sym T 63400 48600 9 10 1 0 0 0 2 Tolerate up to -4.5V charging +5V charging N 62400 43200 62300 43200 4 N 62300 43200 62300 43600 4 T 82400 40400 9 10 1 0 0 0 1 @@ -2511,29 +2511,29 @@ N 65800 67200 67100 67200 4 T 66900 67300 5 10 1 1 0 0 1 netname=tx3 } -C 53400 59600 1 0 1 USBmicroB.sym +C 52400 59600 1 0 1 USBmicroB.sym { -T 52405 62000 5 10 1 1 0 6 1 +T 51405 62000 5 10 1 1 0 6 1 refdes=J5 -T 53045 59995 5 10 0 1 0 6 1 +T 52045 59995 5 10 0 1 0 6 1 footprint=ZX62-B-5PA -T 53400 59600 5 10 0 0 0 0 1 +T 52400 59600 5 10 0 0 0 0 1 vendor=digikey -T 53400 59600 5 10 0 0 0 0 1 +T 52400 59600 5 10 0 0 0 0 1 vendor_part_number=H11634CT-ND -T 53400 59600 5 10 0 0 0 0 1 +T 52400 59600 5 10 0 0 0 0 1 loadstatus=smt -T 53400 59600 5 10 0 0 0 0 1 +T 52400 59600 5 10 0 0 0 0 1 device=CONNECTOR -T 53400 59600 5 10 0 0 0 0 1 +T 52400 59600 5 10 0 0 0 0 1 value=USBmicroB } -N 56300 61200 53400 61200 4 +N 56300 61200 52400 61200 4 { T 55000 61300 5 10 1 1 0 0 1 netname=usbdm } -N 56300 60800 53400 60800 4 +N 56300 60800 52400 60800 4 { T 55000 60900 5 10 1 1 0 0 1 netname=usbdp @@ -2693,9 +2693,9 @@ N 50900 53900 52000 53900 4 T 52000 54000 5 10 1 1 0 6 1 netname=jntrst } -N 65800 52800 67100 52800 4 +N 65800 52400 67100 52400 4 { -T 66800 52900 5 10 1 1 0 0 1 +T 66800 52500 5 10 1 1 0 0 1 netname=mo1 } N 65800 53200 67100 53200 4 @@ -2703,14 +2703,14 @@ N 65800 53200 67100 53200 4 T 66900 53300 5 10 1 1 0 0 1 netname=c1 } -N 65800 52400 67100 52400 4 +N 65800 52800 67100 52800 4 { -T 66800 52500 5 10 1 1 0 0 1 +T 66800 52900 5 10 1 1 0 0 1 netname=mi1 } -N 56300 53600 55000 53600 4 +N 56300 53200 55000 53200 4 { -T 55300 53700 5 10 1 1 0 6 1 +T 55300 53300 5 10 1 1 0 6 1 netname=mo2 } N 56300 54000 55000 54000 4 @@ -2718,9 +2718,9 @@ N 56300 54000 55000 54000 4 T 55200 54100 5 10 1 1 0 6 1 netname=c2 } -N 56300 53200 55000 53200 4 +N 56300 53600 55000 53600 4 { -T 55300 53300 5 10 1 1 0 6 1 +T 55300 53700 5 10 1 1 0 6 1 netname=mi2 } C 54800 70600 1 0 0 capacitor.sym @@ -3198,3 +3198,22 @@ T 55000 62900 5 10 1 1 0 0 1 netname=v_pbatt } N 61900 72100 62300 72100 4 +C 53700 62500 1 270 0 resistor.sym +{ +T 54100 62200 5 10 0 0 270 0 1 +device=RESISTOR +T 54350 62225 5 10 1 1 180 0 1 +refdes=R29 +T 54000 61800 5 10 1 1 0 0 1 +value=1.5k +T 53700 62500 5 10 0 0 180 0 1 +footprint=0402 +T 53700 62500 5 10 0 0 180 0 1 +vendor_part_number=RMCF1/16S1.5K1%RCT-ND +T 53700 62500 5 10 0 0 180 0 1 +vendor=digikey +T 53700 62500 5 10 0 1 180 0 1 +loadstatus=smt +} +N 53800 60800 53800 61600 4 +C 53600 62500 1 0 0 3.3V-plus.sym diff --git a/symbols/STM32L151.sym b/symbols/STM32L151.sym index f2528bc..1696fe5 100644 --- a/symbols/STM32L151.sym +++ b/symbols/STM32L151.sym @@ -710,7 +710,7 @@ P 9500 7200 9100 7200 1 0 0 T 9195 7245 5 10 1 1 0 0 1 pinnumber=62 T 9045 7195 3 10 1 1 0 6 1 -pinlabel=PC15/TIM4_CH4 +pinlabel=PD15/TIM4_CH4 T 9900 7300 5 10 0 1 0 6 1 pinseq=20 T 9500 7200 5 10 0 1 0 6 1 @@ -831,7 +831,7 @@ P 9500 8400 9100 8400 1 0 0 T 9195 8445 5 10 1 1 0 0 1 pinnumber=59 T 9045 8395 3 10 1 1 0 6 1 -pinlabel=PD12/TIM4_CH/USART3_RTS +pinlabel=PD12/TIM4_CH1/USART3_RTS T 9900 8500 5 10 0 1 0 6 1 pinseq=18 T 9500 8400 5 10 0 1 0 6 1