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2010-11-23	Bdale Garbee	make sure all silk elements are within pcb outline	commit \| commitdiff \| tree
2010-11-23	Bdale Garbee	tweaking silk and attributes	commit \| commitdiff \| tree
2010-11-18	Bdale Garbee	new footprint for the IC with vias, DRC clean again	commit \| commitdiff \| tree
2010-11-18	Bdale Garbee	add explicit netlist connection for exposed ground...	commit \| commitdiff \| tree
2010-11-18	Bdale Garbee	move vias outside the battery connector pads	commit \| commitdiff \| tree
2010-11-11	Bdale Garbee	add targets for automating outputs	commit \| commitdiff \| tree
2010-11-11	Bdale Garbee	fix layout name	commit \| commitdiff \| tree
2010-11-11	Bdale Garbee	fix DFM identified soldermask issues	commit \| commitdiff \| tree
2010-11-11	Bdale Garbee	tweaks based on freedfm.com output	commit \| commitdiff \| tree
2010-11-05	Bdale Garbee	ground prog2, fatten supply and output traces	commit \| commitdiff \| tree
2010-11-05	Bdale Garbee	enabling outline layer causes bogus drc errors, so...	commit \| commitdiff \| tree
2010-11-04	Bdale Garbee	initial capture of LiPo charger	commit \| commitdiff \| tree

charger for single-cell Lithium Polymer batteries