From cea7122fc1843b14a179ed9311677f69c10b38eb Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Wed, 10 Jan 2024 17:24:32 -0700 Subject: [PATCH] altos/stm32f1: Set PLLXTPRE value This is the pre-PLL divider value which is needed when we want to use a 16MHz crystal and a 72MHz sysclk Signed-off-by: Keith Packard --- src/stm32f1/ao_clock.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/stm32f1/ao_clock.c b/src/stm32f1/ao_clock.c index c203b012..3fcf33b8 100644 --- a/src/stm32f1/ao_clock.c +++ b/src/stm32f1/ao_clock.c @@ -123,12 +123,15 @@ ao_clock_init(void) while (stm_rcc.cr & (1UL << STM_RCC_CR_PLLRDY)) asm("nop"); - /* PLLVCO */ + /* PLLMUL */ cfgr = stm_rcc.cfgr; cfgr &= ~(STM_RCC_CFGR_PLLMUL_MASK << STM_RCC_CFGR_PLLMUL); - cfgr |= (AO_RCC_CFGR_PLLMUL << STM_RCC_CFGR_PLLMUL); + /* PLLXTPRE */ + cfgr &= ~(STM_RCC_CFGR_PLLXTPRE_MASK << STM_RCC_CFGR_PLLXTPRE); + cfgr |= (AO_RCC_CFGR_PLLXTPRE << STM_RCC_CFGR_PLLXTPRE); + /* PLL source */ cfgr &= ~(1UL << STM_RCC_CFGR_PLLSRC); cfgr |= STM_RCC_CFGR_PLLSRC_TARGET_CLOCK; -- 2.30.2