From e82cf4199761e900ef176a2a6ddd5d7cfc38bc07 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Sat, 13 Jan 2024 20:57:00 -0800 Subject: [PATCH] altos/stm32f1: Support timers 2,3,4 for fast timer Make the code deal with differences between timer 18 and 234 Signed-off-by: Keith Packard --- src/stm32f1/ao_fast_timer.c | 159 ++++++++++++++++++++++++++---------- 1 file changed, 118 insertions(+), 41 deletions(-) diff --git a/src/stm32f1/ao_fast_timer.c b/src/stm32f1/ao_fast_timer.c index bfbc286a..86e74c11 100644 --- a/src/stm32f1/ao_fast_timer.c +++ b/src/stm32f1/ao_fast_timer.c @@ -22,30 +22,119 @@ static void (*ao_fast_timer_callback[AO_FAST_TIMER_MAX])(void); static uint8_t ao_fast_timer_count; static uint8_t ao_fast_timer_users; +#if AO_FAST_TIMER == 1 + +# define AO_FAST_TIMER_TYPE 18 +# define stm_tim stm_tim1 +# define stm_tim_isr stm_tim1_up_isr +# define STM_ISR_TIM_POS STM_ISR_TIM1_UP_POS +# define STM_RCC_APBENR_TIMEN STM_RCC_APB2ENR_TIM1EN + +#elif AO_FAST_TIMER == 2 + +# define AO_FAST_TIMER_TYPE 234 +# define stm_tim stm_tim2 +# define stm_tim_isr stm_tim2_isr +# define STM_ISR_TIM_POS STM_ISR_TIM2_POS +# define STM_RCC_APBENR_TIMEN STM_RCC_APB1ENR_TIM2EN + +#elif AO_FAST_TIMER == 3 + +# define AO_FAST_TIMER_TYPE 234 +# define stm_tim stm_tim3 +# define stm_tim_isr stm_tim3_isr +# define STM_ISR_TIM_POS STM_ISR_TIM3_POS +# define STM_RCC_APBENR_TIMEN STM_RCC_APB1ENR_TIM3EN + +#elif AO_FAST_TIMER == 4 + +# define AO_FAST_TIMER_TYPE 234 +# define stm_tim stm_tim4 +# define stm_tim_isr stm_tim4_isr +# define STM_ISR_TIM_POS STM_ISR_TIM4_POS +# define STM_RCC_APBENR_TIMEN STM_RCC_APB1ENR_TIM4EN + +#else +#error AO_FAST_TIMER +#endif + +#if AO_FAST_TIMER_TYPE == 18 + +#define STM_TIM_CR1(cen) ((0 << STM_TIM18_CR1_CKD) | \ + (0 << STM_TIM18_CR1_ARPE) | \ + (0 << STM_TIM18_CR1_CMS) | \ + (0 << STM_TIM18_CR1_DIR) | \ + (0 << STM_TIM18_CR1_OPM) | \ + (1 << STM_TIM18_CR1_URS) | \ + (0 << STM_TIM18_CR1_UDIS) | \ + ((cen) << STM_TIM18_CR1_CEN)) +#define STM_TIM_SR_UIF STM_TIM18_SR_UIF +#define STM_TIM_DIER_UIE STM_TIM18_DIER_UIE +#define STM_TIM_EGR_UG STM_TIM18_EGR_UG +#define STM_TIM_CR2_MMS STM_TIM18_CR2_MMS +#define STM_TIM_CR2_MMS_RESET STM_TIM18_CR2_MMS_RESET + +#define AO_TIM_PCLK AO_PCLK2 + +/* + * According to the STM clock-configuration, timers 18 run + * twice as fast as the APB2 clock *if* the APB2 prescaler + * is greater than 1. + */ + +#if AO_APB2_PRESCALER > 1 +#define AO_TIM_SCALER 2 +#else +#define AO_TIM_SCALER 1 +#endif + +#define STM_RCC_APB_TIM stm_rcc.apb2enr + +#elif AO_FAST_TIMER_TYPE == 234 + +#define STM_TIM_CR1(cen) ((STM_TIM234_CR1_CKD_1 << STM_TIM234_CR1_CKD) | \ + (0 << STM_TIM234_CR1_ARPE) | \ + (STM_TIM234_CR1_CMS_EDGE << STM_TIM234_CR1_CMS) | \ + (0 << STM_TIM234_CR1_DIR) | \ + (0 << STM_TIM234_CR1_OPM) | \ + (0 << STM_TIM234_CR1_URS) | \ + (0 << STM_TIM234_CR1_UDIS) | \ + ((cen) << STM_TIM234_CR1_CEN)) \ + +#define AO_TIM_PCLK AO_PCLK1 + +/* + * According to the STM clock-configuration, timers 234 run + * twice as fast as the APB1 clock *if* the APB1 prescaler + * is greater than 1. + */ + +#if AO_APB1_PRESCALER > 1 +#define AO_TIM_SCALER 2 +#else +#define AO_TIM_SCALER 1 +#endif + +#define STM_TIM_SR_UIF STM_TIM234_SR_UIF +#define STM_TIM_DIER_UIE STM_TIM234_DIER_UIE +#define STM_TIM_EGR_UG STM_TIM234_EGR_UG +#define STM_TIM_CR2_MMS STM_TIM234_CR2_MMS +#define STM_TIM_CR2_MMS_RESET STM_TIM234_CR2_MMS_RESET + +#define STM_RCC_APB_TIM stm_rcc.apb1enr + +#endif + static void ao_fast_timer_enable(void) { - stm_tim1.cr1 = ((0 << STM_TIM18_CR1_CKD) | - (0 << STM_TIM18_CR1_ARPE) | - (0 << STM_TIM18_CR1_CMS) | - (0 << STM_TIM18_CR1_DIR) | - (0 << STM_TIM18_CR1_OPM) | - (1 << STM_TIM18_CR1_URS) | - (0 << STM_TIM18_CR1_UDIS) | - (1 << STM_TIM18_CR1_CEN)); + stm_tim.cr1 = STM_TIM_CR1(1); } static void ao_fast_timer_disable(void) { - stm_tim1.cr1 = ((0 << STM_TIM18_CR1_CKD) | - (0 << STM_TIM18_CR1_ARPE) | - (0 << STM_TIM18_CR1_CMS) | - (0 << STM_TIM18_CR1_DIR) | - (0 << STM_TIM18_CR1_OPM) | - (1 << STM_TIM18_CR1_URS) | - (0 << STM_TIM18_CR1_UDIS) | - (0 << STM_TIM18_CR1_CEN)); + stm_tim.cr1 = STM_TIM_CR1(0); } void @@ -72,56 +161,44 @@ ao_fast_timer_off(void (*callback)(void)) } } -void stm_tim1_up_isr(void) +void stm_tim_isr(void) { uint8_t i; - if (stm_tim1.sr & (1 << STM_TIM18_SR_UIF)) { - stm_tim1.sr = 0; + if (stm_tim.sr & (1 << STM_TIM_SR_UIF)) { + stm_tim.sr = 0; for (i = 0; i < ao_fast_timer_count; i++) (*ao_fast_timer_callback[i])(); } } -/* - * According to the STM clock-configuration, timers run - * twice as fast as the APB2 clock *if* the APB2 prescaler - * is greater than 1. - */ - -#if AO_APB1_PRESCALER > 1 -#define TIMER_18_SCALER 2 -#else -#define TIMER_18_SCALER 1 -#endif - #ifndef FAST_TIMER_FREQ #define FAST_TIMER_FREQ 10000 #endif -#define TIMER_FAST ((AO_PCLK2 * TIMER_18_SCALER) / FAST_TIMER_FREQ) +#define TIMER_FAST ((AO_TIM_PCLK * AO_TIM_SCALER) / FAST_TIMER_FREQ) void ao_fast_timer_init(void) { if (!ao_fast_timer_users) { - stm_nvic_set_enable(STM_ISR_TIM1_UP_POS); - stm_nvic_set_priority(STM_ISR_TIM1_UP_POS, AO_STM_NVIC_CLOCK_PRIORITY); + stm_nvic_set_enable(STM_ISR_TIM_POS); + stm_nvic_set_priority(STM_ISR_TIM_POS, AO_STM_NVIC_CLOCK_PRIORITY); /* Turn on timer 1 */ - stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_TIM1EN); + STM_RCC_APB_TIM |= (1 << STM_RCC_APBENR_TIMEN); - stm_tim1.psc = TIMER_FAST; - stm_tim1.arr = 9; - stm_tim1.cnt = 0; + stm_tim.psc = TIMER_FAST; + stm_tim.arr = 9; + stm_tim.cnt = 0; /* Enable update interrupt */ - stm_tim1.dier = (1 << STM_TIM18_DIER_UIE); + stm_tim.dier = (1 << STM_TIM_DIER_UIE); /* Poke timer to reload values */ - stm_tim1.egr |= (1 << STM_TIM18_EGR_UG); + stm_tim.egr |= (1 << STM_TIM_EGR_UG); - stm_tim1.cr2 = (STM_TIM18_CR2_MMS_RESET << STM_TIM18_CR2_MMS); + stm_tim.cr2 = (STM_TIM_CR2_MMS_RESET << STM_TIM_CR2_MMS); ao_fast_timer_disable(); } if (ao_fast_timer_users == AO_FAST_TIMER_MAX) -- 2.30.2