From: Keith Packard <keithp@keithp.com>
Date: Mon, 20 Feb 2023 00:29:56 +0000 (-0800)
Subject: altos/stm32f1: Start work on self-flash code
X-Git-Tag: 1.9.18~2^2~88
X-Git-Url: https://git.gag.com/?p=fw%2Faltos;a=commitdiff_plain;h=58f013162125b2143a5a9f1c0544cb20817e9524

altos/stm32f1: Start work on self-flash code

Looks like this uses the same IP block as the stm32f0 series; copied
the code, haven't gotten it working yet.

Signed-off-by: Keith Packard <keithp@keithp.com>
---

diff --git a/src/stm32f1/ao_flash_stm.c b/src/stm32f1/ao_flash_stm.c
new file mode 100644
index 00000000..0e873d77
--- /dev/null
+++ b/src/stm32f1/ao_flash_stm.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright © 2023 Keith Packard <keithp@keithp.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ */
+
+#include <ao.h>
+#include <ao_flash.h>
+
+/* Note that the HSI clock must be running for this code to work.
+ * Also, special care must be taken with the linker to ensure that the
+ * functions marked 'ramtext' land in ram and not rom. An example of that
+ * can be found in altos-loader.ld
+ */
+
+static uint8_t
+ao_flash_is_locked(void)
+{
+	return (stm_flash.cr & (1 << STM_FLASH_CR_LOCK)) != 0;
+}
+
+static void
+ao_flash_unlock(void)
+{
+	if (!ao_flash_is_locked())
+		return;
+
+	/* Unlock FLASH_CR register */
+	stm_flash.keyr = STM_FLASH_KEYR_KEY1;
+	stm_flash.keyr = STM_FLASH_KEYR_KEY2;
+	if (ao_flash_is_locked())
+		ao_panic(AO_PANIC_FLASH);
+}
+
+static void
+ao_flash_lock(void)
+{
+	stm_flash.cr |= (1 << STM_FLASH_CR_LOCK);
+}
+
+#define ao_flash_wait_bsy() do { while (stm_flash.sr & (1 << STM_FLASH_SR_BSY)); } while (0)
+
+static void __attribute__ ((section(".sdata2.flash"), noinline))
+_ao_flash_erase_page(uint32_t *page)
+{
+	stm_flash.cr |= (1 << STM_FLASH_CR_PER);
+
+	stm_flash.ar = (uintptr_t) page;
+
+	stm_flash.cr |= (1 << STM_FLASH_CR_STRT);
+
+	ao_flash_wait_bsy();
+
+	stm_flash.cr &= ~(1UL << STM_FLASH_CR_PER);
+}
+
+static uint32_t
+stm_flash_page_size(void)
+{
+	uint16_t	dev_id = stm_dev_id();
+
+	switch (dev_id) {
+	case 0x440:	/* stm32f05x */
+	case 0x444:	/* stm32f03x */
+	case 0x445:	/* stm32f04x */
+		return 1024;
+	case 0x442:	/* stm32f09x */
+	case 0x448:	/* stm32f07x */
+		return 2048;
+	}
+	ao_panic(AO_PANIC_FLASH);
+	return 0;
+}
+
+void
+ao_flash_erase_page(uint32_t *page)
+{
+	/* Erase the whole page at the start. This assumes we'll be flashing things
+	 * in memory order
+	 */
+
+	if ((uintptr_t) page & (stm_flash_page_size() - 1))
+		return;
+
+	ao_arch_block_interrupts();
+	ao_flash_unlock();
+
+	_ao_flash_erase_page(page);
+
+	ao_flash_lock();
+	ao_arch_release_interrupts();
+}
+
+static void __attribute__ ((section(".sdata2.flash"), noinline))
+_ao_flash_page(uint16_t *dst, uint16_t *src)
+{
+	uint8_t		i;
+
+	stm_flash.cr |= (1 << STM_FLASH_CR_PG);
+
+	for (i = 0; i < 128; i++) {
+		*dst++ = *src++;
+		ao_flash_wait_bsy();
+	}
+
+	stm_flash.cr &= ~(1UL << STM_FLASH_CR_PG);
+}
+
+void
+ao_flash_page(uint32_t *page, uint32_t *src)
+{
+	ao_flash_erase_page(page);
+
+	ao_arch_block_interrupts();
+	ao_flash_unlock();
+
+	_ao_flash_page((uint16_t *) page, (uint16_t *) src);
+
+	ao_flash_lock();
+	ao_arch_release_interrupts();
+}
diff --git a/src/stm32f1/stm32f1.h b/src/stm32f1/stm32f1.h
index b3b97736..acb3b39a 100644
--- a/src/stm32f1/stm32f1.h
+++ b/src/stm32f1/stm32f1.h
@@ -381,9 +381,25 @@ extern struct stm_flash stm_flash;
 #define  STM_FLASH_ACR_LATENCY_1	1
 #define  STM_FLASH_ACR_LATENCY_2	2
 
+#define STM_FLASH_SR_EOP	5
+#define STM_FLASH_SR_WRPRTERR	4
+#define STM_FLASH_SR_PGERR	2
+#define STM_FLASH_SR_BSY	0
+
+#define STM_FLASH_CR_EOPIE	12
+#define STM_FLASH_CR_ERRIE	10
+#define STM_FLASH_CR_OPTWRE	9
+#define STM_FLASH_CR_LOCK	7
+#define STM_FLASH_CR_STRT	6
+#define STM_FLASH_CR_OPTER	5
+#define STM_FLASH_CR_OPTPG	4
+#define STM_FLASH_CR_MER	2
+#define STM_FLASH_CR_PER	1
+#define STM_FLASH_CR_PG		0
+
 #define STM_FLASH_RDPRT_KEY	0x00A5
-#define STM_FLASH_KEY1		0x45670123
-#define STM_FLASH_KEY2		0xCDEF89AB
+#define STM_FLASH_FPEC_KEY1	0x45670123
+#define STM_FLASH_FPEC_KEY2	0xCDEF89AB
 
 
 struct stm_flash_data {