X-Git-Url: https://git.gag.com/?p=fw%2Faltos;a=blobdiff_plain;f=src%2Fstm32f1%2Fstm32f1.h;h=b3b9773617459962b39bd29d53b8e42a2da7f17f;hp=5ac99e6c3d2496e02301fa20145252d4bdbe8e64;hb=87b64a15f55ecb20a0f8bb2556e77b45a4d82b82;hpb=d2cb18542f4f6071232bd046fd1b257228c17a25 diff --git a/src/stm32f1/stm32f1.h b/src/stm32f1/stm32f1.h index 5ac99e6c..b3b97736 100644 --- a/src/stm32f1/stm32f1.h +++ b/src/stm32f1/stm32f1.h @@ -182,8 +182,8 @@ extern struct stm_rcc stm_rcc; #define STM_RCC_APB1ENR_DACEN 29 #define STM_RCC_APB1ENR_PWREN 28 #define STM_RCC_APB1ENR_BKPEN 27 -#define STM_RCC_APB1ENR_CAN2EN 26 -#define STM_RCC_APB1ENR_CAN1EN 25 +#define STM_RCC_APB1ENR_CANEN 26 +#define STM_RCC_APB1ENR_USBEN 23 #define STM_RCC_APB1ENR_I2C2EN 22 #define STM_RCC_APB1ENR_I2C1EN 21 #define STM_RCC_APB1ENR_UART5EN 20 @@ -193,6 +193,9 @@ extern struct stm_rcc stm_rcc; #define STM_RCC_APB1ENR_SPI3EN 15 #define STM_RCC_APB1ENR_SPI2EN 14 #define STM_RCC_APB1ENR_WWDGEN 11 +#define STM_RCC_APB1ENR_TIM14EN 8 +#define STM_RCC_APB1ENR_TIM13EN 7 +#define STM_RCC_APB1ENR_TIM12EN 6 #define STM_RCC_APB1ENR_TIM7EN 5 #define STM_RCC_APB1ENR_TIM6EN 4 #define STM_RCC_APB1ENR_TIM5EN 3 @@ -219,7 +222,7 @@ struct stm_systick { extern struct stm_systick stm_systick; -#define stm_systick (*((struct stm_systick *) 0xe000e010)) +//#define stm_systick (*((struct stm_systick *) 0xe000e010)) #define STM_SYSTICK_CTRL_ENABLE 0 #define STM_SYSTICK_CTRL_TICKINT 1 @@ -231,49 +234,36 @@ extern struct stm_systick stm_systick; /* The NVIC starts at 0xe000e100, so add that to the offsets to find the absolute address */ struct stm_nvic { - vuint32_t iser[8]; /* 0x000 0xe000e100 Set Enable Register */ + vuint32_t iser[3]; /* 0x000 0xe000e100 Set Enable Register */ - uint8_t _unused020[0x080 - 0x020]; + uint8_t _unused00c[0x080 - 0x00c]; - vuint32_t icer[8]; /* 0x080 0xe000e180 Clear Enable Register */ + vuint32_t icer[3]; /* 0x080 0xe000e180 Clear Enable Register */ - uint8_t _unused0a0[0x100 - 0x0a0]; + uint8_t _unused08c[0x100 - 0x08c]; - vuint32_t ispr[8]; /* 0x100 0xe000e200 Set Pending Register */ + vuint32_t ispr[3]; /* 0x100 0xe000e200 Set Pending Register */ - uint8_t _unused120[0x180 - 0x120]; + uint8_t _unused10c[0x180 - 0x10c]; - vuint32_t icpr[8]; /* 0x180 0xe000e280 Clear Pending Register */ + vuint32_t icpr[3]; /* 0x180 0xe000e280 Clear Pending Register */ - uint8_t _unused1a0[0x200 - 0x1a0]; + uint8_t _unused18c[0x200 - 0x18c]; - vuint32_t iabr[8]; /* 0x200 0xe000e300 Active Bit Register */ + vuint32_t iabr[3]; /* 0x200 0xe000e300 Active Bit Register */ - uint8_t _unused220[0x300 - 0x220]; + uint8_t _unused20c[0x300 - 0x20c]; - vuint32_t ipr[60]; /* 0x300 0xe000e400 Priority Register */ + vuint32_t ipr[31]; /* 0x300 0xe000e400 Priority Register */ - uint8_t _unused3f0[0xc00 - 0x3f0]; + uint8_t _unused37c[0xe00 - 0x37c]; /* covers SCB */ - vuint32_t cpuid_base; /* 0xc00 0xe000ed00 CPUID Base Register */ - vuint32_t ics; /* 0xc04 0xe000ed04 Interrupt Control State Register */ - vuint32_t vto; /* 0xc08 0xe000ed08 Vector Table Offset Register */ - vuint32_t ai_rc; /* 0xc0c 0xe000ed0c Application Interrupt/Reset Control Register */ - vuint32_t sc; /* 0xc10 0xe000ed10 System Control Register */ - vuint32_t cc; /* 0xc14 0xe000ed14 Configuration Control Register */ - - vuint32_t shpr7_4; /* 0xc18 0xe000ed18 System Hander Priority Registers */ - vuint32_t shpr11_8; /* 0xc1c */ - vuint32_t shpr15_12; /* 0xc20 */ - - uint8_t _unusedc18[0xe00 - 0xc24]; - - vuint32_t stir; /* 0xe00 */ + vuint32_t stir; /* 0xe00 0xe000ee00 Software Trigger Interrupt Register */ }; extern struct stm_nvic stm_nvic; -#define stm_nvic (*((struct stm_nvic *) 0xe000e100)) +//#define stm_nvic (*((struct stm_nvic *) 0xe000e100)) #define IRQ_REG(irq) ((irq) >> 5) #define IRQ_BIT(irq) ((irq) & 0x1f) @@ -335,6 +325,67 @@ stm_nvic_get_priority(int irq) { return (stm_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0); } +struct stm_scb { + vuint32_t cpuid; + vuint32_t icsr; + vuint32_t vtor; + vuint32_t aircr; + + vuint32_t scr; + vuint32_t ccr; + vuint32_t shpr1; + vuint32_t shpr2; + + vuint32_t shpr3; + vuint32_t shcrs; + vuint32_t cfsr; + vuint32_t hfsr; + + uint32_t unused_30; + vuint32_t mmar; + vuint32_t bfar; +}; + +extern struct stm_scb stm_scb; + +#define STM_SCB_AIRCR_VECTKEY 16 +#define STM_SCB_AIRCR_VECTKEY_KEY 0x05fa +#define STM_SCB_AIRCR_PRIGROUP 8 +#define STM_SCB_AIRCR_SYSRESETREQ 2 +#define STM_SCB_AIRCR_VECTCLRACTIVE 1 +#define STM_SCB_AIRCR_VECTRESET 0 + +struct stm_flash { + vuint32_t acr; + vuint32_t keyr; + vuint32_t optkeyr; + vuint32_t sr; + + vuint32_t cr; + vuint32_t ar; + uint32_t _unused018; + vuint32_t obr; + + vuint32_t wrpr; +}; + +extern struct stm_flash stm_flash; + +//#define stm_flash (*((struct stm_flash *) 0x40022000)) + +#define STM_FLASH_ACR_PRFTBS 5 +#define STM_FLASH_ACR_PRFTBE 4 +#define STM_FLASH_ACR_HLFCYA 3 +#define STM_FLASH_ACR_LATENCY 0 +#define STM_FLASH_ACR_LATENCY_0 0 +#define STM_FLASH_ACR_LATENCY_1 1 +#define STM_FLASH_ACR_LATENCY_2 2 + +#define STM_FLASH_RDPRT_KEY 0x00A5 +#define STM_FLASH_KEY1 0x45670123 +#define STM_FLASH_KEY2 0xCDEF89AB + + struct stm_flash_data { vuint16_t f_size; vuint16_t unused02; @@ -346,7 +397,7 @@ extern struct stm_flash_data stm_flash_data; static inline uint32_t stm_flash_size(void) { return (uint32_t) stm_flash_data.f_size * 1024; } -#define stm_flash_data (*((struct stm_flash_data *) 0x1ffff7e0)) +//#define stm_flash_data (*((struct stm_flash_data *) 0x1ffff7e0)) struct stm_gpio { vuint32_t cr[2]; @@ -425,11 +476,11 @@ extern struct stm_gpio stm_gpioc; extern struct stm_gpio stm_gpiod; extern struct stm_gpio stm_gpioe; -#define stm_gpioe (*((struct stm_gpio *) 0x40011800)) -#define stm_gpiod (*((struct stm_gpio *) 0x40011400)) -#define stm_gpioc (*((struct stm_gpio *) 0x40011000)) -#define stm_gpiob (*((struct stm_gpio *) 0x40010c00)) -#define stm_gpioa (*((struct stm_gpio *) 0x40010800)) +//#define stm_gpioe (*((struct stm_gpio *) 0x40011800)) +//#define stm_gpiod (*((struct stm_gpio *) 0x40011400)) +//#define stm_gpioc (*((struct stm_gpio *) 0x40011000)) +//#define stm_gpiob (*((struct stm_gpio *) 0x40010c00)) +//#define stm_gpioa (*((struct stm_gpio *) 0x40010800)) struct stm_afio { vuint32_t evcr; @@ -440,7 +491,266 @@ struct stm_afio { extern struct stm_afio stm_afio; -#define stm_afio (*((struct stm_afio *) 0x40010000)) +//#define stm_afio (*((struct stm_afio *) 0x40010000)) + +#define STM_AFIO_MAPR_ADC2_ETRGREG_REMAP 20 +#define STM_AFIO_MAPR_ADC2_ETRGINJ_REMAP 19 +#define STM_AFIO_MAPR_ADC1_ETRGREG_REMAP 18 +#define STM_AFIO_MAPR_ADC1_ETRGINJ_REMAP 17 +#define STM_AFIO_MAPR_TIM5CH4_IREMAP 16 +#define STM_AFIO_MAPR_PD01_REMAP 15 +#define STM_AFIO_MAPR_CAN_REMAP 13 +#define STM_AFIO_MAPR_CAN_REMAP_PA11_PA12 0 +#define STM_AFIO_MAPR_CAN_REMAP_PB8_PB9 2 +#define STM_AFIO_MAPR_CAN_REMAP_PD0_PD1 3 +#define STM_AFIO_MAPR_CAN_REMAP_MASK 3 +#define STM_AFIO_MAPR_TIM4_REMAP 12 +#define STM_AFIO_MAPR_TIM3_REMAP 10 +#define STM_AFIO_MAPR_TIM3_REMAP_PA6_PA7_PB0_PB1 0 +#define STM_AFIO_MAPR_TIM3_REMAP_PB4_PB5_PB0_PB1 2 +#define STM_AFIO_MAPR_TIM3_REMAP_PC6_PC7_PC8_PC9 3 +#define STM_AFIO_MAPR_TIM3_REMAP_MASK 3 +#define STM_AFIO_MAPR_TIM2_REMAP 8 +#define STM_AFIO_MAPR_TIM2_REMAP_PA0_PA1_PA2_PA3 0 +#define STM_AFIO_MAPR_TIM2_REMAP_PA15_PB3_PA2_PA3 1 +#define STM_AFIO_MAPR_TIM2_REMAP_PA0_PA1_PB10_PB11 2 +#define STM_AFIO_MAPR_TIM2_REMAP_PA15_PB3_PB10_PB11 3 +#define STM_AFIO_MAPR_TIM2_REMAP_MASK 3 +#define STM_AFIO_MAPR_TIM1_REMAP 6 +#define STM_AFIO_MAPR_TIM1_REMAP_PA12_PA8_PA9_PA10_PA11_PB12_PB13_PB14_PB15 0 +#define STM_AFIO_MAPR_TIM1_REMAP_PA12_PA8_PA9_PA10_PA11_PA6_PA7_PB0_PB1 1 +#define STM_AFIO_MAPR_TIM1_REMAP_PE7_PE9_PE11_PE13_PE14_PE15_PE8_PE10_PE12 3 +#define STM_AFIO_MAPR_TIM1_REMAP_MASK 3 +#define STM_AFIO_MAPR_USART3_REMAP 4 +#define STM_AFIO_MAPR_USART3_REMAP_PB10_PB11_PB12_PB13_PB14 0 +#define STM_AFIO_MAPR_USART3_REMAP_PC10_PC11_PC12_PB13_PB14 1 +#define STM_AFIO_MAPR_USART3_REMAP_PD8_PD9_PD10_PD11_PD12 3 +#define STM_AFIO_MAPR_USART3_REMAP_MASK 3 +#define STM_AFIO_MAPR_USART2_REMAP 3 +#define STM_AFIO_MAPR_USART2_REMAP_PA0_PA1_PA2_PA3_PA4 0 +#define STM_AFIO_MAPR_USART2_REMAP_PD3_PD4_PD5_PD6_PD7 1 +#define STM_AFIO_MAPR_USART2_REMAP_MASK 1 +#define STM_AFIO_MAPR_USART1_REMAP 2 +#define STM_AFIO_MAPR_USART1_REMAP_PA9_PA10 0 +#define STM_AFIO_MAPR_USART1_REMAP_PB6_PB7 1 +#define STM_AFIO_MAPR_USART1_REMAP_MASK 1 +#define STM_AFIO_MAPR_I2C1_REMAP 1 +#define STM_AFIO_MAPR_I2C1_REMAP_PB6_PB7 0 +#define STM_AFIO_MAPR_I2C1_REMAP_PB8_PB9 1 +#define STM_AFIO_MAPR_I2C1_REMAP_MASK 1 +#define STM_AFIO_MAPR_SPI1_REMAP 0 +#define STM_AFIO_MAPR_SPI1_REMAP_PA4_PA5_PA6_PA7 0 +#define STM_AFIO_MAPR_SPI1_REMAP_PA15_PB3_PB4_PB5 1 +#define STM_AFIO_MAPR_SPI1_REMAP_MASK 1 + +static inline void +stm_set_afio_mapr(uint8_t bit, uint32_t val, uint32_t mask) { + uint32_t mapr = stm_afio.mapr; + + mapr &= ~(mask << bit); + mapr |= (val << bit); + stm_afio.mapr = mapr; +} + +struct stm_usart { + vuint32_t sr; /* status register */ + vuint32_t dr; /* data register */ + vuint32_t brr; /* baud rate register */ + vuint32_t cr1; /* control register 1 */ + + vuint32_t cr2; /* control register 2 */ + vuint32_t cr3; /* control register 3 */ + vuint32_t gtpr; /* guard time and prescaler */ +}; + +extern struct stm_usart stm_usart1; +extern struct stm_usart stm_usart2; +extern struct stm_usart stm_usart3; + +//#define stm_usart1 (*((struct stm_usart *) 0x40013800)) +//#define stm_usart2 (*((struct stm_usart *) 0x40004800)) +//#define stm_usart3 (*((struct stm_usart *) 0x40004400)) + +#define STM_USART_SR_CTS (9) /* CTS flag */ +#define STM_USART_SR_LBD (8) /* LIN break detection flag */ +#define STM_USART_SR_TXE (7) /* Transmit data register empty */ +#define STM_USART_SR_TC (6) /* Transmission complete */ +#define STM_USART_SR_RXNE (5) /* Read data register not empty */ +#define STM_USART_SR_IDLE (4) /* IDLE line detected */ +#define STM_USART_SR_ORE (3) /* Overrun error */ +#define STM_USART_SR_NE (2) /* Noise detected flag */ +#define STM_USART_SR_FE (1) /* Framing error */ +#define STM_USART_SR_PE (0) /* Parity error */ + +#define STM_USART_BRR_DIV_MANTISSA (4) +#define STM_USART_BRR_DIV_FRACTION (0) + +#define STM_USART_CR1_UE (13) /* USART enable */ +#define STM_USART_CR1_M (12) /* Word length */ +#define STM_USART_CR1_WAKE (11) /* Wakeup method */ +#define STM_USART_CR1_PCE (10) /* Parity control enable */ +#define STM_USART_CR1_PS (9) /* Parity selection */ +#define STM_USART_CR1_PEIE (8) /* PE interrupt enable */ +#define STM_USART_CR1_TXEIE (7) /* TXE interrupt enable */ +#define STM_USART_CR1_TCIE (6) /* Transmission complete interrupt enable */ +#define STM_USART_CR1_RXNEIE (5) /* RXNE interrupt enable */ +#define STM_USART_CR1_IDLEIE (4) /* IDLE interrupt enable */ +#define STM_USART_CR1_TE (3) /* Transmitter enable */ +#define STM_USART_CR1_RE (2) /* Receiver enable */ +#define STM_USART_CR1_RWU (1) /* Receiver wakeup */ +#define STM_USART_CR1_SBK (0) /* Send break */ + +#define STM_USART_CR2_LINEN (14) /* LIN mode enable */ +#define STM_USART_CR2_STOP (12) /* STOP bits */ +#define STM_USART_CR2_STOP_MASK 3UL +#define STM_USART_CR2_STOP_1 0 +#define STM_USART_CR2_STOP_0_5 1 +#define STM_USART_CR2_STOP_2 2 +#define STM_USART_CR2_STOP_1_5 3 + +#define STM_USART_CR2_CLKEN (11) /* Clock enable */ +#define STM_USART_CR2_CPOL (10) /* Clock polarity */ +#define STM_USART_CR2_CPHA (9) /* Clock phase */ +#define STM_USART_CR2_LBCL (8) /* Last bit clock pulse */ +#define STM_USART_CR2_LBDIE (6) /* LIN break detection interrupt enable */ +#define STM_USART_CR2_LBDL (5) /* lin break detection length */ +#define STM_USART_CR2_ADD (0) +#define STM_USART_CR2_ADD_MASK 0xfUL + +#define STM_USART_CR3_CTSIE (10) /* CTS interrupt enable */ +#define STM_USART_CR3_CTSE (9) /* CTS enable */ +#define STM_USART_CR3_RTSE (8) /* RTS enable */ +#define STM_USART_CR3_DMAT (7) /* DMA enable transmitter */ +#define STM_USART_CR3_DMAR (6) /* DMA enable receiver */ +#define STM_USART_CR3_SCEN (5) /* Smartcard mode enable */ +#define STM_USART_CR3_NACK (4) /* Smartcard NACK enable */ +#define STM_USART_CR3_HDSEL (3) /* Half-duplex selection */ +#define STM_USART_CR3_IRLP (2) /* IrDA low-power */ +#define STM_USART_CR3_IREN (1) /* IrDA mode enable */ +#define STM_USART_CR3_EIE (0) /* Error interrupt enable */ + +struct stm_usb { + vuint32_t epr[8]; + uint8_t reserved_20[0x40 - 0x20]; + vuint32_t cntr; + vuint32_t istr; + vuint32_t fnr; + vuint32_t daddr; + vuint32_t btable; +}; + +/* + * USB DM: PA11 + * USB DP: PA12 + * + * Need a pull-up on a separate GPIO + */ +#define STM_USB_EPR_CTR_RX 15 +#define STM_USB_EPR_CTR_RX_WRITE_INVARIANT 1 +#define STM_USB_EPR_DTOG_RX 14 +#define STM_USB_EPR_DTOG_RX_WRITE_INVARIANT 0 +#define STM_USB_EPR_STAT_RX 12 +#define STM_USB_EPR_STAT_RX_DISABLED 0 +#define STM_USB_EPR_STAT_RX_STALL 1 +#define STM_USB_EPR_STAT_RX_NAK 2 +#define STM_USB_EPR_STAT_RX_VALID 3 +#define STM_USB_EPR_STAT_RX_MASK 3UL +#define STM_USB_EPR_STAT_RX_WRITE_INVARIANT 0 +#define STM_USB_EPR_SETUP 11 +#define STM_USB_EPR_EP_TYPE 9 +#define STM_USB_EPR_EP_TYPE_BULK 0 +#define STM_USB_EPR_EP_TYPE_CONTROL 1 +#define STM_USB_EPR_EP_TYPE_ISO 2 +#define STM_USB_EPR_EP_TYPE_INTERRUPT 3 +#define STM_USB_EPR_EP_TYPE_MASK 3UL +#define STM_USB_EPR_EP_KIND 8 +#define STM_USB_EPR_EP_KIND_DBL_BUF 1 /* Bulk */ +#define STM_USB_EPR_EP_KIND_STATUS_OUT 1 /* Control */ +#define STM_USB_EPR_CTR_TX 7 +#define STM_USB_CTR_TX_WRITE_INVARIANT 1 +#define STM_USB_EPR_DTOG_TX 6 +#define STM_USB_EPR_DTOG_TX_WRITE_INVARIANT 0 +#define STM_USB_EPR_STAT_TX 4 +#define STM_USB_EPR_STAT_TX_DISABLED 0 +#define STM_USB_EPR_STAT_TX_STALL 1 +#define STM_USB_EPR_STAT_TX_NAK 2 +#define STM_USB_EPR_STAT_TX_VALID 3 +#define STM_USB_EPR_STAT_TX_WRITE_INVARIANT 0 +#define STM_USB_EPR_STAT_TX_MASK 3UL +#define STM_USB_EPR_EA 0 +#define STM_USB_EPR_EA_MASK 0xfUL + +#define STM_USB_CNTR_CTRM 15 +#define STM_USB_CNTR_PMAOVRM 14 +#define STM_USB_CNTR_ERRM 13 +#define STM_USB_CNTR_WKUPM 12 +#define STM_USB_CNTR_SUSPM 11 +#define STM_USB_CNTR_RESETM 10 +#define STM_USB_CNTR_SOFM 9 +#define STM_USB_CNTR_ESOFM 8 +#define STM_USB_CNTR_RESUME 4 +#define STM_USB_CNTR_FSUSP 3 +#define STM_USB_CNTR_LP_MODE 2 +#define STM_USB_CNTR_PDWN 1 +#define STM_USB_CNTR_FRES 0 + +#define STM_USB_ISTR_CTR 15 +#define STM_USB_ISTR_PMAOVR 14 +#define STM_USB_ISTR_ERR 13 +#define STM_USB_ISTR_WKUP 12 +#define STM_USB_ISTR_SUSP 11 +#define STM_USB_ISTR_RESET 10 +#define STM_USB_ISTR_SOF 9 +#define STM_USB_ISTR_ESOF 8 +#define STM_USB_ISTR_DIR 4 +#define STM_USB_ISTR_EP_ID 0 +#define STM_USB_ISTR_EP_ID_MASK 0xfUL + +#define STM_USB_FNR_RXDP 15 +#define STM_USB_FNR_RXDM 14 +#define STM_USB_FNR_LCK 13 +#define STM_USB_FNR_LSOF 11 +#define STM_USB_FNR_LSOF_MASK 0x3UL +#define STM_USB_FNR_FN 0 +#define STM_USB_FNR_FN_MASK 0x7ffUL + +#define STM_USB_DADDR_EF 7 +#define STM_USB_DADDR_ADD 0 +#define STM_USB_DADDR_ADD_MASK 0x7fUL + +extern struct stm_usb stm_usb; + + +//#define stm_usb (*((struct stm_usb *) 0x40005c00)) + +union stm_usb_bdt { + struct { + vuint32_t addr_tx; + vuint32_t count_tx; + vuint32_t addr_rx; + vuint32_t count_rx; + } single; + struct { + vuint32_t addr; + vuint32_t count; + } double_tx[2]; + struct { + vuint32_t addr; + vuint32_t count; + } double_rx[2]; +}; + +#define STM_USB_BDT_COUNT_RX_BL_SIZE 15 +#define STM_USB_BDT_COUNT_RX_NUM_BLOCK 10 +#define STM_USB_BDT_COUNT_RX_NUM_BLOCK_MASK 0x1fUL +#define STM_USB_BDT_COUNT_RX_COUNT_RX 0 +#define STM_USB_BDT_COUNT_RX_COUNT_RX_MASK 0x3ffUL + +#define STM_USB_BDT_SIZE 8 + +extern uint8_t stm_usb_sram[] __attribute__ ((aligned(4))); + +//#define stm_usb_sram ((uint8_t *)0x40006000); #define isr_decl(name) void stm_ ## name ## _isr(void) @@ -519,4 +829,65 @@ isr_decl(dma2_channel4_5); #undef isr_decl +#define STM_ISR_WWDG_POS 0 +#define STM_ISR_PVD_POS 1 +#define STM_ISR_TAMPER_STAMP_POS 2 +#define STM_ISR_RTC_WKUP_POS 3 +#define STM_ISR_FLASH_POS 4 +#define STM_ISR_RCC_POS 5 +#define STM_ISR_EXTI0_POS 6 +#define STM_ISR_EXTI1_POS 7 +#define STM_ISR_EXTI2_POS 8 +#define STM_ISR_EXTI3_POS 9 +#define STM_ISR_EXTI4_POS 10 +#define STM_ISR_DMA1_CHANNEL1_POS 11 +#define STM_ISR_DMA1_CHANNEL2_POS 12 +#define STM_ISR_DMA1_CHANNEL3_POS 13 +#define STM_ISR_DMA1_CHANNEL4_POS 14 +#define STM_ISR_DMA1_CHANNEL5_POS 15 +#define STM_ISR_DMA1_CHANNEL6_POS 16 +#define STM_ISR_DMA1_CHANNEL7_POS 17 +#define STM_ISR_ADC1_2_POS 18 +#define STM_ISR_USB_HP_POS 19 +#define STM_ISR_USB_LP_POS 20 +#define STM_ISR_CAN_RX1_POS 21 +#define STM_ISR_CAN_SCE_POS 22 +#define STM_ISR_EXTI9_5_POS 23 +#define STM_ISR_TIM1_BRK_POS 24 +#define STM_ISR_TIM1_UP_POS 25 +#define STM_ISR_TIM1_TRG_COM_POS 26 +#define STM_ISR_TIM1_CC_POS 27 +#define STM_ISR_TIM2_POS 28 +#define STM_ISR_TIM3_POS 29 +#define STM_ISR_TIM4_POS 30 +#define STM_ISR_I2C1_EV_POS 31 +#define STM_ISR_I2C1_ER_POS 32 +#define STM_ISR_I2C2_EV_POS 33 +#define STM_ISR_I2C2_ER_POS 34 +#define STM_ISR_SPI1_POS 35 +#define STM_ISR_SPI2_POS 36 +#define STM_ISR_USART1_POS 37 +#define STM_ISR_USART2_POS 38 +#define STM_ISR_USART3_POS 39 +#define STM_ISR_EXTI15_10_POS 40 +#define STM_ISR_RTC_ALARM_POS 41 +#define STM_ISR_USB_WAKEUP_POS 42 +#define STM_ISR_TIM8_BRK_POS 43 +#define STM_ISR_TIM8_UP_POS 44 +#define STM_ISR_TIM8_TRG_COM_POS 45 +#define STM_ISR_TIM8_CC_POS 46 +#define STM_ISR_ADC3_POS 47 +#define STM_ISR_FSMC_POS 48 +#define STM_ISR_SDIO_POS 49 +#define STM_ISR_TIM5_POS 50 +#define STM_ISR_SPI3_POS 51 +#define STM_ISR_UART4_POS 52 +#define STM_ISR_UART5_POS 53 +#define STM_ISR_TIM6_POS 54 +#define STM_ISR_TIM7_POS 55 +#define STM_ISR_DMA2_CHANNEL1_POS 56 +#define STM_ISR_DMA2_CHANNEL2_POS 57 +#define STM_ISR_DMA2_CHANNEL3_POS 58 +#define STM_ISR_DMA3_CHANNEL4_5_POS 59 + #endif