Imported Upstream version 3.2.2

[debian/gnuradio] / usrp / fpga / toplevel / usrp_std / usrp_std.v

diff --git a/usrp/fpga/toplevel/usrp_std/usrp_std.v b/usrp/fpga/toplevel/usrp_std/usrp_std.v
index ea556d70f0aebac77b0f70c0e0889bbdfa5dc870..8b29a9c21ea712048805d6ad8101109de1634ccb 100644 (file)
--- a/usrp/fpga/toplevel/usrp_std/usrp_std.v
+++ b/usrp/fpga/toplevel/usrp_std/usrp_std.v
@@ -27,7 +27,7 @@
 
 // Uncomment the following to include optional circuitry
 
-`include "usrp_std.vh"
+`include "config.vh"
 `include "../../../firmware/include/fpga_regs_common.v"
 `include "../../../firmware/include/fpga_regs_standard.v"
 
@@ -93,7 +93,7 @@ module usrp_std
    wire [2:0]  tx_numchan;
    
    wire [7:0]  interp_rate, decim_rate;
-   wire [15:0] tx_debugbus, rx_debugbus;
+   wire [31:0] tx_debugbus, rx_debugbus;
    
    wire        enable_tx, enable_rx;
    wire        tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset;
@@ -124,35 +124,44 @@ module usrp_std
    ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
    // Transmit Side
 `ifdef TX_ON
-   assign     bb_tx_i0 = ch0tx;
+   assign      bb_tx_i0 = ch0tx;
    assign      bb_tx_q0 = ch1tx;
    assign      bb_tx_i1 = ch2tx;
    assign      bb_tx_q1 = ch3tx;
    
    tx_buffer tx_buffer
-     ( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),
-       .usbdata(usbdata),.WR(WR),.have_space(have_space),.tx_underrun(tx_underrun),
+     ( .usbclk(usbclk), .bus_reset(tx_bus_reset),
+       .usbdata(usbdata),.WR(WR), .have_space(have_space),
+       .tx_underrun(tx_underrun), .clear_status(clear_status),
+       .txclk(clk64), .reset(tx_dsp_reset),
        .channels({tx_numchan,1'b0}),
        .tx_i_0(ch0tx),.tx_q_0(ch1tx),
        .tx_i_1(ch2tx),.tx_q_1(ch3tx),
-       .tx_i_2(),.tx_q_2(),
-       .tx_i_3(),.tx_q_3(),
-       .txclk(clk64),.txstrobe(strobe_interp),
-       .clear_status(clear_status),
+       .txstrobe(strobe_interp),
        .tx_empty(tx_empty),
        .debugbus(tx_debugbus) );
-
+   
+ `ifdef TX_EN_0
    tx_chain tx_chain_0
      ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
        .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe),
        .interpolator_strobe(strobe_interp),.freq(),
        .i_in(bb_tx_i0),.q_in(bb_tx_q0),.i_out(i_out_0),.q_out(q_out_0) );
+ `else
+   assign      i_out_0=16'd0;
+   assign      q_out_0=16'd0;
+ `endif
 
+ `ifdef TX_EN_1
    tx_chain tx_chain_1
      ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
        .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe),
        .interpolator_strobe(strobe_interp),.freq(),
        .i_in(bb_tx_i1),.q_in(bb_tx_q1),.i_out(i_out_1),.q_out(q_out_1) );
+ `else
+   assign      i_out_1=16'd0;
+   assign      q_out_1=16'd0;
+ `endif
 
    setting_reg #(`FR_TX_MUX) 
      sr_txmux(.clock(clk64),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
@@ -307,8 +316,8 @@ module usrp_std
        .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
        .tx_empty(tx_empty),
        //.debug_0(rx_a_a),.debug_1(ddc0_in_i),
-       .debug_0(rx_debugbus),.debug_1(ddc0_in_i),
-       .debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,tx_underrun,rx_overrun,decim_rate}),
+       .debug_0(tx_debugbus[15:0]),.debug_1(tx_debugbus[31:16]),
+       .debug_2(rx_debugbus[15:0]),.debug_3(rx_debugbus[31:16]),
        .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) );
    
    io_pins io_pins