Imported Upstream version 3.2.2

[debian/gnuradio] / usrp / fpga / toplevel / usrp_multi / usrp_multi.qsf

diff --git a/usrp/fpga/toplevel/usrp_multi/usrp_multi.qsf b/usrp/fpga/toplevel/usrp_multi/usrp_multi.qsf
index e45c683af09642ac7883af29e413009c106f10ab..9f0efbd83d69008b3f49adde60bc30610696bb11 100644 (file)
--- a/usrp/fpga/toplevel/usrp_multi/usrp_multi.qsf
+++ b/usrp/fpga/toplevel/usrp_multi/usrp_multi.qsf
@@ -27,7 +27,7 @@
 # ========================\r
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0\r
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04  JULY 13, 2003"\r
-set_global_assignment -name LAST_QUARTUS_VERSION "5.1 SP1"\r
+set_global_assignment -name LAST_QUARTUS_VERSION 6.1\r
 \r
 # Pin & Location Assignments\r
 # ==========================\r
@@ -223,7 +223,7 @@ set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED
 set_global_assignment -name TOP_LEVEL_ENTITY usrp_multi\r
 set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF\r
 set_global_assignment -name USER_LIBRARIES "H:\\usrp-for2.7\\fpga\\megacells"\r
-set_global_assignment -name AUTO_ENABLE_SMART_COMPILE On\r
+set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON\r
 \r
 # Fitter Assignments\r
 # ==================\r
@@ -314,7 +314,7 @@ set_global_assignment -name HCPY_VREF_PINS OFF
 # ========================\r
 set_global_assignment -name HUB_ENTITY_NAME SLD_HUB\r
 set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST\r
-set_global_assignment -name ENABLE_SIGNALTAP Off\r
+set_global_assignment -name ENABLE_SIGNALTAP OFF\r
 \r
 # LogicLock Region Assignments\r
 # ============================\r
@@ -326,8 +326,8 @@ set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF
        # Timing Assignments\r
        # ==================\r
 set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK\r
-       set_global_assignment -name FMAX_REQUIREMENT "1.0 MHz" -section_id SCLK\r
-       set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id SCLK\r
+set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK\r
+set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id SCLK\r
 \r
 # end CLOCK(SCLK)\r
 # ---------------\r
@@ -338,8 +338,8 @@ set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK
        # Timing Assignments\r
        # ==================\r
 set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk\r
-       set_global_assignment -name FMAX_REQUIREMENT "64.0 MHz" -section_id master_clk\r
-       set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id master_clk\r
+set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk\r
+set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id master_clk\r
 \r
 # end CLOCK(master_clk)\r
 # ---------------------\r
@@ -350,8 +350,8 @@ set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk
        # Timing Assignments\r
        # ==================\r
 set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk\r
-       set_global_assignment -name FMAX_REQUIREMENT "48.0 MHz" -section_id usbclk\r
-       set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id usbclk\r
+set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk\r
+set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id usbclk\r
 \r
 # end CLOCK(usbclk)\r
 # -----------------\r
@@ -361,18 +361,18 @@ set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk
 \r
        # Timing Assignments\r
        # ==================\r
-       set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK\r
-       set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk\r
-       set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk\r
+set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK\r
+set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk\r
+set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk\r
 \r
 # end ENTITY(usrp_multi)\r
 # --------------------\r
 \r
 \r
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/rssi.v\r
 set_global_assignment -name VERILOG_FILE ../../sdr_lib/setting_reg_masked.v\r
 set_global_assignment -name VERILOG_FILE ../../sdr_lib/master_control_multi.v\r
 set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v\r
-set_global_assignment -name VERILOG_FILE usrp_multi.vh\r
 set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k.v\r
 set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/acc.v\r
 set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mult.v\r