Imported Upstream version 3.2.2

[debian/gnuradio] / usrp / firmware / include / fpga_regs_common.v

diff --git a/usrp/firmware/include/fpga_regs_common.v b/usrp/firmware/include/fpga_regs_common.v
index ee87ac025edd63ca8159982eefad6f90da4c67a8..8035d856570a1672416ba8747c48f7d46d8d672b 100644 (file)
--- a/usrp/firmware/include/fpga_regs_common.v
+++ b/usrp/firmware/include/fpga_regs_common.v
@@ -1,5 +1,5 @@
 //
-// This file is machine generated from fpga_regs_common.h
+// This file is machine generated from ./fpga_regs_common.h
 // Do not edit by hand; your edits will be overwritten.
 //
 
@@ -13,8 +13,7 @@
 `define FR_TX_SAMPLE_RATE_DIV     7'd0
 `define FR_RX_SAMPLE_RATE_DIV     7'd1
 
-// 2 is available.
-// 3 is available.
+// 2 and 3 are defined in the ATR section
 
 `define FR_MASTER_CTRL            7'd4 // master enable and reset controls
 
@@ -112,3 +111,7 @@
 `define FR_ATR_TXVAL_3            7'd30
 `define FR_ATR_RXVAL_3            7'd31
 
+// Clock ticks to delay rising and falling edge of T/R signal
+`define FR_ATR_TX_DELAY           7'd2
+`define FR_ATR_RX_DELAY           7'd3
+