From d8880177eb975f240141e0b9abf3a58c3f99b1cb Mon Sep 17 00:00:00 2001 From: frief Date: Mon, 31 Mar 2008 17:07:25 +0000 Subject: [PATCH] * device/include/hc08/mc68hc908jkjl.h: committed fix for bug #1929739, thanks Alejandro Pustowka git-svn-id: https://sdcc.svn.sourceforge.net/svnroot/sdcc/trunk/sdcc@5131 4a8a32a2-be11-0410-ad9d-d568d2c75423 --- ChangeLog | 5 +++++ device/include/hc08/mc68hc908jkjl.h | 27 +++++++++++++-------------- 2 files changed, 18 insertions(+), 14 deletions(-) diff --git a/ChangeLog b/ChangeLog index b2fa61b3..5ae30138 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,8 @@ +2008-03-31 Frieder Ferlemann + + * device/include/hc08/mc68hc908jkjl.h: committed fix for bug #1929739, + thanks Alejandro Pustowka + 2008-03-30 Maarten Brock * src/SDCCloop.c (loopInvariants): applied fix for bug 1717943, thanks diff --git a/device/include/hc08/mc68hc908jkjl.h b/device/include/hc08/mc68hc908jkjl.h index bcfa244b..9bfee75b 100644 --- a/device/include/hc08/mc68hc908jkjl.h +++ b/device/include/hc08/mc68hc908jkjl.h @@ -123,13 +123,12 @@ _VOLDATA _UINT8 __at 0x08 PTE; /* Port E Data Register */ #define PTE0 ((struct __hc08_bits *)(&PTE))->bit0 #define PTE1 ((struct __hc08_bits *)(&PTE))->bit1 +_VOLDATA _UINT8 __at 0x0A PDCR; /* Port D Control Register */ -_VOLDATA _UINT8 __at 0x0A PTE; /* Port D Control Register */ -#define PORTE PTE /* Alias for PDCR */ - #define PTDPU6 ((struct __hc08_bits *)(&PTE))->bit0 - #define PTDPU7 ((struct __hc08_bits *)(&PTE))->bit1 - #define SLOWD6 ((struct __hc08_bits *)(&PTE))->bit2 - #define SLOWD7 ((struct __hc08_bits *)(&PTE))->bit3 + #define PTDPU6 ((struct __hc08_bits *)(&PDCR))->bit0 + #define PTDPU7 ((struct __hc08_bits *)(&PDCR))->bit1 + #define SLOWD6 ((struct __hc08_bits *)(&PDCR))->bit2 + #define SLOWD7 ((struct __hc08_bits *)(&PDCR))->bit3 _VOLDATA _UINT8 __at 0x0C DDRE; /* Data Direction Register E */ #define DDRE0 ((struct __hc08_bits *)(&DDRE))->bit0 @@ -300,14 +299,14 @@ _VOLDATA _UINT8 __at 0x33 T2MODH; /* TIM2 Counter Modulo Register High */ _VOLDATA _UINT8 __at 0x34 T2MODL; /* TIM2 Counter Modulo Register Low */ -_VOLDATA _UINT8 __at 0x35 T2SC1; /* TIM2 Channel 0 Status and Control Register */ - #define CH0MAX_2 ((struct __hc08_bits *)(&T2SC1))->bit0 - #define TOV0_2 ((struct __hc08_bits *)(&T2SC1))->bit1 - #define ELS0A_2 ((struct __hc08_bits *)(&T2SC1))->bit2 - #define ELS0B_2 ((struct __hc08_bits *)(&T2SC1))->bit3 - #define MS0A_2 ((struct __hc08_bits *)(&T2SC1))->bit4 - #define CH0IE_2 ((struct __hc08_bits *)(&T2SC1))->bit6 - #define CH0F_2 ((struct __hc08_bits *)(&T2SC1))->bit7 +_VOLDATA _UINT8 __at 0x35 T2SC0; /* TIM2 Channel 0 Status and Control Register */ + #define CH0MAX_2 ((struct __hc08_bits *)(&T2SC0))->bit0 + #define TOV0_2 ((struct __hc08_bits *)(&T2SC0))->bit1 + #define ELS0A_2 ((struct __hc08_bits *)(&T2SC0))->bit2 + #define ELS0B_2 ((struct __hc08_bits *)(&T2SC0))->bit3 + #define MS0A_2 ((struct __hc08_bits *)(&T2SC0))->bit4 + #define CH0IE_2 ((struct __hc08_bits *)(&T2SC0))->bit6 + #define CH0F_2 ((struct __hc08_bits *)(&T2SC0))->bit7 _VOLDATA _UINT16 __at 0x36 T2CH0; /* TIM2 Channel 0 High & Low Registers */ _VOLDATA _UINT8 __at 0x36 T2CH0H; /* TIM2 Channel 0 Register High */ -- 2.30.2