From a59823d4e0b08b2998275df98f22315bdb1172ea Mon Sep 17 00:00:00 2001 From: jesusc Date: Thu, 9 Aug 2007 22:39:00 +0000 Subject: [PATCH 1/1] device/include/mcs51/at89c51ed.h: Fixed typo in declarations of CKCON0 and CKCON1. git-svn-id: https://sdcc.svn.sourceforge.net/svnroot/sdcc/trunk/sdcc@4898 4a8a32a2-be11-0410-ad9d-d568d2c75423 --- ChangeLog | 5 +++++ device/include/mcs51/at89c51ed2.h | 4 ++-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/ChangeLog b/ChangeLog index 03f8e936..ecb23d09 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,8 @@ +2007-08-09 Jesus Calvino-Fraga + + * device/include/mcs51/at89c51ed.h: Fixed typo in declarations of CKCON0 + and CKCON1. + 2007-08-07 Erik Petrich * sdccconf_in.h: update the endian test so that SPARC Solaris diff --git a/device/include/mcs51/at89c51ed2.h b/device/include/mcs51/at89c51ed2.h index 309779b2..63460d40 100644 --- a/device/include/mcs51/at89c51ed2.h +++ b/device/include/mcs51/at89c51ed2.h @@ -54,7 +54,7 @@ __sfr __at (0xA2) AUXR1; //Auxiliary function register 1 #define DPS 0x01 //Data pointer select. __sfr __at (0x97) CKRL; //Clock Reload Register -__sfr __at (0x8F) CKCKON0; //Clock control Register 0 +__sfr __at (0x8F) CKCON0; //Clock control Register 0 #define WDTX2 0x40 //Watch Dog Clock speed '1'=12 ck/cy, '0'=6 ck/cy #define PCAX2 0x20 //Programmable Counter Array Clock speed '1'=12 ck/cy, '0'=6 ck/cy #define SIX2 0x10 //Enhanced UART Clock (Mode 0 and 2) speed '1'=12 ck/cy, '0'=6 ck/cy @@ -62,7 +62,7 @@ __sfr __at (0x8F) CKCKON0; //Clock control Register 0 #define T1X2 0x04 //Timer1 Clock speed '1'=12 ck/cy, '0'=6 ck/cy #define T0X2 0x02 //Timer0 Clock speed '1'=12 ck/cy, '0'=6 ck/cy #define X2 0x01 //CPU Clock '0'=12 ck/cy, '1'=6 ck/cy -__sfr __at (0x8F) CKCKON1; //Clock control Register 1 +__sfr __at (0x8F) CKCON1; //Clock control Register 1 #define XPIX2 0x01 //SPI Clock speed '1'=12 ck/cy, '0'=6 ck/cy __sfr __at (0xFA) CCAP0H; //Module 0 Capture HIGH. -- 2.30.2