From 2d24ff5a2953070ba0ab97aa8f1cf2990747623e Mon Sep 17 00:00:00 2001
From: Bdale Garbee <bdale@gag.com>
Date: Sun, 27 Nov 2011 15:39:55 -0700
Subject: [PATCH] more silk on pcb, fix slot definitions on DB15 connectors to
 calm DRC

---
 cncfpga.pcb |  3 ++-
 cncfpga.sch | 16 ++++++++++++++++
 2 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/cncfpga.pcb b/cncfpga.pcb
index 6f81b20..930da03 100644
--- a/cncfpga.pcb
+++ b/cncfpga.pcb
@@ -6,7 +6,7 @@ FileVersion[20070407]
 PCB["cncfpga" 510000 200000]
 
 Grid[100.0 0 0 0]
-Cursor[13100 5600 0.000000]
+Cursor[2800 23400 0.000000]
 PolyArea[200000000.000000]
 Thermal[0.500000]
 DRC[600 1000 600 500 1500 700]
@@ -2299,6 +2299,7 @@ Layer(7 "silk")
 	Text[427700 110800 0 100 "3.3V" "clearline"]
 	Text[427500 100400 0 100 "GND" "clearline"]
 	Text[431600 90400 0 100 "5V" "clearline"]
+	Text[7200 52600 0 100 "pcok  dout9" "clearline"]
 )
 NetList()
 (
diff --git a/cncfpga.sch b/cncfpga.sch
index 0929dfb..4c3f770 100644
--- a/cncfpga.sch
+++ b/cncfpga.sch
@@ -108,6 +108,10 @@ T 63000 54200 5 10 0 0 0 0 1
 vendor_part_number=1015FFE-ND
 T 63000 54200 5 10 0 1 0 0 1
 device=CONNECTOR
+T 63000 54200 5 10 0 0 0 0 1
+slot=1
+T 63000 54200 5 10 0 0 0 0 1
+numslots=2
 }
 C 65800 54200 1 0 0 conn-15.sym
 {
@@ -125,6 +129,10 @@ T 65800 54200 5 10 0 1 0 0 1
 vendor=digikey
 T 65800 54200 5 10 0 1 0 0 1
 vendor_part_number=1015FFE-ND
+T 65800 54200 5 10 0 0 0 0 1
+slot=1
+T 65800 54200 5 10 0 0 0 0 1
+numslots=2
 }
 C 55700 43900 1 0 0 conn-9.sym
 {
@@ -1364,6 +1372,10 @@ T 68600 54200 5 10 0 0 0 0 1
 vendor=digikey
 T 68600 54200 5 10 0 0 0 0 1
 vendor_part_number=1015FFE-ND
+T 68600 54200 5 10 0 1 0 0 1
+slot=2
+T 68600 54200 5 10 0 0 0 0 1
+numslots=2
 }
 C 71400 54200 1 0 0 conn-15b.sym
 {
@@ -1381,6 +1393,10 @@ T 71400 54200 5 10 0 1 0 0 1
 vendor=digikey
 T 71400 54200 5 10 0 1 0 0 1
 vendor_part_number=1015FFE-ND
+T 71400 54200 5 10 0 0 0 0 1
+slot=2
+T 71400 54200 5 10 0 0 0 0 1
+numslots=2
 }
 T 63300 53500 9 30 1 0 0 0 1
 X
-- 
2.30.2