From: Bdale Garbee <bdale@gag.com>
Date: Sun, 14 Jul 2013 06:55:29 +0000 (-0400)
Subject: fix outline layer to not trigger DRC errors
X-Git-Tag: fab-1.1~2
X-Git-Url: https://git.gag.com/?a=commitdiff_plain;ds=sidebyside;h=9d5239d316a5c15cefd9de0c7ab14c6d68485ccc;hp=4ec5c19f78fe2ac0d51d89134d9b06485c248a71;p=hw%2Flipocharger

fix outline layer to not trigger DRC errors
---

diff --git a/lipocharger.pcb b/lipocharger.pcb
index d51255b..77d5f99 100644
--- a/lipocharger.pcb
+++ b/lipocharger.pcb
@@ -995,6 +995,7 @@ Layer(2 "bottom")
 )
 Layer(3 "outline")
 (
+	Attribute("PCB::skip-drc" "1")
 	Line[0.0000 0.0000 0.0000 400.00mil 10.00mil 0.0000 ""]
 	Line[0.0000 400.00mil 1000.00mil 400.00mil 10.00mil 0.0000 ""]
 	Line[1000.00mil 400.00mil 1000.00mil 0.0000 10.00mil 0.0000 ""]