--- /dev/null
+//////////////////////////////////////////////////////////////////////\r
+//// ////\r
+//// eth_clockgen.v ////\r
+//// ////\r
+//// This file is part of the Ethernet IP core project ////\r
+//// http://www.opencores.org/projects/ethmac/ ////\r
+//// ////\r
+//// Author(s): ////\r
+//// - Igor Mohor (igorM@opencores.org) ////\r
+//// ////\r
+//// All additional information is avaliable in the Readme.txt ////\r
+//// file. ////\r
+//// ////\r
+//////////////////////////////////////////////////////////////////////\r
+//// ////\r
+//// Copyright (C) 2001 Authors ////\r
+//// ////\r
+//// This source file may be used and distributed without ////\r
+//// restriction provided that this copyright statement is not ////\r
+//// removed from the file and that any derivative work contains ////\r
+//// the original copyright notice and the associated disclaimer. ////\r
+//// ////\r
+//// This source file is free software; you can redistribute it ////\r
+//// and/or modify it under the terms of the GNU Lesser General ////\r
+//// Public License as published by the Free Software Foundation; ////\r
+//// either version 2.1 of the License, or (at your option) any ////\r
+//// later version. ////\r
+//// ////\r
+//// This source is distributed in the hope that it will be ////\r
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\r
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\r
+//// PURPOSE. See the GNU Lesser General Public License for more ////\r
+//// details. ////\r
+//// ////\r
+//// You should have received a copy of the GNU Lesser General ////\r
+//// Public License along with this source; if not, download it ////\r
+//// from http://www.opencores.org/lgpl.shtml ////\r
+//// ////\r
+//////////////////////////////////////////////////////////////////////\r
+//\r
+// CVS Revision History\r
+//\r
+// $Log: eth_clockgen.v,v $\r
+// Revision 1.2 2005/12/13 12:54:49 maverickist\r
+// first simulation passed\r
+//\r
+// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator\r
+// no message\r
+//\r
+// Revision 1.2 2005/04/27 15:58:45 Administrator\r
+// no message\r
+//\r
+// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator\r
+// no message\r
+//\r
+// Revision 1.3 2002/01/23 10:28:16 mohor\r
+// Link in the header changed.\r
+//\r
+// Revision 1.2 2001/10/19 08:43:51 mohor\r
+// eth_timescale.v changed to timescale.v This is done because of the\r
+// simulation of the few cores in a one joined project.\r
+//\r
+// Revision 1.1 2001/08/06 14:44:29 mohor\r
+// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).\r
+// Include files fixed to contain no path.\r
+// File names and module names changed ta have a eth_ prologue in the name.\r
+// File eth_timescale.v is used to define timescale\r
+// All pin names on the top module are changed to contain _I, _O or _OE at the end.\r
+// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O\r
+// and Mdo_OE. The bidirectional signal must be created on the top level. This\r
+// is done due to the ASIC tools.\r
+//\r
+// Revision 1.1 2001/07/30 21:23:42 mohor\r
+// Directory structure changed. Files checked and joind together.\r
+//\r
+// Revision 1.3 2001/06/01 22:28:55 mohor\r
+// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.\r
+//\r
+//\r
+\r
+module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);\r
+\r
+//parameter Tp=1;\r
+\r
+input Clk; // Input clock (Host clock)\r
+input Reset; // Reset signal\r
+input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0])\r
+\r
+output Mdc; // Output clock\r
+output MdcEn; // Enable signal is asserted for one Clk period before Mdc rises.\r
+output MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.\r
+\r
+reg Mdc;\r
+reg [7:0] Counter;\r
+\r
+wire CountEq0;\r
+wire [7:0] CounterPreset;\r
+wire [7:0] TempDivider;\r
+\r
+\r
+assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2\r
+assign CounterPreset[7:0] = (TempDivider[7:0]>>1) -1; // We are counting half of period\r
+\r
+\r
+// Counter counts half period\r
+always @ (posedge Clk or posedge Reset)\r
+begin\r
+ if(Reset)\r
+ Counter[7:0] <= 8'h1;\r
+ else\r
+ begin\r
+ if(CountEq0)\r
+ begin\r
+ Counter[7:0] <= CounterPreset[7:0];\r
+ end\r
+ else\r
+ Counter[7:0] <= Counter - 8'h1;\r
+ end\r
+end\r
+\r
+\r
+// Mdc is asserted every other half period\r
+always @ (posedge Clk or posedge Reset)\r
+begin\r
+ if(Reset)\r
+ Mdc <= 1'b0;\r
+ else\r
+ begin\r
+ if(CountEq0)\r
+ Mdc <= ~Mdc;\r
+ end\r
+end\r
+\r
+\r
+assign CountEq0 = Counter == 8'h0;\r
+assign MdcEn = CountEq0 & ~Mdc;\r
+assign MdcEn_n = CountEq0 & Mdc;\r
+\r
+endmodule\r
+\r
+\r
--- /dev/null
+//////////////////////////////////////////////////////////////////////\r
+//// ////\r
+//// eth_miim.v ////\r
+//// ////\r
+//// This file is part of the Ethernet IP core project ////\r
+//// http://www.opencores.org/projects/ethmac/ ////\r
+//// ////\r
+//// Author(s): ////\r
+//// - Igor Mohor (igorM@opencores.org) ////\r
+//// ////\r
+//// All additional information is avaliable in the Readme.txt ////\r
+//// file. ////\r
+//// ////\r
+//////////////////////////////////////////////////////////////////////\r
+//// ////\r
+//// Copyright (C) 2001 Authors ////\r
+//// ////\r
+//// This source file may be used and distributed without ////\r
+//// restriction provided that this copyright statement is not ////\r
+//// removed from the file and that any derivative work contains ////\r
+//// the original copyright notice and the associated disclaimer. ////\r
+//// ////\r
+//// This source file is free software; you can redistribute it ////\r
+//// and/or modify it under the terms of the GNU Lesser General ////\r
+//// Public License as published by the Free Software Foundation; ////\r
+//// either version 2.1 of the License, or (at your option) any ////\r
+//// later version. ////\r
+//// ////\r
+//// This source is distributed in the hope that it will be ////\r
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\r
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\r
+//// PURPOSE. See the GNU Lesser General Public License for more ////\r
+//// details. ////\r
+//// ////\r
+//// You should have received a copy of the GNU Lesser General ////\r
+//// Public License along with this source; if not, download it ////\r
+//// from http://www.opencores.org/lgpl.shtml ////\r
+//// ////\r
+//////////////////////////////////////////////////////////////////////\r
+//\r
+// CVS Revision History\r
+//\r
+// $Log: eth_miim.v,v $\r
+// Revision 1.3 2006/01/19 14:07:53 maverickist\r
+// verification is complete.\r
+//\r
+// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator\r
+// no message\r
+//\r
+// Revision 1.4 2005/08/16 12:07:57 Administrator\r
+// no message\r
+//\r
+// Revision 1.3 2005/05/19 07:04:29 Administrator\r
+// no message\r
+//\r
+// Revision 1.2 2005/04/27 15:58:46 Administrator\r
+// no message\r
+//\r
+// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator\r
+// no message\r
+//\r
+// Revision 1.5 2003/05/16 10:08:27 mohor\r
+// Busy was set 2 cycles too late. Reported by Dennis Scott.\r
+//\r
+// Revision 1.4 2002/08/14 18:32:10 mohor\r
+// - Busy signal was not set on time when scan status operation was performed\r
+// and clock was divided with more than 2.\r
+// - Nvalid remains valid two more clocks (was previously cleared too soon).\r
+//\r
+// Revision 1.3 2002/01/23 10:28:16 mohor\r
+// Link in the header changed.\r
+//\r
+// Revision 1.2 2001/10/19 08:43:51 mohor\r
+// eth_timescale.v changed to timescale.v This is done because of the\r
+// simulation of the few cores in a one joined project.\r
+//\r
+// Revision 1.1 2001/08/06 14:44:29 mohor\r
+// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).\r
+// Include files fixed to contain no path.\r
+// File names and module names changed ta have a eth_ prologue in the name.\r
+// File eth_timescale.v is used to define timescale\r
+// All pin names on the top module are changed to contain _I, _O or _OE at the end.\r
+// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O\r
+// and Mdo_OE. The bidirectional signal must be created on the top level. This\r
+// is done due to the ASIC tools.\r
+//\r
+// Revision 1.2 2001/08/02 09:25:31 mohor\r
+// Unconnected signals are now connected.\r
+//\r
+// Revision 1.1 2001/07/30 21:23:42 mohor\r
+// Directory structure changed. Files checked and joind together.\r
+//\r
+// Revision 1.3 2001/06/01 22:28:56 mohor\r
+// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.\r
+//\r
+//\r
+\r
+module eth_miim\r
+(\r
+ Clk,\r
+ Reset,\r
+ Divider,\r
+ NoPre,\r
+ CtrlData,\r
+ Rgad,\r
+ Fiad,\r
+ WCtrlData,\r
+ RStat,\r
+ ScanStat,\r
+ Mdio,\r
+ Mdc,\r
+ Busy,\r
+ Prsd,\r
+ LinkFail,\r
+ Nvalid,\r
+ WCtrlDataStart,\r
+ RStatStart,\r
+ UpdateMIIRX_DATAReg\r
+);\r
+\r
+input Clk; // Host Clock\r
+input Reset; // General Reset\r
+input [7:0] Divider; // Divider for the host clock\r
+input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)\r
+input [4:0] Rgad; // Register Address (within the PHY)\r
+input [4:0] Fiad; // PHY Address\r
+input NoPre; // No Preamble (no 32-bit preamble)\r
+input WCtrlData; // Write Control Data operation\r
+input RStat; // Read Status operation\r
+input ScanStat; // Scan Status operation\r
+inout Mdio; // MII Management Data In\r
+\r
+output Mdc; // MII Management Data Clock\r
+\r
+output Busy; // Busy Signal\r
+output LinkFail; // Link Integrity Signal\r
+output Nvalid; // Invalid Status (qualifier for the valid scan result)\r
+\r
+output [15:0] Prsd; // Read Status Data (data read from the PHY)\r
+\r
+output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register\r
+output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register\r
+output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data\r
+\r
+//parameter Tp = 1;\r
+\r
+\r
+reg Nvalid;\r
+reg EndBusy_d; // Pre-end Busy signal\r
+reg EndBusy; // End Busy signal (stops the operation in progress)\r
+\r
+reg WCtrlData_q1; // Write Control Data operation delayed 1 Clk cycle\r
+reg WCtrlData_q2; // Write Control Data operation delayed 2 Clk cycles\r
+reg WCtrlData_q3; // Write Control Data operation delayed 3 Clk cycles\r
+reg WCtrlDataStart; // Start Write Control Data Command (positive edge detected)\r
+reg WCtrlDataStart_q;\r
+reg WCtrlDataStart_q1; // Start Write Control Data Command delayed 1 Mdc cycle\r
+reg WCtrlDataStart_q2; // Start Write Control Data Command delayed 2 Mdc cycles\r
+\r
+reg RStat_q1; // Read Status operation delayed 1 Clk cycle\r
+reg RStat_q2; // Read Status operation delayed 2 Clk cycles\r
+reg RStat_q3; // Read Status operation delayed 3 Clk cycles\r
+reg RStatStart; // Start Read Status Command (positive edge detected)\r
+reg RStatStart_q1; // Start Read Status Command delayed 1 Mdc cycle\r
+reg RStatStart_q2; // Start Read Status Command delayed 2 Mdc cycles\r
+\r
+reg ScanStat_q1; // Scan Status operation delayed 1 cycle\r
+reg ScanStat_q2; // Scan Status operation delayed 2 cycles\r
+reg SyncStatMdcEn; // Scan Status operation delayed at least cycles and synchronized to MdcEn\r
+\r
+wire WriteDataOp; // Write Data Operation (positive edge detected)\r
+wire ReadStatusOp; // Read Status Operation (positive edge detected)\r
+wire ScanStatusOp; // Scan Status Operation (positive edge detected)\r
+wire StartOp; // Start Operation (start of any of the preceding operations)\r
+wire EndOp; // End of Operation\r
+\r
+reg InProgress; // Operation in progress\r
+reg InProgress_q1; // Operation in progress delayed 1 Mdc cycle\r
+reg InProgress_q2; // Operation in progress delayed 2 Mdc cycles\r
+reg InProgress_q3; // Operation in progress delayed 3 Mdc cycles\r
+\r
+reg WriteOp; // Write Operation Latch (When asserted, write operation is in progress)\r
+reg [6:0] BitCounter; // Bit Counter\r
+\r
+\r
+wire [3:0] ByteSelect; // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.\r
+wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.\r
+wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal\r
+\r
+\r
+wire LatchByte1_d2;\r
+wire LatchByte0_d2;\r
+reg LatchByte1_d;\r
+reg LatchByte0_d;\r
+reg [1:0] LatchByte; // Latch Byte selects which part of Read Status Data is updated from the shift register\r
+\r
+reg UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data\r
+\r
+wire Mdo; // MII Management Data Output\r
+wire MdoEn; // MII Management Data Output Enable\r
+wire Mdi;\r
+\r
+assign Mdi=Mdio;\r
+assign Mdio=MdoEn?Mdo:1'bz;\r
+\r
+\r
+\r
+// Generation of the EndBusy signal. It is used for ending the MII Management operation.\r
+always @ (posedge Clk or posedge Reset)\r
+begin\r
+ if(Reset)\r
+ begin\r
+ EndBusy_d <= 1'b0;\r
+ EndBusy <= 1'b0;\r
+ end\r
+ else\r
+ begin\r
+ EndBusy_d <= ~InProgress_q2 & InProgress_q3;\r
+ EndBusy <= EndBusy_d;\r
+ end\r
+end\r
+\r
+\r
+// Update MII RX_DATA register\r
+always @ (posedge Clk or posedge Reset)\r
+begin\r
+ if(Reset)\r
+ UpdateMIIRX_DATAReg <= 0;\r
+ else\r
+ if(EndBusy & ~WCtrlDataStart_q)\r
+ UpdateMIIRX_DATAReg <= 1;\r
+ else\r
+ UpdateMIIRX_DATAReg <= 0; \r
+end\r
+\r
+\r
+\r
+// Generation of the delayed signals used for positive edge triggering.\r
+always @ (posedge Clk or posedge Reset)\r
+begin\r
+ if(Reset)\r
+ begin\r
+ WCtrlData_q1 <= 1'b0;\r
+ WCtrlData_q2 <= 1'b0;\r
+ WCtrlData_q3 <= 1'b0;\r
+ \r
+ RStat_q1 <= 1'b0;\r
+ RStat_q2 <= 1'b0;\r
+ RStat_q3 <= 1'b0;\r
+\r
+ ScanStat_q1 <= 1'b0;\r
+ ScanStat_q2 <= 1'b0;\r
+ SyncStatMdcEn <= 1'b0;\r
+ end\r
+ else\r
+ begin\r
+ WCtrlData_q1 <= WCtrlData;\r
+ WCtrlData_q2 <= WCtrlData_q1;\r
+ WCtrlData_q3 <= WCtrlData_q2;\r
+\r
+ RStat_q1 <= RStat;\r
+ RStat_q2 <= RStat_q1;\r
+ RStat_q3 <= RStat_q2;\r
+\r
+ ScanStat_q1 <= ScanStat;\r
+ ScanStat_q2 <= ScanStat_q1;\r
+ if(MdcEn)\r
+ SyncStatMdcEn <= ScanStat_q2;\r
+ end\r
+end\r
+\r
+\r
+// Generation of the Start Commands (Write Control Data or Read Status)\r
+always @ (posedge Clk or posedge Reset)\r
+begin\r
+ if(Reset)\r
+ begin\r
+ WCtrlDataStart <= 1'b0;\r
+ WCtrlDataStart_q <= 1'b0;\r
+ RStatStart <= 1'b0;\r
+ end\r
+ else\r
+ begin\r
+ if(EndBusy)\r
+ begin\r
+ WCtrlDataStart <= 1'b0;\r
+ RStatStart <= 1'b0;\r
+ end\r
+ else\r
+ begin\r
+ if(WCtrlData_q2 & ~WCtrlData_q3)\r
+ WCtrlDataStart <= 1'b1;\r
+ if(RStat_q2 & ~RStat_q3)\r
+ RStatStart <= 1'b1;\r
+ WCtrlDataStart_q <= WCtrlDataStart;\r
+ end\r
+ end\r
+end \r
+\r
+\r
+// Generation of the Nvalid signal (indicates when the status is invalid)\r
+always @ (posedge Clk or posedge Reset)\r
+begin\r
+ if(Reset)\r
+ Nvalid <= 1'b0;\r
+ else\r
+ begin\r
+ if(~InProgress_q2 & InProgress_q3)\r
+ begin\r
+ Nvalid <= 1'b0;\r
+ end\r
+ else\r
+ begin\r
+ if(ScanStat_q2 & ~SyncStatMdcEn)\r
+ Nvalid <= 1'b1;\r
+ end\r
+ end\r
+end \r
+\r
+// Signals used for the generation of the Operation signals (positive edge)\r
+always @ (posedge Clk or posedge Reset)\r
+begin\r
+ if(Reset)\r
+ begin\r
+ WCtrlDataStart_q1 <= 1'b0;\r
+ WCtrlDataStart_q2 <= 1'b0;\r
+\r
+ RStatStart_q1 <= 1'b0;\r
+ RStatStart_q2 <= 1'b0;\r
+\r
+ InProgress_q1 <= 1'b0;\r
+ InProgress_q2 <= 1'b0;\r
+ InProgress_q3 <= 1'b0;\r
+\r
+ LatchByte0_d <= 1'b0;\r
+ LatchByte1_d <= 1'b0;\r
+\r
+ LatchByte <= 2'b00;\r
+ end\r
+ else\r
+ begin\r
+ if(MdcEn)\r
+ begin\r
+ WCtrlDataStart_q1 <= WCtrlDataStart;\r
+ WCtrlDataStart_q2 <= WCtrlDataStart_q1;\r
+\r
+ RStatStart_q1 <= RStatStart;\r
+ RStatStart_q2 <= RStatStart_q1;\r
+\r
+ LatchByte[0] <= LatchByte0_d;\r
+ LatchByte[1] <= LatchByte1_d;\r
+\r
+ LatchByte0_d <= LatchByte0_d2;\r
+ LatchByte1_d <= LatchByte1_d2;\r
+\r
+ InProgress_q1 <= InProgress;\r
+ InProgress_q2 <= InProgress_q1;\r
+ InProgress_q3 <= InProgress_q2;\r
+ end\r
+ end\r
+end \r
+\r
+\r
+// Generation of the Operation signals\r
+assign WriteDataOp = WCtrlDataStart_q1 & ~WCtrlDataStart_q2; \r
+assign ReadStatusOp = RStatStart_q1 & ~RStatStart_q2;\r
+assign ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q1 & ~InProgress_q2;\r
+assign StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp;\r
+\r
+// Busy\r
+reg Busy;\r
+always @ (posedge Clk or posedge Reset)\r
+ if (Reset)\r
+ Busy <=0;\r
+ else if(WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid)\r
+ Busy <=1;\r
+ else\r
+ Busy <=0;\r
+ \r
+//assign Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;\r
+\r
+\r
+// Generation of the InProgress signal (indicates when an operation is in progress)\r
+// Generation of the WriteOp signal (indicates when a write is in progress)\r
+always @ (posedge Clk or posedge Reset)\r
+begin\r
+ if(Reset)\r
+ begin\r
+ InProgress <= 1'b0;\r
+ WriteOp <= 1'b0;\r
+ end\r
+ else\r
+ begin\r
+ if(MdcEn)\r
+ begin\r
+ if(StartOp)\r
+ begin\r
+ if(~InProgress)\r
+ WriteOp <= WriteDataOp;\r
+ InProgress <= 1'b1;\r
+ end\r
+ else\r
+ begin\r
+ if(EndOp)\r
+ begin\r
+ InProgress <= 1'b0;\r
+ WriteOp <= 1'b0;\r
+ end\r
+ end\r
+ end\r
+ end\r
+end\r
+\r
+\r
+\r
+// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)\r
+always @ (posedge Clk or posedge Reset)\r
+begin\r
+ if(Reset)\r
+ BitCounter[6:0] <= 7'h0;\r
+ else\r
+ begin\r
+ if(MdcEn)\r
+ begin\r
+ if(InProgress)\r
+ begin\r
+ if(NoPre & ( BitCounter == 7'h0 ))\r
+ BitCounter[6:0] <= 7'h21;\r
+ else\r
+ BitCounter[6:0] <= BitCounter[6:0] + 1'b1;\r
+ end\r
+ else\r
+ BitCounter[6:0] <= 7'h0;\r
+ end\r
+ end\r
+end\r
+\r
+\r
+// Operation ends when the Bit Counter reaches 63\r
+assign EndOp = BitCounter==63;\r
+\r
+assign ByteSelect[0] = InProgress & ((NoPre & (BitCounter == 7'h0)) | (~NoPre & (BitCounter == 7'h20)));\r
+assign ByteSelect[1] = InProgress & (BitCounter == 7'h28);\r
+assign ByteSelect[2] = InProgress & WriteOp & (BitCounter == 7'h30);\r
+assign ByteSelect[3] = InProgress & WriteOp & (BitCounter == 7'h38);\r
+\r
+\r
+// Latch Byte selects which part of Read Status Data is updated from the shift register\r
+assign LatchByte1_d2 = InProgress & ~WriteOp & BitCounter == 7'h37;\r
+assign LatchByte0_d2 = InProgress & ~WriteOp & BitCounter == 7'h3F;\r
+\r
+wire MdcEn_n;\r
+\r
+// Connecting the Clock Generator Module\r
+eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc) \r
+ );\r
+\r
+// Connecting the Shift Register Module\r
+eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad), \r
+ .CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte), \r
+ .ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)\r
+ );\r
+\r
+// Connecting the Output Control Module\r
+eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress), \r
+ .ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre), \r
+ .Mdo(Mdo), .MdoEn(MdoEn)\r
+ );\r
+\r
+endmodule\r
--- /dev/null
+//////////////////////////////////////////////////////////////////////\r
+//// ////\r
+//// eth_outputcontrol.v ////\r
+//// ////\r
+//// This file is part of the Ethernet IP core project ////\r
+//// http://www.opencores.org/projects/ethmac/ ////\r
+//// ////\r
+//// Author(s): ////\r
+//// - Igor Mohor (igorM@opencores.org) ////\r
+//// ////\r
+//// All additional information is avaliable in the Readme.txt ////\r
+//// file. ////\r
+//// ////\r
+//////////////////////////////////////////////////////////////////////\r
+//// ////\r
+//// Copyright (C) 2001 Authors ////\r
+//// ////\r
+//// This source file may be used and distributed without ////\r
+//// restriction provided that this copyright statement is not ////\r
+//// removed from the file and that any derivative work contains ////\r
+//// the original copyright notice and the associated disclaimer. ////\r
+//// ////\r
+//// This source file is free software; you can redistribute it ////\r
+//// and/or modify it under the terms of the GNU Lesser General ////\r
+//// Public License as published by the Free Software Foundation; ////\r
+//// either version 2.1 of the License, or (at your option) any ////\r
+//// later version. ////\r
+//// ////\r
+//// This source is distributed in the hope that it will be ////\r
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\r
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\r
+//// PURPOSE. See the GNU Lesser General Public License for more ////\r
+//// details. ////\r
+//// ////\r
+//// You should have received a copy of the GNU Lesser General ////\r
+//// Public License along with this source; if not, download it ////\r
+//// from http://www.opencores.org/lgpl.shtml ////\r
+//// ////\r
+//////////////////////////////////////////////////////////////////////\r
+//\r
+// CVS Revision History\r
+//\r
+// $Log: eth_outputcontrol.v,v $\r
+// Revision 1.2 2005/12/13 12:54:49 maverickist\r
+// first simulation passed\r
+//\r
+// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator\r
+// no message\r
+//\r
+// Revision 1.2 2005/04/27 15:58:46 Administrator\r
+// no message\r
+//\r
+// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator\r
+// no message\r
+//\r
+// Revision 1.4 2002/07/09 20:11:59 mohor\r
+// Comment removed.\r
+//\r
+// Revision 1.3 2002/01/23 10:28:16 mohor\r
+// Link in the header changed.\r
+//\r
+// Revision 1.2 2001/10/19 08:43:51 mohor\r
+// eth_timescale.v changed to timescale.v This is done because of the\r
+// simulation of the few cores in a one joined project.\r
+//\r
+// Revision 1.1 2001/08/06 14:44:29 mohor\r
+// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).\r
+// Include files fixed to contain no path.\r
+// File names and module names changed ta have a eth_ prologue in the name.\r
+// File eth_timescale.v is used to define timescale\r
+// All pin names on the top module are changed to contain _I, _O or _OE at the end.\r
+// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O\r
+// and Mdo_OE. The bidirectional signal must be created on the top level. This\r
+// is done due to the ASIC tools.\r
+//\r
+// Revision 1.1 2001/07/30 21:23:42 mohor\r
+// Directory structure changed. Files checked and joind together.\r
+//\r
+// Revision 1.3 2001/06/01 22:28:56 mohor\r
+// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.\r
+//\r
+//\r
+\r
+module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn);\r
+\r
+input Clk; // Host Clock\r
+input Reset; // General Reset\r
+input WriteOp; // Write Operation Latch (When asserted, write operation is in progress)\r
+input NoPre; // No Preamble (no 32-bit preamble)\r
+input InProgress; // Operation in progress\r
+input ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal\r
+input [6:0] BitCounter; // Bit Counter\r
+input MdcEn_n; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc falls.\r
+\r
+output Mdo; // MII Management Data Output\r
+output MdoEn; // MII Management Data Output Enable\r
+\r
+wire SerialEn;\r
+\r
+reg MdoEn_2d;\r
+reg MdoEn_d;\r
+reg MdoEn;\r
+\r
+reg Mdo_2d;\r
+reg Mdo_d;\r
+reg Mdo; // MII Management Data Output\r
+\r
+\r
+\r
+// Generation of the Serial Enable signal (enables the serialization of the data)\r
+assign SerialEn = WriteOp & InProgress & ( BitCounter>31 | ( ( BitCounter == 0 ) & NoPre ) )\r
+ | ~WriteOp & InProgress & (( BitCounter>31 & BitCounter<46 ) | ( ( BitCounter == 0 ) & NoPre ));\r
+\r
+\r
+// Generation of the MdoEn signal\r
+always @ (posedge Clk or posedge Reset)\r
+begin\r
+ if(Reset)\r
+ begin\r
+ MdoEn_2d <= 1'b0;\r
+ MdoEn_d <= 1'b0;\r
+ MdoEn <= 1'b0;\r
+ end\r
+ else\r
+ begin\r
+ if(MdcEn_n)\r
+ begin\r
+ MdoEn_2d <= SerialEn | InProgress & BitCounter<32;\r
+ MdoEn_d <= MdoEn_2d;\r
+ MdoEn <= MdoEn_d;\r
+ end\r
+ end\r
+end\r
+\r
+\r
+// Generation of the Mdo signal.\r
+always @ (posedge Clk or posedge Reset)\r
+begin\r
+ if(Reset)\r
+ begin\r
+ Mdo_2d <= 1'b0;\r
+ Mdo_d <= 1'b0;\r
+ Mdo <= 1'b0;\r
+ end\r
+ else\r
+ begin\r
+ if(MdcEn_n)\r
+ begin\r
+ Mdo_2d <= ~SerialEn & BitCounter<32;\r
+ Mdo_d <= ShiftedBit | Mdo_2d;\r
+ Mdo <= Mdo_d;\r
+ end\r
+ end\r
+end\r
+\r
+\r
+\r
+endmodule\r
--- /dev/null
+//////////////////////////////////////////////////////////////////////\r
+//// ////\r
+//// eth_shiftreg.v ////\r
+//// ////\r
+//// This file is part of the Ethernet IP core project ////\r
+//// http://www.opencores.org/projects/ethmac/ ////\r
+//// ////\r
+//// Author(s): ////\r
+//// - Igor Mohor (igorM@opencores.org) ////\r
+//// ////\r
+//// All additional information is avaliable in the Readme.txt ////\r
+//// file. ////\r
+//// ////\r
+//////////////////////////////////////////////////////////////////////\r
+//// ////\r
+//// Copyright (C) 2001 Authors ////\r
+//// ////\r
+//// This source file may be used and distributed without ////\r
+//// restriction provided that this copyright statement is not ////\r
+//// removed from the file and that any derivative work contains ////\r
+//// the original copyright notice and the associated disclaimer. ////\r
+//// ////\r
+//// This source file is free software; you can redistribute it ////\r
+//// and/or modify it under the terms of the GNU Lesser General ////\r
+//// Public License as published by the Free Software Foundation; ////\r
+//// either version 2.1 of the License, or (at your option) any ////\r
+//// later version. ////\r
+//// ////\r
+//// This source is distributed in the hope that it will be ////\r
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\r
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\r
+//// PURPOSE. See the GNU Lesser General Public License for more ////\r
+//// details. ////\r
+//// ////\r
+//// You should have received a copy of the GNU Lesser General ////\r
+//// Public License along with this source; if not, download it ////\r
+//// from http://www.opencores.org/lgpl.shtml ////\r
+//// ////\r
+//////////////////////////////////////////////////////////////////////\r
+//\r
+// CVS Revision History\r
+//\r
+// $Log: eth_shiftreg.v,v $\r
+// Revision 1.2 2005/12/13 12:54:49 maverickist\r
+// first simulation passed\r
+//\r
+// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator\r
+// no message\r
+//\r
+// Revision 1.2 2005/04/27 15:58:47 Administrator\r
+// no message\r
+//\r
+// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator\r
+// no message\r
+//\r
+// Revision 1.5 2002/08/14 18:16:59 mohor\r
+// LinkFail signal was not latching appropriate bit.\r
+//\r
+// Revision 1.4 2002/03/02 21:06:01 mohor\r
+// LinkFail signal was not latching appropriate bit.\r
+//\r
+// Revision 1.3 2002/01/23 10:28:16 mohor\r
+// Link in the header changed.\r
+//\r
+// Revision 1.2 2001/10/19 08:43:51 mohor\r
+// eth_timescale.v changed to timescale.v This is done because of the\r
+// simulation of the few cores in a one joined project.\r
+//\r
+// Revision 1.1 2001/08/06 14:44:29 mohor\r
+// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).\r
+// Include files fixed to contain no path.\r
+// File names and module names changed ta have a eth_ prologue in the name.\r
+// File eth_timescale.v is used to define timescale\r
+// All pin names on the top module are changed to contain _I, _O or _OE at the end.\r
+// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O\r
+// and Mdo_OE. The bidirectional signal must be created on the top level. This\r
+// is done due to the ASIC tools.\r
+//\r
+// Revision 1.1 2001/07/30 21:23:42 mohor\r
+// Directory structure changed. Files checked and joind together.\r
+//\r
+// Revision 1.3 2001/06/01 22:28:56 mohor\r
+// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.\r
+//\r
+//\r
+\r
+module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect, \r
+ LatchByte, ShiftedBit, Prsd, LinkFail);\r
+\r
+\r
+input Clk; // Input clock (Host clock)\r
+input Reset; // Reset signal\r
+input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.\r
+input Mdi; // MII input data\r
+input [4:0] Fiad; // PHY address\r
+input [4:0] Rgad; // Register address (within the selected PHY)\r
+input [15:0]CtrlData; // Control data (data to be written to the PHY)\r
+input WriteOp; // The current operation is a PHY register write operation\r
+input [3:0] ByteSelect; // Byte select\r
+input [1:0] LatchByte; // Byte select for latching (read operation)\r
+\r
+output ShiftedBit; // Bit shifted out of the shift register\r
+output[15:0]Prsd; // Read Status Data (data read from the PHY)\r
+output LinkFail; // Link Integrity Signal\r
+\r
+reg [7:0] ShiftReg; // Shift register for shifting the data in and out\r
+reg [15:0]Prsd;\r
+reg LinkFail;\r
+\r
+\r
+\r
+\r
+// ShiftReg[7:0] :: Shift Register Data\r
+always @ (posedge Clk or posedge Reset) \r
+begin\r
+ if(Reset)\r
+ begin\r
+ ShiftReg[7:0] <= 8'h0;\r
+ Prsd[15:0] <= 16'h0;\r
+ LinkFail <= 1'b0;\r
+ end\r
+ else\r
+ begin\r
+ if(MdcEn_n)\r
+ begin \r
+ if(|ByteSelect)\r
+ begin\r
+ case (ByteSelect[3:0])\r
+ 4'h1 : ShiftReg[7:0] <= {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};\r
+ 4'h2 : ShiftReg[7:0] <= {Fiad[0], Rgad[4:0], 2'b10};\r
+ 4'h4 : ShiftReg[7:0] <= CtrlData[15:8];\r
+ 4'h8 : ShiftReg[7:0] <= CtrlData[7:0];\r
+ default : ShiftReg[7:0] <= 8'h0;\r
+ endcase\r
+ end \r
+ else\r
+ begin\r
+ ShiftReg[7:0] <= {ShiftReg[6:0], Mdi};\r
+ if(LatchByte[0])\r
+ begin\r
+ Prsd[7:0] <= {ShiftReg[6:0], Mdi};\r
+ if(Rgad == 5'h01)\r
+ LinkFail <= ~ShiftReg[1]; // this is bit [2], because it is not shifted yet\r
+ end\r
+ else\r
+ begin\r
+ if(LatchByte[1])\r
+ Prsd[15:8] <= {ShiftReg[6:0], Mdi};\r
+ end\r
+ end\r
+ end\r
+ end\r
+end\r
+\r
+\r
+assign ShiftedBit = ShiftReg[7];\r
+\r
+\r
+endmodule\r
projects / debian / gnuradio / commitdiff