org {LIST; return ORG;}
equ {LIST; return EQU;}
-sfr {LIST; return EQU;}
+sfr {LIST; return SFR;}
db {LIST; return DB;}
dw {LIST; return DW;}
byte {LIST; return DB;}
area {LIST; return AREA;}
ds {LIST; return DS;}
DSEG {LIST; yylval = AREA_DSEG; return AREA_NAME;}
-OSEG {LIST; yylval = AREA_OSEG; return AREA_NAME;}
-ISEG {LIST; yylval = AREA_ISEG; return AREA_NAME;}
BSEG {LIST; yylval = AREA_BSEG; return AREA_NAME;}
XSEG {LIST; yylval = AREA_XSEG; return AREA_NAME;}
XISEG {LIST; yylval = AREA_XISEG; return AREA_NAME;}
GSINIT {LIST; yylval = AREA_GSINIT; return AREA_NAME;}
GSFINAL {LIST; yylval = AREA_GSFINAL; return AREA_NAME;}
HOME {LIST; yylval = AREA_HOME; return AREA_NAME;}
+SSEG {LIST; yylval = AREA_SSEG; return AREA_NAME;}
CSEG {LIST; yylval = AREA_CSEG; return AREA_NAME;}
module {LIST; return MODULE;}
globl {LIST; return GLOBL;}
\(DATA\) {LIST; return AREA_DESC;}
-\(OVR,DATA\) {LIST; return AREA_DESC;}
+\(OVR,XDATA\) {LIST; return AREA_DESC;}
\(BIT\) {LIST; return AREA_DESC;}
\(XDATA\) {LIST; return AREA_DESC;}
\(CODE\) {LIST; return AREA_DESC;}
%token SETB SEXT SUB SUBB TRAP XCH XOR
%token REG DPTR PC A C USP
%token WORD BIT NUMBER CHAR STRING EOL LOCAL_LABEL
-%token ORG EQU DB DW BITDEF REGDEF LOW HIGH
+%token ORG EQU SFR DB DW BITDEF REGDEF LOW HIGH
%token RSHIFT LSHIFT
%token AREA AREA_NAME AREA_DESC DS
%token MODULE GLOBL
if (p1) build_sym_list(symbol_name);
if (p1 || p2) assign_value(symbol_name, $3);
}
- | symbol EQU expr {
+ | symbol SFR expr {
if (p1) build_sym_list(symbol_name);
if (p1 || p2) assign_value(symbol_name, $3);
+ if (p1 || p2) mk_sfr(symbol_name);
$$ = 0;
}
| '.' BITDEF bitsymbol ',' bit {
{
case AREA_CSEG: return "CSEG";
case AREA_DSEG: return "DSEG";
- case AREA_OSEG: return "OSEG";
- case AREA_ISEG: return "ISEG";
+ //case AREA_OSEG: return "OSEG";
+ //case AREA_ISEG: return "ISEG";
case AREA_BSEG: return "BSEG";
case AREA_XSEG: return "XSEG";
case AREA_XISEG: return "XISEG";
case AREA_XINIT: return "XINIT";
+ case AREA_GSINIT: return "GSINIT";
+ case AREA_GSFINAL: return "GSFINAL";
+ case AREA_HOME: return "HOME";
+ case AREA_SSEG: return "SSEG";
}
return ("UNKNOW");
}
exit(1);
}
+int mk_sfr(char *thename)
+{
+ struct symbol *p;
+
+ p = sym_list;
+ while (p != NULL) {
+ if (!(strcasecmp(thename, p->name))) {
+ p->issfr = 1;
+ return (0);
+ }
+ p = p->next;
+ }
+ fprintf(stderr, "Internal Error! Couldn't find symbol\n");
+ exit(1);
+}
+
int mk_reg(char *thename)
{
struct symbol *p;
p = sym_list;
while (p != NULL) {
+#if 0
fprintf(sym_fp, "Sym in %-5s: %s\n", areaToString(p->area), p->name);
fprintf(sym_fp, " at: 0x%04X (%5d)", p->value, p->value);
fprintf(sym_fp, " Def:%s", p->isdef ? "Yes" : "No ");
fprintf(sym_fp, " Bit:%s", p->isbit ? "Yes" : "No ");
fprintf(sym_fp, " Target:%s", p->istarget ? "Yes" : "No ");
fprintf(sym_fp, " Line %d\n", p->line_def);
+#else
+ if (p->issfr) {
+ fprintf (sym_fp, "%-5s", "SFR");
+ } else if (p->isbit) {
+ fprintf (sym_fp, "%-5s", "BIT");
+ } else {
+ fprintf (sym_fp, "%-5s", areaToString(p->area));
+ }
+ fprintf (sym_fp, " 0x%04x (%5d)", p->value, p->value);
+ fprintf (sym_fp, " %s", p->isdef ? "D" : "-");
+ fprintf (sym_fp, "%s", p->isbit ? "B" : "-");
+ fprintf (sym_fp, "%s", p->istarget ? "T" : "-");
+ fprintf (sym_fp, " %s\n", p->name);
+#endif
p = p->next;
}
}
{
area[AREA_CSEG].start=area[AREA_CSEG].alloc_position = 0;
area[AREA_DSEG].start=area[AREA_DSEG].alloc_position = 0x30;
- area[AREA_OSEG].start=area[AREA_OSEG].alloc_position = 0x80;
- area[AREA_ISEG].start=area[AREA_ISEG].alloc_position = 0;
area[AREA_BSEG].start=area[AREA_BSEG].alloc_position = 0;
area[AREA_XSEG].start=area[AREA_XSEG].alloc_position = 0;
area[AREA_XISEG].start=area[AREA_XISEG].alloc_position = 0;
area[AREA_XINIT].start=area[AREA_XINIT].alloc_position = 0;
area[AREA_GSINIT].start=area[AREA_GSINIT].alloc_position = 0;
area[AREA_GSFINAL].start=area[AREA_GSFINAL].alloc_position = 0;
- area[AREA_HOME].alloc_position = 0;
+ area[AREA_HOME].start=area[AREA_HOME].alloc_position = 0;
+}
+
+void addAreaSymbols() {
+ char buffer[132];
+ int i;
+ for (i=0; i<NUM_AREAS; i++) {
+ current_area=i;
+ sprintf (buffer, "s_%s", areaToString(i));
+ build_sym_list (buffer);
+ assign_value (buffer, area[i].start);
+ buffer[0]='l';
+ build_sym_list (buffer);
+ assign_value (buffer, area[i].alloc_position-area[i].start);
+ }
}
void printVersion() {
init_areas();
yyparse();
flag_targets();
- if (createSymbolFile) print_symbol_table();
check_redefine();
if (verbose) printf("Pass 2: Aligning Branch Targets:\n");
init_areas();
yyparse();
+ addAreaSymbols();
+ if (createSymbolFile) print_symbol_table();
+
if (verbose) printf("Pass 3: Generating Object Code:\n");
p2 = 0;
p3 = 1;
int isdef; /* 1 if defined, 0 if no value yet */
int line_def; /* line in which is was defined */
int isbit; /* 1 if a bit address, 0 otherwise */
+ int issfr;
int isreg; /* 1 if a register, 0 otehrwise */
int area; /* the area that this symbol is in */
struct symbol *next; };
#define MEM_POS (area[current_area].alloc_position)
-#define AREA_CSEG 0
-#define AREA_DSEG 1
-#define AREA_OSEG 2
-#define AREA_ISEG 3
-#define AREA_BSEG 4
-#define AREA_XSEG 5
-#define AREA_XISEG 6
-#define AREA_XINIT 7
-#define AREA_GSINIT 8
-#define AREA_GSFINAL 9
-#define AREA_HOME 10
-#define NUM_AREAS 11
+enum {
+ AREA_CSEG=0,
+ AREA_DSEG,
+ // AREA_OSEG,
+ // AREA_ISEG,
+ AREA_BSEG,
+ AREA_XSEG,
+ AREA_XISEG,
+ AREA_XINIT,
+ AREA_GSINIT,
+ AREA_GSFINAL,
+ AREA_HOME,
+ AREA_SSEG,
+ NUM_AREAS
+};
extern struct area_struct area[NUM_AREAS];
--- /dev/null
+CC = sdcc
+
+#CFLAGS=
+#MFLAGS=
+#LFLAGS=
+
+all: hello.hex
+
+
+hello.hex: hello.c
+ $(CC) -mxa51 hello.c
+
+clean:
+ rm -f core *~ \#* *.asm *.cdb *.rel *.hex *.ihx *.lst *.map \
+ *.xa *.rst *.sym *.lnk *.lib *.bin *.dump*
+
--- /dev/null
+#include <xa.h>
+
+bit b1, b2;
+data d1, d2;
+xdata x1, x2;
+
+#define BAUD_RATE 9600
+#define OSC 20000000L /* Xtal frequency */
+
+#define DIVIDER (OSC/(64L*BAUD_RATE))
+
+void external_startup(void) {
+ _asm
+ mov.b _WDCON,#0 ;shut down the watchdog
+ mov.b _WFEED1,#0a5h
+ mov.b _WFEED2,#05ah
+; mov.b _BCR,#1 ;BCR: 8 data, 16 address
+; mov.b _SCR,#1 ;SCR: page zero mode
+ _endasm;
+
+ // init serial io
+ TL1 = RTL1 = -DIVIDER;
+ TH1 = RTH1 = -DIVIDER >> 8;
+ TR1 = 1; /* enable timer 1 */
+
+ S0CON = 0x52; /* mode 1, receiver enable */
+ IPA4 |= 0x6; /* maximum priority */
+ ERI0=1; /* enable receiver interupts */
+ TI0==1; /* transmitter empty */
+ RI0=0; /* receiver empty */
+
+ //PSWH &= 0xf0; /* start interupt system */
+}
+
+void putchar(char c) {
+ while(!TI0)
+ ;
+ S0BUF = c;
+ TI0 = 0;
+}
+
+
+char getchar(void) {
+ char c;
+
+ while (!RI0)
+ ;
+ c=S0BUF;
+ RI0=0;
+ return c;
+}
+
+void puts(char *s) {
+ while (*s) {
+ putchar (*s++);
+ }
+}
+
+int kbhit(void) {
+ return RI0;
+}
+
+void main(void) {
+ puts ("Hello world.\n\r");
+}
--- /dev/null
+/*
+ * XA G3 SFR definitions
+ * Extracted directly from Philips documentation
+ */
+
+#ifndef XA_H
+#define XA_H
+
+sfr at 0x400 /*unsigned short*/ PSW; /* Program status word */
+sfr at 0x400 PSWL; /* Program status word (low byte) */
+sfr at 0x401 PSWH; /* Program status word (high byte) */
+sfr at 0x402 PSW51; /* 80C51 compatible PSW */
+sfr at 0x403 SSEL; /* Segment selection register */
+sfr at 0x404 PCON; /* Power control register */
+sfr at 0x410 TCON; /* Timer 0 and 1 control register */
+sfr at 0x411 TSTAT; /* Timer 0 and 1 extended status */
+sfr at 0x418 T2CON; /* Timer 2 control register */
+sfr at 0x419 T2MOD; /* Timer 2 mode control */
+sfr at 0x41F WDCON; /* Watchdog control register */
+sfr at 0x420 S0CON; /* Serial port 0 control register */
+sfr at 0x421 S0STAT; /* Serial port 0 extended status */
+sfr at 0x424 S1CON; /* Serial port 1 control register */
+sfr at 0x425 S1STAT; /* Serial port 1 extended status */
+sfr at 0x426 IEL; /* Interrupt enable low byte */
+sfr at 0x427 IEH; /* Interrupt enable high byte */
+sfr at 0x42A SWR; /* Software Interrupt Request */
+sfr at 0x430 P0; /* Port 0 */
+sfr at 0x431 P1; /* Port 1 */
+sfr at 0x432 P2; /* Port 2 */
+sfr at 0x433 P3; /* Port3 */
+sfr at 0x440 SCR; /* System configuration register */
+sfr at 0x441 DS; /* Data segment */
+sfr at 0x442 ES; /* Extra segment */
+sfr at 0x443 CS; /* Code segment */
+sfr at 0x450 TL0; /* Timer 0 low byte */
+sfr at 0x451 TH0; /* Timer 0 high byte */
+sfr at 0x452 TL1; /* Timer 1 low byte */
+sfr at 0x453 TH1; /* Timer 1 high byte */
+sfr at 0x454 RTL0; /* Timer 0 extended reload, low byte */
+sfr at 0x455 RTH0; /* Timer 0 extended reload, high byte */
+sfr at 0x456 RTL1; /* Timer 1 extended reload, low byte */
+sfr at 0x457 RTH1; /* Timer 1 extended reload, high byte */
+sfr at 0x458 TL2; /* Timer 2 low byte */
+sfr at 0x459 TH2; /* Timer 2 high byte */
+sfr at 0x45A T2CAPL; /* Timer 2 capture register, low byte */
+sfr at 0x45B T2CAPH; /* Timer 2 capture register, high byte */
+sfr at 0x45C TMOD; /* Timer 0 and 1 mode register */
+sfr at 0x45D WFEED1; /* Watchdog feed 1 */
+sfr at 0x45E WFEED2; /* Watchdog feed 2 */
+sfr at 0x45F WDL; /* Watchdog timer reload */
+sfr at 0x460 S0BUF; /* Serial port 0 buffer register */
+sfr at 0x461 S0ADDR; /* Serial port 0 address register */
+sfr at 0x462 S0ADEN; /* Serial port 0 address enable register */
+sfr at 0x464 S1BUF; /* Serial port 1 buffer register */
+sfr at 0x465 S1ADDR; /* Serial port 1 address register */
+sfr at 0x466 S1ADEN; /* Serial port 1 address enable register */
+sfr at 0x468 BTRL; /* Bus timing register high byte */
+sfr at 0x469 BTRH; /* Bus timing register low byte */
+sfr at 0x46A BCR; /* Bus configuration register */
+sfr at 0x470 P0CFGA; /* Port 0 configuration A */
+sfr at 0x471 P1CFGA; /* Port 1 configuration A */
+sfr at 0x472 P2CFGA; /* Port 2 configuration A */
+sfr at 0x473 P3CFGA; /* Port 3 configuration A */
+sfr at 0x47A SWE; /* Software Interrupt Enable */
+sfr at 0x4A0 IPA0; /* Interrupt priority 0 */
+sfr at 0x4A1 IPA1; /* Interrupt priority 1 */
+sfr at 0x4A2 IPA2; /* Interrupt priority 2 */
+sfr at 0x4A4 IPA4; /* Interrupt priority 4 */
+sfr at 0x4A5 IPA5; /* Interrupt priority 5 */
+sfr at 0x4F0 P0CFGB; /* Port 0 configuration B */
+sfr at 0x4F1 P1CFGB; /* Port 1 configuration B */
+sfr at 0x4F2 P2CFGB; /* Port 2 configuration B */
+sfr at 0x4F3 P3CFGB; /* Port 3 configuration B */
+
+sbit at 0x33B ETI1; /* TX interrupt enable 1 */
+sbit at 0x33A ERI1; /* RX interrupt enable 1 */
+sbit at 0x339 ETI0; /* TX interrupt enable 0 */
+sbit at 0x338 ERI0; /* RX interrupt enable 0 */
+sbit at 0x337 EA; /* global int. enable */
+sbit at 0x334 ET2; /* timer 2 interrupt */
+sbit at 0x333 ET1; /* timer 1 interrupt */
+sbit at 0x332 EX1; /* external interrupt 1 */
+sbit at 0x331 ET0; /* timer 0 interrupt */
+sbit at 0x330 EX0; /* external interrupt 0 */
+sbit at 0x221 PD; /* power down */
+sbit at 0x220 IDL;
+sbit at 0x20F SM;
+sbit at 0x20E TM;
+sbit at 0x20D RS1;
+sbit at 0x20C RS0;
+sbit at 0x20B IM3;
+sbit at 0x20A IM2;
+sbit at 0x209 IM1;
+sbit at 0x208 IM0;
+sbit at 0x307 S0M0;
+sbit at 0x306 S0M1;
+sbit at 0x305 S0M2;
+sbit at 0x304 R0EN;
+sbit at 0x303 T0B8;
+sbit at 0x302 R0B8;
+sbit at 0x301 TI0; /* serial port 0 tx ready */
+sbit at 0x300 RI0; /* serial port 0 rx ready */
+sbit at 0x30B FE0;
+sbit at 0x30A BR0;
+sbit at 0x309 OE0;
+sbit at 0x308 STINT0;
+sbit at 0x327 S1M0;
+sbit at 0x326 S1M1;
+sbit at 0x325 S1M2;
+sbit at 0x324 R1EN;
+sbit at 0x323 T1B8;
+sbit at 0x322 R1B8;
+sbit at 0x321 TI1; /* serial port 0 tx ready */
+sbit at 0x320 RI1; /* serial port 0 rx ready */
+sbit at 0x32B FE1;
+sbit at 0x32A BR1;
+sbit at 0x329 OE1;
+sbit at 0x328 STINT1;
+sbit at 0x356 SWR7;
+sbit at 0x355 SWR6;
+sbit at 0x354 SWR5;
+sbit at 0x353 SWR4;
+sbit at 0x352 SWR3;
+sbit at 0x351 SWR2;
+sbit at 0x350 SWR1;
+sbit at 0x2C7 TF2;
+sbit at 0x2C6 EXF2;
+sbit at 0x2C5 RCLK0;
+sbit at 0x2C4 TCLK0;
+sbit at 0x2CD RCLK1;
+sbit at 0x2CC TCLK1;
+sbit at 0x2C3 EXEN2;
+sbit at 0x2C2 TR2;
+sbit at 0x2C1 CT2;
+sbit at 0x2C0 CPRL2;
+sbit at 0x2C9 T2OE;
+sbit at 0x2C8 DCEN;
+sbit at 0x287 TF1;
+sbit at 0x286 TR1;
+sbit at 0x285 TF0;
+sbit at 0x284 TR0;
+sbit at 0x283 IE1;
+sbit at 0x282 IT1;
+sbit at 0x281 IE0;
+sbit at 0x280 IT0;
+sbit at 0x28A T1OE;
+sbit at 0x288 T0OE;
+sbit at 0x2FF PRE2;
+sbit at 0x2FE PRE1;
+sbit at 0x2FD PRE0;
+sbit at 0x2FA WDRUN;
+sbit at 0x2F9 WDTOF;
+sbit at 0x2F8 WDMOD;
+sbit at 0x388 WR1;
+sbit at 0x38F T2EX;
+sbit at 0x38C RXD1;
+sbit at 0x38D TXD1;
+sbit at 0x398 RXD0;
+sbit at 0x399 TXD0;
+sbit at 0x39A INT0;
+sbit at 0x39B INT1;
+sbit at 0x39C T0;
+sbit at 0x39D T1;
+sbit at 0x39E WR;
+sbit at 0x39F RD;
+
+/*
+ * Interrupt stuff
+ */
+
+
+/* Vectors */
+
+#define IV_BRKPT 0x04 /* breakpoint vector */
+#define IV_TRACE 0x08 /* Trace mode bit set */
+#define IV_STKOVER 0x0C /* stack overflow */
+#define IV_DIVZERO 0x10 /* divide by zero */
+#define IV_IRET 0x14 /* user mode IRET */
+
+#define IV_EX0 0x80
+#define IV_T0 0x84
+#define IV_EX1 0x88
+#define IV_T1 0x8C
+#define IV_T2 0x90
+#define IV_RI0 0xA0
+#define IV_TI0 0xA4
+#define IV_RI1 0xA8
+#define IV_TI1 0xAC
+#define IV_SWI1 0x100 /* software interrupts */
+#define IV_SWI2 0x104
+#define IV_SWI3 0x108
+#define IV_SWI4 0x10C
+#define IV_SWI5 0x110
+#define IV_SWI6 0x114
+#define IV_SWI7 0x118
+
+/* PSW Values for interrupt vectors */
+
+#define IV_PSW 0x8F00 /* System mode, high priority, bank 0 */
+
+#define IV_SYSTEM 0x8000
+
+#define IV_PRI00 0x0000 /* priorities 0 - 15 */
+#define IV_PRI01 0x0100
+#define IV_PRI02 0x0200
+#define IV_PRI03 0x0300
+#define IV_PRI04 0x0400
+#define IV_PRI05 0x0500
+#define IV_PRI06 0x0600
+#define IV_PRI07 0x0700
+#define IV_PRI08 0x0800
+#define IV_PRI09 0x0900
+#define IV_PRI10 0x0A00
+#define IV_PRI11 0x0B00
+#define IV_PRI12 0x0C00
+#define IV_PRI13 0x0D00
+#define IV_PRI14 0x0E00
+#define IV_PRI15 0x0F00
+
+#define IV_BANK0 0x0000
+#define IV_BANK1 0x1000
+#define IV_BANK2 0x2000
+#define IV_BANK3 0x3000
+
+#endif /* XA_H */
/* create the overlay segments */
- fprintf (asmFile, "%s", iComments2);
- fprintf (asmFile, "; overlayable items in internal ram \n");
- fprintf (asmFile, "%s", iComments2);
- copyFile (asmFile, ovrFile);
+ if (overlay) {
+ fprintf (asmFile, "%s", iComments2);
+ fprintf (asmFile, "; overlayable items in internal ram \n");
+ fprintf (asmFile, "%s", iComments2);
+ copyFile (asmFile, ovrFile);
+ }
/* create the stack segment MOF */
if (mainf && IFFUNC_HASBODY(mainf->type))
}
/* create the idata segment */
- fprintf (asmFile, "%s", iComments2);
- fprintf (asmFile, "; indirectly addressable internal ram data\n");
- fprintf (asmFile, "%s", iComments2);
- copyFile (asmFile, idata->oFile);
+ if (idata) {
+ fprintf (asmFile, "%s", iComments2);
+ fprintf (asmFile, "; indirectly addressable internal ram data\n");
+ fprintf (asmFile, "%s", iComments2);
+ copyFile (asmFile, idata->oFile);
+ }
/* copy the bit segment */
fprintf (asmFile, "%s", iComments2);
DEBUG-NAME - 'B'
POINTER-TYPE - POINTER
*/
- istack = allocMap (0, 0, 0, 0, 0, 0, options.stack_loc, ISTACK_NAME, 'B', POINTER);
+ if (ISTACK_NAME) {
+ istack = allocMap (0, 0, 0, 0, 0, 0, options.stack_loc,
+ ISTACK_NAME, 'B', POINTER);
+ } else {
+ istack=NULL;
+ }
/* code segment ;
SFRSPACE - NO
DEBUG-NAME - 'E'
POINTER-TYPE - POINTER
*/
- overlay = allocMap (0, 0, 0, 1, 0, 0, options.data_loc, DATA_NAME, 'E', POINTER);
+ if (OVERLAY_NAME) {
+ overlay = allocMap (0, 0, 0, 1, 0, 0, options.data_loc, DATA_NAME, 'E', POINTER);
+ } else {
+ overlay = NULL;
+ }
/* Xternal Data segment -
SFRSPACE - NO
DEBUG-NAME - 'G'
POINTER-TYPE - IPOINTER
*/
- idata = allocMap (0, 0, 0, 0, 0, 0, options.idata_loc, IDATA_NAME, 'G', IPOINTER);
+ if (IDATA_NAME) {
+ idata = allocMap (0, 0, 0, 0, 0, 0, options.idata_loc,
+ IDATA_NAME, 'G', IPOINTER);
+ } else {
+ idata=NULL;
+ }
/* Static segment (code for variables );
SFRSPACE - NO
void
doOverlays (eBBlock ** ebbs, int count)
{
+ if (!overlay) {
+ return;
+ }
+
/* check if the parameters and local variables
of this function can be put in the overlay segment
This check is essentially to see if the function
#define REG_NAME port->mem.reg_name
#define STATIC_NAME port->mem.static_name
#define HOME_NAME port->mem.home_name
+#define OVERLAY_NAME port->mem.overlay_name
/* forward definition for variables */
extern memmap *xstack; /* xternal stack data */
//"_pdata",
//"_idata",
"_naked",
- "_overlay",
+ //"_overlay",
NULL
};
options.stackAuto=1;
options.intlong_rent=1;
options.float_rent=1;
+ options.stack_loc=0x100;
}
static const char *
return "err";
}
-static void
-_xa51_genAssemblerPreamble (FILE * of)
-{
- fprintf (of, "_errno\tsfr\t0x00; to keep the fp-lib's happy for now\n");
-}
-
/* Generate interrupt vector table. */
static int
_xa51_genIVT (FILE * of, symbol ** interrupts, int maxInterrupts)
{
- fprintf (of, "\t.dw\t0x8f00\n");
- fprintf (of, "\t.dw\t__sdcc_gsinit_startup\n");
- // no IVT yet
return TRUE;
}
fprintf (of, " beq 00002$\n");
fprintf (of, " mov r1,#s_XINIT\n");
fprintf (of, " mov r2,#s_XISEG\n");
- fprintf (of, "00001$ movc r3l,[r1+]\n");
+ fprintf (of, "00001$: movc r3l,[r1+]\n");
fprintf (of, " mov [r2+],r3l\n");
fprintf (of, " djnz r0,00001$\n");
fprintf (of, "00002$:\n");
fprintf (of, "; _xa51_genXINIT() end\n");
}
+static void
+_xa51_genAssemblerPreamble (FILE * of)
+{
+ fprintf (of, "_errno\tsfr\t0x00; to keep the fp-lib's happy for now\n\n");
+ fprintf (of, "\t.area CSEG\t(CODE)\n");
+ fprintf (of, "__interrupt_vect:\n");
+ fprintf (of, "\t.dw\t0x8f00\n");
+ fprintf (of, "\t.dw\t__sdcc_gsinit_startup\n");
+ fprintf (of, "\n");
+ fprintf (of, "__sdcc_gsinit_startup:\n");
+ fprintf (of, "\tmov\tr7,#0x%04x\n", options.stack_loc);
+ fprintf (of, "\tcall\t_external_startup\n");
+ _xa51_genXINIT(of);
+ fprintf (of, "\tcall\t_main\n");
+ fprintf (of, "\treset\t;main should not return\n");
+}
+
+/* dummy linker for now */
+void xa_link(void) {
+}
/* Do CSE estimation */
static bool cseCostEstimation (iCode *ic, iCode *pdic)
return 1;
}
+#if 0
/** $1 is always the basename.
$2 is always the output file.
$3 varies
{
"{bindir}{sep}aslink", "-nf", "$1", NULL
};
+#endif
/* $3 is replaced by assembler.debug_opts resp. port->assembler.plain_opts */
static const char *_asmCmd[] =
"xa51",
"MCU 80C51XA", /* Target name */
{
- TRUE, /* Emit glue around main */
+ FALSE, /* Emit glue around main */
MODEL_LARGE,
MODEL_LARGE
},
NULL /* no do_assemble function */
},
{
- _linkCmd,
- NULL,
+ NULL, //_linkCmd,
NULL,
+ xa_link,
".rel"
},
{
},
{
"XSEG (XDATA)",
- "STACK (DATA)",
+ "STACK (XDATA)",
"CSEG (CODE)",
"DSEG (DATA)",
- "ISEG (DATA)",
+ NULL, //"ISEG (DATA)",
"XSEG (XDATA)",
"BSEG (BIT)",
- "RSEG (DATA)",
+ NULL, //"RSEG (DATA)",
"GSINIT (CODE)",
- "OSEG (OVR,DATA)",
+ NULL, //"OSEG (OVR,XDATA)",
"GSFINAL (CODE)",
"HOME (CODE)",
"XISEG (XDATA)", // initialized xdata
}
- return 0;
if (!dic)
return 0; /* did not find */
projects / fw / sdcc / commitdiff