--- /dev/null
+LIB = libstm32l_discovery.a
+
+CC = arm-none-eabi-gcc
+AR = arm-none-eabi-ar
+RANLIB = arm-none-eabi-ranlib
+
+CFLAGS = -Wall -O2 -mlittle-endian -mthumb
+CFLAGS += -mcpu=cortex-m3 -ffreestanding -nostdlib -nostdinc
+CFLAGS += -I../inc -I../inc/device_support -I../inc/core_support -I../inc/base
+
+SRCS = \
+../src/misc.c \
+../src/stm32l1xx_adc.c \
+../src/stm32l1xx_comp.c \
+../src/stm32l1xx_crc.c \
+../src/stm32l1xx_dac.c \
+../src/stm32l1xx_dbgmcu.c \
+../src/stm32l1xx_dma.c \
+../src/stm32l1xx_exti.c \
+../src/stm32l1xx_flash.c \
+../src/stm32l1xx_flash_ramfunc.c \
+../src/stm32l1xx_gpio.c \
+../src/stm32l1xx_i2c.c \
+../src/stm32l1xx_iwdg.c \
+../src/stm32l1xx_lcd.c \
+../src/stm32l1xx_pwr.c \
+../src/stm32l1xx_rcc.c \
+../src/stm32l1xx_rtc.c \
+../src/stm32l1xx_spi.c \
+../src/stm32l1xx_syscfg.c \
+../src/stm32l1xx_tim.c \
+../src/stm32l1xx_usart.c \
+../src/stm32l1xx_wwdg.c \
+../inc/core_support/core_cm3.c
+
+OBJS = $(SRCS:.c=.o)
+
+all: $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) -r $(LIB) $(OBJS)
+ $(RANLIB) $(LIB)
+
+%.o : %.c
+ $(CC) $(CFLAGS) -c -o $@ $^
+
+clean:
+ -rm -f $(OBJS)
+ -rm -f $(LIB)
+
+.PHONY: all clean
--- /dev/null
+#ifndef STDINT_H_INCLUDED
+# define STDINT_H_INCLUDED
+
+
+typedef char int8_t;
+typedef short int16_t;
+typedef int int32_t;
+typedef long long int64_t;
+
+typedef unsigned char uint8_t;
+typedef unsigned short uint16_t;
+typedef unsigned int uint32_t;
+typedef unsigned long long uint64_t;
+
+
+#endif /* ! STDINT_H_INCLUDED */
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm3.c\r
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File\r
+ * @version V1.30\r
+ * @date 30. October 2009\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#include <stdint.h>\r
+\r
+/* define compiler specific symbols */\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+\r
+#endif\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+__ASM uint32_t __get_PSP(void)\r
+{\r
+ mrs r0, psp\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param topOfProcStack Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+__ASM void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ msr psp, r0\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+__ASM uint32_t __get_MSP(void)\r
+{\r
+ mrs r0, msp\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param topOfMainStack Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+__ASM void __set_MSP(uint32_t mainStackPointer)\r
+{\r
+ msr msp, r0\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+__ASM uint32_t __REV16(uint16_t value)\r
+{\r
+ rev16 r0, r0\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+__ASM int32_t __REVSH(int16_t value)\r
+{\r
+ revsh r0, r0\r
+ bx lr\r
+}\r
+\r
+\r
+#if (__ARMCC_VERSION < 400000)\r
+\r
+/**\r
+ * @brief Remove the exclusive lock created by ldrex\r
+ *\r
+ * Removes the exclusive lock which is created by ldrex.\r
+ */\r
+__ASM void __CLREX(void)\r
+{\r
+ clrex\r
+}\r
+\r
+/**\r
+ * @brief Return the Base Priority value\r
+ *\r
+ * @return BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+__ASM uint32_t __get_BASEPRI(void)\r
+{\r
+ mrs r0, basepri\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Set the Base Priority value\r
+ *\r
+ * @param basePri BasePriority\r
+ *\r
+ * Set the base priority register\r
+ */\r
+__ASM void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ msr basepri, r0\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Return the Priority Mask value\r
+ *\r
+ * @return PriMask\r
+ *\r
+ * Return state of the priority mask bit from the priority mask register\r
+ */\r
+__ASM uint32_t __get_PRIMASK(void)\r
+{\r
+ mrs r0, primask\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Set the Priority Mask value\r
+ *\r
+ * @param priMask PriMask\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+__ASM void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ msr primask, r0\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Return the Fault Mask value\r
+ *\r
+ * @return FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+__ASM uint32_t __get_FAULTMASK(void)\r
+{\r
+ mrs r0, faultmask\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Set the Fault Mask value\r
+ *\r
+ * @param faultMask faultMask value\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+__ASM void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ msr faultmask, r0\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Return the Control Register value\r
+ * \r
+ * @return Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+__ASM uint32_t __get_CONTROL(void)\r
+{\r
+ mrs r0, control\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Set the Control Register value\r
+ *\r
+ * @param control Control value\r
+ *\r
+ * Set the control register\r
+ */\r
+__ASM void __set_CONTROL(uint32_t control)\r
+{\r
+ msr control, r0\r
+ bx lr\r
+}\r
+\r
+#endif /* __ARMCC_VERSION */ \r
+\r
+\r
+\r
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+#pragma diag_suppress=Pe940\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+uint32_t __get_PSP(void)\r
+{\r
+ __ASM("mrs r0, psp");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param topOfProcStack Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM("msr psp, r0");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+uint32_t __get_MSP(void)\r
+{\r
+ __ASM("mrs r0, msp");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param topOfMainStack Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM("msr msp, r0");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+uint32_t __REV16(uint16_t value)\r
+{\r
+ __ASM("rev16 r0, r0");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief Reverse bit order of value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+uint32_t __RBIT(uint32_t value)\r
+{\r
+ __ASM("rbit r0, r0");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief LDR Exclusive (8 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 8 bit values)\r
+ */\r
+uint8_t __LDREXB(uint8_t *addr)\r
+{\r
+ __ASM("ldrexb r0, [r0]");\r
+ __ASM("bx lr"); \r
+}\r
+\r
+/**\r
+ * @brief LDR Exclusive (16 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 16 bit values\r
+ */\r
+uint16_t __LDREXH(uint16_t *addr)\r
+{\r
+ __ASM("ldrexh r0, [r0]");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief LDR Exclusive (32 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 32 bit values\r
+ */\r
+uint32_t __LDREXW(uint32_t *addr)\r
+{\r
+ __ASM("ldrex r0, [r0]");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief STR Exclusive (8 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 8 bit values\r
+ */\r
+uint32_t __STREXB(uint8_t value, uint8_t *addr)\r
+{\r
+ __ASM("strexb r0, r0, [r1]");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief STR Exclusive (16 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 16 bit values\r
+ */\r
+uint32_t __STREXH(uint16_t value, uint16_t *addr)\r
+{\r
+ __ASM("strexh r0, r0, [r1]");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief STR Exclusive (32 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 32 bit values\r
+ */\r
+uint32_t __STREXW(uint32_t value, uint32_t *addr)\r
+{\r
+ __ASM("strex r0, r0, [r1]");\r
+ __ASM("bx lr");\r
+}\r
+\r
+#pragma diag_default=Pe940\r
+\r
+\r
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+uint32_t __get_PSP(void) __attribute__( ( naked ) );\r
+uint32_t __get_PSP(void)\r
+{\r
+ uint32_t result=0;\r
+\r
+ __ASM volatile ("MRS %0, psp\n\t" \r
+ "MOV r0, %0 \n\t"\r
+ "BX lr \n\t" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param topOfProcStack Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );\r
+void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp, %0\n\t"\r
+ "BX lr \n\t" : : "r" (topOfProcStack) );\r
+}\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+uint32_t __get_MSP(void) __attribute__( ( naked ) );\r
+uint32_t __get_MSP(void)\r
+{\r
+ uint32_t result=0;\r
+\r
+ __ASM volatile ("MRS %0, msp\n\t" \r
+ "MOV r0, %0 \n\t"\r
+ "BX lr \n\t" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param topOfMainStack Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );\r
+void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp, %0\n\t"\r
+ "BX lr \n\t" : : "r" (topOfMainStack) );\r
+}\r
+\r
+/**\r
+ * @brief Return the Base Priority value\r
+ *\r
+ * @return BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+uint32_t __get_BASEPRI(void)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Set the Base Priority value\r
+ *\r
+ * @param basePri BasePriority\r
+ *\r
+ * Set the base priority register\r
+ */\r
+void __set_BASEPRI(uint32_t value)\r
+{\r
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) );\r
+}\r
+\r
+/**\r
+ * @brief Return the Priority Mask value\r
+ *\r
+ * @return PriMask\r
+ *\r
+ * Return state of the priority mask bit from the priority mask register\r
+ */\r
+uint32_t __get_PRIMASK(void)\r
+{\r
+ uint32_t result=0;\r
+\r
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Set the Priority Mask value\r
+ *\r
+ * @param priMask PriMask\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) );\r
+}\r
+\r
+/**\r
+ * @brief Return the Fault Mask value\r
+ *\r
+ * @return FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+uint32_t __get_FAULTMASK(void)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Set the Fault Mask value\r
+ *\r
+ * @param faultMask faultMask value\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );\r
+}\r
+\r
+/**\r
+ * @brief Return the Control Register value\r
+* \r
+* @return Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+uint32_t __get_CONTROL(void)\r
+{\r
+ uint32_t result=0;\r
+\r
+ __ASM volatile ("MRS %0, control" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Set the Control Register value\r
+ *\r
+ * @param control Control value\r
+ *\r
+ * Set the control register\r
+ */\r
+void __set_CONTROL(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control, %0" : : "r" (control) );\r
+}\r
+\r
+\r
+/**\r
+ * @brief Reverse byte order in integer value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in integer value\r
+ */\r
+uint32_t __REV(uint32_t value)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+uint32_t __REV16(uint16_t value)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+int32_t __REVSH(int16_t value)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Reverse bit order of value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+uint32_t __RBIT(uint32_t value)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief LDR Exclusive (8 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 8 bit value\r
+ */\r
+uint8_t __LDREXB(uint8_t *addr)\r
+{\r
+ uint8_t result=0;\r
+ \r
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief LDR Exclusive (16 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 16 bit values\r
+ */\r
+uint16_t __LDREXH(uint16_t *addr)\r
+{\r
+ uint16_t result=0;\r
+ \r
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief LDR Exclusive (32 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 32 bit values\r
+ */\r
+uint32_t __LDREXW(uint32_t *addr)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief STR Exclusive (8 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 8 bit values\r
+ */\r
+uint32_t __STREXB(uint8_t value, uint8_t *addr)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief STR Exclusive (16 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 16 bit values\r
+ */\r
+uint32_t __STREXH(uint16_t value, uint16_t *addr)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief STR Exclusive (32 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 32 bit values\r
+ */\r
+uint32_t __STREXW(uint32_t value, uint32_t *addr)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all instrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm3.h\r
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
+ * @version V1.30\r
+ * @date 30. October 2009\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __CM3_CORE_H__\r
+#define __CM3_CORE_H__\r
+\r
+/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration\r
+ *\r
+ * List of Lint messages which will be suppressed and not shown:\r
+ * - Error 10: \n\r
+ * register uint32_t __regBasePri __asm("basepri"); \n\r
+ * Error 10: Expecting ';'\r
+ * .\r
+ * - Error 530: \n\r
+ * return(__regBasePri); \n\r
+ * Warning 530: Symbol '__regBasePri' (line 264) not initialized\r
+ * . \r
+ * - Error 550: \n\r
+ * __regBasePri = (basePri & 0x1ff); \n\r
+ * Warning 550: Symbol '__regBasePri' (line 271) not accessed\r
+ * .\r
+ * - Error 754: \n\r
+ * uint32_t RESERVED0[24]; \n\r
+ * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced\r
+ * .\r
+ * - Error 750: \n\r
+ * #define __CM3_CORE_H__ \n\r
+ * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced\r
+ * .\r
+ * - Error 528: \n\r
+ * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n\r
+ * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced\r
+ * .\r
+ * - Error 751: \n\r
+ * } InterruptType_Type; \n\r
+ * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced\r
+ * .\r
+ * Note: To re-enable a Message, insert a space before 'lint' *\r
+ *\r
+ */\r
+\r
+/*lint -save */\r
+/*lint -e10 */\r
+/*lint -e530 */\r
+/*lint -e550 */\r
+/*lint -e754 */\r
+/*lint -e750 */\r
+/*lint -e528 */\r
+/*lint -e751 */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions\r
+ This file defines all structures and symbols for CMSIS core:\r
+ - CMSIS version number\r
+ - Cortex-M core registers and bitfields\r
+ - Cortex-M core peripheral base address\r
+ @{\r
+ */\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0x03) /*!< Cortex core */\r
+\r
+#include <stdint.h> /* Include standard types */\r
+\r
+#if defined (__ICCARM__)\r
+ #include <intrinsics.h> /* IAR Intrinsics */\r
+#endif\r
+\r
+\r
+#ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */\r
+#endif\r
+\r
+\r
+\r
+\r
+/**\r
+ * IO definitions\r
+ *\r
+ * define access restrictions to peripheral registers\r
+ */\r
+\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< defines 'write only' permissions */\r
+#define __IO volatile /*!< defines 'read / write' permissions */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ ******************************************************************************/\r
+/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register\r
+ @{\r
+*/\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC\r
+ memory mapped structure for Nested Vectored Interrupt Controller (NVIC)\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24]; \r
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24]; \r
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24]; \r
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24]; \r
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56]; \r
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644]; \r
+ __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */\r
+} NVIC_Type; \r
+/*@}*/ /* end of group CMSIS_CM3_NVIC */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB\r
+ memory mapped structure for System Control Block (SCB)\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */\r
+ __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */\r
+ __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */\r
+ __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */\r
+ __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */\r
+ __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */\r
+ __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */\r
+ __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */\r
+ __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */\r
+ __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */\r
+ __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */\r
+ __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */\r
+ __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */\r
+ __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */\r
+ __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */\r
+ __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */\r
+ __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */\r
+ __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */\r
+} SCB_Type; \r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */\r
+#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */\r
+\r
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+ \r
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Registers Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* SCB Hard Fault Status Registers Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_SCB */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick\r
+ memory mapped structure for SysTick\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_SysTick */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM\r
+ memory mapped structure for Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ __O union \r
+ {\r
+ __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */\r
+ __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */\r
+ __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */\r
+ } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864]; \r
+ __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15]; \r
+ __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15]; \r
+ __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */\r
+ uint32_t RESERVED3[29]; \r
+ __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */\r
+ __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */\r
+ __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43]; \r
+ __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */\r
+ __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */\r
+ uint32_t RESERVED5[6]; \r
+ __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */\r
+ __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */\r
+ __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */\r
+ __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */\r
+ __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */\r
+ __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */\r
+ __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */\r
+ __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */\r
+ __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */\r
+ __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */\r
+ __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */\r
+ __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */\r
+} ITM_Type; \r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_ITM */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type\r
+ memory mapped structure for Interrupt Type\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0;\r
+ __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */\r
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))\r
+ __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */\r
+#else\r
+ uint32_t RESERVED1;\r
+#endif\r
+} InterruptType_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */\r
+#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */\r
+#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */\r
+\r
+#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */\r
+#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */\r
+\r
+#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */\r
+#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_InterruptType */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
+/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU\r
+ memory mapped structure for Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */\r
+ __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */\r
+ __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */\r
+ __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */\r
+ __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */\r
+ __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */\r
+ __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */\r
+ __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type; \r
+\r
+/* MPU Type Register */\r
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register */\r
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register */\r
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register */\r
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */\r
+#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */\r
+#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */\r
+#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */\r
+#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */\r
+\r
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */\r
+#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */\r
+\r
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */\r
+#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_MPU */\r
+#endif\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug\r
+ memory mapped structure for Core Debug Register\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */\r
+ __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */\r
+ __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */\r
+ __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_CoreDebug */\r
+\r
+\r
+/* Memory mapping of Cortex-M3 Hardware */\r
+#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000) /*!< ITM Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */\r
+\r
+#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */\r
+#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_core_register */\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ ******************************************************************************/\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+\r
+#endif\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+#define __enable_fault_irq __enable_fiq\r
+#define __disable_fault_irq __disable_fiq\r
+\r
+#define __NOP __nop\r
+#define __WFI __wfi\r
+#define __WFE __wfe\r
+#define __SEV __sev\r
+#define __ISB() __isb(0)\r
+#define __DSB() __dsb(0)\r
+#define __DMB() __dmb(0)\r
+#define __REV __rev\r
+#define __RBIT __rbit\r
+#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))\r
+#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))\r
+#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))\r
+#define __STREXB(value, ptr) __strex(value, ptr)\r
+#define __STREXH(value, ptr) __strex(value, ptr)\r
+#define __STREXW(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */\r
+/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */\r
+/* intrinsic void __enable_irq(); */\r
+/* intrinsic void __disable_irq(); */\r
+\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+extern uint32_t __get_PSP(void);\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param topOfProcStack Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+extern void __set_PSP(uint32_t topOfProcStack);\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+extern uint32_t __get_MSP(void);\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param topOfMainStack Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+extern void __set_MSP(uint32_t topOfMainStack);\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+extern uint32_t __REV16(uint16_t value);\r
+\r
+/**\r
+ * @brief Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+extern int32_t __REVSH(int16_t value);\r
+\r
+\r
+#if (__ARMCC_VERSION < 400000)\r
+\r
+/**\r
+ * @brief Remove the exclusive lock created by ldrex\r
+ *\r
+ * Removes the exclusive lock which is created by ldrex.\r
+ */\r
+extern void __CLREX(void);\r
+\r
+/**\r
+ * @brief Return the Base Priority value\r
+ *\r
+ * @return BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+extern uint32_t __get_BASEPRI(void);\r
+\r
+/**\r
+ * @brief Set the Base Priority value\r
+ *\r
+ * @param basePri BasePriority\r
+ *\r
+ * Set the base priority register\r
+ */\r
+extern void __set_BASEPRI(uint32_t basePri);\r
+\r
+/**\r
+ * @brief Return the Priority Mask value\r
+ *\r
+ * @return PriMask\r
+ *\r
+ * Return state of the priority mask bit from the priority mask register\r
+ */\r
+extern uint32_t __get_PRIMASK(void);\r
+\r
+/**\r
+ * @brief Set the Priority Mask value\r
+ *\r
+ * @param priMask PriMask\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+extern void __set_PRIMASK(uint32_t priMask);\r
+\r
+/**\r
+ * @brief Return the Fault Mask value\r
+ *\r
+ * @return FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+extern uint32_t __get_FAULTMASK(void);\r
+\r
+/**\r
+ * @brief Set the Fault Mask value\r
+ *\r
+ * @param faultMask faultMask value\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+extern void __set_FAULTMASK(uint32_t faultMask);\r
+\r
+/**\r
+ * @brief Return the Control Register value\r
+ * \r
+ * @return Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+extern uint32_t __get_CONTROL(void);\r
+\r
+/**\r
+ * @brief Set the Control Register value\r
+ *\r
+ * @param control Control value\r
+ *\r
+ * Set the control register\r
+ */\r
+extern void __set_CONTROL(uint32_t control);\r
+\r
+#else /* (__ARMCC_VERSION >= 400000) */\r
+\r
+/**\r
+ * @brief Remove the exclusive lock created by ldrex\r
+ *\r
+ * Removes the exclusive lock which is created by ldrex.\r
+ */\r
+#define __CLREX __clrex\r
+\r
+/**\r
+ * @brief Return the Base Priority value\r
+ *\r
+ * @return BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+static __INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ return(__regBasePri);\r
+}\r
+\r
+/**\r
+ * @brief Set the Base Priority value\r
+ *\r
+ * @param basePri BasePriority\r
+ *\r
+ * Set the base priority register\r
+ */\r
+static __INLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ __regBasePri = (basePri & 0xff);\r
+}\r
+\r
+/**\r
+ * @brief Return the Priority Mask value\r
+ *\r
+ * @return PriMask\r
+ *\r
+ * Return state of the priority mask bit from the priority mask register\r
+ */\r
+static __INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ return(__regPriMask);\r
+}\r
+\r
+/**\r
+ * @brief Set the Priority Mask value\r
+ *\r
+ * @param priMask PriMask\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+static __INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ __regPriMask = (priMask);\r
+}\r
+\r
+/**\r
+ * @brief Return the Fault Mask value\r
+ *\r
+ * @return FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+static __INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ return(__regFaultMask);\r
+}\r
+\r
+/**\r
+ * @brief Set the Fault Mask value\r
+ *\r
+ * @param faultMask faultMask value\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+static __INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ __regFaultMask = (faultMask & 1);\r
+}\r
+\r
+/**\r
+ * @brief Return the Control Register value\r
+ * \r
+ * @return Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+static __INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ return(__regControl);\r
+}\r
+\r
+/**\r
+ * @brief Set the Control Register value\r
+ *\r
+ * @param control Control value\r
+ *\r
+ * Set the control register\r
+ */\r
+static __INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ __regControl = control;\r
+}\r
+\r
+#endif /* __ARMCC_VERSION */ \r
+\r
+\r
+\r
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+#define __enable_irq __enable_interrupt /*!< global Interrupt enable */\r
+#define __disable_irq __disable_interrupt /*!< global Interrupt disable */\r
+\r
+static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }\r
+static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }\r
+\r
+#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ \r
+static __INLINE void __WFI() { __ASM ("wfi"); }\r
+static __INLINE void __WFE() { __ASM ("wfe"); }\r
+static __INLINE void __SEV() { __ASM ("sev"); }\r
+static __INLINE void __CLREX() { __ASM ("clrex"); }\r
+\r
+/* intrinsic void __ISB(void) */\r
+/* intrinsic void __DSB(void) */\r
+/* intrinsic void __DMB(void) */\r
+/* intrinsic void __set_PRIMASK(); */\r
+/* intrinsic void __get_PRIMASK(); */\r
+/* intrinsic void __set_FAULTMASK(); */\r
+/* intrinsic void __get_FAULTMASK(); */\r
+/* intrinsic uint32_t __REV(uint32_t value); */\r
+/* intrinsic uint32_t __REVSH(uint32_t value); */\r
+/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */\r
+/* intrinsic unsigned long __LDREX(unsigned long *); */\r
+\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+extern uint32_t __get_PSP(void);\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param topOfProcStack Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+extern void __set_PSP(uint32_t topOfProcStack);\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+extern uint32_t __get_MSP(void);\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param topOfMainStack Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+extern void __set_MSP(uint32_t topOfMainStack);\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+extern uint32_t __REV16(uint16_t value);\r
+\r
+/**\r
+ * @brief Reverse bit order of value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+extern uint32_t __RBIT(uint32_t value);\r
+\r
+/**\r
+ * @brief LDR Exclusive (8 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 8 bit values)\r
+ */\r
+extern uint8_t __LDREXB(uint8_t *addr);\r
+\r
+/**\r
+ * @brief LDR Exclusive (16 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 16 bit values\r
+ */\r
+extern uint16_t __LDREXH(uint16_t *addr);\r
+\r
+/**\r
+ * @brief LDR Exclusive (32 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 32 bit values\r
+ */\r
+extern uint32_t __LDREXW(uint32_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive (8 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 8 bit values\r
+ */\r
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive (16 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 16 bit values\r
+ */\r
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive (32 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 32 bit values\r
+ */\r
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
+\r
+\r
+\r
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }\r
+static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }\r
+\r
+static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }\r
+static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }\r
+\r
+static __INLINE void __NOP() { __ASM volatile ("nop"); }\r
+static __INLINE void __WFI() { __ASM volatile ("wfi"); }\r
+static __INLINE void __WFE() { __ASM volatile ("wfe"); }\r
+static __INLINE void __SEV() { __ASM volatile ("sev"); }\r
+static __INLINE void __ISB() { __ASM volatile ("isb"); }\r
+static __INLINE void __DSB() { __ASM volatile ("dsb"); }\r
+static __INLINE void __DMB() { __ASM volatile ("dmb"); }\r
+static __INLINE void __CLREX() { __ASM volatile ("clrex"); }\r
+\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+extern uint32_t __get_PSP(void);\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param topOfProcStack Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+extern void __set_PSP(uint32_t topOfProcStack);\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+extern uint32_t __get_MSP(void);\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param topOfMainStack Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+extern void __set_MSP(uint32_t topOfMainStack);\r
+\r
+/**\r
+ * @brief Return the Base Priority value\r
+ *\r
+ * @return BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+extern uint32_t __get_BASEPRI(void);\r
+\r
+/**\r
+ * @brief Set the Base Priority value\r
+ *\r
+ * @param basePri BasePriority\r
+ *\r
+ * Set the base priority register\r
+ */\r
+extern void __set_BASEPRI(uint32_t basePri);\r
+\r
+/**\r
+ * @brief Return the Priority Mask value\r
+ *\r
+ * @return PriMask\r
+ *\r
+ * Return state of the priority mask bit from the priority mask register\r
+ */\r
+extern uint32_t __get_PRIMASK(void);\r
+\r
+/**\r
+ * @brief Set the Priority Mask value\r
+ *\r
+ * @param priMask PriMask\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+extern void __set_PRIMASK(uint32_t priMask);\r
+\r
+/**\r
+ * @brief Return the Fault Mask value\r
+ *\r
+ * @return FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+extern uint32_t __get_FAULTMASK(void);\r
+\r
+/**\r
+ * @brief Set the Fault Mask value\r
+ *\r
+ * @param faultMask faultMask value\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+extern void __set_FAULTMASK(uint32_t faultMask);\r
+\r
+/**\r
+ * @brief Return the Control Register value\r
+* \r
+* @return Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+extern uint32_t __get_CONTROL(void);\r
+\r
+/**\r
+ * @brief Set the Control Register value\r
+ *\r
+ * @param control Control value\r
+ *\r
+ * Set the control register\r
+ */\r
+extern void __set_CONTROL(uint32_t control);\r
+\r
+/**\r
+ * @brief Reverse byte order in integer value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in integer value\r
+ */\r
+extern uint32_t __REV(uint32_t value);\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+extern uint32_t __REV16(uint16_t value);\r
+\r
+/**\r
+ * @brief Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+extern int32_t __REVSH(int16_t value);\r
+\r
+/**\r
+ * @brief Reverse bit order of value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+extern uint32_t __RBIT(uint32_t value);\r
+\r
+/**\r
+ * @brief LDR Exclusive (8 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 8 bit value\r
+ */\r
+extern uint8_t __LDREXB(uint8_t *addr);\r
+\r
+/**\r
+ * @brief LDR Exclusive (16 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 16 bit values\r
+ */\r
+extern uint16_t __LDREXH(uint16_t *addr);\r
+\r
+/**\r
+ * @brief LDR Exclusive (32 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 32 bit values\r
+ */\r
+extern uint32_t __LDREXW(uint32_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive (8 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 8 bit values\r
+ */\r
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive (16 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 16 bit values\r
+ */\r
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive (32 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 32 bit values\r
+ */\r
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
+\r
+\r
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all instrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface\r
+ Core Function Interface containing:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Reset Functions\r
+*/\r
+/*@{*/\r
+\r
+/* ########################## NVIC functions #################################### */\r
+\r
+/**\r
+ * @brief Set the Priority Grouping in NVIC Interrupt Controller\r
+ *\r
+ * @param PriorityGroup is priority grouping field\r
+ *\r
+ * Set the priority grouping field using the required unlock sequence.\r
+ * The parameter priority_grouping is assigned to the field \r
+ * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.\r
+ * In case of a conflict between priority grouping and available\r
+ * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ */\r
+static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ \r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ (0x5FA << SCB_AIRCR_VECTKEY_Pos) | \r
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+/**\r
+ * @brief Get the Priority Grouping from NVIC Interrupt Controller\r
+ *\r
+ * @return priority grouping field \r
+ *\r
+ * Get the priority grouping from NVIC Interrupt Controller.\r
+ * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.\r
+ */\r
+static __INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */\r
+}\r
+\r
+/**\r
+ * @brief Enable Interrupt in NVIC Interrupt Controller\r
+ *\r
+ * @param IRQn The positive number of the external interrupt to enable\r
+ *\r
+ * Enable a device specific interupt in the NVIC interrupt controller.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */\r
+}\r
+\r
+/**\r
+ * @brief Disable the interrupt line for external interrupt specified\r
+ * \r
+ * @param IRQn The positive number of the external interrupt to disable\r
+ * \r
+ * Disable a device specific interupt in the NVIC interrupt controller.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
+}\r
+\r
+/**\r
+ * @brief Read the interrupt pending bit for a device specific interrupt source\r
+ * \r
+ * @param IRQn The number of the device specifc interrupt\r
+ * @return 1 = interrupt pending, 0 = interrupt not pending\r
+ *\r
+ * Read the pending register in NVIC and return 1 if its status is pending, \r
+ * otherwise it returns 0\r
+ */\r
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
+}\r
+\r
+/**\r
+ * @brief Set the pending bit for an external interrupt\r
+ * \r
+ * @param IRQn The number of the interrupt for set pending\r
+ *\r
+ * Set the pending bit for the specified interrupt.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
+}\r
+\r
+/**\r
+ * @brief Clear the pending bit for an external interrupt\r
+ *\r
+ * @param IRQn The number of the interrupt for clear pending\r
+ *\r
+ * Clear the pending bit for the specified interrupt. \r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+/**\r
+ * @brief Read the active bit for an external interrupt\r
+ *\r
+ * @param IRQn The number of the interrupt for read active bit\r
+ * @return 1 = interrupt active, 0 = interrupt not active\r
+ *\r
+ * Read the active register in NVIC and returns 1 if its status is active, \r
+ * otherwise it returns 0.\r
+ */\r
+static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
+}\r
+\r
+/**\r
+ * @brief Set the priority for an interrupt\r
+ *\r
+ * @param IRQn The number of the interrupt for set priority\r
+ * @param priority The priority to set\r
+ *\r
+ * Set the priority for the specified interrupt. The interrupt \r
+ * number can be positive to specify an external (device specific) \r
+ * interrupt, or negative to specify an internal (core) interrupt.\r
+ *\r
+ * Note: The priority cannot be set for every core interrupt.\r
+ */\r
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if(IRQn < 0) {\r
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */\r
+ else {\r
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
+}\r
+\r
+/**\r
+ * @brief Read the priority for an interrupt\r
+ *\r
+ * @param IRQn The number of the interrupt for get priority\r
+ * @return The priority for the interrupt\r
+ *\r
+ * Read the priority for the specified interrupt. The interrupt \r
+ * number can be positive to specify an external (device specific) \r
+ * interrupt, or negative to specify an internal (core) interrupt.\r
+ *\r
+ * The returned priority value is automatically aligned to the implemented\r
+ * priority bits of the microcontroller.\r
+ *\r
+ * Note: The priority cannot be set for every core interrupt.\r
+ */\r
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if(IRQn < 0) {\r
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */\r
+ else {\r
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+}\r
+\r
+\r
+/**\r
+ * @brief Encode the priority for an interrupt\r
+ *\r
+ * @param PriorityGroup The used priority group\r
+ * @param PreemptPriority The preemptive priority value (starting from 0)\r
+ * @param SubPriority The sub priority value (starting from 0)\r
+ * @return The encoded priority for the interrupt\r
+ *\r
+ * Encode the priority for an interrupt with the given priority group,\r
+ * preemptive priority value and sub priority value.\r
+ * In case of a conflict between priority grouping and available\r
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+ *\r
+ * The returned priority value can be used for NVIC_SetPriority(...) function\r
+ */\r
+static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+ \r
+ return (\r
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ * @brief Decode the priority of an interrupt\r
+ *\r
+ * @param Priority The priority for the interrupt\r
+ * @param PriorityGroup The used priority group\r
+ * @param pPreemptPriority The preemptive priority value (starting from 0)\r
+ * @param pSubPriority The sub priority value (starting from 0)\r
+ *\r
+ * Decode an interrupt priority value with the given priority group to \r
+ * preemptive priority value and sub priority value.\r
+ * In case of a conflict between priority grouping and available\r
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+ *\r
+ * The priority value can be retrieved with NVIC_GetPriority(...) function\r
+ */\r
+static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+ \r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
+}\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+\r
+#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)\r
+\r
+/**\r
+ * @brief Initialize and start the SysTick counter and its interrupt.\r
+ *\r
+ * @param ticks number of ticks between two interrupts\r
+ * @return 1 = failed, 0 = successful\r
+ *\r
+ * Initialise the system tick timer and its interrupt and start the\r
+ * system tick timer / counter in free running mode to generate \r
+ * periodical interrupts.\r
+ */\r
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{ \r
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+ \r
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | \r
+ SysTick_CTRL_TICKINT_Msk | \r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+\r
+\r
+\r
+/* ################################## Reset function ############################################ */\r
+\r
+/**\r
+ * @brief Initiate a system reset request.\r
+ *\r
+ * Initiate a system reset request to reset the MCU\r
+ */\r
+static __INLINE void NVIC_SystemReset(void)\r
+{\r
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | \r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | \r
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */ \r
+ while(1); /* wait until reset */\r
+}\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+\r
+/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface\r
+ Core Debug Interface containing:\r
+ - Core Debug Receive / Transmit Functions\r
+ - Core Debug Defines\r
+ - Core Debug Variables\r
+*/\r
+/*@{*/\r
+\r
+extern volatile int ITM_RxBuffer; /*!< variable to receive characters */\r
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */\r
+\r
+\r
+/**\r
+ * @brief Outputs a character via the ITM channel 0\r
+ *\r
+ * @param ch character to output\r
+ * @return character to output\r
+ *\r
+ * The function outputs a character via the ITM channel 0. \r
+ * The function returns when no debugger is connected that has booked the output. \r
+ * It is blocking when a debugger is connected, but the previous character send is not transmitted. \r
+ */\r
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */\r
+ (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */\r
+ (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0].u32 == 0);\r
+ ITM->PORT[0].u8 = (uint8_t) ch;\r
+ } \r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Inputs a character via variable ITM_RxBuffer\r
+ *\r
+ * @return received character, -1 = no character received\r
+ *\r
+ * The function inputs a character via variable ITM_RxBuffer. \r
+ * The function returns when no debugger is connected that has booked the output. \r
+ * It is blocking when a debugger is connected, but the previous character send is not transmitted. \r
+ */\r
+static __INLINE int ITM_ReceiveChar (void) {\r
+ int ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+ \r
+ return (ch); \r
+}\r
+\r
+\r
+/**\r
+ * @brief Check if a character via variable ITM_RxBuffer is available\r
+ *\r
+ * @return 1 = character available, 0 = no character available\r
+ *\r
+ * The function checks variable ITM_RxBuffer whether a character is available or not. \r
+ * The function returns '1' if a character is available and '0' if no character is available. \r
+ */\r
+static __INLINE int ITM_CheckChar (void) {\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {\r
+ return (0); /* no character available */\r
+ } else {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_core_definitions */\r
+\r
+#endif /* __CM3_CORE_H__ */\r
+\r
+/*lint -restore */\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. \r
+ * This file contains all the peripheral register's definitions, bits \r
+ * definitions and memory mapping for STM32L1xx devices. \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32l1xx\r
+ * @{\r
+ */\r
+ \r
+#ifndef __STM32L1XX_H\r
+#define __STM32L1XX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+#define assert_param(__p)\r
+ \r
+/** @addtogroup Library_configuration_section\r
+ * @{\r
+ */\r
+ \r
+/* Uncomment the line below according to the target STM32L device used in your \r
+ application \r
+ */\r
+\r
+#if !defined (STM32L1XX_MD)\r
+ #define STM32L1XX_MD /*!< STM32L1XX_MD: STM32L Ultra Low Power Medium-density devices */\r
+#endif\r
+/* Tip: To avoid modifying this file each time you need to switch between these\r
+ devices, you can define the device in your toolchain compiler preprocessor.\r
+\r
+ - Ultra Low Power Medium-density devices are STM32L151xx and STM32L152xx \r
+ microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.\r
+\r
+ */\r
+\r
+#if !defined (STM32L1XX_MD)\r
+ #error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)"\r
+#endif\r
+\r
+#if !defined USE_STDPERIPH_DRIVER\r
+/**\r
+ * @brief Comment the line below if you will not use the peripherals drivers.\r
+ In this case, these drivers will not be included and the application code will \r
+ be based on direct access to peripherals registers \r
+ */\r
+ /*#define USE_STDPERIPH_DRIVER*/\r
+#endif\r
+\r
+/**\r
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)\r
+ used in your application \r
+ \r
+ Tip: To avoid modifying this file each time you need to use different HSE, you\r
+ can define the HSE value in your toolchain compiler preprocessor.\r
+ */ \r
+#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/\r
+\r
+/**\r
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup \r
+ Timeout value \r
+ */\r
+#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */\r
+\r
+/**\r
+ * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup \r
+ Timeout value \r
+ */\r
+#define HSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSI start up */\r
+\r
+#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal High Speed oscillator in Hz.\r
+ The real value may vary depending on the variations\r
+ in voltage and temperature. */\r
+#define LSI_VALUE ((uint32_t)37000) /*!< Value of the Internal Low Speed oscillator in Hz\r
+ The real value may vary depending on the variations\r
+ in voltage and temperature. */\r
+#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */\r
+\r
+/**\r
+ * @brief STM32L1xx Standard Peripheral Library version number\r
+ */\r
+#define __STM32L1XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ \r
+#define __STM32L1XX_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */\r
+#define __STM32L1XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */\r
+#define __STM32L1XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ \r
+#define __STM32L1XX_STDPERIPH_VERSION ( (__STM32L1XX_STDPERIPH_VERSION_MAIN << 24)\\r
+ |(__STM32L1XX_STDPERIPH_VERSION_SUB1 << 16)\\r
+ |(__STM32L1XX_STDPERIPH_VERSION_SUB2 << 8)\\r
+ |(__STM32L1XX_STDPERIPH_VERSION_RC))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Configuration_section_for_CMSIS\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief STM32L1xx Interrupt Number Definition, according to the selected device \r
+ * in @ref Library_configuration_section \r
+ */\r
+#define __MPU_PRESENT 1 /*!< STM32L provides MPU */\r
+#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
+\r
+/*!< Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M3 Processor Exceptions Numbers ******************************************************/\r
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
+\r
+/****** STM32L specific Interrupt Numbers ***********************************************************/\r
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */\r
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */\r
+ TAMPER_STAMP_IRQn = 2, /*!< Tamper and Time Stamp through EXTI Line Interrupts */\r
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */\r
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */\r
+ RCC_IRQn = 5, /*!< RCC global Interrupt */\r
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */\r
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */\r
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */\r
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */\r
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */\r
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */\r
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */\r
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */\r
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */\r
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */\r
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */\r
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */\r
+ ADC1_IRQn = 18, /*!< ADC1 global Interrupt */\r
+ USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */\r
+ USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */\r
+ DAC_IRQn = 21, /*!< DAC Interrupt */\r
+ COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */\r
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
+ LCD_IRQn = 24, /*!< LCD Interrupt */\r
+ TIM9_IRQn = 25, /*!< TIM9 global Interrupt */\r
+ TIM10_IRQn = 26, /*!< TIM10 global Interrupt */\r
+ TIM11_IRQn = 27, /*!< TIM11 global Interrupt */\r
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */\r
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */\r
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */\r
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */\r
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */\r
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */\r
+ USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */\r
+ TIM6_IRQn = 43, /*!< TIM6 global Interrupt */\r
+ TIM7_IRQn = 44 /*!< TIM7 global Interrupt */\r
+} IRQn_Type;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#include "core_cm3.h"\r
+#include "system_stm32l1xx.h"\r
+#include <stdint.h>\r
+\r
+/** @addtogroup Exported_types\r
+ * @{\r
+ */ \r
+\r
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;\r
+\r
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;\r
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))\r
+\r
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;\r
+\r
+/** \r
+ * @brief __RAM_FUNC definition \r
+ */ \r
+#if defined ( __CC_ARM )\r
+/* ARM Compiler\r
+ ------------\r
+ RAM functions are defined using the toolchain options. \r
+ Functions that are executed in RAM should reside in a separate source \r
+ module. Using the 'Options for File' dialog you can simply change the \r
+ 'Code / Const' area of a module to a memory space in physical RAM.\r
+ Available memory areas are declared in the 'Target' tab of the \r
+ 'Options for Target' dialog. \r
+*/\r
+ #define __RAM_FUNC FLASH_Status \r
+\r
+#elif defined ( __ICCARM__ )\r
+/* ICCARM Compiler\r
+ ---------------\r
+ RAM functions are defined using a specific toolchain keyword "__ramfunc". \r
+*/\r
+ #define __RAM_FUNC __ramfunc FLASH_Status\r
+\r
+#elif defined ( __GNUC__ )\r
+/* GNU Compiler\r
+ ------------\r
+ RAM functions are defined using a specific toolchain attribute \r
+ "__attribute__((section(".data")))". \r
+*/\r
+ #define __RAM_FUNC FLASH_Status __attribute__((section(".data")))\r
+\r
+#elif defined ( __TASKING__ )\r
+/* TASKING Compiler\r
+ ----------------\r
+ RAM functions are defined using a specific toolchain pragma. This pragma is \r
+ defined in the stm32l1xx_flash_ramfunc.c \r
+*/\r
+ #define __RAM_FUNC FLASH_Status\r
+\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Peripheral_registers_structures\r
+ * @{\r
+ */ \r
+\r
+/** \r
+ * @brief Analog to Digital Converter \r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t SR;\r
+ __IO uint32_t CR1;\r
+ __IO uint32_t CR2;\r
+ __IO uint32_t SMPR1;\r
+ __IO uint32_t SMPR2;\r
+ __IO uint32_t SMPR3;\r
+ __IO uint32_t JOFR1;\r
+ __IO uint32_t JOFR2;\r
+ __IO uint32_t JOFR3;\r
+ __IO uint32_t JOFR4;\r
+ __IO uint32_t HTR;\r
+ __IO uint32_t LTR;\r
+ __IO uint32_t SQR1;\r
+ __IO uint32_t SQR2;\r
+ __IO uint32_t SQR3;\r
+ __IO uint32_t SQR4;\r
+ __IO uint32_t SQR5;\r
+ __IO uint32_t JSQR;\r
+ __IO uint32_t JDR1;\r
+ __IO uint32_t JDR2;\r
+ __IO uint32_t JDR3;\r
+ __IO uint32_t JDR4;\r
+ __IO uint32_t DR;\r
+} ADC_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CSR;\r
+ __IO uint32_t CCR;\r
+} ADC_Common_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief Comparator \r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CSR;\r
+} COMP_TypeDef;\r
+\r
+/** \r
+ * @brief CRC calculation unit \r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t DR;\r
+ __IO uint8_t IDR;\r
+ uint8_t RESERVED0;\r
+ uint16_t RESERVED1;\r
+ __IO uint32_t CR;\r
+} CRC_TypeDef;\r
+\r
+/** \r
+ * @brief Digital to Analog Converter\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR;\r
+ __IO uint32_t SWTRIGR;\r
+ __IO uint32_t DHR12R1;\r
+ __IO uint32_t DHR12L1;\r
+ __IO uint32_t DHR8R1;\r
+ __IO uint32_t DHR12R2;\r
+ __IO uint32_t DHR12L2;\r
+ __IO uint32_t DHR8R2;\r
+ __IO uint32_t DHR12RD;\r
+ __IO uint32_t DHR12LD;\r
+ __IO uint32_t DHR8RD;\r
+ __IO uint32_t DOR1;\r
+ __IO uint32_t DOR2;\r
+ __IO uint32_t SR; \r
+} DAC_TypeDef;\r
+\r
+/** \r
+ * @brief Debug MCU\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t IDCODE;\r
+ __IO uint32_t CR;\r
+ __IO uint32_t APB1FZ;\r
+ __IO uint32_t APB2FZ; \r
+}DBGMCU_TypeDef;\r
+\r
+/** \r
+ * @brief DMA Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CCR;\r
+ __IO uint32_t CNDTR;\r
+ __IO uint32_t CPAR;\r
+ __IO uint32_t CMAR;\r
+} DMA_Channel_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t ISR;\r
+ __IO uint32_t IFCR;\r
+} DMA_TypeDef;\r
+\r
+/** \r
+ * @brief External Interrupt/Event Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t IMR;\r
+ __IO uint32_t EMR;\r
+ __IO uint32_t RTSR;\r
+ __IO uint32_t FTSR;\r
+ __IO uint32_t SWIER;\r
+ __IO uint32_t PR;\r
+} EXTI_TypeDef;\r
+\r
+/** \r
+ * @brief FLASH Registers\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t ACR;\r
+ __IO uint32_t PECR;\r
+ __IO uint32_t PDKEYR;\r
+ __IO uint32_t PEKEYR;\r
+ __IO uint32_t PRGKEYR;\r
+ __IO uint32_t OPTKEYR;\r
+ __IO uint32_t SR;\r
+ __IO uint32_t OBR;\r
+ __IO uint32_t WRPR; \r
+} FLASH_TypeDef;\r
+\r
+/** \r
+ * @brief Option Bytes Registers\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t RDP;\r
+ __IO uint32_t USER;\r
+ __IO uint32_t WRP01;\r
+ __IO uint32_t WRP23;\r
+} OB_TypeDef;\r
+\r
+/** \r
+ * @brief General Purpose IO\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t MODER;\r
+ __IO uint16_t OTYPER;\r
+ uint16_t RESERVED0;\r
+ __IO uint32_t OSPEEDR;\r
+ __IO uint32_t PUPDR;\r
+ __IO uint16_t IDR;\r
+ uint16_t RESERVED1;\r
+ __IO uint16_t ODR;\r
+ uint16_t RESERVED2;\r
+ __IO uint16_t BSRRL; /* BSRR register is split to 2 * 16-bit fields BSRRL */\r
+ __IO uint16_t BSRRH; /* BSRR register is split to 2 * 16-bit fields BSRRH */\r
+ __IO uint32_t LCKR;\r
+ __IO uint32_t AFR[2];\r
+} GPIO_TypeDef;\r
+\r
+/** \r
+ * @brief SysTem Configuration\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t MEMRMP;\r
+ __IO uint32_t PMC;\r
+ __IO uint32_t EXTICR[4];\r
+} SYSCFG_TypeDef;\r
+\r
+/** \r
+ * @brief Inter-integrated Circuit Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint16_t CR1;\r
+ uint16_t RESERVED0;\r
+ __IO uint16_t CR2;\r
+ uint16_t RESERVED1;\r
+ __IO uint16_t OAR1;\r
+ uint16_t RESERVED2;\r
+ __IO uint16_t OAR2;\r
+ uint16_t RESERVED3;\r
+ __IO uint16_t DR;\r
+ uint16_t RESERVED4;\r
+ __IO uint16_t SR1;\r
+ uint16_t RESERVED5;\r
+ __IO uint16_t SR2;\r
+ uint16_t RESERVED6;\r
+ __IO uint16_t CCR;\r
+ uint16_t RESERVED7;\r
+ __IO uint16_t TRISE;\r
+ uint16_t RESERVED8;\r
+} I2C_TypeDef;\r
+\r
+/** \r
+ * @brief Independent WATCHDOG\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t KR;\r
+ __IO uint32_t PR;\r
+ __IO uint32_t RLR;\r
+ __IO uint32_t SR;\r
+} IWDG_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief LCD\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR;\r
+ __IO uint32_t FCR;\r
+ __IO uint32_t SR;\r
+ __IO uint32_t CLR;\r
+ uint32_t RESERVED;\r
+ __IO uint32_t RAM[16];\r
+} LCD_TypeDef;\r
+\r
+/** \r
+ * @brief Power Control\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR;\r
+ __IO uint32_t CSR;\r
+} PWR_TypeDef;\r
+\r
+/** \r
+ * @brief Reset and Clock Control\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR;\r
+ __IO uint32_t ICSCR;\r
+ __IO uint32_t CFGR;\r
+ __IO uint32_t CIR;\r
+ __IO uint32_t AHBRSTR;\r
+ __IO uint32_t APB2RSTR;\r
+ __IO uint32_t APB1RSTR;\r
+ __IO uint32_t AHBENR;\r
+ __IO uint32_t APB2ENR;\r
+ __IO uint32_t APB1ENR;\r
+ __IO uint32_t AHBLPENR;\r
+ __IO uint32_t APB2LPENR;\r
+ __IO uint32_t APB1LPENR; \r
+ __IO uint32_t CSR; \r
+} RCC_TypeDef;\r
+\r
+/** \r
+ * @brief Routing Interface \r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t ICR;\r
+ __IO uint32_t ASCR1;\r
+ __IO uint32_t ASCR2;\r
+ __IO uint32_t HYSCR1;\r
+ __IO uint32_t HYSCR2;\r
+ __IO uint32_t HYSCR3;\r
+} RI_TypeDef;\r
+\r
+/** \r
+ * @brief Real-Time Clock\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t TR;\r
+ __IO uint32_t DR;\r
+ __IO uint32_t CR;\r
+ __IO uint32_t ISR;\r
+ __IO uint32_t PRER;\r
+ __IO uint32_t WUTR;\r
+ __IO uint32_t CALIBR;\r
+ __IO uint32_t ALRMAR;\r
+ __IO uint32_t ALRMBR;\r
+ __IO uint32_t WPR;\r
+ uint32_t RESERVED1;\r
+ uint32_t RESERVED2;\r
+ __IO uint32_t TSTR;\r
+ __IO uint32_t TSDR;\r
+ uint32_t RESERVED3;\r
+ uint32_t RESERVED4;\r
+ __IO uint32_t TAFCR;\r
+ uint32_t RESERVED5;\r
+ uint32_t RESERVED6;\r
+ uint32_t RESERVED7;\r
+ __IO uint32_t BKP0R;\r
+ __IO uint32_t BKP1R;\r
+ __IO uint32_t BKP2R;\r
+ __IO uint32_t BKP3R;\r
+ __IO uint32_t BKP4R;\r
+ __IO uint32_t BKP5R;\r
+ __IO uint32_t BKP6R;\r
+ __IO uint32_t BKP7R;\r
+ __IO uint32_t BKP8R;\r
+ __IO uint32_t BKP9R;\r
+ __IO uint32_t BKP10R;\r
+ __IO uint32_t BKP11R;\r
+ __IO uint32_t BKP12R;\r
+ __IO uint32_t BKP13R;\r
+ __IO uint32_t BKP14R;\r
+ __IO uint32_t BKP15R;\r
+ __IO uint32_t BKP16R;\r
+ __IO uint32_t BKP17R;\r
+ __IO uint32_t BKP18R;\r
+ __IO uint32_t BKP19R;\r
+} RTC_TypeDef;\r
+\r
+/** \r
+ * @brief Serial Peripheral Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint16_t CR1;\r
+ uint16_t RESERVED0;\r
+ __IO uint16_t CR2;\r
+ uint16_t RESERVED1;\r
+ __IO uint16_t SR;\r
+ uint16_t RESERVED2;\r
+ __IO uint16_t DR;\r
+ uint16_t RESERVED3;\r
+ __IO uint16_t CRCPR;\r
+ uint16_t RESERVED4;\r
+ __IO uint16_t RXCRCR;\r
+ uint16_t RESERVED5;\r
+ __IO uint16_t TXCRCR;\r
+ uint16_t RESERVED6; \r
+} SPI_TypeDef;\r
+\r
+/** \r
+ * @brief TIM\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint16_t CR1;\r
+ uint16_t RESERVED0;\r
+ __IO uint16_t CR2;\r
+ uint16_t RESERVED1;\r
+ __IO uint16_t SMCR;\r
+ uint16_t RESERVED2;\r
+ __IO uint16_t DIER;\r
+ uint16_t RESERVED3;\r
+ __IO uint16_t SR;\r
+ uint16_t RESERVED4;\r
+ __IO uint16_t EGR;\r
+ uint16_t RESERVED5;\r
+ __IO uint16_t CCMR1;\r
+ uint16_t RESERVED6;\r
+ __IO uint16_t CCMR2;\r
+ uint16_t RESERVED7;\r
+ __IO uint16_t CCER;\r
+ uint16_t RESERVED8;\r
+ __IO uint16_t CNT;\r
+ uint16_t RESERVED9;\r
+ __IO uint16_t PSC;\r
+ uint16_t RESERVED10;\r
+ __IO uint16_t ARR;\r
+ uint16_t RESERVED11;\r
+ uint32_t RESERVED12;\r
+ __IO uint16_t CCR1;\r
+ uint16_t RESERVED13;\r
+ __IO uint16_t CCR2;\r
+ uint16_t RESERVED14;\r
+ __IO uint16_t CCR3;\r
+ uint16_t RESERVED15;\r
+ __IO uint16_t CCR4;\r
+ uint16_t RESERVED16;\r
+ uint32_t RESERVED17;\r
+ __IO uint16_t DCR;\r
+ uint16_t RESERVED18;\r
+ __IO uint16_t DMAR;\r
+ uint16_t RESERVED19;\r
+ __IO uint16_t OR;\r
+ uint16_t RESERVED20;\r
+} TIM_TypeDef;\r
+\r
+/** \r
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint16_t SR;\r
+ uint16_t RESERVED0;\r
+ __IO uint16_t DR;\r
+ uint16_t RESERVED1;\r
+ __IO uint16_t BRR;\r
+ uint16_t RESERVED2;\r
+ __IO uint16_t CR1;\r
+ uint16_t RESERVED3;\r
+ __IO uint16_t CR2;\r
+ uint16_t RESERVED4;\r
+ __IO uint16_t CR3;\r
+ uint16_t RESERVED5;\r
+ __IO uint16_t GTPR;\r
+ uint16_t RESERVED6;\r
+} USART_TypeDef;\r
+\r
+/** \r
+ * @brief Window WATCHDOG\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR;\r
+ __IO uint32_t CFR;\r
+ __IO uint32_t SR;\r
+} WWDG_TypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @addtogroup Peripheral_memory_map\r
+ * @{\r
+ */\r
+\r
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */\r
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */\r
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */\r
+\r
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */\r
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */\r
+\r
+/*!< Peripheral memory map */\r
+#define APB1PERIPH_BASE PERIPH_BASE\r
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)\r
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)\r
+\r
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)\r
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)\r
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)\r
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)\r
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)\r
+#define LCD_BASE (APB1PERIPH_BASE + 0x2400)\r
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)\r
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)\r
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)\r
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)\r
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)\r
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)\r
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)\r
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)\r
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)\r
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)\r
+#define COMP_BASE (APB1PERIPH_BASE + 0x7C00)\r
+#define RI_BASE (APB1PERIPH_BASE + 0x7C04)\r
+\r
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000)\r
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)\r
+#define TIM9_BASE (APB2PERIPH_BASE + 0x0800)\r
+#define TIM10_BASE (APB2PERIPH_BASE + 0x0C00)\r
+#define TIM11_BASE (APB2PERIPH_BASE + 0x1000)\r
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)\r
+#define ADC_BASE (APB2PERIPH_BASE + 0x2700)\r
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)\r
+#define USART1_BASE (APB2PERIPH_BASE + 0x3800)\r
+\r
+#define GPIOA_BASE (AHBPERIPH_BASE + 0x0000)\r
+#define GPIOB_BASE (AHBPERIPH_BASE + 0x0400)\r
+#define GPIOC_BASE (AHBPERIPH_BASE + 0x0800)\r
+#define GPIOD_BASE (AHBPERIPH_BASE + 0x0C00)\r
+#define GPIOE_BASE (AHBPERIPH_BASE + 0x1000)\r
+#define GPIOH_BASE (AHBPERIPH_BASE + 0x1400)\r
+#define CRC_BASE (AHBPERIPH_BASE + 0x3000)\r
+#define RCC_BASE (AHBPERIPH_BASE + 0x3800)\r
+\r
+\r
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x3C00) /*!< FLASH registers base address */\r
+#define OB_BASE ((uint32_t)0x1FF80000) /*!< FLASH Option Bytes base address */\r
+\r
+#define DMA1_BASE (AHBPERIPH_BASE + 0x6000)\r
+#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008)\r
+#define DMA1_Channel2_BASE (DMA1_BASE + 0x001C)\r
+#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030)\r
+#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044)\r
+#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058)\r
+#define DMA1_Channel6_BASE (DMA1_BASE + 0x006C)\r
+#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080)\r
+\r
+\r
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @addtogroup Peripheral_declaration\r
+ * @{\r
+ */ \r
+\r
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)\r
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)\r
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)\r
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)\r
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)\r
+#define LCD ((LCD_TypeDef *) LCD_BASE)\r
+#define RTC ((RTC_TypeDef *) RTC_BASE)\r
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)\r
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)\r
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)\r
+#define USART2 ((USART_TypeDef *) USART2_BASE)\r
+#define USART3 ((USART_TypeDef *) USART3_BASE)\r
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)\r
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)\r
+#define PWR ((PWR_TypeDef *) PWR_BASE)\r
+#define DAC ((DAC_TypeDef *) DAC_BASE)\r
+#define COMP ((COMP_TypeDef *) COMP_BASE)\r
+#define RI ((RI_TypeDef *) RI_BASE)\r
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)\r
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)\r
+\r
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)\r
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)\r
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)\r
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)\r
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)\r
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)\r
+#define USART1 ((USART_TypeDef *) USART1_BASE)\r
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)\r
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)\r
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)\r
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)\r
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)\r
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)\r
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)\r
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)\r
+#define RCC ((RCC_TypeDef *) RCC_BASE)\r
+#define CRC ((CRC_TypeDef *) CRC_BASE)\r
+\r
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)\r
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)\r
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)\r
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)\r
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)\r
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)\r
+\r
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)\r
+#define OB ((OB_TypeDef *) OB_BASE) \r
+\r
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Exported_constants\r
+ * @{\r
+ */\r
+ \r
+ /** @addtogroup Peripheral_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+ \r
+/******************************************************************************/\r
+/* Peripheral Registers Bits Definition */\r
+/******************************************************************************/\r
+/******************************************************************************/\r
+/* */\r
+/* Analog to Digital Converter (ADC) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************** Bit definition for ADC_SR register ********************/\r
+#define ADC_SR_AWD ((uint32_t)0x00000001) /*!< Analog watchdog flag */\r
+#define ADC_SR_EOC ((uint32_t)0x00000002) /*!< End of conversion */\r
+#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!< Injected channel end of conversion */\r
+#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!< Injected channel Start flag */\r
+#define ADC_SR_STRT ((uint32_t)0x00000010) /*!< Regular channel Start flag */\r
+#define ADC_SR_OVR ((uint32_t)0x00000020) /*!< Overrun flag */\r
+#define ADC_SR_ADONS ((uint32_t)0x00000040) /*!< ADC ON status */\r
+#define ADC_SR_RCNR ((uint32_t)0x00000100) /*!< Regular channel not ready flag */\r
+#define ADC_SR_JCNR ((uint32_t)0x00000200) /*!< Injected channel not ready flag */\r
+\r
+/******************* Bit definition for ADC_CR1 register ********************/\r
+#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */\r
+#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
+\r
+#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */\r
+#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */\r
+#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */\r
+#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */\r
+#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */\r
+#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */\r
+#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */\r
+#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */\r
+\r
+#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */\r
+#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */\r
+#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */\r
+#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */\r
+\r
+#define ADC_CR1_PDD ((uint32_t)0x00010000) /*!< Power Down during Delay phase */\r
+#define ADC_CR1_PDI ((uint32_t)0x00020000) /*!< Power Down during Idle phase */\r
+\r
+#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */\r
+#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */\r
+\r
+#define ADC_CR1_RES ((uint32_t)0x03000000) /*!< RES[1:0] bits (Resolution) */\r
+#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
+#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
+\r
+#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!< Overrun interrupt enable */\r
+ \r
+/******************* Bit definition for ADC_CR2 register ********************/\r
+#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */\r
+#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */\r
+\r
+#define ADC_CR2_DELS ((uint32_t)0x00000070) /*!< DELS[2:0] bits (Delay selection) */\r
+#define ADC_CR2_DELS_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
+#define ADC_CR2_DELS_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
+#define ADC_CR2_DELS_2 ((uint32_t)0x00000040) /*!< Bit 2 */\r
+\r
+#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */\r
+#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!< DMA disable selection (Single ADC) */\r
+#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!< End of conversion selection */\r
+#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */\r
+\r
+#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!< JEXTSEL[3:0] bits (External event select for injected group) */\r
+#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
+#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!< Bit 2 */\r
+#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!< Bit 3 */\r
+\r
+#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!< JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels) */\r
+#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */\r
+#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */\r
+\r
+#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!< Start Conversion of injected channels */\r
+\r
+#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!< EXTSEL[3:0] bits (External Event Select for regular group) */\r
+#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
+#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
+#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */\r
+#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!< Bit 3 */\r
+\r
+#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */\r
+#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!< Bit 0 */\r
+#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!< Bit 1 */\r
+\r
+#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!< Start Conversion of regular channels */\r
+\r
+/****************** Bit definition for ADC_SMPR1 register *******************/\r
+#define ADC_SMPR1_SMP20 ((uint32_t)0x00000007) /*!< SMP20[2:0] bits (Channel 20 Sample time selection) */\r
+#define ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR1_SMP21 ((uint32_t)0x00000038) /*!< SMP21[2:0] bits (Channel 21 Sample time selection) */\r
+#define ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008) /*!< Bit 0 */\r
+#define ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010) /*!< Bit 1 */\r
+#define ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR1_SMP22 ((uint32_t)0x000001C0) /*!< SMP22[2:0] bits (Channel 22 Sample time selection) */\r
+#define ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040) /*!< Bit 0 */\r
+#define ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080) /*!< Bit 1 */\r
+#define ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR1_SMP23 ((uint32_t)0x00000E00) /*!< SMP23[2:0] bits (Channel 23 Sample time selection) */\r
+#define ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200) /*!< Bit 0 */\r
+#define ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400) /*!< Bit 1 */\r
+#define ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR1_SMP24 ((uint32_t)0x00007000) /*!< SMP24[2:0] bits (Channel 24 Sample time selection) */\r
+#define ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000) /*!< Bit 0 */\r
+#define ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000) /*!< Bit 1 */\r
+#define ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR1_SMP25 ((uint32_t)0x00038000) /*!< SMP25[2:0] bits (Channel 25 Sample time selection) */\r
+#define ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000) /*!< Bit 0 */\r
+#define ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000) /*!< Bit 1 */\r
+#define ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000) /*!< Bit 2 */\r
+\r
+/****************** Bit definition for ADC_SMPR2 register *******************/\r
+#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */\r
+#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */\r
+#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */\r
+#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */\r
+#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */\r
+#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */\r
+#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */\r
+#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */\r
+#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */\r
+#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */\r
+#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */\r
+#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */\r
+#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */\r
+#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 5 Sample time selection) */\r
+#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */\r
+#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */\r
+#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */\r
+#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */\r
+#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */\r
+#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */\r
+#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */\r
+#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */\r
+#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< SMP18[2:0] bits (Channel 18 Sample time selection) */\r
+#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
+#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
+#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR2_SMP19 ((uint32_t)0x38000000) /*!< SMP19[2:0] bits (Channel 19 Sample time selection) */\r
+#define ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000) /*!< Bit 0 */\r
+#define ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000) /*!< Bit 1 */\r
+#define ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000) /*!< Bit 2 */\r
+\r
+/****************** Bit definition for ADC_SMPR3 register *******************/\r
+#define ADC_SMPR3_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */\r
+#define ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+ \r
+#define ADC_SMPR3_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */\r
+#define ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */\r
+#define ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */\r
+#define ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR3_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */\r
+#define ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */\r
+#define ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */\r
+#define ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR3_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */\r
+#define ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */\r
+#define ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */\r
+#define ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR3_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */\r
+#define ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */\r
+#define ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */\r
+#define ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR3_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */\r
+#define ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */\r
+#define ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */\r
+#define ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR3_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */\r
+#define ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */\r
+#define ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */\r
+#define ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR3_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */\r
+#define ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */\r
+#define ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */\r
+#define ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR3_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */\r
+#define ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
+#define ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
+#define ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR3_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */\r
+#define ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */\r
+#define ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */\r
+#define ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */\r
+\r
+\r
+/****************** Bit definition for ADC_JOFR1 register *******************/\r
+#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */\r
+\r
+/****************** Bit definition for ADC_JOFR2 register *******************/\r
+#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */\r
+\r
+/****************** Bit definition for ADC_JOFR3 register *******************/\r
+#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */\r
+\r
+/****************** Bit definition for ADC_JOFR4 register *******************/\r
+#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */\r
+\r
+/******************* Bit definition for ADC_HTR register ********************/\r
+#define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */\r
+\r
+/******************* Bit definition for ADC_LTR register ********************/\r
+#define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */\r
+\r
+/******************* Bit definition for ADC_SQR1 register *******************/\r
+#define ADC_SQR1_SQ25 ((uint32_t)0x0000001F) /*!< SQ25[4:0] bits (25th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ25_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define ADC_SQR1_SQ25_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define ADC_SQR1_SQ25_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define ADC_SQR1_SQ25_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+#define ADC_SQR1_SQ25_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
+\r
+#define ADC_SQR1_SQ26 ((uint32_t)0x000003E0) /*!< SQ26[4:0] bits (26th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ26_0 ((uint32_t)0x00000020) /*!< Bit 0 */\r
+#define ADC_SQR1_SQ26_1 ((uint32_t)0x00000040) /*!< Bit 1 */\r
+#define ADC_SQR1_SQ26_2 ((uint32_t)0x00000080) /*!< Bit 2 */\r
+#define ADC_SQR1_SQ26_3 ((uint32_t)0x00000100) /*!< Bit 3 */\r
+#define ADC_SQR1_SQ26_4 ((uint32_t)0x00000200) /*!< Bit 4 */\r
+\r
+#define ADC_SQR1_SQ27 ((uint32_t)0x00007C00) /*!< SQ27[4:0] bits (27th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ27_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define ADC_SQR1_SQ27_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define ADC_SQR1_SQ27_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define ADC_SQR1_SQ27_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define ADC_SQR1_SQ27_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */\r
+#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */\r
+#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */\r
+#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */\r
+#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */\r
+\r
+/******************* Bit definition for ADC_SQR2 register *******************/\r
+#define ADC_SQR2_SQ19 ((uint32_t)0x0000001F) /*!< SQ19[4:0] bits (19th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ19_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define ADC_SQR2_SQ19_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define ADC_SQR2_SQ19_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define ADC_SQR2_SQ19_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+#define ADC_SQR2_SQ19_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
+\r
+#define ADC_SQR2_SQ20 ((uint32_t)0x000003E0) /*!< SQ20[4:0] bits (20th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ20_0 ((uint32_t)0x00000020) /*!< Bit 0 */\r
+#define ADC_SQR2_SQ20_1 ((uint32_t)0x00000040) /*!< Bit 1 */\r
+#define ADC_SQR2_SQ20_2 ((uint32_t)0x00000080) /*!< Bit 2 */\r
+#define ADC_SQR2_SQ20_3 ((uint32_t)0x00000100) /*!< Bit 3 */\r
+#define ADC_SQR2_SQ20_4 ((uint32_t)0x00000200) /*!< Bit 4 */\r
+\r
+#define ADC_SQR2_SQ21 ((uint32_t)0x00007C00) /*!< SQ21[4:0] bits (21th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ21_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define ADC_SQR2_SQ21_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define ADC_SQR2_SQ21_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define ADC_SQR2_SQ21_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define ADC_SQR2_SQ21_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define ADC_SQR2_SQ22 ((uint32_t)0x000F8000) /*!< SQ22[4:0] bits (22th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ22_0 ((uint32_t)0x00008000) /*!< Bit 0 */\r
+#define ADC_SQR2_SQ22_1 ((uint32_t)0x00010000) /*!< Bit 1 */\r
+#define ADC_SQR2_SQ22_2 ((uint32_t)0x00020000) /*!< Bit 2 */\r
+#define ADC_SQR2_SQ22_3 ((uint32_t)0x00040000) /*!< Bit 3 */\r
+#define ADC_SQR2_SQ22_4 ((uint32_t)0x00080000) /*!< Bit 4 */\r
+\r
+#define ADC_SQR2_SQ23 ((uint32_t)0x01F00000) /*!< SQ23[4:0] bits (23th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ23_0 ((uint32_t)0x00100000) /*!< Bit 0 */\r
+#define ADC_SQR2_SQ23_1 ((uint32_t)0x00200000) /*!< Bit 1 */\r
+#define ADC_SQR2_SQ23_2 ((uint32_t)0x00400000) /*!< Bit 2 */\r
+#define ADC_SQR2_SQ23_3 ((uint32_t)0x00800000) /*!< Bit 3 */\r
+#define ADC_SQR2_SQ23_4 ((uint32_t)0x01000000) /*!< Bit 4 */\r
+\r
+#define ADC_SQR2_SQ24 ((uint32_t)0x3E000000) /*!< SQ24[4:0] bits (24th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ24_0 ((uint32_t)0x02000000) /*!< Bit 0 */\r
+#define ADC_SQR2_SQ24_1 ((uint32_t)0x04000000) /*!< Bit 1 */\r
+#define ADC_SQR2_SQ24_2 ((uint32_t)0x08000000) /*!< Bit 2 */\r
+#define ADC_SQR2_SQ24_3 ((uint32_t)0x10000000) /*!< Bit 3 */\r
+#define ADC_SQR2_SQ24_4 ((uint32_t)0x20000000) /*!< Bit 4 */\r
+\r
+/******************* Bit definition for ADC_SQR3 register *******************/\r
+#define ADC_SQR3_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define ADC_SQR3_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define ADC_SQR3_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define ADC_SQR3_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+#define ADC_SQR3_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
+\r
+#define ADC_SQR3_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */\r
+#define ADC_SQR3_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */\r
+#define ADC_SQR3_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */\r
+#define ADC_SQR3_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */\r
+#define ADC_SQR3_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */\r
+\r
+#define ADC_SQR3_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define ADC_SQR3_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define ADC_SQR3_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define ADC_SQR3_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define ADC_SQR3_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define ADC_SQR3_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */\r
+#define ADC_SQR3_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */\r
+#define ADC_SQR3_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */\r
+#define ADC_SQR3_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */\r
+#define ADC_SQR3_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */\r
+\r
+#define ADC_SQR3_SQ17 ((uint32_t)0x01F00000) /*!< SQ17[4:0] bits (17th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ17_0 ((uint32_t)0x00100000) /*!< Bit 0 */\r
+#define ADC_SQR3_SQ17_1 ((uint32_t)0x00200000) /*!< Bit 1 */\r
+#define ADC_SQR3_SQ17_2 ((uint32_t)0x00400000) /*!< Bit 2 */\r
+#define ADC_SQR3_SQ17_3 ((uint32_t)0x00800000) /*!< Bit 3 */\r
+#define ADC_SQR3_SQ17_4 ((uint32_t)0x01000000) /*!< Bit 4 */\r
+\r
+#define ADC_SQR3_SQ18 ((uint32_t)0x3E000000) /*!< SQ18[4:0] bits (18th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ18_0 ((uint32_t)0x02000000) /*!< Bit 0 */\r
+#define ADC_SQR3_SQ18_1 ((uint32_t)0x04000000) /*!< Bit 1 */\r
+#define ADC_SQR3_SQ18_2 ((uint32_t)0x08000000) /*!< Bit 2 */\r
+#define ADC_SQR3_SQ18_3 ((uint32_t)0x10000000) /*!< Bit 3 */\r
+#define ADC_SQR3_SQ18_4 ((uint32_t)0x20000000) /*!< Bit 4 */\r
+\r
+/******************* Bit definition for ADC_SQR4 register *******************/\r
+#define ADC_SQR4_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */\r
+#define ADC_SQR4_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define ADC_SQR4_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define ADC_SQR4_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define ADC_SQR4_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+#define ADC_SQR4_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
+\r
+#define ADC_SQR4_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */\r
+#define ADC_SQR4_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */\r
+#define ADC_SQR4_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */\r
+#define ADC_SQR4_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */\r
+#define ADC_SQR4_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */\r
+#define ADC_SQR4_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */\r
+\r
+#define ADC_SQR4_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */\r
+#define ADC_SQR4_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define ADC_SQR4_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define ADC_SQR4_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define ADC_SQR4_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define ADC_SQR4_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define ADC_SQR4_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */\r
+#define ADC_SQR4_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */\r
+#define ADC_SQR4_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */\r
+#define ADC_SQR4_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */\r
+#define ADC_SQR4_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */\r
+#define ADC_SQR4_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */\r
+\r
+#define ADC_SQR4_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */\r
+#define ADC_SQR4_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */\r
+#define ADC_SQR4_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */\r
+#define ADC_SQR4_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */\r
+#define ADC_SQR4_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */\r
+#define ADC_SQR4_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */\r
+\r
+#define ADC_SQR4_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */\r
+#define ADC_SQR4_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */\r
+#define ADC_SQR4_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */\r
+#define ADC_SQR4_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */\r
+#define ADC_SQR4_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */\r
+#define ADC_SQR4_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */\r
+\r
+/******************* Bit definition for ADC_SQR5 register *******************/\r
+#define ADC_SQR5_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */\r
+#define ADC_SQR5_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define ADC_SQR5_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define ADC_SQR5_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define ADC_SQR5_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+#define ADC_SQR5_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
+\r
+#define ADC_SQR5_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */\r
+#define ADC_SQR5_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */\r
+#define ADC_SQR5_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */\r
+#define ADC_SQR5_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */\r
+#define ADC_SQR5_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */\r
+#define ADC_SQR5_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */\r
+\r
+#define ADC_SQR5_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */\r
+#define ADC_SQR5_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define ADC_SQR5_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define ADC_SQR5_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define ADC_SQR5_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define ADC_SQR5_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define ADC_SQR5_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */\r
+#define ADC_SQR5_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */\r
+#define ADC_SQR5_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */\r
+#define ADC_SQR5_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */\r
+#define ADC_SQR5_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */\r
+#define ADC_SQR5_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */\r
+\r
+#define ADC_SQR5_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */\r
+#define ADC_SQR5_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */\r
+#define ADC_SQR5_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */\r
+#define ADC_SQR5_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */\r
+#define ADC_SQR5_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */\r
+#define ADC_SQR5_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */\r
+\r
+#define ADC_SQR5_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */\r
+#define ADC_SQR5_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */\r
+#define ADC_SQR5_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */\r
+#define ADC_SQR5_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */\r
+#define ADC_SQR5_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */\r
+#define ADC_SQR5_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */\r
+\r
+\r
+/******************* Bit definition for ADC_JSQR register *******************/\r
+#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */ \r
+#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
+\r
+#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */\r
+#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */\r
+#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */\r
+#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */\r
+#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */\r
+#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */\r
+\r
+#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */\r
+#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */\r
+#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */\r
+#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */\r
+#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */\r
+#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */\r
+#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */\r
+\r
+#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */\r
+#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */\r
+#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */\r
+\r
+/******************* Bit definition for ADC_JDR1 register *******************/\r
+#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */\r
+\r
+/******************* Bit definition for ADC_JDR2 register *******************/\r
+#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */\r
+\r
+/******************* Bit definition for ADC_JDR3 register *******************/\r
+#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */\r
+\r
+/******************* Bit definition for ADC_JDR4 register *******************/\r
+#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */\r
+\r
+/******************** Bit definition for ADC_DR register ********************/\r
+#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */\r
+\r
+\r
+/******************* Bit definition for ADC_CSR register ********************/\r
+#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!< ADC1 Analog watchdog flag */\r
+#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!< ADC1 End of conversion */\r
+#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!< ADC1 Injected channel end of conversion */\r
+#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!< ADC1 Injected channel Start flag */\r
+#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!< ADC1 Regular channel Start flag */\r
+#define ADC_CSR_OVR1 ((uint32_t)0x00000020) /*!< ADC1 overrun flag */\r
+#define ADC_CSR_ADONS1 ((uint32_t)0x00000040) /*!< ADON status of ADC1 */\r
+\r
+/******************* Bit definition for ADC_CCR register ********************/\r
+#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!< ADC prescaler*/\r
+#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!< Bit 1 */ \r
+#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Analog Comparators (COMP) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/****************** Bit definition for COMP_CSR register ********************/\r
+#define COMP_CSR_10KPU ((uint32_t)0x00000001) /*!< 10K pull-up resistor */\r
+#define COMP_CSR_400KPU ((uint32_t)0x00000002) /*!< 400K pull-up resistor */\r
+#define COMP_CSR_10KPD ((uint32_t)0x00000004) /*!< 10K pull-down resistor */\r
+#define COMP_CSR_400KPD ((uint32_t)0x00000008) /*!< 400K pull-down resistor */\r
+\r
+#define COMP_CSR_CMP1EN ((uint32_t)0x00000010) /*!< Comparator 1 enable */\r
+#define COMP_CSR_CMP1OUT ((uint32_t)0x00000080) /*!< Comparator 1 output */\r
+\r
+#define COMP_CSR_SPEED ((uint32_t)0x00001000) /*!< Comparator 2 speed */\r
+#define COMP_CSR_CMP2OUT ((uint32_t)0x00002000) /*!< Comparator 2 ouput */\r
+\r
+#define COMP_CSR_VREFOUTEN ((uint32_t)0x00010000) /*!< Comparator Vref Enable */\r
+#define COMP_CSR_WNDWE ((uint32_t)0x00020000) /*!< Window mode enable */\r
+\r
+#define COMP_CSR_INSEL ((uint32_t)0x001C0000) /*!< INSEL[2:0] Inversion input Selection */\r
+#define COMP_CSR_INSEL_0 ((uint32_t)0x00040000) /*!< Bit 0 */\r
+#define COMP_CSR_INSEL_1 ((uint32_t)0x00080000) /*!< Bit 1 */\r
+#define COMP_CSR_INSEL_2 ((uint32_t)0x00100000) /*!< Bit 2 */\r
+\r
+#define COMP_CSR_OUTSEL ((uint32_t)0x00E00000) /*!< OUTSEL[2:0] comparator 2 output redirection */\r
+#define COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000) /*!< Bit 0 */\r
+#define COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000) /*!< Bit 1 */\r
+#define COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000) /*!< Bit 2 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* CRC calculation unit (CRC) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for CRC_DR register *********************/\r
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */\r
+\r
+/******************* Bit definition for CRC_IDR register ********************/\r
+#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */\r
+\r
+/******************** Bit definition for CRC_CR register ********************/\r
+#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET bit */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Digital to Analog Converter (DAC) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************** Bit definition for DAC_CR register ********************/\r
+#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */\r
+#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */\r
+#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */\r
+\r
+#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */\r
+#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */\r
+#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */\r
+#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */\r
+\r
+#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */\r
+#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */\r
+#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */\r
+\r
+#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */\r
+#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+\r
+#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */\r
+#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */\r
+#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */\r
+#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */\r
+\r
+#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */\r
+#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */\r
+#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */\r
+#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */\r
+\r
+#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */\r
+#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */\r
+#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */\r
+\r
+#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */\r
+#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */\r
+\r
+/***************** Bit definition for DAC_SWTRIGR register ******************/\r
+#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!<DAC channel1 software trigger */\r
+#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!<DAC channel2 software trigger */\r
+\r
+/***************** Bit definition for DAC_DHR12R1 register ******************/\r
+#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12L1 register ******************/\r
+#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */\r
+\r
+/****************** Bit definition for DAC_DHR8R1 register ******************/\r
+#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12R2 register ******************/\r
+#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12L2 register ******************/\r
+#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */\r
+\r
+/****************** Bit definition for DAC_DHR8R2 register ******************/\r
+#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12RD register ******************/\r
+#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */\r
+#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12LD register ******************/\r
+#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */\r
+#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */\r
+\r
+/****************** Bit definition for DAC_DHR8RD register ******************/\r
+#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */\r
+#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */\r
+\r
+/******************* Bit definition for DAC_DOR1 register *******************/\r
+#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!<DAC channel1 data output */\r
+\r
+/******************* Bit definition for DAC_DOR2 register *******************/\r
+#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!<DAC channel2 data output */\r
+\r
+/******************** Bit definition for DAC_SR register ********************/\r
+#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */\r
+#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Debug MCU (DBGMCU) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/**************** Bit definition for DBGMCU_IDCODE register *****************/\r
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */\r
+\r
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */\r
+#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
+#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */\r
+#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */\r
+#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */\r
+#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */\r
+#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */\r
+#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */\r
+#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */\r
+#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */\r
+#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */\r
+#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */\r
+#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */\r
+#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */\r
+#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */\r
+#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */\r
+\r
+/****************** Bit definition for DBGMCU_CR register *******************/\r
+#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */\r
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */\r
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */\r
+#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!< Trace Pin Assignment Control */\r
+\r
+#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */\r
+#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!< Bit 0 */\r
+#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!< Bit 1 */\r
+\r
+/****************** Bit definition for DBGMCU_APB1_FZ register **************/\r
+\r
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004) /*!< TIM4 counter stopped when core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) /*!< TIM7 counter stopped when core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< SMBUS timeout mode stopped when Core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) /*!< SMBUS timeout mode stopped when Core is halted */\r
+\r
+/****************** Bit definition for DBGMCU_APB2_FZ register **************/\r
+\r
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00000004) /*!< TIM9 counter stopped when core is halted */\r
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00000008) /*!< TIM10 counter stopped when core is halted */\r
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00000010) /*!< TIM11 counter stopped when core is halted */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* DMA Controller (DMA) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for DMA_ISR register ********************/\r
+#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */\r
+#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */\r
+#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */\r
+#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */\r
+#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */\r
+#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */\r
+#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */\r
+#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */\r
+#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */\r
+#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */\r
+#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */\r
+#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */\r
+#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */\r
+#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */\r
+#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */\r
+#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */\r
+#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */\r
+#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */\r
+#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */\r
+#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */\r
+#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */\r
+#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */\r
+#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */\r
+#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */\r
+#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */\r
+#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */\r
+#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */\r
+#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */\r
+\r
+/******************* Bit definition for DMA_IFCR register *******************/\r
+#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clearr */\r
+#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */\r
+#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */\r
+#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */\r
+#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */\r
+#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */\r
+#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */\r
+#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */\r
+\r
+/******************* Bit definition for DMA_CCR1 register *******************/\r
+#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/\r
+#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */\r
+#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */\r
+#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */\r
+#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */\r
+#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */\r
+#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */\r
+#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */\r
+\r
+#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */\r
+#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */\r
+#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */\r
+\r
+#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */\r
+#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+\r
+#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */\r
+#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */\r
+#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */\r
+\r
+#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */\r
+\r
+/******************* Bit definition for DMA_CCR2 register *******************/\r
+#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */\r
+#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< ransfer complete interrupt enable */\r
+#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */\r
+#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */\r
+#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */\r
+#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */\r
+#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */\r
+#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */\r
+\r
+#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */\r
+#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */\r
+#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */\r
+\r
+#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */\r
+#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+\r
+#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */\r
+#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */\r
+#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */\r
+\r
+#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */\r
+\r
+/******************* Bit definition for DMA_CCR3 register *******************/\r
+#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */\r
+#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */\r
+#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */\r
+#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */\r
+#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */\r
+#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */\r
+#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */\r
+#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */\r
+\r
+#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */\r
+#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */\r
+#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */\r
+\r
+#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */\r
+#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+\r
+#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */\r
+#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */\r
+#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */\r
+\r
+#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */\r
+\r
+/*!<****************** Bit definition for DMA_CCR4 register *******************/\r
+#define DMA_CCR4_EN ((uint16_t)0x0001) /*!< Channel enable */\r
+#define DMA_CCR4_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */\r
+#define DMA_CCR4_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */\r
+#define DMA_CCR4_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */\r
+#define DMA_CCR4_DIR ((uint16_t)0x0010) /*!< Data transfer direction */\r
+#define DMA_CCR4_CIRC ((uint16_t)0x0020) /*!< Circular mode */\r
+#define DMA_CCR4_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */\r
+#define DMA_CCR4_MINC ((uint16_t)0x0080) /*!< Memory increment mode */\r
+\r
+#define DMA_CCR4_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */\r
+#define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */\r
+#define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */\r
+\r
+#define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */\r
+#define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+\r
+#define DMA_CCR4_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */\r
+#define DMA_CCR4_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */\r
+#define DMA_CCR4_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */\r
+\r
+#define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */\r
+\r
+/****************** Bit definition for DMA_CCR5 register *******************/\r
+#define DMA_CCR5_EN ((uint16_t)0x0001) /*!< Channel enable */\r
+#define DMA_CCR5_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */\r
+#define DMA_CCR5_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */\r
+#define DMA_CCR5_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */\r
+#define DMA_CCR5_DIR ((uint16_t)0x0010) /*!< Data transfer direction */\r
+#define DMA_CCR5_CIRC ((uint16_t)0x0020) /*!< Circular mode */\r
+#define DMA_CCR5_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */\r
+#define DMA_CCR5_MINC ((uint16_t)0x0080) /*!< Memory increment mode */\r
+\r
+#define DMA_CCR5_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */\r
+#define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */\r
+#define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */\r
+\r
+#define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */\r
+#define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+\r
+#define DMA_CCR5_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */\r
+#define DMA_CCR5_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */\r
+#define DMA_CCR5_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */\r
+\r
+#define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */\r
+\r
+/******************* Bit definition for DMA_CCR6 register *******************/\r
+#define DMA_CCR6_EN ((uint16_t)0x0001) /*!< Channel enable */\r
+#define DMA_CCR6_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */\r
+#define DMA_CCR6_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */\r
+#define DMA_CCR6_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */\r
+#define DMA_CCR6_DIR ((uint16_t)0x0010) /*!< Data transfer direction */\r
+#define DMA_CCR6_CIRC ((uint16_t)0x0020) /*!< Circular mode */\r
+#define DMA_CCR6_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */\r
+#define DMA_CCR6_MINC ((uint16_t)0x0080) /*!< Memory increment mode */\r
+\r
+#define DMA_CCR6_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */\r
+#define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */\r
+#define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */\r
+\r
+#define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */\r
+#define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+\r
+#define DMA_CCR6_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */\r
+#define DMA_CCR6_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */\r
+#define DMA_CCR6_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */\r
+\r
+#define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */\r
+\r
+/******************* Bit definition for DMA_CCR7 register *******************/\r
+#define DMA_CCR7_EN ((uint16_t)0x0001) /*!< Channel enable */\r
+#define DMA_CCR7_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */\r
+#define DMA_CCR7_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */\r
+#define DMA_CCR7_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */\r
+#define DMA_CCR7_DIR ((uint16_t)0x0010) /*!< Data transfer direction */\r
+#define DMA_CCR7_CIRC ((uint16_t)0x0020) /*!< Circular mode */\r
+#define DMA_CCR7_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */\r
+#define DMA_CCR7_MINC ((uint16_t)0x0080) /*!< Memory increment mode */\r
+\r
+#define DMA_CCR7_PSIZE , ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */\r
+#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */\r
+#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */\r
+\r
+#define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */\r
+#define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+\r
+#define DMA_CCR7_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */\r
+#define DMA_CCR7_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */\r
+#define DMA_CCR7_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */\r
+\r
+#define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */\r
+\r
+/****************** Bit definition for DMA_CNDTR1 register ******************/\r
+#define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */\r
+\r
+/****************** Bit definition for DMA_CNDTR2 register ******************/\r
+#define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */\r
+\r
+/****************** Bit definition for DMA_CNDTR3 register ******************/\r
+#define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */\r
+\r
+/****************** Bit definition for DMA_CNDTR4 register ******************/\r
+#define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */\r
+\r
+/****************** Bit definition for DMA_CNDTR5 register ******************/\r
+#define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */\r
+\r
+/****************** Bit definition for DMA_CNDTR6 register ******************/\r
+#define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */\r
+\r
+/****************** Bit definition for DMA_CNDTR7 register ******************/\r
+#define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */\r
+\r
+/****************** Bit definition for DMA_CPAR1 register *******************/\r
+#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */\r
+\r
+/****************** Bit definition for DMA_CPAR2 register *******************/\r
+#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */\r
+\r
+/****************** Bit definition for DMA_CPAR3 register *******************/\r
+#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */\r
+\r
+\r
+/****************** Bit definition for DMA_CPAR4 register *******************/\r
+#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */\r
+\r
+/****************** Bit definition for DMA_CPAR5 register *******************/\r
+#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */\r
+\r
+/****************** Bit definition for DMA_CPAR6 register *******************/\r
+#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */\r
+\r
+\r
+/****************** Bit definition for DMA_CPAR7 register *******************/\r
+#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */\r
+\r
+/****************** Bit definition for DMA_CMAR1 register *******************/\r
+#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
+\r
+/****************** Bit definition for DMA_CMAR2 register *******************/\r
+#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
+\r
+/****************** Bit definition for DMA_CMAR3 register *******************/\r
+#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
+\r
+\r
+/****************** Bit definition for DMA_CMAR4 register *******************/\r
+#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
+\r
+/****************** Bit definition for DMA_CMAR5 register *******************/\r
+#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
+\r
+/****************** Bit definition for DMA_CMAR6 register *******************/\r
+#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
+\r
+/****************** Bit definition for DMA_CMAR7 register *******************/\r
+#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* External Interrupt/Event Controller (EXTI) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for EXTI_IMR register *******************/\r
+#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */\r
+#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */\r
+#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */\r
+#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */\r
+#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */\r
+#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */\r
+#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */\r
+#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */\r
+#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */\r
+#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */\r
+#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */\r
+#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */\r
+#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */\r
+#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */\r
+#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */\r
+#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */\r
+#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */\r
+#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */\r
+#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */\r
+#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */\r
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */\r
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */\r
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */\r
+\r
+/******************* Bit definition for EXTI_EMR register *******************/\r
+#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */\r
+#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */\r
+#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */\r
+#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */\r
+#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */\r
+#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */\r
+#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */\r
+#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */\r
+#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */\r
+#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */\r
+#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */\r
+#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */\r
+#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */\r
+#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */\r
+#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */\r
+#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */\r
+#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */\r
+#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */\r
+#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */\r
+#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */\r
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */\r
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */\r
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */\r
+\r
+/****************** Bit definition for EXTI_RTSR register *******************/\r
+#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */\r
+#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */\r
+#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */\r
+#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */\r
+#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */\r
+#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */\r
+#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */\r
+#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */\r
+#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */\r
+#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */\r
+#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */\r
+#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */\r
+#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */\r
+#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */\r
+#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */\r
+#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */\r
+#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */\r
+#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */\r
+#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */\r
+#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */\r
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */\r
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */\r
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */\r
+\r
+/****************** Bit definition for EXTI_FTSR register *******************/\r
+#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */\r
+#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */\r
+#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */\r
+#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */\r
+#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */\r
+#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */\r
+#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */\r
+#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */\r
+#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */\r
+#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */\r
+#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */\r
+#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */\r
+#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */\r
+#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */\r
+#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */\r
+#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */\r
+#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */\r
+#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */\r
+#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */\r
+#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */\r
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */\r
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */\r
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */\r
+\r
+/****************** Bit definition for EXTI_SWIER register ******************/\r
+#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */\r
+#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */\r
+#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */\r
+#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */\r
+#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */\r
+#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */\r
+#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */\r
+#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */\r
+#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */\r
+#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */\r
+#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */\r
+#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */\r
+#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */\r
+#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */\r
+#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */\r
+#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */\r
+#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */\r
+#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */\r
+#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */\r
+#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */\r
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */\r
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */\r
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */\r
+\r
+/******************* Bit definition for EXTI_PR register ********************/\r
+#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */\r
+#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */\r
+#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */\r
+#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */\r
+#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */\r
+#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */\r
+#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */\r
+#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */\r
+#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */\r
+#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */\r
+#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */\r
+#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */\r
+#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */\r
+#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */\r
+#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */\r
+#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */\r
+#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */\r
+#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */\r
+#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit 18 */\r
+#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */\r
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit 20 */\r
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit 21 */\r
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit 22 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* FLASH, DATA EEPROM and Option Bytes Registers */\r
+/* (FLASH, DATA_EEPROM, OB) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for FLASH_ACR register ******************/\r
+#define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< Latency */\r
+#define FLASH_ACR_PRFTEN ((uint32_t)0x00000002) /*!< Prefetch Buffer Enable */\r
+#define FLASH_ACR_ACC64 ((uint32_t)0x00000004) /*!< Access 64 bits */\r
+#define FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008) /*!< Flash mode during sleep mode */\r
+#define FLASH_ACR_RUN_PD ((uint32_t)0x00000010) /*!< Flash mode during RUN mode */\r
+\r
+/******************* Bit definition for FLASH_PECR register ******************/\r
+#define FLASH_PECR_PELOCK ((uint32_t)0x00000001) /*!< FLASH_PECR and Flash data Lock */\r
+#define FLASH_PECR_PRGLOCK ((uint32_t)0x00000002) /*!< Program matrix Lock */\r
+#define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004) /*!< Option byte matrix Lock */\r
+#define FLASH_PECR_PROG ((uint32_t)0x00000008) /*!< Program matrix selection */\r
+#define FLASH_PECR_DATA ((uint32_t)0x00000010) /*!< Data matrix selection */\r
+#define FLASH_PECR_FTDW ((uint32_t)0x00000100) /*!< Fixed Time Data write for Word/Half Word/Byte programming */\r
+#define FLASH_PECR_ERASE ((uint32_t)0x00000200) /*!< Page erasing mode */\r
+#define FLASH_PECR_FPRG ((uint32_t)0x00000400) /*!< Fast Page/Half Page programming mode */\r
+#define FLASH_PECR_EOPIE ((uint32_t)0x00010000) /*!< End of programming interrupt */ \r
+#define FLASH_PECR_ERRIE ((uint32_t)0x00020000) /*!< Error interrupt */ \r
+#define FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000) /*!< Launch the option byte loading */ \r
+\r
+/****************** Bit definition for FLASH_PDKEYR register ******************/\r
+#define FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFF) /*!< FLASH_PEC and data matrix Key */\r
+\r
+/****************** Bit definition for FLASH_PEKEYR register ******************/\r
+#define FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFF) /*!< FLASH_PEC and data matrix Key */\r
+\r
+/****************** Bit definition for FLASH_PRGKEYR register ******************/\r
+#define FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFF) /*!< Program matrix Key */\r
+\r
+/****************** Bit definition for FLASH_OPTKEYR register ******************/\r
+#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option bytes matrix Key */\r
+\r
+/****************** Bit definition for FLASH_SR register *******************/\r
+#define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */\r
+#define FLASH_SR_EOP ((uint32_t)0x00000002) /*!< End Of Programming*/\r
+#define FLASH_SR_ENHV ((uint32_t)0x00000004) /*!< End of high voltage */\r
+#define FLASH_SR_READY ((uint32_t)0x00000008) /*!< Flash ready after low power mode */\r
+\r
+#define FLASH_SR_WRPERR ((uint32_t)0x00000100) /*!< Write protected error */\r
+#define FLASH_SR_PGAERR ((uint32_t)0x00000200) /*!< Programming Alignment Error */\r
+#define FLASH_SR_SIZERR ((uint32_t)0x00000400) /*!< Size error */\r
+#define FLASH_SR_OPTVERR ((uint32_t)0x00000800) /*!< Option validity error */\r
+\r
+/****************** Bit definition for FLASH_OBR register *******************/\r
+#define FLASH_OBR_RDPRT ((uint16_t)0x000000AA) /*!< Read Protection */\r
+#define FLASH_OBR_BOR_LEV ((uint16_t)0x000F0000) /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/\r
+#define FLASH_OBR_USER ((uint32_t)0x00700000) /*!< User Option Bytes */\r
+#define FLASH_OBR_IWDG_SW ((uint32_t)0x00100000) /*!< IWDG_SW */\r
+#define FLASH_OBR_nRST_STOP ((uint32_t)0x00200000) /*!< nRST_STOP */\r
+#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00400000) /*!< nRST_STDBY */\r
+\r
+/****************** Bit definition for FLASH_WRPR register ******************/\r
+#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* General Purpose IOs (GPIO) */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for GPIO_MODER register *****************/ \r
+#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)\r
+#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)\r
+#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)\r
+#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)\r
+#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)\r
+#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)\r
+#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)\r
+#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)\r
+#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)\r
+#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)\r
+#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)\r
+#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)\r
+#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)\r
+#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)\r
+#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)\r
+#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)\r
+#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)\r
+#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)\r
+#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)\r
+#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)\r
+#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)\r
+#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)\r
+#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)\r
+#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)\r
+#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)\r
+#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)\r
+#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)\r
+#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)\r
+#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)\r
+#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)\r
+#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)\r
+#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)\r
+#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)\r
+#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)\r
+#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)\r
+#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)\r
+#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)\r
+#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)\r
+#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)\r
+#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)\r
+#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)\r
+#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)\r
+#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)\r
+#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)\r
+#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)\r
+#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)\r
+#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)\r
+#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)\r
+\r
+/******************* Bit definition for GPIO_OTYPER register ****************/ \r
+#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)\r
+#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)\r
+#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)\r
+#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)\r
+#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)\r
+#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)\r
+#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)\r
+#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)\r
+#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)\r
+#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)\r
+#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)\r
+#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)\r
+#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)\r
+#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)\r
+#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)\r
+#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)\r
+\r
+/******************* Bit definition for GPIO_OSPEEDR register ***************/ \r
+#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)\r
+#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)\r
+#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)\r
+#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)\r
+#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)\r
+#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)\r
+#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)\r
+#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)\r
+#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)\r
+#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)\r
+#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)\r
+#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)\r
+#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)\r
+#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)\r
+#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)\r
+#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)\r
+#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)\r
+#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)\r
+#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)\r
+#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)\r
+#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)\r
+#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)\r
+#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)\r
+#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)\r
+#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)\r
+#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)\r
+#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)\r
+#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)\r
+#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)\r
+#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)\r
+#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)\r
+#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)\r
+#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)\r
+#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)\r
+#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)\r
+#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)\r
+#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)\r
+#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)\r
+#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)\r
+#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)\r
+#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)\r
+#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)\r
+#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)\r
+#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)\r
+#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)\r
+#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)\r
+#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)\r
+#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)\r
+\r
+/******************* Bit definition for GPIO_PUPDR register *****************/ \r
+#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)\r
+#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)\r
+#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)\r
+#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)\r
+#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)\r
+#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)\r
+#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)\r
+#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)\r
+#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)\r
+#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)\r
+#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)\r
+#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)\r
+#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)\r
+#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)\r
+#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)\r
+#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)\r
+#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)\r
+#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)\r
+#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)\r
+#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)\r
+#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)\r
+#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)\r
+#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)\r
+#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)\r
+#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)\r
+#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)\r
+#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)\r
+#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)\r
+#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)\r
+#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)\r
+#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)\r
+#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)\r
+#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)\r
+#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)\r
+#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)\r
+#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)\r
+#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)\r
+#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)\r
+#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)\r
+#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)\r
+#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)\r
+#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)\r
+#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)\r
+#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)\r
+#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)\r
+#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)\r
+#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)\r
+#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)\r
+\r
+/******************* Bit definition for GPIO_IDR register *******************/ \r
+#define GPIO_OTYPER_IDR_0 ((uint32_t)0x00000001)\r
+#define GPIO_OTYPER_IDR_1 ((uint32_t)0x00000002)\r
+#define GPIO_OTYPER_IDR_2 ((uint32_t)0x00000004)\r
+#define GPIO_OTYPER_IDR_3 ((uint32_t)0x00000008)\r
+#define GPIO_OTYPER_IDR_4 ((uint32_t)0x00000010)\r
+#define GPIO_OTYPER_IDR_5 ((uint32_t)0x00000020)\r
+#define GPIO_OTYPER_IDR_6 ((uint32_t)0x00000040)\r
+#define GPIO_OTYPER_IDR_7 ((uint32_t)0x00000080)\r
+#define GPIO_OTYPER_IDR_8 ((uint32_t)0x00000100)\r
+#define GPIO_OTYPER_IDR_9 ((uint32_t)0x00000200)\r
+#define GPIO_OTYPER_IDR_10 ((uint32_t)0x00000400)\r
+#define GPIO_OTYPER_IDR_11 ((uint32_t)0x00000800)\r
+#define GPIO_OTYPER_IDR_12 ((uint32_t)0x00001000)\r
+#define GPIO_OTYPER_IDR_13 ((uint32_t)0x00002000)\r
+#define GPIO_OTYPER_IDR_14 ((uint32_t)0x00004000)\r
+#define GPIO_OTYPER_IDR_15 ((uint32_t)0x00008000)\r
+\r
+/******************* Bit definition for GPIO_ODR register *******************/ \r
+#define GPIO_OTYPER_ODR_0 ((uint32_t)0x00000001)\r
+#define GPIO_OTYPER_ODR_1 ((uint32_t)0x00000002)\r
+#define GPIO_OTYPER_ODR_2 ((uint32_t)0x00000004)\r
+#define GPIO_OTYPER_ODR_3 ((uint32_t)0x00000008)\r
+#define GPIO_OTYPER_ODR_4 ((uint32_t)0x00000010)\r
+#define GPIO_OTYPER_ODR_5 ((uint32_t)0x00000020)\r
+#define GPIO_OTYPER_ODR_6 ((uint32_t)0x00000040)\r
+#define GPIO_OTYPER_ODR_7 ((uint32_t)0x00000080)\r
+#define GPIO_OTYPER_ODR_8 ((uint32_t)0x00000100)\r
+#define GPIO_OTYPER_ODR_9 ((uint32_t)0x00000200)\r
+#define GPIO_OTYPER_ODR_10 ((uint32_t)0x00000400)\r
+#define GPIO_OTYPER_ODR_11 ((uint32_t)0x00000800)\r
+#define GPIO_OTYPER_ODR_12 ((uint32_t)0x00001000)\r
+#define GPIO_OTYPER_ODR_13 ((uint32_t)0x00002000)\r
+#define GPIO_OTYPER_ODR_14 ((uint32_t)0x00004000)\r
+#define GPIO_OTYPER_ODR_15 ((uint32_t)0x00008000)\r
+\r
+/******************* Bit definition for GPIO_BSRR register ******************/ \r
+#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)\r
+#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)\r
+#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)\r
+#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)\r
+#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)\r
+#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)\r
+#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)\r
+#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)\r
+#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)\r
+#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)\r
+#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)\r
+#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)\r
+#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)\r
+#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)\r
+#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)\r
+#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)\r
+#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)\r
+#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)\r
+#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)\r
+#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)\r
+#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)\r
+#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)\r
+#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)\r
+#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)\r
+#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)\r
+#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)\r
+#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)\r
+#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)\r
+#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)\r
+#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)\r
+#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)\r
+#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)\r
+\r
+/******************* Bit definition for GPIO_LCKR register ******************/\r
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)\r
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)\r
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)\r
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)\r
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)\r
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)\r
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)\r
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)\r
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)\r
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)\r
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)\r
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)\r
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)\r
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)\r
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)\r
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)\r
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)\r
+\r
+/******************* Bit definition for GPIO_AFRL register ******************/\r
+#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)\r
+#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)\r
+#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)\r
+#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)\r
+#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)\r
+#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)\r
+#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)\r
+#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)\r
+\r
+/******************* Bit definition for GPIO_AFRH register ******************/\r
+#define GPIO_AFRH_AFRH8 ((uint32_t)0x0000000F)\r
+#define GPIO_AFRH_AFRH9 ((uint32_t)0x000000F0)\r
+#define GPIO_AFRH_AFRH10 ((uint32_t)0x00000F00)\r
+#define GPIO_AFRH_AFRH11 ((uint32_t)0x0000F000)\r
+#define GPIO_AFRH_AFRH12 ((uint32_t)0x000F0000)\r
+#define GPIO_AFRH_AFRH13 ((uint32_t)0x00F00000)\r
+#define GPIO_AFRH_AFRH14 ((uint32_t)0x0F000000)\r
+#define GPIO_AFRH_AFRH15 ((uint32_t)0xF0000000)\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Inter-integrated Circuit Interface (I2C) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for I2C_CR1 register ********************/\r
+#define I2C_CR1_PE ((uint16_t)0x0001) /*!< Peripheral Enable */\r
+#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!< SMBus Mode */\r
+#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!< SMBus Type */\r
+#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!< ARP Enable */\r
+#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!< PEC Enable */\r
+#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!< General Call Enable */\r
+#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!< Clock Stretching Disable (Slave mode) */\r
+#define I2C_CR1_START ((uint16_t)0x0100) /*!< Start Generation */\r
+#define I2C_CR1_STOP ((uint16_t)0x0200) /*!< Stop Generation */\r
+#define I2C_CR1_ACK ((uint16_t)0x0400) /*!< Acknowledge Enable */\r
+#define I2C_CR1_POS ((uint16_t)0x0800) /*!< Acknowledge/PEC Position (for data reception) */\r
+#define I2C_CR1_PEC ((uint16_t)0x1000) /*!< Packet Error Checking */\r
+#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!< SMBus Alert */\r
+#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!< Software Reset */\r
+\r
+/******************* Bit definition for I2C_CR2 register ********************/\r
+#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */\r
+#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!< Bit 0 */\r
+#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!< Bit 1 */\r
+#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!< Bit 2 */\r
+#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!< Bit 3 */\r
+#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!< Bit 4 */\r
+#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!< Bit 5 */\r
+\r
+#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!< Error Interrupt Enable */\r
+#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!< Event Interrupt Enable */\r
+#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!< Buffer Interrupt Enable */\r
+#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!< DMA Requests Enable */\r
+#define I2C_CR2_LAST ((uint16_t)0x1000) /*!< DMA Last Transfer */\r
+\r
+/******************* Bit definition for I2C_OAR1 register *******************/\r
+#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!< Interface Address */\r
+#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!< Interface Address */\r
+\r
+#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!< Bit 0 */\r
+#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!< Bit 1 */\r
+#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!< Bit 2 */\r
+#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!< Bit 3 */\r
+#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!< Bit 4 */\r
+#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!< Bit 5 */\r
+#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!< Bit 6 */\r
+#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!< Bit 7 */\r
+#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!< Bit 8 */\r
+#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!< Bit 9 */\r
+\r
+#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!< Addressing Mode (Slave mode) */\r
+\r
+/******************* Bit definition for I2C_OAR2 register *******************/\r
+#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!< Dual addressing mode enable */\r
+#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!< Interface address */\r
+\r
+/******************** Bit definition for I2C_DR register ********************/\r
+#define I2C_DR_DR ((uint8_t)0xFF) /*!< 8-bit Data Register */\r
+\r
+/******************* Bit definition for I2C_SR1 register ********************/\r
+#define I2C_SR1_SB ((uint16_t)0x0001) /*!< Start Bit (Master mode) */\r
+#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!< Address sent (master mode)/matched (slave mode) */\r
+#define I2C_SR1_BTF ((uint16_t)0x0004) /*!< Byte Transfer Finished */\r
+#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!< 10-bit header sent (Master mode) */\r
+#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!< Stop detection (Slave mode) */\r
+#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!< Data Register not Empty (receivers) */\r
+#define I2C_SR1_TXE ((uint16_t)0x0080) /*!< Data Register Empty (transmitters) */\r
+#define I2C_SR1_BERR ((uint16_t)0x0100) /*!< Bus Error */\r
+#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!< Arbitration Lost (master mode) */\r
+#define I2C_SR1_AF ((uint16_t)0x0400) /*!< Acknowledge Failure */\r
+#define I2C_SR1_OVR ((uint16_t)0x0800) /*!< Overrun/Underrun */\r
+#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!< PEC Error in reception */\r
+#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!< Timeout or Tlow Error */\r
+#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!< SMBus Alert */\r
+\r
+/******************* Bit definition for I2C_SR2 register ********************/\r
+#define I2C_SR2_MSL ((uint16_t)0x0001) /*!< Master/Slave */\r
+#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!< Bus Busy */\r
+#define I2C_SR2_TRA ((uint16_t)0x0004) /*!< Transmitter/Receiver */\r
+#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!< General Call Address (Slave mode) */\r
+#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!< SMBus Device Default Address (Slave mode) */\r
+#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!< SMBus Host Header (Slave mode) */\r
+#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!< Dual Flag (Slave mode) */\r
+#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!< Packet Error Checking Register */\r
+\r
+/******************* Bit definition for I2C_CCR register ********************/\r
+#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */\r
+#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!< Fast Mode Duty Cycle */\r
+#define I2C_CCR_FS ((uint16_t)0x8000) /*!< I2C Master Mode Selection */\r
+\r
+/****************** Bit definition for I2C_TRISE register *******************/\r
+#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Independent WATCHDOG (IWDG) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for IWDG_KR register ********************/\r
+#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */\r
+\r
+/******************* Bit definition for IWDG_PR register ********************/\r
+#define IWDG_PR_PR ((uint8_t)0x07) /*!< PR[2:0] (Prescaler divider) */\r
+#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */\r
+#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */\r
+#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */\r
+\r
+/******************* Bit definition for IWDG_RLR register *******************/\r
+#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */\r
+\r
+/******************* Bit definition for IWDG_SR register ********************/\r
+#define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */\r
+#define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* LCD Controller (LCD) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for LCD_CR register *********************/\r
+#define LCD_CR_LCDEN ((uint32_t)0x00000001) /*!< LCD Enable Bit */\r
+#define LCD_CR_VSEL ((uint32_t)0x00000002) /*!< Voltage source selector Bit */\r
+\r
+#define LCD_CR_DUTY ((uint32_t)0x0000001C) /*!< DUTY[2:0] bits (Duty selector) */\r
+#define LCD_CR_DUTY_0 ((uint32_t)0x00000004) /*!< Duty selector Bit 0 */\r
+#define LCD_CR_DUTY_1 ((uint32_t)0x00000008) /*!< Duty selector Bit 1 */\r
+#define LCD_CR_DUTY_2 ((uint32_t)0x00000010) /*!< Duty selector Bit 2 */\r
+\r
+#define LCD_CR_BIAS ((uint32_t)0x00000060) /*!< BIAS[1:0] bits (Bias selector) */\r
+#define LCD_CR_BIAS_0 ((uint32_t)0x00000020) /*!< Bias selector Bit 0 */\r
+#define LCD_CR_BIAS_1 ((uint32_t)0x00000040) /*!< Bias selector Bit 1 */\r
+\r
+#define LCD_CR_MUX_SEG ((uint32_t)0x00000080) /*!< Mux Segment Enable Bit */\r
+\r
+/******************* Bit definition for LCD_FCR register ********************/\r
+#define LCD_FCR_HD ((uint32_t)0x00000001) /*!< High Drive Enable Bit */\r
+#define LCD_FCR_SOFIE ((uint32_t)0x00000002) /*!< Start of Frame Interrupt Enable Bit */\r
+#define LCD_FCR_UDDIE ((uint32_t)0x00000008) /*!< Update Display Done Interrupt Enable Bit */\r
+\r
+#define LCD_FCR_PON ((uint32_t)0x00000070) /*!< PON[2:0] bits (Puls ON Duration) */\r
+#define LCD_FCR_PON_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
+#define LCD_FCR_PON_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
+#define LCD_FCR_PON_2 ((uint32_t)0x00000040) /*!< Bit 2 */\r
+\r
+#define LCD_FCR_DEAD ((uint32_t)0x00000380) /*!< DEAD[2:0] bits (DEAD Time) */\r
+#define LCD_FCR_DEAD_0 ((uint32_t)0x00000080) /*!< Bit 0 */\r
+#define LCD_FCR_DEAD_1 ((uint32_t)0x00000100) /*!< Bit 1 */\r
+#define LCD_FCR_DEAD_2 ((uint32_t)0x00000200) /*!< Bit 2 */\r
+\r
+#define LCD_FCR_CC ((uint32_t)0x00001C00) /*!< CC[2:0] bits (Contrast Control) */\r
+#define LCD_FCR_CC_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define LCD_FCR_CC_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define LCD_FCR_CC_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+\r
+#define LCD_FCR_BLINKF ((uint32_t)0x0000E000) /*!< BLINKF[2:0] bits (Blink Frequency) */\r
+#define LCD_FCR_BLINKF_0 ((uint32_t)0x00002000) /*!< Bit 0 */\r
+#define LCD_FCR_BLINKF_1 ((uint32_t)0x00004000) /*!< Bit 1 */\r
+#define LCD_FCR_BLINKF_2 ((uint32_t)0x00008000) /*!< Bit 2 */\r
+\r
+#define LCD_FCR_BLINK ((uint32_t)0x00030000) /*!< BLINK[1:0] bits (Blink Enable) */\r
+#define LCD_FCR_BLINK_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define LCD_FCR_BLINK_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
+\r
+#define LCD_FCR_DIV ((uint32_t)0x003C0000) /*!< DIV[3:0] bits (Divider) */\r
+#define LCD_FCR_PS ((uint32_t)0x03C00000) /*!< PS[3:0] bits (Prescaler) */\r
+\r
+/******************* Bit definition for LCD_SR register *********************/\r
+#define LCD_SR_ENS ((uint32_t)0x00000001) /*!< LCD Enabled Bit */\r
+#define LCD_SR_SOF ((uint32_t)0x00000002) /*!< Start Of Frame Flag Bit */\r
+#define LCD_SR_UDR ((uint32_t)0x00000004) /*!< Update Display Request Bit */\r
+#define LCD_SR_UDD ((uint32_t)0x00000008) /*!< Update Display Done Flag Bit */\r
+#define LCD_SR_RDY ((uint32_t)0x00000010) /*!< Ready Flag Bit */\r
+#define LCD_SR_FCRSR ((uint32_t)0x00000020) /*!< LCD FCR Register Synchronization Flag Bit */\r
+\r
+/******************* Bit definition for LCD_CLR register ********************/\r
+#define LCD_CLR_SOFC ((uint32_t)0x00000002) /*!< Start Of Frame Flag Clear Bit */\r
+#define LCD_CLR_UDDC ((uint32_t)0x00000008) /*!< Update Display Done Flag Clear Bit */\r
+\r
+/******************* Bit definition for LCD_RAM register ********************/\r
+#define LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFF) /*!< Segment Data Bits */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Power Control (PWR) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************** Bit definition for PWR_CR register ********************/\r
+#define PWR_CR_LPSDSR ((uint16_t)0x0001) /*!< Low-power deepsleep/sleep/low power run */\r
+#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */\r
+#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */\r
+#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */\r
+#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */\r
+\r
+#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */\r
+#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */\r
+#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */\r
+#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */\r
+\r
+/*!< PVD level configuration */\r
+#define PWR_CR_PLS_LEV0 ((uint16_t)0x0000) /*!< PVD level 0 */\r
+#define PWR_CR_PLS_LEV1 ((uint16_t)0x0020) /*!< PVD level 1 */\r
+#define PWR_CR_PLS_LEV2 ((uint16_t)0x0040) /*!< PVD level 2 */\r
+#define PWR_CR_PLS_LEV3 ((uint16_t)0x0060) /*!< PVD level 3 */\r
+#define PWR_CR_PLS_LEV4 ((uint16_t)0x0080) /*!< PVD level 4 */\r
+#define PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) /*!< PVD level 5 */\r
+#define PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) /*!< PVD level 6 */\r
+#define PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) /*!< PVD level 7 */\r
+\r
+#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */\r
+#define PWR_CR_ULP ((uint16_t)0x0200) /*!< Ultra Low Power mode */\r
+#define PWR_CR_FWU ((uint16_t)0x0400) /*!< Fast wakeup */\r
+\r
+#define PWR_CR_VOS ((uint16_t)0x1800) /*!< VOS[1:0] bits (Voltage scaling range selection) */\r
+#define PWR_CR_VOS_0 ((uint16_t)0x0800) /*!< Bit 0 */\r
+#define PWR_CR_VOS_1 ((uint16_t)0x1000) /*!< Bit 1 */\r
+#define PWR_CR_LPRUN ((uint16_t)0x4000) /*!< Low power run mode */\r
+\r
+/******************* Bit definition for PWR_CSR register ********************/\r
+#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */\r
+#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */\r
+#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */\r
+#define PWR_CSR_VREFINTRDYF ((uint16_t)0x0008) /*!< Internal voltage reference (VREFINT) ready flag */\r
+#define PWR_CSR_VOSF ((uint16_t)0x0010) /*!< Voltage Scaling select flag */\r
+#define PWR_CSR_REGLPF ((uint16_t)0x0020) /*!< Regulator LP flag */\r
+\r
+#define PWR_CSR_EWUP1 ((uint16_t)0x0100) /*!< Enable WKUP pin 1 */\r
+#define PWR_CSR_EWUP2 ((uint16_t)0x0200) /*!< Enable WKUP pin 2 */\r
+#define PWR_CSR_EWUP3 ((uint16_t)0x0400) /*!< Enable WKUP pin 3 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Reset and Clock Control (RCC) */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for RCC_CR register ********************/\r
+#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */\r
+#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */\r
+\r
+#define RCC_CR_MSION ((uint32_t)0x00000100) /*!< Internal Multi Speed clock enable */\r
+#define RCC_CR_MSIRDY ((uint32_t)0x00000200) /*!< Internal Multi Speed clock ready flag */\r
+\r
+#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */\r
+#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */\r
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */\r
+\r
+#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */\r
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */\r
+#define RCC_CR_CSSON ((uint32_t)0x10000000) /*!< Clock Security System enable */\r
+\r
+#define RCC_CR_RTCPRE ((uint32_t)0x60000000) /*!< RTC/LCD Prescaler */\r
+#define RCC_CR_RTCPRE_0 ((uint32_t)0x20000000) /*!< Bit0 */\r
+#define RCC_CR_RTCPRE_1 ((uint32_t)0x40000000) /*!< Bit1 */\r
+\r
+/******************** Bit definition for RCC_ICSCR register *****************/\r
+#define RCC_ICSCR_HSICAL ((uint32_t)0x000000FF) /*!< Internal High Speed clock Calibration */\r
+#define RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00) /*!< Internal High Speed clock trimming */\r
+\r
+#define RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000) /*!< Internal Multi Speed clock Range */\r
+#define RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000) /*!< Internal Multi Speed clock Range 65.536 KHz */\r
+#define RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000) /*!< Internal Multi Speed clock Range 131.072 KHz */\r
+#define RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000) /*!< Internal Multi Speed clock Range 262.144 KHz */\r
+#define RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000) /*!< Internal Multi Speed clock Range 524.288 KHz */\r
+#define RCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000) /*!< Internal Multi Speed clock Range 1.048 MHz */\r
+#define RCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000) /*!< Internal Multi Speed clock Range 2.097 MHz */\r
+#define RCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000) /*!< Internal Multi Speed clock Range 4.194 MHz */\r
+#define RCC_ICSCR_MSICAL ((uint32_t)0x00FF0000) /*!< Internal Multi Speed clock Calibration */\r
+#define RCC_ICSCR_MSITRIM ((uint32_t)0xFF000000) /*!< Internal Multi Speed clock trimming */\r
+\r
+/******************** Bit definition for RCC_CFGR register ******************/\r
+#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */\r
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+\r
+/*!< SW configuration */\r
+#define RCC_CFGR_SW_MSI ((uint32_t)0x00000000) /*!< MSI selected as system clock */\r
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000001) /*!< HSI selected as system clock */\r
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000002) /*!< HSE selected as system clock */\r
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000003) /*!< PLL selected as system clock */\r
+\r
+#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */\r
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */\r
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */\r
+\r
+/*!< SWS configuration */\r
+#define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000) /*!< MSI oscillator used as system clock */\r
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004) /*!< HSI oscillator used as system clock */\r
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008) /*!< HSE oscillator used as system clock */\r
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000C) /*!< PLL used as system clock */\r
+\r
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */\r
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */\r
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */\r
+\r
+/*!< HPRE configuration */\r
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */\r
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */\r
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */\r
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */\r
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */\r
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */\r
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */\r
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */\r
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */\r
+\r
+#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */\r
+#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
+#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
+#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */\r
+\r
+/*!< PPRE1 configuration */\r
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */\r
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */\r
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */\r
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */\r
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */\r
+\r
+#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */\r
+#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */\r
+#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */\r
+#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */\r
+\r
+/*!< PPRE2 configuration */\r
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */\r
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */\r
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */\r
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */\r
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */\r
+\r
+/*!< PLL entry clock source*/\r
+#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */\r
+\r
+#define RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI as PLL entry clock source */\r
+#define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE as PLL entry clock source */\r
+\r
+\r
+#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */\r
+#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */\r
+#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */\r
+#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */\r
+#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */\r
+\r
+/*!< PLLMUL configuration */\r
+#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000) /*!< PLL input clock * 3 */\r
+#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00040000) /*!< PLL input clock * 4 */\r
+#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000) /*!< PLL input clock * 6 */\r
+#define RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000) /*!< PLL input clock * 8 */\r
+#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000) /*!< PLL input clock * 12 */\r
+#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000) /*!< PLL input clock * 16 */\r
+#define RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000) /*!< PLL input clock * 24 */\r
+#define RCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000) /*!< PLL input clock * 32 */\r
+#define RCC_CFGR_PLLMUL48 ((uint32_t)0x00200000) /*!< PLL input clock * 48 */\r
+\r
+/*!< PLLDIV configuration */\r
+#define RCC_CFGR_PLLDIV ((uint32_t)0x00C00000) /*!< PLLDIV[1:0] bits (PLL Output Division) */\r
+#define RCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000) /*!< Bit0 */\r
+#define RCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000) /*!< Bit1 */\r
+\r
+\r
+/*!< PLLDIV configuration */\r
+#define RCC_CFGR_PLLDIV1 ((uint32_t)0x00000000) /*!< PLL clock output = CKVCO / 1 */\r
+#define RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000) /*!< PLL clock output = CKVCO / 2 */\r
+#define RCC_CFGR_PLLDIV3 ((uint32_t)0x00800000) /*!< PLL clock output = CKVCO / 3 */\r
+#define RCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000) /*!< PLL clock output = CKVCO / 4 */\r
+\r
+\r
+#define RCC_CFGR_MCOSEL ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */\r
+#define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
+#define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
+#define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */\r
+\r
+/*!< MCO configuration */\r
+#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */\r
+#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x01000000) /*!< System clock selected */\r
+#define RCC_CFGR_MCO_HSI ((uint32_t)0x02000000) /*!< Internal 16 MHz RC oscillator clock selected */\r
+#define RCC_CFGR_MCO_MSI ((uint32_t)0x03000000) /*!< Internal Medium Speed RC oscillator clock selected */\r
+#define RCC_CFGR_MCO_HSE ((uint32_t)0x04000000) /*!< External 1-25 MHz oscillator clock selected */\r
+#define RCC_CFGR_MCO_PLL ((uint32_t)0x05000000) /*!< PLL clock divided */\r
+#define RCC_CFGR_MCO_LSI ((uint32_t)0x06000000) /*!< LSI selected */\r
+#define RCC_CFGR_MCO_LSE ((uint32_t)0x07000000) /*!< LSE selected */\r
+\r
+#define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */\r
+#define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000) /*!< Bit 0 */\r
+#define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000) /*!< Bit 1 */\r
+#define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000) /*!< Bit 2 */\r
+\r
+/*!< MCO Prescaler configuration */\r
+#define RCC_CFGR_MCO_DIV1 ((uint32_t)0x00000000) /*!< MCO Clock divided by 1 */\r
+#define RCC_CFGR_MCO_DIV2 ((uint32_t)0x10000000) /*!< MCO Clock divided by 2 */\r
+#define RCC_CFGR_MCO_DIV4 ((uint32_t)0x20000000) /*!< MCO Clock divided by 4 */\r
+#define RCC_CFGR_MCO_DIV8 ((uint32_t)0x30000000) /*!< MCO Clock divided by 8 */\r
+#define RCC_CFGR_MCO_DIV16 ((uint32_t)0x40000000) /*!< MCO Clock divided by 16 */\r
+\r
+/*!<****************** Bit definition for RCC_CIR register ********************/\r
+#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */\r
+#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */\r
+#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */\r
+#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */\r
+#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */\r
+#define RCC_CIR_MSIRDYF ((uint32_t)0x00000020) /*!< MSI Ready Interrupt flag */\r
+#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */\r
+\r
+#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */\r
+#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */\r
+#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */\r
+#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */\r
+#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */\r
+#define RCC_CIR_MSIRDYIE ((uint32_t)0x00002000) /*!< MSI Ready Interrupt Enable */\r
+\r
+#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */\r
+#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */\r
+#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */\r
+#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */\r
+#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */\r
+#define RCC_CIR_MSIRDYC ((uint32_t)0x00200000) /*!< MSI Ready Interrupt Clear */\r
+#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */\r
+\r
+\r
+/***************** Bit definition for RCC_AHBRSTR register ******************/\r
+#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00000001) /*!< GPIO port A reset */\r
+#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00000002) /*!< GPIO port B reset */\r
+#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00000004) /*!< GPIO port C reset */\r
+#define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00000008) /*!< GPIO port D reset */\r
+#define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00000010) /*!< GPIO port E reset */\r
+#define RCC_AHBRSTR_GPIOHRST ((uint32_t)0x00000020) /*!< GPIO port H reset */\r
+#define RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000) /*!< CRC reset */\r
+#define RCC_AHBRSTR_FLITFRST ((uint32_t)0x00008000) /*!< FLITF reset */\r
+#define RCC_AHBRSTR_DMA1RST ((uint32_t)0x01000000) /*!< DMA1 reset */\r
+ \r
+/***************** Bit definition for RCC_APB2RSTR register *****************/\r
+#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< System Configuration SYSCFG reset */\r
+#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00000004) /*!< TIM9 reset */\r
+#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00000008) /*!< TIM10 reset */\r
+#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00000010) /*!< TIM11 reset */\r
+#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC1 reset */\r
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 reset */\r
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */\r
+\r
+/***************** Bit definition for RCC_APB1RSTR register *****************/\r
+#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */\r
+#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */\r
+#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */\r
+#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */\r
+#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */\r
+#define RCC_APB1RSTR_LCDRST ((uint32_t)0x00000200) /*!< LCD reset */\r
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */\r
+#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */\r
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */\r
+#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< RUSART 3 reset */\r
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */\r
+#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */\r
+#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB reset */\r
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */\r
+#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */\r
+#define RCC_APB1RSTR_COMPRST ((uint32_t)0x80000000) /*!< Comparator interface reset */\r
+\r
+/****************** Bit definition for RCC_AHBENR register ******************/\r
+#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00000001) /*!< GPIO port A clock enable */\r
+#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00000002) /*!< GPIO port B clock enable */\r
+#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00000004) /*!< GPIO port C clock enable */\r
+#define RCC_AHBENR_GPIODEN ((uint32_t)0x00000008) /*!< GPIO port D clock enable */\r
+#define RCC_AHBENR_GPIOEEN ((uint32_t)0x00000010) /*!< GPIO port E clock enable */\r
+#define RCC_AHBENR_GPIOHEN ((uint32_t)0x00000020) /*!< GPIO port H clock enable */\r
+#define RCC_AHBENR_CRCEN ((uint32_t)0x00001000) /*!< CRC clock enable */\r
+#define RCC_AHBENR_FLITFEN ((uint32_t)0x00008000) /*!< FLITF clock enable (has effect only when\r
+ the Flash memory is in power down mode) */\r
+#define RCC_AHBENR_DMA1EN ((uint32_t)0x01000000) /*!< DMA1 clock enable */\r
+\r
+\r
+/****************** Bit definition for RCC_APB2ENR register *****************/\r
+#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< System Configuration SYSCFG clock enable */\r
+#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00000004) /*!< TIM9 interface clock enable */\r
+#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00000008) /*!< TIM10 interface clock enable */\r
+#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00000010) /*!< TIM11 Timer clock enable */\r
+#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC1 clock enable */\r
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */\r
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */\r
+\r
+\r
+/***************** Bit definition for RCC_APB1ENR register ******************/\r
+#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/\r
+#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */\r
+#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */\r
+#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */\r
+#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */\r
+#define RCC_APB1ENR_LCDEN ((uint32_t)0x00000200) /*!< LCD clock enable */\r
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */\r
+#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */\r
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */\r
+#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */\r
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */\r
+#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */\r
+#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */\r
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */\r
+#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */\r
+#define RCC_APB1ENR_COMPEN ((uint32_t)0x80000000) /*!< Comparator interface clock enable */\r
+\r
+/****************** Bit definition for RCC_AHBLPENR register ****************/\r
+#define RCC_AHBLPENR_GPIOALPEN ((uint32_t)0x00000001) /*!< GPIO port A clock enabled in sleep mode */\r
+#define RCC_AHBLPENR_GPIOBLPEN ((uint32_t)0x00000002) /*!< GPIO port B clock enabled in sleep mode */\r
+#define RCC_AHBLPENR_GPIOCLPEN ((uint32_t)0x00000004) /*!< GPIO port C clock enabled in sleep mode */\r
+#define RCC_AHBLPENR_GPIODLPEN ((uint32_t)0x00000008) /*!< GPIO port D clock enabled in sleep mode */\r
+#define RCC_AHBLPENR_GPIOELPEN ((uint32_t)0x00000010) /*!< GPIO port E clock enabled in sleep mode */\r
+#define RCC_AHBLPENR_GPIOHLPEN ((uint32_t)0x00000020) /*!< GPIO port H clock enabled in sleep mode */\r
+#define RCC_AHBLPENR_CRCLPEN ((uint32_t)0x00001000) /*!< CRC clock enabled in sleep mode */\r
+#define RCC_AHBLPENR_FLITFLPEN ((uint32_t)0x00008000) /*!< Flash Interface clock enabled in sleep mode\r
+ (has effect only when the Flash memory is\r
+ in power down mode) */\r
+#define RCC_AHBLPENR_SRAMLPEN ((uint32_t)0x00010000) /*!< SRAM clock enabled in sleep mode */\r
+#define RCC_AHBLPENR_DMA1LPEN ((uint32_t)0x01000000) /*!< DMA1 clock enabled in sleep mode */\r
+\r
+/****************** Bit definition for RCC_APB2LPENR register ***************/\r
+#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00000001) /*!< System Configuration SYSCFG clock enabled in sleep mode */\r
+#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00000004) /*!< TIM9 interface clock enabled in sleep mode */\r
+#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00000008) /*!< TIM10 interface clock enabled in sleep mode */\r
+#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00000010) /*!< TIM11 Timer clock enabled in sleep mode */\r
+#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000200) /*!< ADC1 clock enabled in sleep mode */\r
+#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000) /*!< SPI1 clock enabled in sleep mode */\r
+#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00004000) /*!< USART1 clock enabled in sleep mode */\r
+\r
+/***************** Bit definition for RCC_APB1LPENR register ****************/\r
+#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002) /*!< Timer 3 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004) /*!< Timer 4 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010) /*!< Timer 6 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020) /*!< Timer 7 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_LCDLPEN ((uint32_t)0x00000200) /*!< LCD clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000) /*!< SPI 2 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000) /*!< USART 2 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000) /*!< USART 3 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000) /*!< I2C 1 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000) /*!< I2C 2 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_USBLPEN ((uint32_t)0x00800000) /*!< USB clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000) /*!< Power interface clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000) /*!< DAC interface clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_COMPLPEN ((uint32_t)0x80000000) /*!< Comparator interface clock enabled in sleep mode*/\r
+\r
+/******************* Bit definition for RCC_CSR register ********************/\r
+#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */\r
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */\r
+\r
+#define RCC_CSR_LSEON ((uint32_t)0x00000100) /*!< External Low Speed oscillator enable */\r
+#define RCC_CSR_LSERDY ((uint32_t)0x00000200) /*!< External Low Speed oscillator Ready */\r
+#define RCC_CSR_LSEBYP ((uint32_t)0x00000400) /*!< External Low Speed oscillator Bypass */\r
+\r
+#define RCC_CSR_RTCSEL ((uint32_t)0x00030000) /*!< RTCSEL[1:0] bits (RTC clock source selection) */\r
+#define RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
+\r
+/*!< RTC congiguration */\r
+#define RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */\r
+#define RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000) /*!< LSE oscillator clock used as RTC clock */\r
+#define RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000) /*!< LSI oscillator clock used as RTC clock */\r
+#define RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000) /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */\r
+\r
+#define RCC_CSR_RTCEN ((uint32_t)0x00400000) /*!< RTC clock enable */\r
+#define RCC_CSR_RTCRST ((uint32_t)0x00800000) /*!< RTC reset */\r
+ \r
+#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */\r
+#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< Option Bytes Loader reset flag */\r
+#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */\r
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */\r
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */\r
+#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */\r
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */\r
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Real-Time Clock (RTC) */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bits definition for RTC_TR register *******************/\r
+#define RTC_TR_PM ((uint32_t)0x00400000)\r
+#define RTC_TR_HT ((uint32_t)0x00300000)\r
+#define RTC_TR_HT_0 ((uint32_t)0x00100000)\r
+#define RTC_TR_HT_1 ((uint32_t)0x00200000)\r
+#define RTC_TR_HU ((uint32_t)0x000F0000)\r
+#define RTC_TR_HU_0 ((uint32_t)0x00010000)\r
+#define RTC_TR_HU_1 ((uint32_t)0x00020000)\r
+#define RTC_TR_HU_2 ((uint32_t)0x00040000)\r
+#define RTC_TR_HU_3 ((uint32_t)0x00080000)\r
+#define RTC_TR_MNT ((uint32_t)0x00007000)\r
+#define RTC_TR_MNT_0 ((uint32_t)0x00001000)\r
+#define RTC_TR_MNT_1 ((uint32_t)0x00002000)\r
+#define RTC_TR_MNT_2 ((uint32_t)0x00004000)\r
+#define RTC_TR_MNU ((uint32_t)0x00000F00)\r
+#define RTC_TR_MNU_0 ((uint32_t)0x00000100)\r
+#define RTC_TR_MNU_1 ((uint32_t)0x00000200)\r
+#define RTC_TR_MNU_2 ((uint32_t)0x00000400)\r
+#define RTC_TR_MNU_3 ((uint32_t)0x00000800)\r
+#define RTC_TR_ST ((uint32_t)0x00000070)\r
+#define RTC_TR_ST_0 ((uint32_t)0x00000010)\r
+#define RTC_TR_ST_1 ((uint32_t)0x00000020)\r
+#define RTC_TR_ST_2 ((uint32_t)0x00000040)\r
+#define RTC_TR_SU ((uint32_t)0x0000000F)\r
+#define RTC_TR_SU_0 ((uint32_t)0x00000001)\r
+#define RTC_TR_SU_1 ((uint32_t)0x00000002)\r
+#define RTC_TR_SU_2 ((uint32_t)0x00000004)\r
+#define RTC_TR_SU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_DR register *******************/\r
+#define RTC_DR_YT ((uint32_t)0x00F00000)\r
+#define RTC_DR_YT_0 ((uint32_t)0x00100000)\r
+#define RTC_DR_YT_1 ((uint32_t)0x00200000)\r
+#define RTC_DR_YT_2 ((uint32_t)0x00400000)\r
+#define RTC_DR_YT_3 ((uint32_t)0x00800000)\r
+#define RTC_DR_YU ((uint32_t)0x000F0000)\r
+#define RTC_DR_YU_0 ((uint32_t)0x00010000)\r
+#define RTC_DR_YU_1 ((uint32_t)0x00020000)\r
+#define RTC_DR_YU_2 ((uint32_t)0x00040000)\r
+#define RTC_DR_YU_3 ((uint32_t)0x00080000)\r
+#define RTC_DR_WDU ((uint32_t)0x0000E000)\r
+#define RTC_DR_WDU_0 ((uint32_t)0x00002000)\r
+#define RTC_DR_WDU_1 ((uint32_t)0x00004000)\r
+#define RTC_DR_WDU_2 ((uint32_t)0x00008000)\r
+#define RTC_DR_MT ((uint32_t)0x00001000)\r
+#define RTC_DR_MU ((uint32_t)0x00000F00)\r
+#define RTC_DR_MU_0 ((uint32_t)0x00000100)\r
+#define RTC_DR_MU_1 ((uint32_t)0x00000200)\r
+#define RTC_DR_MU_2 ((uint32_t)0x00000400)\r
+#define RTC_DR_MU_3 ((uint32_t)0x00000800)\r
+#define RTC_DR_DT ((uint32_t)0x00000030)\r
+#define RTC_DR_DT_0 ((uint32_t)0x00000010)\r
+#define RTC_DR_DT_1 ((uint32_t)0x00000020)\r
+#define RTC_DR_DU ((uint32_t)0x0000000F)\r
+#define RTC_DR_DU_0 ((uint32_t)0x00000001)\r
+#define RTC_DR_DU_1 ((uint32_t)0x00000002)\r
+#define RTC_DR_DU_2 ((uint32_t)0x00000004)\r
+#define RTC_DR_DU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_CR register *******************/\r
+#define RTC_CR_COE ((uint32_t)0x00800000)\r
+#define RTC_CR_OSEL ((uint32_t)0x00600000)\r
+#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)\r
+#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)\r
+#define RTC_CR_POL ((uint32_t)0x00100000)\r
+#define RTC_CR_BCK ((uint32_t)0x00040000)\r
+#define RTC_CR_SUB1H ((uint32_t)0x00020000)\r
+#define RTC_CR_ADD1H ((uint32_t)0x00010000)\r
+#define RTC_CR_TSIE ((uint32_t)0x00008000)\r
+#define RTC_CR_WUTIE ((uint32_t)0x00004000)\r
+#define RTC_CR_ALRBIE ((uint32_t)0x00002000)\r
+#define RTC_CR_ALRAIE ((uint32_t)0x00001000)\r
+#define RTC_CR_TSE ((uint32_t)0x00000800)\r
+#define RTC_CR_WUTE ((uint32_t)0x00000400)\r
+#define RTC_CR_ALRBE ((uint32_t)0x00000200)\r
+#define RTC_CR_ALRAE ((uint32_t)0x00000100)\r
+#define RTC_CR_DCE ((uint32_t)0x00000080)\r
+#define RTC_CR_FMT ((uint32_t)0x00000040)\r
+#define RTC_CR_REFCKON ((uint32_t)0x00000010)\r
+#define RTC_CR_TSEDGE ((uint32_t)0x00000008)\r
+#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)\r
+#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)\r
+#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)\r
+#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)\r
+\r
+/******************** Bits definition for RTC_ISR register ******************/\r
+#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)\r
+#define RTC_ISR_TSOVF ((uint32_t)0x00001000)\r
+#define RTC_ISR_TSF ((uint32_t)0x00000800)\r
+#define RTC_ISR_WUTF ((uint32_t)0x00000400)\r
+#define RTC_ISR_ALRBF ((uint32_t)0x00000200)\r
+#define RTC_ISR_ALRAF ((uint32_t)0x00000100)\r
+#define RTC_ISR_INIT ((uint32_t)0x00000080)\r
+#define RTC_ISR_INITF ((uint32_t)0x00000040)\r
+#define RTC_ISR_RSF ((uint32_t)0x00000020)\r
+#define RTC_ISR_INITS ((uint32_t)0x00000010)\r
+#define RTC_ISR_WUTWF ((uint32_t)0x00000004)\r
+#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)\r
+#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)\r
+\r
+/******************** Bits definition for RTC_PRER register *****************/\r
+#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)\r
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)\r
+\r
+/******************** Bits definition for RTC_WUTR register *****************/\r
+#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)\r
+\r
+/******************** Bits definition for RTC_CALIBR register ***************/\r
+#define RTC_CALIBR_DCS ((uint32_t)0x00000080)\r
+#define RTC_CALIBR_DC ((uint32_t)0x0000001F)\r
+\r
+/******************** Bits definition for RTC_ALRMAR register ***************/\r
+#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)\r
+#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)\r
+#define RTC_ALRMAR_DT ((uint32_t)0x30000000)\r
+#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)\r
+#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)\r
+#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)\r
+#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)\r
+#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)\r
+#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)\r
+#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)\r
+#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)\r
+#define RTC_ALRMAR_PM ((uint32_t)0x00400000)\r
+#define RTC_ALRMAR_HT ((uint32_t)0x00300000)\r
+#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)\r
+#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)\r
+#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)\r
+#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)\r
+#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)\r
+#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)\r
+#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)\r
+#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)\r
+#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)\r
+#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)\r
+#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)\r
+#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)\r
+#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)\r
+#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)\r
+#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)\r
+#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)\r
+#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)\r
+#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)\r
+#define RTC_ALRMAR_ST ((uint32_t)0x00000070)\r
+#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)\r
+#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)\r
+#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)\r
+#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)\r
+#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)\r
+#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)\r
+#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)\r
+#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_ALRMBR register ***************/\r
+#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)\r
+#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)\r
+#define RTC_ALRMBR_DT ((uint32_t)0x30000000)\r
+#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)\r
+#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)\r
+#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)\r
+#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)\r
+#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)\r
+#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)\r
+#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)\r
+#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)\r
+#define RTC_ALRMBR_PM ((uint32_t)0x00400000)\r
+#define RTC_ALRMBR_HT ((uint32_t)0x00300000)\r
+#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)\r
+#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)\r
+#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)\r
+#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)\r
+#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)\r
+#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)\r
+#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)\r
+#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)\r
+#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)\r
+#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)\r
+#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)\r
+#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)\r
+#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)\r
+#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)\r
+#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)\r
+#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)\r
+#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)\r
+#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)\r
+#define RTC_ALRMBR_ST ((uint32_t)0x00000070)\r
+#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)\r
+#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)\r
+#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)\r
+#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)\r
+#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)\r
+#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)\r
+#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)\r
+#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_WPR register ******************/\r
+#define RTC_WPR_KEY ((uint32_t)0x000000FF)\r
+\r
+/******************** Bits definition for RTC_TSTR register *****************/\r
+#define RTC_TSTR_PM ((uint32_t)0x00400000)\r
+#define RTC_TSTR_HT ((uint32_t)0x00300000)\r
+#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)\r
+#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)\r
+#define RTC_TSTR_HU ((uint32_t)0x000F0000)\r
+#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)\r
+#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)\r
+#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)\r
+#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)\r
+#define RTC_TSTR_MNT ((uint32_t)0x00007000)\r
+#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)\r
+#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)\r
+#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)\r
+#define RTC_TSTR_MNU ((uint32_t)0x00000F00)\r
+#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)\r
+#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)\r
+#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)\r
+#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)\r
+#define RTC_TSTR_ST ((uint32_t)0x00000070)\r
+#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)\r
+#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)\r
+#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)\r
+#define RTC_TSTR_SU ((uint32_t)0x0000000F)\r
+#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)\r
+#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)\r
+#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)\r
+#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_TSDR register *****************/\r
+#define RTC_TSDR_WDU ((uint32_t)0x0000E000)\r
+#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)\r
+#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)\r
+#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)\r
+#define RTC_TSDR_MT ((uint32_t)0x00001000)\r
+#define RTC_TSDR_MU ((uint32_t)0x00000F00)\r
+#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)\r
+#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)\r
+#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)\r
+#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)\r
+#define RTC_TSDR_DT ((uint32_t)0x00000030)\r
+#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)\r
+#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)\r
+#define RTC_TSDR_DU ((uint32_t)0x0000000F)\r
+#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)\r
+#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)\r
+#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)\r
+#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_TAFCR register ****************/\r
+#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)\r
+#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)\r
+#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)\r
+#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)\r
+\r
+/******************** Bits definition for RTC_BKP0R register ****************/\r
+#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP1R register ****************/\r
+#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP2R register ****************/\r
+#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP3R register ****************/\r
+#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP4R register ****************/\r
+#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP5R register ****************/\r
+#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP6R register ****************/\r
+#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP7R register ****************/\r
+#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP8R register ****************/\r
+#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP9R register ****************/\r
+#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP10R register ***************/\r
+#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP11R register ***************/\r
+#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP12R register ***************/\r
+#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP13R register ***************/\r
+#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP14R register ***************/\r
+#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP15R register ***************/\r
+#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP16R register ***************/\r
+#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP17R register ***************/\r
+#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP18R register ***************/\r
+#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP19R register ***************/\r
+#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Serial Peripheral Interface (SPI) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for SPI_CR1 register ********************/\r
+#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */\r
+#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */\r
+#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */\r
+\r
+#define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */\r
+#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */\r
+#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */\r
+#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */\r
+\r
+#define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */\r
+#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */\r
+#define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */\r
+#define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */\r
+#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */\r
+#define SPI_CR1_DFF ((uint16_t)0x0800) /*!< Data Frame Format */\r
+#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */\r
+#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */\r
+#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */\r
+#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */\r
+\r
+/******************* Bit definition for SPI_CR2 register ********************/\r
+#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!< Rx Buffer DMA Enable */\r
+#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!< Tx Buffer DMA Enable */\r
+#define SPI_CR2_SSOE ((uint8_t)0x04) /*!< SS Output Enable */\r
+#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!< Error Interrupt Enable */\r
+#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!< RX buffer Not Empty Interrupt Enable */\r
+#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!< Tx buffer Empty Interrupt Enable */\r
+\r
+/******************** Bit definition for SPI_SR register ********************/\r
+#define SPI_SR_RXNE ((uint8_t)0x01) /*!< Receive buffer Not Empty */\r
+#define SPI_SR_TXE ((uint8_t)0x02) /*!< Transmit buffer Empty */\r
+#define SPI_SR_CRCERR ((uint8_t)0x10) /*!< CRC Error flag */\r
+#define SPI_SR_MODF ((uint8_t)0x20) /*!< Mode fault */\r
+#define SPI_SR_OVR ((uint8_t)0x40) /*!< Overrun flag */\r
+#define SPI_SR_BSY ((uint8_t)0x80) /*!< Busy flag */\r
+\r
+/******************** Bit definition for SPI_DR register ********************/\r
+#define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */\r
+\r
+/******************* Bit definition for SPI_CRCPR register ******************/\r
+#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */\r
+\r
+/****************** Bit definition for SPI_RXCRCR register ******************/\r
+#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */\r
+\r
+/****************** Bit definition for SPI_TXCRCR register ******************/\r
+#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* System Configuration (SYSCFG) */\r
+/* */\r
+/******************************************************************************/\r
+/***************** Bit definition for SYSCFG_MEMRMP register ****************/\r
+#define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */\r
+#define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+\r
+/***************** Bit definition for SYSCFG_PMC register *******************/\r
+#define SYSCFG_PMC_USB_PU ((uint32_t)0x00000001) /*!< SYSCFG PMC */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/\r
+#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */\r
+#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */\r
+#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */\r
+#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */\r
+\r
+/** \r
+ * @brief EXTI0 configuration \r
+ */ \r
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0005) /*!< PH[0] pin */\r
+\r
+/** \r
+ * @brief EXTI1 configuration \r
+ */ \r
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0050) /*!< PH[1] pin */\r
+\r
+/** \r
+ * @brief EXTI2 configuration \r
+ */ \r
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0500) /*!< PH[2] pin */\r
+\r
+/** \r
+ * @brief EXTI3 configuration \r
+ */ \r
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR2 register *****************/\r
+#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */\r
+#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */\r
+#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */\r
+#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */\r
+\r
+/** \r
+ * @brief EXTI4 configuration \r
+ */ \r
+#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */\r
+\r
+/** \r
+ * @brief EXTI5 configuration \r
+ */ \r
+#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */\r
+\r
+/** \r
+ * @brief EXTI6 configuration \r
+ */ \r
+#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */\r
+\r
+/** \r
+ * @brief EXTI7 configuration \r
+ */ \r
+#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR3 register *****************/\r
+#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */\r
+#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */\r
+#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */\r
+#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */\r
+ \r
+/** \r
+ * @brief EXTI8 configuration \r
+ */ \r
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */\r
+\r
+/** \r
+ * @brief EXTI9 configuration \r
+ */ \r
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */\r
+\r
+/** \r
+ * @brief EXTI10 configuration \r
+ */ \r
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */\r
+\r
+/** \r
+ * @brief EXTI11 configuration \r
+ */ \r
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR4 register *****************/\r
+#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */\r
+#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */\r
+#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */\r
+#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */\r
+\r
+/** \r
+ * @brief EXTI12 configuration \r
+ */ \r
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */\r
+\r
+/** \r
+ * @brief EXTI13 configuration \r
+ */ \r
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */\r
+\r
+/** \r
+ * @brief EXTI14 configuration \r
+ */ \r
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */\r
+\r
+/** \r
+ * @brief EXTI15 configuration \r
+ */ \r
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */\r
+ \r
+/******************************************************************************/\r
+/* */\r
+/* Routing Interface (RI) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************** Bit definition for RI_ICR register ********************/\r
+#define RI_ICR_IC1Z ((uint32_t)0x0000000F) /*!< IC1Z[3:0] bits (Input Capture 1 select bits) */\r
+#define RI_ICR_IC1Z_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define RI_ICR_IC1Z_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define RI_ICR_IC1Z_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define RI_ICR_IC1Z_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+\r
+#define RI_ICR_IC2Z ((uint32_t)0x000000F0) /*!< IC2Z[3:0] bits (Input Capture 2 select bits) */\r
+#define RI_ICR_IC2Z_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
+#define RI_ICR_IC2Z_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
+#define RI_ICR_IC2Z_2 ((uint32_t)0x00000040) /*!< Bit 2 */\r
+#define RI_ICR_IC2Z_3 ((uint32_t)0x00000080) /*!< Bit 3 */\r
+\r
+#define RI_ICR_IC3Z ((uint32_t)0x00000F00) /*!< IC3Z[3:0] bits (Input Capture 3 select bits) */\r
+#define RI_ICR_IC3Z_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
+#define RI_ICR_IC3Z_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
+#define RI_ICR_IC3Z_2 ((uint32_t)0x00000400) /*!< Bit 2 */\r
+#define RI_ICR_IC3Z_3 ((uint32_t)0x00000800) /*!< Bit 3 */\r
+\r
+#define RI_ICR_IC4Z ((uint32_t)0x0000F000) /*!< IC4Z[3:0] bits (Input Capture 4 select bits) */\r
+#define RI_ICR_IC4Z_0 ((uint32_t)0x00001000) /*!< Bit 0 */\r
+#define RI_ICR_IC4Z_1 ((uint32_t)0x00002000) /*!< Bit 1 */\r
+#define RI_ICR_IC4Z_2 ((uint32_t)0x00004000) /*!< Bit 2 */\r
+#define RI_ICR_IC4Z_3 ((uint32_t)0x00008000) /*!< Bit 3 */\r
+\r
+#define RI_ICR_TIM ((uint32_t)0x00030000) /*!< TIM[3:0] bits (Timers select bits) */\r
+#define RI_ICR_TIM_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define RI_ICR_TIM_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
+\r
+#define RI_ICR_IC1 ((uint32_t)0x00040000) /*!< Input capture 1 */\r
+#define RI_ICR_IC2 ((uint32_t)0x00080000) /*!< Input capture 2 */\r
+#define RI_ICR_IC3 ((uint32_t)0x00100000) /*!< Input capture 3 */\r
+#define RI_ICR_IC4 ((uint32_t)0x00200000) /*!< Input capture 4 */\r
+\r
+/******************** Bit definition for RI_ASCR1 register ********************/\r
+#define RI_ASCR1_CH ((uint32_t)0x03FCFFFF) /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */\r
+#define RI_ASCR1_CH_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define RI_ASCR1_CH_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define RI_ASCR1_CH_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define RI_ASCR1_CH_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+#define RI_ASCR1_CH_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
+#define RI_ASCR1_CH_5 ((uint32_t)0x00000020) /*!< Bit 5 */\r
+#define RI_ASCR1_CH_6 ((uint32_t)0x00000040) /*!< Bit 6 */\r
+#define RI_ASCR1_CH_7 ((uint32_t)0x00000080) /*!< Bit 7 */\r
+#define RI_ASCR1_CH_8 ((uint32_t)0x00000100) /*!< Bit 8 */\r
+#define RI_ASCR1_CH_9 ((uint32_t)0x00000200) /*!< Bit 9 */\r
+#define RI_ASCR1_CH_10 ((uint32_t)0x00000400) /*!< Bit 10 */\r
+#define RI_ASCR1_CH_11 ((uint32_t)0x00000800) /*!< Bit 11 */\r
+#define RI_ASCR1_CH_12 ((uint32_t)0x00001000) /*!< Bit 12 */\r
+#define RI_ASCR1_CH_13 ((uint32_t)0x00002000) /*!< Bit 13 */\r
+#define RI_ASCR1_CH_14 ((uint32_t)0x00004000) /*!< Bit 14 */\r
+#define RI_ASCR1_CH_15 ((uint32_t)0x00008000) /*!< Bit 15 */\r
+#define RI_ASCR1_CH_18 ((uint32_t)0x00040000) /*!< Bit 18 */\r
+#define RI_ASCR1_CH_19 ((uint32_t)0x00080000) /*!< Bit 19 */\r
+#define RI_ASCR1_CH_20 ((uint32_t)0x00100000) /*!< Bit 20 */\r
+#define RI_ASCR1_CH_21 ((uint32_t)0x00200000) /*!< Bit 21 */\r
+#define RI_ASCR1_CH_22 ((uint32_t)0x00400000) /*!< Bit 22 */\r
+#define RI_ASCR1_CH_23 ((uint32_t)0x00800000) /*!< Bit 23 */\r
+#define RI_ASCR1_CH_24 ((uint32_t)0x01000000) /*!< Bit 24 */\r
+#define RI_ASCR1_CH_25 ((uint32_t)0x02000000) /*!< Bit 25 */\r
+\r
+#define RI_ASCR1_VCOMP ((uint32_t)0x04000000) /*!< ADC analog switch selection for internal node to COMP1 */\r
+#define RI_ASCR1_SCM ((uint32_t)0x80000000) /*!< I/O Switch control mode */\r
+\r
+/******************** Bit definition for RI_ASCR2 register ********************/\r
+#define RI_ASCR2_GR10_1 ((uint32_t)0x00000001) /*!< GR10-1 selection bit */\r
+#define RI_ASCR2_GR10_2 ((uint32_t)0x00000002) /*!< GR10-2 selection bit */\r
+#define RI_ASCR2_GR10_3 ((uint32_t)0x00000004) /*!< GR10-3 selection bit */\r
+#define RI_ASCR2_GR10_4 ((uint32_t)0x00000008) /*!< GR10-4 selection bit */\r
+#define RI_ASCR2_GR6_1 ((uint32_t)0x00000010) /*!< GR6-1 selection bit */\r
+#define RI_ASCR2_GR6_2 ((uint32_t)0x00000020) /*!< GR6-2 selection bit */\r
+#define RI_ASCR2_GR5_1 ((uint32_t)0x00000040) /*!< GR5-1 selection bit */\r
+#define RI_ASCR2_GR5_2 ((uint32_t)0x00000080) /*!< GR5-2 selection bit */\r
+#define RI_ASCR2_GR5_3 ((uint32_t)0x00000100) /*!< GR5-3 selection bit */\r
+#define RI_ASCR2_GR4_1 ((uint32_t)0x00000200) /*!< GR4-1 selection bit */\r
+#define RI_ASCR2_GR4_2 ((uint32_t)0x00000400) /*!< GR4-2 selection bit */\r
+#define RI_ASCR2_GR4_3 ((uint32_t)0x00000800) /*!< GR4-3 selection bit */\r
+\r
+\r
+/******************** Bit definition for RI_HYSCR1 register ********************/\r
+#define RI_HYSCR1_PA ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A Hysteresis selection */\r
+#define RI_HYSCR1_PA_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define RI_HYSCR1_PA_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define RI_HYSCR1_PA_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define RI_HYSCR1_PA_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+#define RI_HYSCR1_PA_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
+#define RI_HYSCR1_PA_5 ((uint32_t)0x00000020) /*!< Bit 5 */\r
+#define RI_HYSCR1_PA_6 ((uint32_t)0x00000040) /*!< Bit 6 */\r
+#define RI_HYSCR1_PA_7 ((uint32_t)0x00000080) /*!< Bit 7 */\r
+#define RI_HYSCR1_PA_8 ((uint32_t)0x00000100) /*!< Bit 8 */\r
+#define RI_HYSCR1_PA_9 ((uint32_t)0x00000200) /*!< Bit 9 */\r
+#define RI_HYSCR1_PA_10 ((uint32_t)0x00000400) /*!< Bit 10 */\r
+#define RI_HYSCR1_PA_11 ((uint32_t)0x00000800) /*!< Bit 11 */\r
+#define RI_HYSCR1_PA_12 ((uint32_t)0x00001000) /*!< Bit 12 */\r
+#define RI_HYSCR1_PA_13 ((uint32_t)0x00002000) /*!< Bit 13 */\r
+#define RI_HYSCR1_PA_14 ((uint32_t)0x00004000) /*!< Bit 14 */\r
+#define RI_HYSCR1_PA_15 ((uint32_t)0x00008000) /*!< Bit 15 */\r
+\r
+#define RI_HYSCR1_PB ((uint32_t)0xFFFF0000) /*!< PB[15:0] Port B Hysteresis selection */\r
+#define RI_HYSCR1_PB_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define RI_HYSCR1_PB_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
+#define RI_HYSCR1_PB_2 ((uint32_t)0x00040000) /*!< Bit 2 */\r
+#define RI_HYSCR1_PB_3 ((uint32_t)0x00080000) /*!< Bit 3 */\r
+#define RI_HYSCR1_PB_4 ((uint32_t)0x00100000) /*!< Bit 4 */\r
+#define RI_HYSCR1_PB_5 ((uint32_t)0x00200000) /*!< Bit 5 */\r
+#define RI_HYSCR1_PB_6 ((uint32_t)0x00400000) /*!< Bit 6 */\r
+#define RI_HYSCR1_PB_7 ((uint32_t)0x00800000) /*!< Bit 7 */\r
+#define RI_HYSCR1_PB_8 ((uint32_t)0x01000000) /*!< Bit 8 */\r
+#define RI_HYSCR1_PB_9 ((uint32_t)0x02000000) /*!< Bit 9 */\r
+#define RI_HYSCR1_PB_10 ((uint32_t)0x04000000) /*!< Bit 10 */\r
+#define RI_HYSCR1_PB_11 ((uint32_t)0x08000000) /*!< Bit 11 */\r
+#define RI_HYSCR1_PB_12 ((uint32_t)0x10000000) /*!< Bit 12 */\r
+#define RI_HYSCR1_PB_13 ((uint32_t)0x20000000) /*!< Bit 13 */\r
+#define RI_HYSCR1_PB_14 ((uint32_t)0x40000000) /*!< Bit 14 */\r
+#define RI_HYSCR1_PB_15 ((uint32_t)0x80000000) /*!< Bit 15 */\r
+\r
+/******************** Bit definition for RI_HYSCR2 register ********************/\r
+#define RI_HYSCR2_PC ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C Hysteresis selection */\r
+#define RI_HYSCR2_PC_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define RI_HYSCR2_PC_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define RI_HYSCR2_PC_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define RI_HYSCR2_PC_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+#define RI_HYSCR2_PC_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
+#define RI_HYSCR2_PC_5 ((uint32_t)0x00000020) /*!< Bit 5 */\r
+#define RI_HYSCR2_PC_6 ((uint32_t)0x00000040) /*!< Bit 6 */\r
+#define RI_HYSCR2_PC_7 ((uint32_t)0x00000080) /*!< Bit 7 */\r
+#define RI_HYSCR2_PC_8 ((uint32_t)0x00000100) /*!< Bit 8 */\r
+#define RI_HYSCR2_PC_9 ((uint32_t)0x00000200) /*!< Bit 9 */\r
+#define RI_HYSCR2_PC_10 ((uint32_t)0x00000400) /*!< Bit 10 */\r
+#define RI_HYSCR2_PC_11 ((uint32_t)0x00000800) /*!< Bit 11 */\r
+#define RI_HYSCR2_PC_12 ((uint32_t)0x00001000) /*!< Bit 12 */\r
+#define RI_HYSCR2_PC_13 ((uint32_t)0x00002000) /*!< Bit 13 */\r
+#define RI_HYSCR2_PC_14 ((uint32_t)0x00004000) /*!< Bit 14 */\r
+#define RI_HYSCR2_PC_15 ((uint32_t)0x00008000) /*!< Bit 15 */\r
+\r
+#define RI_HYSCR2_PD ((uint32_t)0xFFFF0000) /*!< PD[15:0] Port D Hysteresis selection */\r
+#define RI_HYSCR2_PD_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define RI_HYSCR2_PD_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
+#define RI_HYSCR2_PD_2 ((uint32_t)0x00040000) /*!< Bit 2 */\r
+#define RI_HYSCR2_PD_3 ((uint32_t)0x00080000) /*!< Bit 3 */\r
+#define RI_HYSCR2_PD_4 ((uint32_t)0x00100000) /*!< Bit 4 */\r
+#define RI_HYSCR2_PD_5 ((uint32_t)0x00200000) /*!< Bit 5 */\r
+#define RI_HYSCR2_PD_6 ((uint32_t)0x00400000) /*!< Bit 6 */\r
+#define RI_HYSCR2_PD_7 ((uint32_t)0x00800000) /*!< Bit 7 */\r
+#define RI_HYSCR2_PD_8 ((uint32_t)0x01000000) /*!< Bit 8 */\r
+#define RI_HYSCR2_PD_9 ((uint32_t)0x02000000) /*!< Bit 9 */\r
+#define RI_HYSCR2_PD_10 ((uint32_t)0x04000000) /*!< Bit 10 */\r
+#define RI_HYSCR2_PD_11 ((uint32_t)0x08000000) /*!< Bit 11 */\r
+#define RI_HYSCR2_PD_12 ((uint32_t)0x10000000) /*!< Bit 12 */\r
+#define RI_HYSCR2_PD_13 ((uint32_t)0x20000000) /*!< Bit 13 */\r
+#define RI_HYSCR2_PD_14 ((uint32_t)0x40000000) /*!< Bit 14 */\r
+#define RI_HYSCR2_PD_15 ((uint32_t)0x80000000) /*!< Bit 15 */\r
+\r
+/******************** Bit definition for RI_HYSCR3 register ********************/\r
+#define RI_HYSCR2_PE ((uint32_t)0x0000FFFF) /*!< PE[15:0] Port E Hysteresis selection */\r
+#define RI_HYSCR2_PE_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define RI_HYSCR2_PE_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define RI_HYSCR2_PE_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define RI_HYSCR2_PE_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+#define RI_HYSCR2_PE_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
+#define RI_HYSCR2_PE_5 ((uint32_t)0x00000020) /*!< Bit 5 */\r
+#define RI_HYSCR2_PE_6 ((uint32_t)0x00000040) /*!< Bit 6 */\r
+#define RI_HYSCR2_PE_7 ((uint32_t)0x00000080) /*!< Bit 7 */\r
+#define RI_HYSCR2_PE_8 ((uint32_t)0x00000100) /*!< Bit 8 */\r
+#define RI_HYSCR2_PE_9 ((uint32_t)0x00000200) /*!< Bit 9 */\r
+#define RI_HYSCR2_PE_10 ((uint32_t)0x00000400) /*!< Bit 10 */\r
+#define RI_HYSCR2_PE_11 ((uint32_t)0x00000800) /*!< Bit 11 */\r
+#define RI_HYSCR2_PE_12 ((uint32_t)0x00001000) /*!< Bit 12 */\r
+#define RI_HYSCR2_PE_13 ((uint32_t)0x00002000) /*!< Bit 13 */\r
+#define RI_HYSCR2_PE_14 ((uint32_t)0x00004000) /*!< Bit 14 */\r
+#define RI_HYSCR2_PE_15 ((uint32_t)0x00008000) /*!< Bit 15 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Timers (TIM) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for TIM_CR1 register ********************/\r
+#define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */\r
+#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */\r
+#define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */\r
+#define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */\r
+#define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */\r
+\r
+#define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */\r
+#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */\r
+#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */\r
+\r
+#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */\r
+\r
+#define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */\r
+#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+\r
+/******************* Bit definition for TIM_CR2 register ********************/\r
+#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!<Capture/Compare Preloaded Control */\r
+#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!<Capture/Compare Control Update Selection */\r
+#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */\r
+\r
+#define TIM_CR2_MMS ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */\r
+#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+\r
+#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!<TI1 Selection */\r
+#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!<Output Idle state 1 (OC1 output) */\r
+#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!<Output Idle state 1 (OC1N output) */\r
+#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!<Output Idle state 2 (OC2 output) */\r
+#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!<Output Idle state 2 (OC2N output) */\r
+#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!<Output Idle state 3 (OC3 output) */\r
+#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!<Output Idle state 3 (OC3N output) */\r
+#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!<Output Idle state 4 (OC4 output) */\r
+\r
+/******************* Bit definition for TIM_SMCR register *******************/\r
+#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */\r
+#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!<Bit 2 */\r
+\r
+#define TIM_SMCR_OCCS ((uint16_t)0x0008) /*!<OCCS bits (OCref Clear Selection) */\r
+\r
+#define TIM_SMCR_TS ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */\r
+#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+\r
+#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!<Master/slave mode */\r
+\r
+#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */\r
+#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!<Bit 2 */\r
+#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!<Bit 3 */\r
+\r
+#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */\r
+#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!<External clock enable */\r
+#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!<External trigger polarity */\r
+\r
+/******************* Bit definition for TIM_DIER register *******************/\r
+#define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */\r
+#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */\r
+#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */\r
+#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */\r
+#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */\r
+#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */\r
+#define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */\r
+#define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */\r
+#define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */\r
+#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */\r
+#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */\r
+#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */\r
+#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */\r
+#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */\r
+#define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */\r
+\r
+/******************** Bit definition for TIM_SR register ********************/\r
+#define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Flag */\r
+#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */\r
+#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */\r
+#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */\r
+#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */\r
+#define TIM_SR_COMIF ((uint16_t)0x0020) /*!<COM interrupt Flag */\r
+#define TIM_SR_TIF ((uint16_t)0x0040) /*!<Trigger interrupt Flag */\r
+#define TIM_SR_BIF ((uint16_t)0x0080) /*!<Break interrupt Flag */\r
+#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */\r
+#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */\r
+#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */\r
+#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */\r
+\r
+/******************* Bit definition for TIM_EGR register ********************/\r
+#define TIM_EGR_UG ((uint8_t)0x01) /*!<Update Generation */\r
+#define TIM_EGR_CC1G ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */\r
+#define TIM_EGR_CC2G ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */\r
+#define TIM_EGR_CC3G ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */\r
+#define TIM_EGR_CC4G ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */\r
+#define TIM_EGR_COMG ((uint8_t)0x20) /*!<Capture/Compare Control Update Generation */\r
+#define TIM_EGR_TG ((uint8_t)0x40) /*!<Trigger Generation */\r
+#define TIM_EGR_BG ((uint8_t)0x80) /*!<Break Generation */\r
+\r
+/****************** Bit definition for TIM_CCMR1 register *******************/\r
+#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\r
+#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */\r
+#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */\r
+\r
+#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */\r
+#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+\r
+#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */\r
+\r
+#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\r
+#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */\r
+#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */\r
+\r
+#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */\r
+#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!<Bit 2 */\r
+\r
+#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\r
+#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */\r
+#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */\r
+#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!<Bit 3 */\r
+\r
+#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */\r
+#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
+#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */\r
+#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!<Bit 2 */\r
+#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!<Bit 3 */\r
+\r
+/****************** Bit definition for TIM_CCMR2 register *******************/\r
+#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */\r
+#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */\r
+#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */\r
+\r
+#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\r
+#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+\r
+#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */\r
+\r
+#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\r
+#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */\r
+#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */\r
+\r
+#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\r
+#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!<Bit 2 */\r
+\r
+#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\r
+#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */\r
+#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\r
+#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!<Bit 3 */\r
+\r
+#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\r
+#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
+#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\r
+#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!<Bit 2 */\r
+#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!<Bit 3 */\r
+\r
+/******************* Bit definition for TIM_CCER register *******************/\r
+#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */\r
+#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */\r
+#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */\r
+#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */\r
+#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */\r
+#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */\r
+#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */\r
+#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */\r
+#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */\r
+#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */\r
+#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */\r
+#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */\r
+#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */\r
+#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */\r
+#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */\r
+\r
+/******************* Bit definition for TIM_CNT register ********************/\r
+#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */\r
+\r
+/******************* Bit definition for TIM_PSC register ********************/\r
+#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */\r
+\r
+/******************* Bit definition for TIM_ARR register ********************/\r
+#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!<actual auto-reload Value */\r
+\r
+/******************* Bit definition for TIM_RCR register ********************/\r
+#define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */\r
+\r
+/******************* Bit definition for TIM_CCR1 register *******************/\r
+#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */\r
+\r
+/******************* Bit definition for TIM_CCR2 register *******************/\r
+#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */\r
+\r
+/******************* Bit definition for TIM_CCR3 register *******************/\r
+#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */\r
+\r
+/******************* Bit definition for TIM_CCR4 register *******************/\r
+#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */\r
+\r
+/******************* Bit definition for TIM_DCR register ********************/\r
+#define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */\r
+#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */\r
+#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */\r
+#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */\r
+\r
+#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */\r
+#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */\r
+#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */\r
+#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */\r
+\r
+/******************* Bit definition for TIM_DMAR register *******************/\r
+#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */\r
+\r
+/******************* Bit definition for TIM_OR register *********************/\r
+#define TIM_OR_TI1RMP ((uint16_t)0x0003) /*!<Option register for TI1 Remapping */\r
+#define TIM_OR_TI1RMP_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define TIM_OR_TI1RMP_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for USART_SR register *******************/\r
+#define USART_SR_PE ((uint16_t)0x0001) /*!< Parity Error */\r
+#define USART_SR_FE ((uint16_t)0x0002) /*!< Framing Error */\r
+#define USART_SR_NE ((uint16_t)0x0004) /*!< Noise Error Flag */\r
+#define USART_SR_ORE ((uint16_t)0x0008) /*!< OverRun Error */\r
+#define USART_SR_IDLE ((uint16_t)0x0010) /*!< IDLE line detected */\r
+#define USART_SR_RXNE ((uint16_t)0x0020) /*!< Read Data Register Not Empty */\r
+#define USART_SR_TC ((uint16_t)0x0040) /*!< Transmission Complete */\r
+#define USART_SR_TXE ((uint16_t)0x0080) /*!< Transmit Data Register Empty */\r
+#define USART_SR_LBD ((uint16_t)0x0100) /*!< LIN Break Detection Flag */\r
+#define USART_SR_CTS ((uint16_t)0x0200) /*!< CTS Flag */\r
+\r
+/******************* Bit definition for USART_DR register *******************/\r
+#define USART_DR_DR ((uint16_t)0x01FF) /*!< Data value */\r
+\r
+/****************** Bit definition for USART_BRR register *******************/\r
+#define USART_BRR_DIV_FRACTION ((uint16_t)0x000F) /*!< Fraction of USARTDIV */\r
+#define USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */\r
+\r
+/****************** Bit definition for USART_CR1 register *******************/\r
+#define USART_CR1_SBK ((uint16_t)0x0001) /*!< Send Break */\r
+#define USART_CR1_RWU ((uint16_t)0x0002) /*!< Receiver wakeup */\r
+#define USART_CR1_RE ((uint16_t)0x0004) /*!< Receiver Enable */\r
+#define USART_CR1_TE ((uint16_t)0x0008) /*!< Transmitter Enable */\r
+#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!< IDLE Interrupt Enable */\r
+#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!< RXNE Interrupt Enable */\r
+#define USART_CR1_TCIE ((uint16_t)0x0040) /*!< Transmission Complete Interrupt Enable */\r
+#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!< PE Interrupt Enable */\r
+#define USART_CR1_PEIE ((uint16_t)0x0100) /*!< PE Interrupt Enable */\r
+#define USART_CR1_PS ((uint16_t)0x0200) /*!< Parity Selection */\r
+#define USART_CR1_PCE ((uint16_t)0x0400) /*!< Parity Control Enable */\r
+#define USART_CR1_WAKE ((uint16_t)0x0800) /*!< Wakeup method */\r
+#define USART_CR1_M ((uint16_t)0x1000) /*!< Word length */\r
+#define USART_CR1_UE ((uint16_t)0x2000) /*!< USART Enable */\r
+#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!< Oversampling by 8-bit mode */\r
+\r
+/****************** Bit definition for USART_CR2 register *******************/\r
+#define USART_CR2_ADD ((uint16_t)0x000F) /*!< Address of the USART node */\r
+#define USART_CR2_LBDL ((uint16_t)0x0020) /*!< LIN Break Detection Length */\r
+#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!< LIN Break Detection Interrupt Enable */\r
+#define USART_CR2_LBCL ((uint16_t)0x0100) /*!< Last Bit Clock pulse */\r
+#define USART_CR2_CPHA ((uint16_t)0x0200) /*!< Clock Phase */\r
+#define USART_CR2_CPOL ((uint16_t)0x0400) /*!< Clock Polarity */\r
+#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!< Clock Enable */\r
+\r
+#define USART_CR2_STOP ((uint16_t)0x3000) /*!< STOP[1:0] bits (STOP bits) */\r
+#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!< Bit 0 */\r
+#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!< Bit 1 */\r
+\r
+#define USART_CR2_LINEN ((uint16_t)0x4000) /*!< LIN mode enable */\r
+\r
+/****************** Bit definition for USART_CR3 register *******************/\r
+#define USART_CR3_EIE ((uint16_t)0x0001) /*!< Error Interrupt Enable */\r
+#define USART_CR3_IREN ((uint16_t)0x0002) /*!< IrDA mode Enable */\r
+#define USART_CR3_IRLP ((uint16_t)0x0004) /*!< IrDA Low-Power */\r
+#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!< Half-Duplex Selection */\r
+#define USART_CR3_NACK ((uint16_t)0x0010) /*!< Smartcard NACK enable */\r
+#define USART_CR3_SCEN ((uint16_t)0x0020) /*!< Smartcard mode enable */\r
+#define USART_CR3_DMAR ((uint16_t)0x0040) /*!< DMA Enable Receiver */\r
+#define USART_CR3_DMAT ((uint16_t)0x0080) /*!< DMA Enable Transmitter */\r
+#define USART_CR3_RTSE ((uint16_t)0x0100) /*!< RTS Enable */\r
+#define USART_CR3_CTSE ((uint16_t)0x0200) /*!< CTS Enable */\r
+#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!< CTS Interrupt Enable */\r
+#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!< One sample bit method enable */\r
+\r
+/****************** Bit definition for USART_GTPR register ******************/\r
+#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */\r
+#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!< Bit 0 */\r
+#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!< Bit 1 */\r
+#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!< Bit 2 */\r
+#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!< Bit 3 */\r
+#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!< Bit 4 */\r
+#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!< Bit 5 */\r
+#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!< Bit 6 */\r
+#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!< Bit 7 */\r
+\r
+#define USART_GTPR_GT ((uint16_t)0xFF00) /*!< Guard time value */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Universal Serial Bus (USB) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/*!<Endpoint-specific registers */\r
+/******************* Bit definition for USB_EP0R register *******************/\r
+#define USB_EP0R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
+\r
+#define USB_EP0R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+\r
+#define USB_EP0R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
+#define USB_EP0R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
+#define USB_EP0R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
+\r
+#define USB_EP0R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
+#define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
+\r
+#define USB_EP0R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
+\r
+#define USB_EP0R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define USB_EP0R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
+#define USB_EP0R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
+\r
+/******************* Bit definition for USB_EP1R register *******************/\r
+#define USB_EP1R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
+\r
+#define USB_EP1R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+\r
+#define USB_EP1R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
+#define USB_EP1R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
+#define USB_EP1R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
+\r
+#define USB_EP1R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
+#define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
+\r
+#define USB_EP1R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
+\r
+#define USB_EP1R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define USB_EP1R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
+#define USB_EP1R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
+\r
+/******************* Bit definition for USB_EP2R register *******************/\r
+#define USB_EP2R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
+\r
+#define USB_EP2R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+\r
+#define USB_EP2R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
+#define USB_EP2R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
+#define USB_EP2R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
+\r
+#define USB_EP2R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
+#define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
+\r
+#define USB_EP2R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
+\r
+#define USB_EP2R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define USB_EP2R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
+#define USB_EP2R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
+\r
+/******************* Bit definition for USB_EP3R register *******************/\r
+#define USB_EP3R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
+\r
+#define USB_EP3R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+\r
+#define USB_EP3R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
+#define USB_EP3R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
+#define USB_EP3R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
+\r
+#define USB_EP3R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
+#define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
+\r
+#define USB_EP3R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
+\r
+#define USB_EP3R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define USB_EP3R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
+#define USB_EP3R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
+\r
+/******************* Bit definition for USB_EP4R register *******************/\r
+#define USB_EP4R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
+\r
+#define USB_EP4R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+\r
+#define USB_EP4R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
+#define USB_EP4R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
+#define USB_EP4R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
+\r
+#define USB_EP4R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
+#define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
+\r
+#define USB_EP4R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
+\r
+#define USB_EP4R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define USB_EP4R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
+#define USB_EP4R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
+\r
+/******************* Bit definition for USB_EP5R register *******************/\r
+#define USB_EP5R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
+\r
+#define USB_EP5R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+\r
+#define USB_EP5R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
+#define USB_EP5R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
+#define USB_EP5R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
+\r
+#define USB_EP5R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
+#define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
+\r
+#define USB_EP5R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
+\r
+#define USB_EP5R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define USB_EP5R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
+#define USB_EP5R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
+\r
+/******************* Bit definition for USB_EP6R register *******************/\r
+#define USB_EP6R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
+\r
+#define USB_EP6R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+\r
+#define USB_EP6R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
+#define USB_EP6R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
+#define USB_EP6R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
+\r
+#define USB_EP6R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
+#define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
+\r
+#define USB_EP6R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
+\r
+#define USB_EP6R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define USB_EP6R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
+#define USB_EP6R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
+\r
+/******************* Bit definition for USB_EP7R register *******************/\r
+#define USB_EP7R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
+\r
+#define USB_EP7R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+\r
+#define USB_EP7R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
+#define USB_EP7R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
+#define USB_EP7R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
+\r
+#define USB_EP7R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
+#define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
+\r
+#define USB_EP7R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
+\r
+#define USB_EP7R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define USB_EP7R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
+#define USB_EP7R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
+\r
+/*!<Common registers */\r
+/******************* Bit definition for USB_CNTR register *******************/\r
+#define USB_CNTR_FRES ((uint16_t)0x0001) /*!<Force USB Reset */\r
+#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!<Power down */\r
+#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!<Low-power mode */\r
+#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!<Force suspend */\r
+#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!<Resume request */\r
+#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!<Expected Start Of Frame Interrupt Mask */\r
+#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!<Start Of Frame Interrupt Mask */\r
+#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!<RESET Interrupt Mask */\r
+#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!<Suspend mode Interrupt Mask */\r
+#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!<Wakeup Interrupt Mask */\r
+#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!<Error Interrupt Mask */\r
+#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!<Packet Memory Area Over / Underrun Interrupt Mask */\r
+#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!<Correct Transfer Interrupt Mask */\r
+\r
+/******************* Bit definition for USB_ISTR register *******************/\r
+#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!<Endpoint Identifier */\r
+#define USB_ISTR_DIR ((uint16_t)0x0010) /*!<Direction of transaction */\r
+#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!<Expected Start Of Frame */\r
+#define USB_ISTR_SOF ((uint16_t)0x0200) /*!<Start Of Frame */\r
+#define USB_ISTR_RESET ((uint16_t)0x0400) /*!<USB RESET request */\r
+#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!<Suspend mode request */\r
+#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!<Wake up */\r
+#define USB_ISTR_ERR ((uint16_t)0x2000) /*!<Error */\r
+#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!<Packet Memory Area Over / Underrun */\r
+#define USB_ISTR_CTR ((uint16_t)0x8000) /*!<Correct Transfer */\r
+\r
+/******************* Bit definition for USB_FNR register ********************/\r
+#define USB_FNR_FN ((uint16_t)0x07FF) /*!<Frame Number */\r
+#define USB_FNR_LSOF ((uint16_t)0x1800) /*!<Lost SOF */\r
+#define USB_FNR_LCK ((uint16_t)0x2000) /*!<Locked */\r
+#define USB_FNR_RXDM ((uint16_t)0x4000) /*!<Receive Data - Line Status */\r
+#define USB_FNR_RXDP ((uint16_t)0x8000) /*!<Receive Data + Line Status */\r
+\r
+/****************** Bit definition for USB_DADDR register *******************/\r
+#define USB_DADDR_ADD ((uint8_t)0x7F) /*!<ADD[6:0] bits (Device Address) */\r
+#define USB_DADDR_ADD0 ((uint8_t)0x01) /*!<Bit 0 */\r
+#define USB_DADDR_ADD1 ((uint8_t)0x02) /*!<Bit 1 */\r
+#define USB_DADDR_ADD2 ((uint8_t)0x04) /*!<Bit 2 */\r
+#define USB_DADDR_ADD3 ((uint8_t)0x08) /*!<Bit 3 */\r
+#define USB_DADDR_ADD4 ((uint8_t)0x10) /*!<Bit 4 */\r
+#define USB_DADDR_ADD5 ((uint8_t)0x20) /*!<Bit 5 */\r
+#define USB_DADDR_ADD6 ((uint8_t)0x40) /*!<Bit 6 */\r
+\r
+#define USB_DADDR_EF ((uint8_t)0x80) /*!<Enable Function */\r
+\r
+/****************** Bit definition for USB_BTABLE register ******************/ \r
+#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) /*!<Buffer Table */\r
+\r
+/*!< Buffer descriptor table */\r
+/***************** Bit definition for USB_ADDR0_TX register *****************/\r
+#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 0 */\r
+\r
+/***************** Bit definition for USB_ADDR1_TX register *****************/\r
+#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 1 */\r
+\r
+/***************** Bit definition for USB_ADDR2_TX register *****************/\r
+#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 2 */\r
+\r
+/***************** Bit definition for USB_ADDR3_TX register *****************/\r
+#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 3 */\r
+\r
+/***************** Bit definition for USB_ADDR4_TX register *****************/\r
+#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 4 */\r
+\r
+/***************** Bit definition for USB_ADDR5_TX register *****************/\r
+#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 5 */\r
+\r
+/***************** Bit definition for USB_ADDR6_TX register *****************/\r
+#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 6 */\r
+\r
+/***************** Bit definition for USB_ADDR7_TX register *****************/\r
+#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 7 */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/***************** Bit definition for USB_COUNT0_TX register ****************/\r
+#define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 0 */\r
+\r
+/***************** Bit definition for USB_COUNT1_TX register ****************/\r
+#define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 1 */\r
+\r
+/***************** Bit definition for USB_COUNT2_TX register ****************/\r
+#define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 2 */\r
+\r
+/***************** Bit definition for USB_COUNT3_TX register ****************/\r
+#define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 3 */\r
+\r
+/***************** Bit definition for USB_COUNT4_TX register ****************/\r
+#define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 4 */\r
+\r
+/***************** Bit definition for USB_COUNT5_TX register ****************/\r
+#define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 5 */\r
+\r
+/***************** Bit definition for USB_COUNT6_TX register ****************/\r
+#define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 6 */\r
+\r
+/***************** Bit definition for USB_COUNT7_TX register ****************/\r
+#define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 7 */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/**************** Bit definition for USB_COUNT0_TX_0 register ***************/\r
+#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */\r
+\r
+/**************** Bit definition for USB_COUNT0_TX_1 register ***************/\r
+#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */\r
+\r
+/**************** Bit definition for USB_COUNT1_TX_0 register ***************/\r
+#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */\r
+\r
+/**************** Bit definition for USB_COUNT1_TX_1 register ***************/\r
+#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */\r
+\r
+/**************** Bit definition for USB_COUNT2_TX_0 register ***************/\r
+#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */\r
+\r
+/**************** Bit definition for USB_COUNT2_TX_1 register ***************/\r
+#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */\r
+\r
+/**************** Bit definition for USB_COUNT3_TX_0 register ***************/\r
+#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */\r
+\r
+/**************** Bit definition for USB_COUNT3_TX_1 register ***************/\r
+#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */\r
+\r
+/**************** Bit definition for USB_COUNT4_TX_0 register ***************/\r
+#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */\r
+\r
+/**************** Bit definition for USB_COUNT4_TX_1 register ***************/\r
+#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */\r
+\r
+/**************** Bit definition for USB_COUNT5_TX_0 register ***************/\r
+#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */\r
+\r
+/**************** Bit definition for USB_COUNT5_TX_1 register ***************/\r
+#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */\r
+\r
+/**************** Bit definition for USB_COUNT6_TX_0 register ***************/\r
+#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */\r
+\r
+/**************** Bit definition for USB_COUNT6_TX_1 register ***************/\r
+#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */\r
+\r
+/**************** Bit definition for USB_COUNT7_TX_0 register ***************/\r
+#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */\r
+\r
+/**************** Bit definition for USB_COUNT7_TX_1 register ***************/\r
+#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/***************** Bit definition for USB_ADDR0_RX register *****************/\r
+#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 0 */\r
+\r
+/***************** Bit definition for USB_ADDR1_RX register *****************/\r
+#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 1 */\r
+\r
+/***************** Bit definition for USB_ADDR2_RX register *****************/\r
+#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 2 */\r
+\r
+/***************** Bit definition for USB_ADDR3_RX register *****************/\r
+#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 3 */\r
+\r
+/***************** Bit definition for USB_ADDR4_RX register *****************/\r
+#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 4 */\r
+\r
+/***************** Bit definition for USB_ADDR5_RX register *****************/\r
+#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 5 */\r
+\r
+/***************** Bit definition for USB_ADDR6_RX register *****************/\r
+#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 6 */\r
+\r
+/***************** Bit definition for USB_ADDR7_RX register *****************/\r
+#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 7 */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/***************** Bit definition for USB_COUNT0_RX register ****************/\r
+#define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */\r
+\r
+#define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */\r
+#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */\r
+#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */\r
+\r
+/***************** Bit definition for USB_COUNT1_RX register ****************/\r
+#define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */\r
+\r
+#define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */\r
+#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */\r
+#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */\r
+\r
+/***************** Bit definition for USB_COUNT2_RX register ****************/\r
+#define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */\r
+\r
+#define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */\r
+#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */\r
+#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */\r
+\r
+/***************** Bit definition for USB_COUNT3_RX register ****************/\r
+#define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */\r
+\r
+#define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */\r
+#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */\r
+#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */\r
+\r
+/***************** Bit definition for USB_COUNT4_RX register ****************/\r
+#define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */\r
+\r
+#define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */\r
+#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */\r
+#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */\r
+\r
+/***************** Bit definition for USB_COUNT5_RX register ****************/\r
+#define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */\r
+\r
+#define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */\r
+#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */\r
+#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */\r
+\r
+/***************** Bit definition for USB_COUNT6_RX register ****************/\r
+#define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */\r
+\r
+#define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */\r
+#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */\r
+#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */\r
+\r
+/***************** Bit definition for USB_COUNT7_RX register ****************/\r
+#define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */\r
+\r
+#define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */\r
+#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */\r
+#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/**************** Bit definition for USB_COUNT0_RX_0 register ***************/\r
+#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */\r
+\r
+#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */\r
+\r
+/**************** Bit definition for USB_COUNT0_RX_1 register ***************/\r
+#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */\r
+\r
+#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */\r
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */\r
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */\r
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */\r
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */\r
+\r
+/**************** Bit definition for USB_COUNT1_RX_0 register ***************/\r
+#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */\r
+\r
+#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */\r
+\r
+/**************** Bit definition for USB_COUNT1_RX_1 register ***************/\r
+#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */\r
+\r
+#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */\r
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */\r
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */\r
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */\r
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */\r
+\r
+/**************** Bit definition for USB_COUNT2_RX_0 register ***************/\r
+#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */\r
+\r
+#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */\r
+\r
+/**************** Bit definition for USB_COUNT2_RX_1 register ***************/\r
+#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */\r
+\r
+#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */\r
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */\r
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */\r
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */\r
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */\r
+\r
+/**************** Bit definition for USB_COUNT3_RX_0 register ***************/\r
+#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */\r
+\r
+#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */\r
+\r
+/**************** Bit definition for USB_COUNT3_RX_1 register ***************/\r
+#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */\r
+\r
+#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */\r
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */\r
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */\r
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */\r
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */\r
+\r
+/**************** Bit definition for USB_COUNT4_RX_0 register ***************/\r
+#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */\r
+\r
+#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */\r
+\r
+/**************** Bit definition for USB_COUNT4_RX_1 register ***************/\r
+#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */\r
+\r
+#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */\r
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */\r
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */\r
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */\r
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */\r
+\r
+/**************** Bit definition for USB_COUNT5_RX_0 register ***************/\r
+#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */\r
+\r
+#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */\r
+\r
+/**************** Bit definition for USB_COUNT5_RX_1 register ***************/\r
+#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */\r
+\r
+#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */\r
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */\r
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */\r
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */\r
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */\r
+\r
+/*************** Bit definition for USB_COUNT6_RX_0 register ***************/\r
+#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */\r
+\r
+#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */\r
+\r
+/**************** Bit definition for USB_COUNT6_RX_1 register ***************/\r
+#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */\r
+\r
+#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */\r
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */\r
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */\r
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */\r
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */\r
+\r
+/*************** Bit definition for USB_COUNT7_RX_0 register ****************/\r
+#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */\r
+\r
+#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */\r
+\r
+/*************** Bit definition for USB_COUNT7_RX_1 register ****************/\r
+#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */\r
+\r
+#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */\r
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */\r
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */\r
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */\r
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Window WATCHDOG (WWDG) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for WWDG_CR register ********************/\r
+#define WWDG_CR_T ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */\r
+#define WWDG_CR_T0 ((uint8_t)0x01) /*!< Bit 0 */\r
+#define WWDG_CR_T1 ((uint8_t)0x02) /*!< Bit 1 */\r
+#define WWDG_CR_T2 ((uint8_t)0x04) /*!< Bit 2 */\r
+#define WWDG_CR_T3 ((uint8_t)0x08) /*!< Bit 3 */\r
+#define WWDG_CR_T4 ((uint8_t)0x10) /*!< Bit 4 */\r
+#define WWDG_CR_T5 ((uint8_t)0x20) /*!< Bit 5 */\r
+#define WWDG_CR_T6 ((uint8_t)0x40) /*!< Bit 6 */\r
+\r
+#define WWDG_CR_WDGA ((uint8_t)0x80) /*!< Activation bit */\r
+\r
+/******************* Bit definition for WWDG_CFR register *******************/\r
+#define WWDG_CFR_W ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */\r
+#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!< Bit 0 */\r
+#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!< Bit 1 */\r
+#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!< Bit 2 */\r
+#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!< Bit 3 */\r
+#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!< Bit 4 */\r
+#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!< Bit 5 */\r
+#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!< Bit 6 */\r
+\r
+#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!< WDGTB[1:0] bits (Timer Base) */\r
+#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!< Bit 0 */\r
+#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!< Bit 1 */\r
+\r
+#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */\r
+\r
+/******************* Bit definition for WWDG_SR register ********************/\r
+#define WWDG_SR_EWIF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* SystemTick (SysTick) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/***************** Bit definition for SysTick_CTRL register *****************/\r
+#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */\r
+#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */\r
+#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */\r
+#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */\r
+\r
+/***************** Bit definition for SysTick_LOAD register *****************/\r
+#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */\r
+\r
+/***************** Bit definition for SysTick_VAL register ******************/\r
+#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */\r
+\r
+/***************** Bit definition for SysTick_CALIB register ****************/\r
+#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */\r
+#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */\r
+#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Nested Vectored Interrupt Controller (NVIC) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/****************** Bit definition for NVIC_ISER register *******************/\r
+#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */\r
+#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */\r
+#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */\r
+#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */\r
+#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */\r
+#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */\r
+#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */\r
+#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */\r
+#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */\r
+#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */\r
+#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */\r
+#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */\r
+#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */\r
+#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */\r
+#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */\r
+#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */\r
+#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */\r
+#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */\r
+#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */\r
+#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */\r
+#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */\r
+#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */\r
+#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */\r
+#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */\r
+#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */\r
+#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */\r
+#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */\r
+#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */\r
+#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */\r
+#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */\r
+#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */\r
+#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */\r
+#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */\r
+\r
+/****************** Bit definition for NVIC_ICER register *******************/\r
+#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */\r
+#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */\r
+#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */\r
+#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */\r
+#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */\r
+#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */\r
+#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */\r
+#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */\r
+#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */\r
+#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */\r
+#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */\r
+#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */\r
+#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */\r
+#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */\r
+#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */\r
+#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */\r
+#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */\r
+#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */\r
+#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */\r
+#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */\r
+#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */\r
+#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */\r
+#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */\r
+#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */\r
+#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */\r
+#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */\r
+#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */\r
+#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */\r
+#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */\r
+#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */\r
+#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */\r
+#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */\r
+#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */\r
+\r
+/****************** Bit definition for NVIC_ISPR register *******************/\r
+#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */\r
+#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */\r
+#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */\r
+#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */\r
+#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */\r
+#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */\r
+#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */\r
+#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */\r
+#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */\r
+#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */\r
+#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */\r
+#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */\r
+#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */\r
+#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */\r
+#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */\r
+#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */\r
+#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */\r
+#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */\r
+#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */\r
+#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */\r
+#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */\r
+#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */\r
+#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */\r
+#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */\r
+#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */\r
+#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */\r
+#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */\r
+#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */\r
+#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */\r
+#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */\r
+#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */\r
+#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */\r
+#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */\r
+\r
+/****************** Bit definition for NVIC_ICPR register *******************/\r
+#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */\r
+#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */\r
+#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */\r
+#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */\r
+#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */\r
+#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */\r
+#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */\r
+#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */\r
+#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */\r
+#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */\r
+#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */\r
+#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */\r
+#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */\r
+#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */\r
+#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */\r
+#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */\r
+#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */\r
+#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */\r
+#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */\r
+#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */\r
+#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */\r
+#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */\r
+#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */\r
+#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */\r
+#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */\r
+#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */\r
+#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */\r
+#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */\r
+#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */\r
+#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */\r
+#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */\r
+#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */\r
+#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */\r
+\r
+/****************** Bit definition for NVIC_IABR register *******************/\r
+#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */\r
+#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */\r
+#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */\r
+#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */\r
+#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */\r
+#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */\r
+#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */\r
+#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */\r
+#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */\r
+#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */\r
+#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */\r
+#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */\r
+#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */\r
+#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */\r
+#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */\r
+#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */\r
+#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */\r
+#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */\r
+#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */\r
+#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */\r
+#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */\r
+#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */\r
+#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */\r
+#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */\r
+#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */\r
+#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */\r
+#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */\r
+#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */\r
+#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */\r
+#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */\r
+#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */\r
+#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */\r
+#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */\r
+\r
+/****************** Bit definition for NVIC_PRI0 register *******************/\r
+#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */\r
+#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */\r
+#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */\r
+#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */\r
+\r
+/****************** Bit definition for NVIC_PRI1 register *******************/\r
+#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */\r
+#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */\r
+#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */\r
+#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */\r
+\r
+/****************** Bit definition for NVIC_PRI2 register *******************/\r
+#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */\r
+#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */\r
+#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */\r
+#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */\r
+\r
+/****************** Bit definition for NVIC_PRI3 register *******************/\r
+#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */\r
+#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */\r
+#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */\r
+#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */\r
+\r
+/****************** Bit definition for NVIC_PRI4 register *******************/\r
+#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */\r
+#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */\r
+#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */\r
+#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */\r
+\r
+/****************** Bit definition for NVIC_PRI5 register *******************/\r
+#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */\r
+#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */\r
+#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */\r
+#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */\r
+\r
+/****************** Bit definition for NVIC_PRI6 register *******************/\r
+#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */\r
+#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */\r
+#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */\r
+#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */\r
+\r
+/****************** Bit definition for NVIC_PRI7 register *******************/\r
+#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */\r
+#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */\r
+#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */\r
+#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */\r
+\r
+/****************** Bit definition for SCB_CPUID register *******************/\r
+#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */\r
+#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */\r
+#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */\r
+#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */\r
+#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */\r
+\r
+/******************* Bit definition for SCB_ICSR register *******************/\r
+#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */\r
+#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */\r
+#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */\r
+#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */\r
+#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */\r
+#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */\r
+#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */\r
+#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */\r
+#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */\r
+#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */\r
+\r
+/******************* Bit definition for SCB_VTOR register *******************/\r
+#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */\r
+#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */\r
+\r
+/*!<***************** Bit definition for SCB_AIRCR register *******************/\r
+#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */\r
+#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */\r
+#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */\r
+\r
+#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */\r
+#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
+#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
+#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */\r
+\r
+/* prority group configuration */\r
+#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */\r
+#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */\r
+#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */\r
+#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */\r
+#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */\r
+#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */\r
+#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */\r
+#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */\r
+\r
+#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */\r
+#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */\r
+\r
+/******************* Bit definition for SCB_SCR register ********************/\r
+#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */\r
+#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */\r
+#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */\r
+\r
+/******************** Bit definition for SCB_CCR register *******************/\r
+#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */\r
+#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */\r
+#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */\r
+#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */\r
+#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */\r
+#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */\r
+\r
+/******************* Bit definition for SCB_SHPR register ********************/\r
+#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */\r
+#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */\r
+#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */\r
+#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */\r
+\r
+/****************** Bit definition for SCB_SHCSR register *******************/\r
+#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */\r
+#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */\r
+#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */\r
+#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */\r
+#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */\r
+#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */\r
+#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */\r
+#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */\r
+#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */\r
+#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */\r
+#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */\r
+#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */\r
+#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */\r
+#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */\r
+\r
+/******************* Bit definition for SCB_CFSR register *******************/\r
+/*!< MFSR */\r
+#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */\r
+#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */\r
+#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */\r
+#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */\r
+#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */\r
+/*!< BFSR */\r
+#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */\r
+#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */\r
+#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */\r
+#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */\r
+#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */\r
+#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */\r
+/*!< UFSR */\r
+#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to excecute an undefined instruction */\r
+#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */\r
+#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */\r
+#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */\r
+#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */\r
+#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */\r
+\r
+/******************* Bit definition for SCB_HFSR register *******************/\r
+#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occures because of vector table read on exception processing */\r
+#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */\r
+#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */\r
+\r
+/******************* Bit definition for SCB_DFSR register *******************/\r
+#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */\r
+#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */\r
+#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */\r
+#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */\r
+#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */\r
+\r
+/******************* Bit definition for SCB_MMFAR register ******************/\r
+#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */\r
+\r
+/******************* Bit definition for SCB_BFAR register *******************/\r
+#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */\r
+\r
+/******************* Bit definition for SCB_afsr register *******************/\r
+#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */\r
+/**\r
+ * @}\r
+ */\r
+\r
+ /**\r
+ * @}\r
+ */ \r
+\r
+#ifdef USE_STDPERIPH_DRIVER\r
+ #include "stm32l1xx_conf.h"\r
+#endif\r
+\r
+/** @addtogroup Exported_macro\r
+ * @{\r
+ */\r
+\r
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))\r
+\r
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))\r
+\r
+#define READ_BIT(REG, BIT) ((REG) & (BIT))\r
+\r
+#define CLEAR_REG(REG) ((REG) = (0x0))\r
+\r
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))\r
+\r
+#define READ_REG(REG) ((REG))\r
+\r
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1XX_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+ /**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file system_stm32l1xx.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.\r
+ ****************************************************************************** \r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */\r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32l1xx_system\r
+ * @{\r
+ */ \r
+ \r
+/**\r
+ * @brief Define to prevent recursive inclusion\r
+ */\r
+#ifndef __SYSTEM_STM32L1XX_H\r
+#define __SYSTEM_STM32L1XX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+/** @addtogroup STM32L1xx_System_Includes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @addtogroup STM32L1xx_System_Exported_types\r
+ * @{\r
+ */\r
+\r
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32L1xx_System_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32L1xx_System_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32L1xx_System_Exported_Functions\r
+ * @{\r
+ */\r
+ \r
+extern void SystemInit(void);\r
+extern void SystemCoreClockUpdate(void);\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__SYSTEM_STM32L1XX_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file misc.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the miscellaneous\r
+ * firmware library functions (add-on to CMSIS functions).\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __MISC_H\r
+#define __MISC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup MISC\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief NVIC Init Structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.\r
+ This parameter can be a value of @ref IRQn_Type \r
+ (For the complete STM32 Devices IRQ Channels list, please\r
+ refer to stm32l1xx.h file) */\r
+\r
+ uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel\r
+ specified in NVIC_IRQChannel. This parameter can be a value\r
+ between 0 and 15 as described in the table @ref NVIC_Priority_Table */\r
+\r
+ uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified\r
+ in NVIC_IRQChannel. This parameter can be a value\r
+ between 0 and 15 as described in the table @ref NVIC_Priority_Table */\r
+\r
+ FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel\r
+ will be enabled or disabled. \r
+ This parameter can be set either to ENABLE or DISABLE */ \r
+} NVIC_InitTypeDef;\r
+\r
+/** \r
+ *\r
+@verbatim \r
+ The table below gives the allowed values of the pre-emption priority and subpriority according\r
+ to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function\r
+ ============================================================================================================================\r
+ NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description\r
+ ============================================================================================================================\r
+ NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority\r
+ | | | 4 bits for subpriority\r
+ ----------------------------------------------------------------------------------------------------------------------------\r
+ NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority\r
+ | | | 3 bits for subpriority\r
+ ---------------------------------------------------------------------------------------------------------------------------- \r
+ NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority\r
+ | | | 2 bits for subpriority\r
+ ---------------------------------------------------------------------------------------------------------------------------- \r
+ NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority\r
+ | | | 1 bits for subpriority\r
+ ---------------------------------------------------------------------------------------------------------------------------- \r
+ NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority\r
+ | | | 0 bits for subpriority \r
+ ============================================================================================================================\r
+@endverbatim\r
+*/\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup MISC_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup Vector_Table_Base \r
+ * @{\r
+ */\r
+\r
+#define NVIC_VectTab_RAM ((uint32_t)0x20000000)\r
+#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)\r
+#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \\r
+ ((VECTTAB) == NVIC_VectTab_FLASH))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup System_Low_Power \r
+ * @{\r
+ */\r
+\r
+#define NVIC_LP_SEVONPEND ((uint8_t)0x10)\r
+#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)\r
+#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)\r
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \\r
+ ((LP) == NVIC_LP_SLEEPDEEP) || \\r
+ ((LP) == NVIC_LP_SLEEPONEXIT))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Preemption_Priority_Group \r
+ * @{\r
+ */\r
+\r
+#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority\r
+ 4 bits for subpriority */\r
+#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority\r
+ 3 bits for subpriority */\r
+#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority\r
+ 2 bits for subpriority */\r
+#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority\r
+ 1 bits for subpriority */\r
+#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority\r
+ 0 bits for subpriority */\r
+\r
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \\r
+ ((GROUP) == NVIC_PriorityGroup_1) || \\r
+ ((GROUP) == NVIC_PriorityGroup_2) || \\r
+ ((GROUP) == NVIC_PriorityGroup_3) || \\r
+ ((GROUP) == NVIC_PriorityGroup_4))\r
+\r
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)\r
+\r
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)\r
+\r
+#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0001FFFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SysTick_clock_source \r
+ * @{\r
+ */\r
+\r
+#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)\r
+#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)\r
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \\r
+ ((SOURCE) == SysTick_CLKSource_HCLK_Div8))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */ \r
+\r
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);\r
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);\r
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);\r
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);\r
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __MISC_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_adc.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the ADC firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_ADC_H\r
+#define __STM32L1xx_ADC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup ADC\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief ADC Init structure definition \r
+ */\r
+ \r
+typedef struct\r
+{\r
+ uint32_t ADC_Resolution; /*!< Selects the resolution of the conversion.\r
+ This parameter can be a value of @ref ADC_Resolution */\r
+ \r
+ FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in\r
+ Scan (multichannel) or Single (one channel) mode.\r
+ This parameter can be set to ENABLE or DISABLE */\r
+ \r
+ FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in\r
+ Continuous or Single mode.\r
+ This parameter can be set to ENABLE or DISABLE. */\r
+ \r
+ uint32_t ADC_ExternalTrigConvEdge; /*!< Selects the external trigger Edge and enables the\r
+ trigger of a regular group. This parameter can be a value\r
+ of @ref ADC_external_trigger_edge_for_regular_channels_conversion */\r
+ \r
+ uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog\r
+ to digital conversion of regular channels. This parameter\r
+ can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */\r
+ \r
+ uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.\r
+ This parameter can be a value of @ref ADC_data_align */\r
+ \r
+ uint8_t ADC_NbrOfConversion; /*!< Specifies the number of ADC conversions that will be done\r
+ using the sequencer for regular channel group.\r
+ This parameter must range from 1 to 27. */\r
+}ADC_InitTypeDef;\r
+\r
+typedef struct \r
+{ \r
+ uint32_t ADC_Prescaler; /*!< Selects the ADC prescaler.\r
+ This parameter can be a value \r
+ of @ref ADC_Prescaler */\r
+}ADC_CommonInitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup ADC_Exported_Constants\r
+ * @{\r
+ */ \r
+#define IS_ADC_ALL_PERIPH(PERIPH) ((PERIPH) == ADC1)\r
+#define IS_ADC_DMA_PERIPH(PERIPH) ((PERIPH) == ADC1)\r
+\r
+/** @defgroup ADC_Power_down_during_Idle_and_or_Delay_phase \r
+ * @{\r
+ */ \r
+#define ADC_PowerDown_Delay ((uint32_t)0x00010000)\r
+#define ADC_PowerDown_Idle ((uint32_t)0x00020000)\r
+#define ADC_PowerDown_Idle_Delay ((uint32_t)0x00030000)\r
+\r
+#define IS_ADC_POWER_DOWN(DWON) (((DWON) == ADC_PowerDown_Delay) || \\r
+ ((DWON) == ADC_PowerDown_Idle) || \\r
+ ((DWON) == ADC_PowerDown_Idle_Delay))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ADC_Prescaler \r
+ * @{\r
+ */ \r
+#define ADC_Prescaler_Div1 ((uint32_t)0x00000000)\r
+#define ADC_Prescaler_Div2 ((uint32_t)0x00010000)\r
+#define ADC_Prescaler_Div4 ((uint32_t)0x00020000)\r
+\r
+#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div1) || \\r
+ ((PRESCALER) == ADC_Prescaler_Div2) || \\r
+ ((PRESCALER) == ADC_Prescaler_Div4))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+\r
+/** @defgroup ADC_resolution \r
+ * @{\r
+ */ \r
+#define ADC_Resolution_12b ((uint32_t)0x00000000)\r
+#define ADC_Resolution_10b ((uint32_t)0x01000000)\r
+#define ADC_Resolution_8b ((uint32_t)0x02000000)\r
+#define ADC_Resolution_6b ((uint32_t)0x03000000)\r
+\r
+#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \\r
+ ((RESOLUTION) == ADC_Resolution_10b) || \\r
+ ((RESOLUTION) == ADC_Resolution_8b) || \\r
+ ((RESOLUTION) == ADC_Resolution_6b))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion \r
+ * @{\r
+ */ \r
+#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000)\r
+#define ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000)\r
+#define ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000)\r
+#define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000)\r
+\r
+#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \\r
+ ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \\r
+ ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \\r
+ ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion\r
+ * @{\r
+ */ \r
+\r
+/* TIM2 */\r
+#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x02000000)\r
+#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000)\r
+#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000)\r
+\r
+/* TIM3 */\r
+#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000)\r
+#define ADC_ExternalTrigConv_T3_CC3 ((uint32_t)0x08000000)\r
+#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x04000000)\r
+\r
+/* TIM4 */\r
+#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x05000000)\r
+#define ADC_ExternalTrigConv_T4_TRGO ((uint32_t)0x09000000)\r
+\r
+/* TIM6 */\r
+#define ADC_ExternalTrigConv_T6_TRGO ((uint32_t)0x0A000000)\r
+\r
+/* TIM9 */\r
+#define ADC_ExternalTrigConv_T9_CC2 ((uint32_t)0x00000000)\r
+#define ADC_ExternalTrigConv_T9_TRGO ((uint32_t)0x01000000)\r
+\r
+/* EXTI */\r
+#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000)\r
+\r
+#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T9_CC2) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T9_TRGO) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T3_CC3) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T4_TRGO) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T6_TRGO) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_data_align \r
+ * @{\r
+ */ \r
+ \r
+#define ADC_DataAlign_Right ((uint32_t)0x00000000)\r
+#define ADC_DataAlign_Left ((uint32_t)0x00000800)\r
+\r
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \\r
+ ((ALIGN) == ADC_DataAlign_Left))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_channels \r
+ * @{\r
+ */ \r
+ \r
+#define ADC_Channel_0 ((uint8_t)0x00)\r
+#define ADC_Channel_1 ((uint8_t)0x01)\r
+#define ADC_Channel_2 ((uint8_t)0x02)\r
+#define ADC_Channel_3 ((uint8_t)0x03)\r
+#define ADC_Channel_4 ((uint8_t)0x04)\r
+#define ADC_Channel_5 ((uint8_t)0x05)\r
+#define ADC_Channel_6 ((uint8_t)0x06)\r
+#define ADC_Channel_7 ((uint8_t)0x07)\r
+#define ADC_Channel_8 ((uint8_t)0x08)\r
+#define ADC_Channel_9 ((uint8_t)0x09)\r
+#define ADC_Channel_10 ((uint8_t)0x0A)\r
+#define ADC_Channel_11 ((uint8_t)0x0B)\r
+#define ADC_Channel_12 ((uint8_t)0x0C)\r
+#define ADC_Channel_13 ((uint8_t)0x0D)\r
+#define ADC_Channel_14 ((uint8_t)0x0E)\r
+#define ADC_Channel_15 ((uint8_t)0x0F)\r
+#define ADC_Channel_16 ((uint8_t)0x10)\r
+#define ADC_Channel_17 ((uint8_t)0x11)\r
+#define ADC_Channel_18 ((uint8_t)0x12)\r
+#define ADC_Channel_19 ((uint8_t)0x13)\r
+#define ADC_Channel_20 ((uint8_t)0x14)\r
+#define ADC_Channel_21 ((uint8_t)0x15)\r
+#define ADC_Channel_22 ((uint8_t)0x16)\r
+#define ADC_Channel_23 ((uint8_t)0x17)\r
+#define ADC_Channel_24 ((uint8_t)0x18)\r
+#define ADC_Channel_25 ((uint8_t)0x19)\r
+\r
+#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)\r
+#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)\r
+\r
+\r
+\r
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \\r
+ ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \\r
+ ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \\r
+ ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \\r
+ ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \\r
+ ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \\r
+ ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \\r
+ ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \\r
+ ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17) || \\r
+ ((CHANNEL) == ADC_Channel_18) || ((CHANNEL) == ADC_Channel_19) || \\r
+ ((CHANNEL) == ADC_Channel_20) || ((CHANNEL) == ADC_Channel_21) || \\r
+ ((CHANNEL) == ADC_Channel_22) || ((CHANNEL) == ADC_Channel_23) || \\r
+ ((CHANNEL) == ADC_Channel_24) || ((CHANNEL) == ADC_Channel_25) )\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_sampling_times \r
+ * @{\r
+ */ \r
+\r
+#define ADC_SampleTime_4Cycles ((uint8_t)0x00)\r
+#define ADC_SampleTime_9Cycles ((uint8_t)0x01)\r
+#define ADC_SampleTime_16Cycles ((uint8_t)0x02)\r
+#define ADC_SampleTime_24Cycles ((uint8_t)0x03)\r
+#define ADC_SampleTime_48Cycles ((uint8_t)0x04)\r
+#define ADC_SampleTime_96Cycles ((uint8_t)0x05)\r
+#define ADC_SampleTime_192Cycles ((uint8_t)0x06)\r
+#define ADC_SampleTime_384Cycles ((uint8_t)0x07)\r
+\r
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_4Cycles) || \\r
+ ((TIME) == ADC_SampleTime_9Cycles) || \\r
+ ((TIME) == ADC_SampleTime_16Cycles) || \\r
+ ((TIME) == ADC_SampleTime_24Cycles) || \\r
+ ((TIME) == ADC_SampleTime_48Cycles) || \\r
+ ((TIME) == ADC_SampleTime_96Cycles) || \\r
+ ((TIME) == ADC_SampleTime_192Cycles) || \\r
+ ((TIME) == ADC_SampleTime_384Cycles))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_Delay_length \r
+ * @{\r
+ */ \r
+\r
+#define ADC_DelayLength_None ((uint8_t)0x00)\r
+#define ADC_DelayLength_Freeze ((uint8_t)0x10)\r
+#define ADC_DelayLength_7Cycles ((uint8_t)0x20)\r
+#define ADC_DelayLength_15Cycles ((uint8_t)0x30)\r
+#define ADC_DelayLength_31Cycles ((uint8_t)0x40)\r
+#define ADC_DelayLength_63Cycles ((uint8_t)0x50)\r
+#define ADC_DelayLength_127Cycles ((uint8_t)0x60)\r
+#define ADC_DelayLength_255Cycles ((uint8_t)0x70)\r
+\r
+#define IS_ADC_DELAY_LENGTH(LENGTH) (((LENGTH) == ADC_DelayLength_None) || \\r
+ ((LENGTH) == ADC_DelayLength_Freeze) || \\r
+ ((LENGTH) == ADC_DelayLength_7Cycles) || \\r
+ ((LENGTH) == ADC_DelayLength_15Cycles) || \\r
+ ((LENGTH) == ADC_DelayLength_31Cycles) || \\r
+ ((LENGTH) == ADC_DelayLength_63Cycles) || \\r
+ ((LENGTH) == ADC_DelayLength_127Cycles) || \\r
+ ((LENGTH) == ADC_DelayLength_255Cycles))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion \r
+ * @{\r
+ */ \r
+#define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000)\r
+#define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000)\r
+#define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000)\r
+#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000)\r
+\r
+#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \\r
+ ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \\r
+ ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \\r
+ ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion \r
+ * @{\r
+ */ \r
+\r
+\r
+/* TIM2 */\r
+#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00020000)\r
+#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00030000)\r
+\r
+/* TIM3 */\r
+#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00040000)\r
+\r
+/* TIM4 */\r
+#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00050000)\r
+#define ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000)\r
+#define ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000)\r
+#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000)\r
+\r
+/* TIM7 */\r
+#define ADC_ExternalTrigInjecConv_T7_TRGO ((uint32_t)0x000A0000)\r
+\r
+/* TIM9 */\r
+#define ADC_ExternalTrigInjecConv_T9_CC1 ((uint32_t)0x00000000)\r
+#define ADC_ExternalTrigInjecConv_T9_TRGO ((uint32_t)0x00010000)\r
+\r
+/* TIM10 */\r
+#define ADC_ExternalTrigInjecConv_T10_CC1 ((uint32_t)0x00090000)\r
+\r
+/* EXTI */\r
+#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000)\r
+\r
+#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T9_CC1) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T9_TRGO) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T10_CC1) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T7_TRGO) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_injected_channel_selection \r
+ * @{\r
+ */ \r
+#define ADC_InjectedChannel_1 ((uint8_t)0x18)\r
+#define ADC_InjectedChannel_2 ((uint8_t)0x1C)\r
+#define ADC_InjectedChannel_3 ((uint8_t)0x20)\r
+#define ADC_InjectedChannel_4 ((uint8_t)0x24)\r
+\r
+#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \\r
+ ((CHANNEL) == ADC_InjectedChannel_2) || \\r
+ ((CHANNEL) == ADC_InjectedChannel_3) || \\r
+ ((CHANNEL) == ADC_InjectedChannel_4))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_analog_watchdog_selection \r
+ * @{\r
+ */ \r
+ \r
+#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)\r
+#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)\r
+#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) \r
+#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)\r
+#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)\r
+#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)\r
+#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)\r
+\r
+#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_None))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_interrupts_definition \r
+ * @{\r
+ */ \r
+ \r
+#define ADC_IT_AWD ((uint16_t)0x0106) \r
+#define ADC_IT_EOC ((uint16_t)0x0205) \r
+#define ADC_IT_JEOC ((uint16_t)0x0407) \r
+#define ADC_IT_OVR ((uint16_t)0x201A) \r
+ \r
+#define IS_ADC_IT(IT) (((IT) == ADC_IT_AWD) || ((IT) == ADC_IT_EOC) || \\r
+ ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR)) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_flags_definition \r
+ * @{\r
+ */ \r
+ \r
+#define ADC_FLAG_AWD ((uint16_t)0x0001)\r
+#define ADC_FLAG_EOC ((uint16_t)0x0002)\r
+#define ADC_FLAG_JEOC ((uint16_t)0x0004)\r
+#define ADC_FLAG_JSTRT ((uint16_t)0x0008)\r
+#define ADC_FLAG_STRT ((uint16_t)0x0010)\r
+#define ADC_FLAG_OVR ((uint16_t)0x0020)\r
+#define ADC_FLAG_ADONS ((uint16_t)0x0040)\r
+#define ADC_FLAG_RCNR ((uint16_t)0x0100)\r
+#define ADC_FLAG_JCNR ((uint16_t)0x0200) \r
+ \r
+#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFC0) == 0x00) && ((FLAG) != 0x00))\r
+ \r
+#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \\r
+ ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \\r
+ ((FLAG) == ADC_FLAG_STRT) || ((FLAG)== ADC_FLAG_OVR) || \\r
+ ((FLAG) == ADC_FLAG_ADONS) || ((FLAG)== ADC_FLAG_RCNR) || \\r
+ ((FLAG) == ADC_FLAG_JCNR))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_thresholds \r
+ * @{\r
+ */ \r
+ \r
+#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_injected_offset \r
+ * @{\r
+ */\r
+ \r
+#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_injected_length \r
+ * @{\r
+ */\r
+ \r
+#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_injected_rank \r
+ * @{\r
+ */ \r
+ \r
+#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_regular_length \r
+ * @{\r
+ */\r
+ \r
+#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1) && ((LENGTH) <= 27))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_regular_rank \r
+ * @{\r
+ */ \r
+ \r
+#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x1B))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_regular_discontinuous_mode_number \r
+ * @{\r
+ */\r
+ \r
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */ \r
+\r
+/* Function used to set the ADC configuration to the default reset state *****/ \r
+void ADC_DeInit(ADC_TypeDef* ADCx); \r
+\r
+/* Initialization and Configuration functions *********************************/ \r
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);\r
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);\r
+void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);\r
+void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);\r
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+\r
+/* Power saving functions *****************************************************/\r
+void ADC_PowerDownCmd(ADC_TypeDef* ADCx, uint32_t ADC_PowerDown, FunctionalState NewState);\r
+void ADC_DelaySelectionConfig(ADC_TypeDef* ADCx, uint8_t ADC_DelayLength);\r
+\r
+/* Analog Watchdog configuration functions ************************************/\r
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);\r
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);\r
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);\r
+\r
+/* Temperature Sensor & Vrefint (Voltage Reference internal) management function */\r
+void ADC_TempSensorVrefintCmd(FunctionalState NewState);\r
+\r
+/* Regular Channels Configuration functions ***********************************/\r
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);\r
+void ADC_SoftwareStartConv(ADC_TypeDef* ADCx);\r
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);\r
+void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);\r
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);\r
+\r
+/* Regular Channels DMA Configuration functions *******************************/\r
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+\r
+/* Injected channels Configuration functions **********************************/\r
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);\r
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);\r
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);\r
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);\r
+void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge);\r
+void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx);\r
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);\r
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);\r
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint16_t ADC_FLAG);\r
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint16_t ADC_FLAG);\r
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);\r
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32L1xx_ADC_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_comp.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the COMP firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_COMP_H\r
+#define __STM32L1xx_COMP_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup COMP\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief COMP Init structure definition \r
+ */\r
+ \r
+typedef struct\r
+{\r
+ uint32_t COMP_Speed; /*!< Defines the speed of comparator 2.\r
+ This parameter can be a value of @ref COMP_Speed */\r
+ uint32_t COMP_InvertingInput; /*!< Selects the inverting input of the comparator 2.\r
+ This parameter can be a value of @ref COMP_InvertingInput */\r
+ uint32_t COMP_OutputSelect; /*!< Selects the output redirection of the comparator 2.\r
+ This parameter can be a value of @ref COMP_OutputSelect */\r
+ \r
+}COMP_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+ \r
+/** @defgroup COMP_Exported_Constants\r
+ * @{\r
+ */ \r
+\r
+#define COMP_OutputLevel_High ((uint32_t)0x00000001)\r
+#define COMP_OutputLevel_Low ((uint32_t)0x00000000)\r
+\r
+/** @defgroup COMP_Selection\r
+ * @{\r
+ */\r
+\r
+#define COMP_Selection_COMP1 ((uint32_t)0x00000001)\r
+#define COMP_Selection_COMP2 ((uint32_t)0x00000002)\r
+\r
+#define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP_Selection_COMP1) || \\r
+ ((PERIPH) == COMP_Selection_COMP2))\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup COMP_InvertingInput\r
+ * @{\r
+ */\r
+\r
+#define COMP_InvertingInput_None ((uint32_t)0x00000000) /* COMP2 is disabled when this parameter is selected */\r
+#define COMP_InvertingInput_IO ((uint32_t)0x00040000)\r
+#define COMP_InvertingInput_VREFINT ((uint32_t)0x00080000)\r
+#define COMP_InvertingInput_3_4VREFINT ((uint32_t)0x000C0000)\r
+#define COMP_InvertingInput_1_2VREFINT ((uint32_t)0x00100000)\r
+#define COMP_InvertingInput_1_4VREFINT ((uint32_t)0x00140000)\r
+#define COMP_InvertingInput_DAC1 ((uint32_t)0x00180000)\r
+#define COMP_InvertingInput_DAC2 ((uint32_t)0x001C0000)\r
+\r
+#define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_InvertingInput_None) || \\r
+ ((INPUT) == COMP_InvertingInput_IO) || \\r
+ ((INPUT) == COMP_InvertingInput_VREFINT) || \\r
+ ((INPUT) == COMP_InvertingInput_3_4VREFINT) || \\r
+ ((INPUT) == COMP_InvertingInput_1_2VREFINT) || \\r
+ ((INPUT) == COMP_InvertingInput_1_4VREFINT) || \\r
+ ((INPUT) == COMP_InvertingInput_DAC1) || \\r
+ ((INPUT) == COMP_InvertingInput_DAC2))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup COMP_OutputSelect\r
+ * @{\r
+ */\r
+\r
+#define COMP_OutputSelect_TIM2IC4 ((uint32_t)0x00000000)\r
+#define COMP_OutputSelect_TIM2OCREFCLR ((uint32_t)0x00200000)\r
+#define COMP_OutputSelect_TIM3IC4 ((uint32_t)0x00400000)\r
+#define COMP_OutputSelect_TIM3OCREFCLR ((uint32_t)0x00600000)\r
+#define COMP_OutputSelect_TIM4IC4 ((uint32_t)0x00800000)\r
+#define COMP_OutputSelect_TIM4OCREFCLR ((uint32_t)0x00A00000)\r
+#define COMP_OutputSelect_TIM10IC1 ((uint32_t)0x00C00000)\r
+#define COMP_OutputSelect_None ((uint32_t)0x00E00000)\r
+\r
+#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OutputSelect_TIM2IC4) || \\r
+ ((OUTPUT) == COMP_OutputSelect_TIM2OCREFCLR) || \\r
+ ((OUTPUT) == COMP_OutputSelect_TIM3IC4) || \\r
+ ((OUTPUT) == COMP_OutputSelect_TIM3OCREFCLR) || \\r
+ ((OUTPUT) == COMP_OutputSelect_TIM4IC4) || \\r
+ ((OUTPUT) == COMP_OutputSelect_TIM4OCREFCLR) || \\r
+ ((OUTPUT) == COMP_OutputSelect_TIM10IC1) || \\r
+ ((OUTPUT) == COMP_OutputSelect_None))\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup COMP_Speed\r
+ * @{\r
+ */\r
+\r
+#define COMP_Speed_Slow ((uint32_t)0x00000000)\r
+#define COMP_Speed_Fast ((uint32_t)0x00001000)\r
+\r
+#define IS_COMP_SPEED(SPEED) (((SPEED) == COMP_Speed_Slow) || \\r
+ ((SPEED) == COMP_Speed_Fast))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Function used to set the COMP configuration to the default reset state ****/\r
+void COMP_DeInit(void);\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+void COMP_Init(COMP_InitTypeDef* COMP_InitStruct);\r
+void COMP_Cmd(FunctionalState NewState);\r
+uint8_t COMP_GetOutputLevel(uint32_t COMP_Selection);\r
+\r
+/* Window mode control function ***********************************************/\r
+void COMP_WindowCmd(FunctionalState NewState);\r
+\r
+/* Internal Reference Voltage (VREFINT) output function ***********************/\r
+void COMP_VrefintOutputCmd(FunctionalState NewState);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32L1xx_COMP_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_crc.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the CRC firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_CRC_H\r
+#define __STM32L1xx_CRC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup CRC\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup CRC_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */ \r
+\r
+void CRC_ResetDR(void);\r
+uint32_t CRC_CalcCRC(uint32_t Data);\r
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);\r
+uint32_t CRC_GetCRC(void);\r
+void CRC_SetIDRegister(uint8_t IDValue);\r
+uint8_t CRC_GetIDRegister(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_CRC_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_dac.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the DAC firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_DAC_H\r
+#define __STM32L1xx_DAC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+ \r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DAC\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief DAC Init structure definition\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.\r
+ This parameter can be a value of @ref DAC_trigger_selection */\r
+\r
+ uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves\r
+ are generated, or whether no wave is generated.\r
+ This parameter can be a value of @ref DAC_wave_generation */\r
+\r
+ uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or\r
+ the maximum amplitude triangle generation for the DAC channel. \r
+ This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */\r
+\r
+ uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.\r
+ This parameter can be a value of @ref DAC_output_buffer */\r
+}DAC_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup DAC_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DAC_trigger_selection \r
+ * @{\r
+ */\r
+ \r
+#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register \r
+ has been loaded, and not by external trigger */\r
+#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */\r
+#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */\r
+#define DAC_Trigger_T9_TRGO ((uint32_t)0x0000001C) /*!< TIM9 TRGO selected as external conversion trigger for DAC channel */\r
+#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */\r
+#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */\r
+#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */\r
+#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */\r
+\r
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \\r
+ ((TRIGGER) == DAC_Trigger_T6_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_T7_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_T9_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_T2_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_T4_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_Ext_IT9) || \\r
+ ((TRIGGER) == DAC_Trigger_Software))\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup DAC_wave_generation \r
+ * @{\r
+ */\r
+\r
+#define DAC_WaveGeneration_None ((uint32_t)0x00000000)\r
+#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)\r
+#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)\r
+#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \\r
+ ((WAVE) == DAC_WaveGeneration_Noise) || \\r
+ ((WAVE) == DAC_WaveGeneration_Triangle))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup DAC_lfsrunmask_triangleamplitude\r
+ * @{\r
+ */\r
+\r
+#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */\r
+#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */\r
+#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */\r
+#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */\r
+#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */\r
+#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */\r
+#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */\r
+#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */\r
+#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */\r
+#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */\r
+#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */\r
+#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */\r
+#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */\r
+\r
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_1) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_3) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_7) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_15) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_31) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_63) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_127) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_255) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_511) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_1023) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_2047) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_4095))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_output_buffer \r
+ * @{\r
+ */\r
+\r
+#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)\r
+#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)\r
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \\r
+ ((STATE) == DAC_OutputBuffer_Disable))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup DAC_Channel_selection \r
+ * @{\r
+ */\r
+\r
+#define DAC_Channel_1 ((uint32_t)0x00000000)\r
+#define DAC_Channel_2 ((uint32_t)0x00000010)\r
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \\r
+ ((CHANNEL) == DAC_Channel_2))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_data_alignment \r
+ * @{\r
+ */\r
+\r
+#define DAC_Align_12b_R ((uint32_t)0x00000000)\r
+#define DAC_Align_12b_L ((uint32_t)0x00000004)\r
+#define DAC_Align_8b_R ((uint32_t)0x00000008)\r
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \\r
+ ((ALIGN) == DAC_Align_12b_L) || \\r
+ ((ALIGN) == DAC_Align_8b_R))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_wave_generation \r
+ * @{\r
+ */\r
+\r
+#define DAC_Wave_Noise ((uint32_t)0x00000040)\r
+#define DAC_Wave_Triangle ((uint32_t)0x00000080)\r
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \\r
+ ((WAVE) == DAC_Wave_Triangle))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_data \r
+ * @{\r
+ */\r
+\r
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_interrupts_definition \r
+ * @{\r
+ */ \r
+ \r
+#define DAC_IT_DMAUDR ((uint32_t)0x00002000) \r
+#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup DAC_flags_definition \r
+ * @{\r
+ */ \r
+ \r
+#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) \r
+ \r
+#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */ \r
+\r
+/* Function used to set the DAC configuration to the default reset state *****/ \r
+void DAC_DeInit(void);\r
+\r
+/* DAC channels configuration: trigger, output buffer, data format functions */\r
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);\r
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);\r
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);\r
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);\r
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);\r
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);\r
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);\r
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);\r
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);\r
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);\r
+\r
+/* DMA management functions ***************************************************/\r
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);\r
+FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);\r
+void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);\r
+ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);\r
+void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32L1xx_DAC_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_dbgmcu.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the DBGMCU \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_DBGMCU_H\r
+#define __STM32L1xx_DBGMCU_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DBGMCU\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup DBGMCU_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+#define DBGMCU_SLEEP ((uint32_t)0x00000001)\r
+#define DBGMCU_STOP ((uint32_t)0x00000002)\r
+#define DBGMCU_STANDBY ((uint32_t)0x00000004)\r
+#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00))\r
+\r
+#define DBGMCU_TIM2_STOP ((uint32_t)0x00000001)\r
+#define DBGMCU_TIM3_STOP ((uint32_t)0x00000002)\r
+#define DBGMCU_TIM4_STOP ((uint32_t)0x00000004)\r
+#define DBGMCU_TIM6_STOP ((uint32_t)0x00000010)\r
+#define DBGMCU_TIM7_STOP ((uint32_t)0x00000020)\r
+#define DBGMCU_RTC_STOP ((uint32_t)0x00000400)\r
+#define DBGMCU_WWDG_STOP ((uint32_t)0x00000800)\r
+#define DBGMCU_IWDG_STOP ((uint32_t)0x00001000)\r
+#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)\r
+#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)\r
+#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xFF9FE3C8) == 0x00) && ((PERIPH) != 0x00))\r
+\r
+#define DBGMCU_TIM9_STOP ((uint32_t)0x00000004)\r
+#define DBGMCU_TIM10_STOP ((uint32_t)0x00000008)\r
+#define DBGMCU_TIM11_STOP ((uint32_t)0x00000010)\r
+#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFE3) == 0x00) && ((PERIPH) != 0x00))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+uint32_t DBGMCU_GetREVID(void);\r
+uint32_t DBGMCU_GetDEVID(void);\r
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);\r
+void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);\r
+void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_DBGMCU_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_dma.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the DMA firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_DMA_H\r
+#define __STM32L1xx_DMA_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DMA\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief DMA Init structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */\r
+\r
+ uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */\r
+\r
+ uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.\r
+ This parameter can be a value of @ref DMA_data_transfer_direction */\r
+\r
+ uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. \r
+ The data unit is equal to the configuration set in DMA_PeripheralDataSize\r
+ or DMA_MemoryDataSize members depending in the transfer direction. */\r
+\r
+ uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.\r
+ This parameter can be a value of @ref DMA_peripheral_incremented_mode */\r
+\r
+ uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.\r
+ This parameter can be a value of @ref DMA_memory_incremented_mode */\r
+\r
+ uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.\r
+ This parameter can be a value of @ref DMA_peripheral_data_size */\r
+\r
+ uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.\r
+ This parameter can be a value of @ref DMA_memory_data_size */\r
+\r
+ uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.\r
+ This parameter can be a value of @ref DMA_circular_normal_mode.\r
+ @note: The circular buffer mode cannot be used if the memory-to-memory\r
+ data transfer is configured on the selected Channel */\r
+\r
+ uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.\r
+ This parameter can be a value of @ref DMA_priority_level */\r
+\r
+ uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.\r
+ This parameter can be a value of @ref DMA_memory_to_memory */\r
+}DMA_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup DMA_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \\r
+ ((PERIPH) == DMA1_Channel2) || \\r
+ ((PERIPH) == DMA1_Channel3) || \\r
+ ((PERIPH) == DMA1_Channel4) || \\r
+ ((PERIPH) == DMA1_Channel5) || \\r
+ ((PERIPH) == DMA1_Channel6) || \\r
+ ((PERIPH) == DMA1_Channel7))\r
+\r
+/** @defgroup DMA_data_transfer_direction \r
+ * @{\r
+ */\r
+\r
+#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)\r
+#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)\r
+#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \\r
+ ((DIR) == DMA_DIR_PeripheralSRC))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_peripheral_incremented_mode \r
+ * @{\r
+ */\r
+\r
+#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)\r
+#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)\r
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \\r
+ ((STATE) == DMA_PeripheralInc_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_memory_incremented_mode \r
+ * @{\r
+ */\r
+\r
+#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)\r
+#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)\r
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \\r
+ ((STATE) == DMA_MemoryInc_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_peripheral_data_size \r
+ * @{\r
+ */\r
+\r
+#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)\r
+#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)\r
+#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)\r
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \\r
+ ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \\r
+ ((SIZE) == DMA_PeripheralDataSize_Word))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_memory_data_size \r
+ * @{\r
+ */\r
+\r
+#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)\r
+#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)\r
+#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)\r
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \\r
+ ((SIZE) == DMA_MemoryDataSize_HalfWord) || \\r
+ ((SIZE) == DMA_MemoryDataSize_Word))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_circular_normal_mode \r
+ * @{\r
+ */\r
+\r
+#define DMA_Mode_Circular ((uint32_t)0x00000020)\r
+#define DMA_Mode_Normal ((uint32_t)0x00000000)\r
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_priority_level \r
+ * @{\r
+ */\r
+\r
+#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)\r
+#define DMA_Priority_High ((uint32_t)0x00002000)\r
+#define DMA_Priority_Medium ((uint32_t)0x00001000)\r
+#define DMA_Priority_Low ((uint32_t)0x00000000)\r
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \\r
+ ((PRIORITY) == DMA_Priority_High) || \\r
+ ((PRIORITY) == DMA_Priority_Medium) || \\r
+ ((PRIORITY) == DMA_Priority_Low))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_memory_to_memory \r
+ * @{\r
+ */\r
+\r
+#define DMA_M2M_Enable ((uint32_t)0x00004000)\r
+#define DMA_M2M_Disable ((uint32_t)0x00000000)\r
+#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_interrupts_definition \r
+ * @{\r
+ */\r
+\r
+#define DMA_IT_TC ((uint32_t)0x00000002)\r
+#define DMA_IT_HT ((uint32_t)0x00000004)\r
+#define DMA_IT_TE ((uint32_t)0x00000008)\r
+#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))\r
+\r
+#define DMA1_IT_GL1 ((uint32_t)0x00000001)\r
+#define DMA1_IT_TC1 ((uint32_t)0x00000002)\r
+#define DMA1_IT_HT1 ((uint32_t)0x00000004)\r
+#define DMA1_IT_TE1 ((uint32_t)0x00000008)\r
+#define DMA1_IT_GL2 ((uint32_t)0x00000010)\r
+#define DMA1_IT_TC2 ((uint32_t)0x00000020)\r
+#define DMA1_IT_HT2 ((uint32_t)0x00000040)\r
+#define DMA1_IT_TE2 ((uint32_t)0x00000080)\r
+#define DMA1_IT_GL3 ((uint32_t)0x00000100)\r
+#define DMA1_IT_TC3 ((uint32_t)0x00000200)\r
+#define DMA1_IT_HT3 ((uint32_t)0x00000400)\r
+#define DMA1_IT_TE3 ((uint32_t)0x00000800)\r
+#define DMA1_IT_GL4 ((uint32_t)0x00001000)\r
+#define DMA1_IT_TC4 ((uint32_t)0x00002000)\r
+#define DMA1_IT_HT4 ((uint32_t)0x00004000)\r
+#define DMA1_IT_TE4 ((uint32_t)0x00008000)\r
+#define DMA1_IT_GL5 ((uint32_t)0x00010000)\r
+#define DMA1_IT_TC5 ((uint32_t)0x00020000)\r
+#define DMA1_IT_HT5 ((uint32_t)0x00040000)\r
+#define DMA1_IT_TE5 ((uint32_t)0x00080000)\r
+#define DMA1_IT_GL6 ((uint32_t)0x00100000)\r
+#define DMA1_IT_TC6 ((uint32_t)0x00200000)\r
+#define DMA1_IT_HT6 ((uint32_t)0x00400000)\r
+#define DMA1_IT_TE6 ((uint32_t)0x00800000)\r
+#define DMA1_IT_GL7 ((uint32_t)0x01000000)\r
+#define DMA1_IT_TC7 ((uint32_t)0x02000000)\r
+#define DMA1_IT_HT7 ((uint32_t)0x04000000)\r
+#define DMA1_IT_TE7 ((uint32_t)0x08000000)\r
+\r
+#define IS_DMA_CLEAR_IT(IT) ((((IT) & 0xF0000000) == 0x00) && ((IT) != 0x00))\r
+\r
+#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \\r
+ ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \\r
+ ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \\r
+ ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \\r
+ ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \\r
+ ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \\r
+ ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \\r
+ ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \\r
+ ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \\r
+ ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \\r
+ ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \\r
+ ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \\r
+ ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \\r
+ ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_flags_definition \r
+ * @{\r
+ */\r
+#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)\r
+#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)\r
+#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)\r
+#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)\r
+#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)\r
+#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)\r
+#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)\r
+#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)\r
+#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)\r
+#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)\r
+#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)\r
+#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)\r
+#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)\r
+#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)\r
+#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)\r
+#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)\r
+#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)\r
+#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)\r
+#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)\r
+#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)\r
+#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)\r
+#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)\r
+#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)\r
+#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)\r
+#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)\r
+#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)\r
+#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)\r
+#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)\r
+\r
+#define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0xF0000000) == 0x00) && ((FLAG) != 0x00))\r
+\r
+#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \\r
+ ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \\r
+ ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \\r
+ ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \\r
+ ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \\r
+ ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \\r
+ ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \\r
+ ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \\r
+ ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \\r
+ ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \\r
+ ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \\r
+ ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \\r
+ ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \\r
+ ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Buffer_Size \r
+ * @{\r
+ */\r
+\r
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Function used to set the DMA configuration to the default reset state *****/ \r
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);\r
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);\r
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);\r
+\r
+/* Data Counter functions *****************************************************/\r
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);\r
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);\r
+FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);\r
+void DMA_ClearFlag(uint32_t DMA_FLAG);\r
+ITStatus DMA_GetITStatus(uint32_t DMA_IT);\r
+void DMA_ClearITPendingBit(uint32_t DMA_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32L1xx_DMA_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_exti.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the EXTI firmware\r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_EXTI_H\r
+#define __STM32L1xx_EXTI_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup EXTI\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief EXTI mode enumeration \r
+ */\r
+\r
+typedef enum\r
+{\r
+ EXTI_Mode_Interrupt = 0x00,\r
+ EXTI_Mode_Event = 0x04\r
+}EXTIMode_TypeDef;\r
+\r
+#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))\r
+\r
+/** \r
+ * @brief EXTI Trigger enumeration \r
+ */\r
+\r
+typedef enum\r
+{\r
+ EXTI_Trigger_Rising = 0x08,\r
+ EXTI_Trigger_Falling = 0x0C, \r
+ EXTI_Trigger_Rising_Falling = 0x10\r
+}EXTITrigger_TypeDef;\r
+\r
+#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \\r
+ ((TRIGGER) == EXTI_Trigger_Falling) || \\r
+ ((TRIGGER) == EXTI_Trigger_Rising_Falling))\r
+/** \r
+ * @brief EXTI Init Structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.\r
+ This parameter can be any combination of @ref EXTI_Lines */\r
+ \r
+ EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.\r
+ This parameter can be a value of @ref EXTIMode_TypeDef */\r
+\r
+ EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.\r
+ This parameter can be a value of @ref EXTIMode_TypeDef */\r
+\r
+ FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.\r
+ This parameter can be set either to ENABLE or DISABLE */ \r
+}EXTI_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup EXTI_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup EXTI_Lines \r
+ * @{\r
+ */\r
+\r
+#define EXTI_Line0 ((uint32_t)0x00000001) /*!< External interrupt line 0 */\r
+#define EXTI_Line1 ((uint32_t)0x00000002) /*!< External interrupt line 1 */\r
+#define EXTI_Line2 ((uint32_t)0x00000004) /*!< External interrupt line 2 */\r
+#define EXTI_Line3 ((uint32_t)0x00000008) /*!< External interrupt line 3 */\r
+#define EXTI_Line4 ((uint32_t)0x00000010) /*!< External interrupt line 4 */\r
+#define EXTI_Line5 ((uint32_t)0x00000020) /*!< External interrupt line 5 */\r
+#define EXTI_Line6 ((uint32_t)0x00000040) /*!< External interrupt line 6 */\r
+#define EXTI_Line7 ((uint32_t)0x00000080) /*!< External interrupt line 7 */\r
+#define EXTI_Line8 ((uint32_t)0x00000100) /*!< External interrupt line 8 */\r
+#define EXTI_Line9 ((uint32_t)0x00000200) /*!< External interrupt line 9 */\r
+#define EXTI_Line10 ((uint32_t)0x00000400) /*!< External interrupt line 10 */\r
+#define EXTI_Line11 ((uint32_t)0x00000800) /*!< External interrupt line 11 */\r
+#define EXTI_Line12 ((uint32_t)0x00001000) /*!< External interrupt line 12 */\r
+#define EXTI_Line13 ((uint32_t)0x00002000) /*!< External interrupt line 13 */\r
+#define EXTI_Line14 ((uint32_t)0x00004000) /*!< External interrupt line 14 */\r
+#define EXTI_Line15 ((uint32_t)0x00008000) /*!< External interrupt line 15 */\r
+#define EXTI_Line16 ((uint32_t)0x00010000) /*!< External interrupt line 16 \r
+ Connected to the PVD Output */\r
+#define EXTI_Line17 ((uint32_t)0x00020000) /*!< External interrupt line 17 \r
+ Connected to the RTC Alarm \r
+ event */\r
+#define EXTI_Line18 ((uint32_t)0x00040000) /*!< External interrupt line 18 \r
+ Connected to the USB Device \r
+ FS Wakeup from suspend event */\r
+#define EXTI_Line19 ((uint32_t)0x00080000) /*!< External interrupt line 19 \r
+ Connected to the RTC Tamper \r
+ and Time Stamp events */ \r
+#define EXTI_Line20 ((uint32_t)0x00100000) /*!< External interrupt line 20 \r
+ Connected to the RTC Wakeup \r
+ event */\r
+#define EXTI_Line21 ((uint32_t)0x00200000) /*!< External interrupt line 21 \r
+ Connected to the Comparator 1 \r
+ event */\r
+\r
+#define EXTI_Line22 ((uint32_t)0x00400000) /*!< External interrupt line 22 \r
+ Connected to the Comparator 2\r
+ event */\r
+ \r
+#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00))\r
+\r
+#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \\r
+ ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \\r
+ ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \\r
+ ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \\r
+ ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \\r
+ ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \\r
+ ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \\r
+ ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \\r
+ ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \\r
+ ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \\r
+ ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || \\r
+ ((LINE) == EXTI_Line22))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+/* Function used to set the EXTI configuration to the default reset state *****/\r
+void EXTI_DeInit(void);\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);\r
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);\r
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);\r
+void EXTI_ClearFlag(uint32_t EXTI_Line);\r
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);\r
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_EXTI_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_flash.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the FLASH \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_FLASH_H\r
+#define __STM32L1xx_FLASH_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup FLASH\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief FLASH Status \r
+ */ \r
+typedef enum\r
+{ \r
+ FLASH_BUSY = 1,\r
+ FLASH_ERROR_WRP,\r
+ FLASH_ERROR_PROGRAM,\r
+ FLASH_COMPLETE,\r
+ FLASH_TIMEOUT\r
+}FLASH_Status;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+ \r
+/** @defgroup FLASH_Exported_Constants\r
+ * @{\r
+ */ \r
+ \r
+/** @defgroup FLASH_Latency \r
+ * @{\r
+ */ \r
+#define FLASH_Latency_0 ((uint8_t)0x00) /*!< FLASH Zero Latency cycle */\r
+#define FLASH_Latency_1 ((uint8_t)0x01) /*!< FLASH One Latency cycle */\r
+\r
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \\r
+ ((LATENCY) == FLASH_Latency_1))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASH_Interrupts \r
+ * @{\r
+ */\r
+ \r
+#define FLASH_IT_EOP FLASH_PECR_EOPIE /*!< End of programming interrupt source */\r
+#define FLASH_IT_ERR FLASH_PECR_ERRIE /*!< Error interrupt source */\r
+#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFCFFFF) == 0x00000000) && (((IT) != 0x00000000)))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASH_Address \r
+ * @{\r
+ */\r
+ \r
+#define IS_FLASH_DATA_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08080000) && ((ADDRESS) <= 0x08080FFF))\r
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0801FFFF)) \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup Option_Bytes_Write_Protection \r
+ * @{\r
+ */\r
+ \r
+\r
+#define OB_WRP_Pages0to15 ((uint32_t)0x00000001) /* Write protection of Sector0 */\r
+#define OB_WRP_Pages16to31 ((uint32_t)0x00000002) /* Write protection of Sector1 */\r
+#define OB_WRP_Pages32to47 ((uint32_t)0x00000004) /* Write protection of Sector2 */\r
+#define OB_WRP_Pages48to63 ((uint32_t)0x00000008) /* Write protection of Sector3 */\r
+#define OB_WRP_Pages64to79 ((uint32_t)0x00000010) /* Write protection of Sector4 */\r
+#define OB_WRP_Pages80to95 ((uint32_t)0x00000020) /* Write protection of Sector5 */\r
+#define OB_WRP_Pages96to111 ((uint32_t)0x00000040) /* Write protection of Sector6 */\r
+#define OB_WRP_Pages112to127 ((uint32_t)0x00000080) /* Write protection of Sector7 */\r
+#define OB_WRP_Pages128to143 ((uint32_t)0x00000100) /* Write protection of Sector8 */\r
+#define OB_WRP_Pages144to159 ((uint32_t)0x00000200) /* Write protection of Sector9 */\r
+#define OB_WRP_Pages160to175 ((uint32_t)0x00000400) /* Write protection of Sector10 */\r
+#define OB_WRP_Pages176to191 ((uint32_t)0x00000800) /* Write protection of Sector11 */\r
+#define OB_WRP_Pages192to207 ((uint32_t)0x00001000) /* Write protection of Sector12 */\r
+#define OB_WRP_Pages208to223 ((uint32_t)0x00002000) /* Write protection of Sector13 */\r
+#define OB_WRP_Pages224to239 ((uint32_t)0x00004000) /* Write protection of Sector14 */\r
+#define OB_WRP_Pages240to255 ((uint32_t)0x00008000) /* Write protection of Sector15 */\r
+#define OB_WRP_Pages256to271 ((uint32_t)0x00010000) /* Write protection of Sector16 */\r
+#define OB_WRP_Pages272to287 ((uint32_t)0x00020000) /* Write protection of Sector17 */\r
+#define OB_WRP_Pages288to303 ((uint32_t)0x00040000) /* Write protection of Sector18 */\r
+#define OB_WRP_Pages304to319 ((uint32_t)0x00080000) /* Write protection of Sector19 */\r
+#define OB_WRP_Pages320to335 ((uint32_t)0x00100000) /* Write protection of Sector20 */\r
+#define OB_WRP_Pages336to351 ((uint32_t)0x00200000) /* Write protection of Sector21 */\r
+#define OB_WRP_Pages352to367 ((uint32_t)0x00400000) /* Write protection of Sector22 */\r
+#define OB_WRP_Pages368to383 ((uint32_t)0x00800000) /* Write protection of Sector23 */\r
+#define OB_WRP_Pages384to399 ((uint32_t)0x01000000) /* Write protection of Sector24 */\r
+#define OB_WRP_Pages400to415 ((uint32_t)0x02000000) /* Write protection of Sector25 */\r
+#define OB_WRP_Pages416to431 ((uint32_t)0x04000000) /* Write protection of Sector26 */\r
+#define OB_WRP_Pages432to447 ((uint32_t)0x08000000) /* Write protection of Sector27 */\r
+#define OB_WRP_Pages448to463 ((uint32_t)0x10000000) /* Write protection of Sector28 */\r
+#define OB_WRP_Pages464to479 ((uint32_t)0x20000000) /* Write protection of Sector29 */\r
+#define OB_WRP_Pages480to495 ((uint32_t)0x40000000) /* Write protection of Sector30 */\r
+#define OB_WRP_Pages496to511 ((uint32_t)0x80000000) /* Write protection of Sector31 */\r
+\r
+#define OB_WRP_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */\r
+\r
+#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Option_Bytes_Read_Protection \r
+ * @{\r
+ */ \r
+\r
+/** \r
+ * @brief Read Protection Level \r
+ */ \r
+#define OB_RDP_Level_0 ((uint8_t)0xAA)\r
+#define OB_RDP_Level_1 ((uint8_t)0xBB)\r
+/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2 \r
+ it's no more possible to go back to level 1 or 0 */\r
+\r
+#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\\r
+ ((LEVEL) == OB_RDP_Level_1))/*||\\r
+ ((LEVEL) == OB_RDP_Level_2))*/\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup Option_Bytes_IWatchdog \r
+ * @{\r
+ */\r
+\r
+#define OB_IWDG_SW ((uint8_t)0x10) /*!< Software WDG selected */\r
+#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware WDG selected */\r
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Option_Bytes_nRST_STOP \r
+ * @{\r
+ */\r
+\r
+#define OB_STOP_NoRST ((uint8_t)0x20) /*!< No reset generated when entering in STOP */\r
+#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */\r
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Option_Bytes_nRST_STDBY \r
+ * @{\r
+ */\r
+\r
+#define OB_STDBY_NoRST ((uint8_t)0x40) /*!< No reset generated when entering in STANDBY */\r
+#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */\r
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Option_Bytes_BOR_Level \r
+ * @{\r
+ */\r
+\r
+#define OB_BOR_OFF ((uint8_t)0x00) /*!< BOR is disabled at power down, the reset is asserted when the VDD \r
+ power supply reaches the PDR(Power Down Reset) threshold (1.5V) */\r
+#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< BOR Reset threshold levels for 1.7V - 1.8V VDD power supply */\r
+#define OB_BOR_LEVEL2 ((uint8_t)0x09) /*!< BOR Reset threshold levels for 1.9V - 2.0V VDD power supply */\r
+#define OB_BOR_LEVEL3 ((uint8_t)0x0A) /*!< BOR Reset threshold levels for 2.3V - 2.4V VDD power supply */\r
+#define OB_BOR_LEVEL4 ((uint8_t)0x0B) /*!< BOR Reset threshold levels for 2.55V - 2.65V VDD power supply */\r
+#define OB_BOR_LEVEL5 ((uint8_t)0x0C) /*!< BOR Reset threshold levels for 2.8V - 2.9V VDD power supply */\r
+\r
+#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_OFF) || \\r
+ ((LEVEL) == OB_BOR_LEVEL1) || \\r
+ ((LEVEL) == OB_BOR_LEVEL2) || \\r
+ ((LEVEL) == OB_BOR_LEVEL3) || \\r
+ ((LEVEL) == OB_BOR_LEVEL4) || \\r
+ ((LEVEL) == OB_BOR_LEVEL5))\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FLASH_Flags \r
+ * @{\r
+ */ \r
+\r
+#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */\r
+#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */\r
+#define FLASH_FLAG_ENDHV FLASH_SR_ENHV /*!< FLASH End of High Voltage flag */\r
+#define FLASH_FLAG_READY FLASH_SR_READY /*!< FLASH Ready flag after low power mode */\r
+#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */\r
+#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */\r
+#define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */\r
+#define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option Validity error flag */\r
+ \r
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFF0FD) == 0x00000000) && ((FLAG) != 0x00000000))\r
+\r
+#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \\r
+ ((FLAG) == FLASH_FLAG_ENDHV) || ((FLAG) == FLASH_FLAG_READY ) || \\r
+ ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR ) || \\r
+ ((FLAG) == FLASH_FLAG_SIZERR) || ((FLAG) == FLASH_FLAG_OPTVERR))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASH_Keys \r
+ * @{\r
+ */ \r
+\r
+#define FLASH_PDKEY1 ((uint32_t)0x04152637) /*!< Flash power down key1 */\r
+#define FLASH_PDKEY2 ((uint32_t)0xFAFBFCFD) /*!< Flash power down key2: used with FLASH_PDKEY1 \r
+ to unlock the RUN_PD bit in FLASH_ACR */\r
+\r
+#define FLASH_PEKEY1 ((uint32_t)0x89ABCDEF) /*!< Flash program erase key1 */\r
+#define FLASH_PEKEY2 ((uint32_t)0x02030405) /*!< Flash program erase key: used with FLASH_PEKEY2\r
+ to unlock the write access to the FLASH_PECR register and\r
+ data EEPROM */\r
+\r
+#define FLASH_PRGKEY1 ((uint32_t)0x8C9DAEBF) /*!< Flash program memory key1 */\r
+#define FLASH_PRGKEY2 ((uint32_t)0x13141516) /*!< Flash program memory key2: used with FLASH_PRGKEY2\r
+ to unlock the program memory */\r
+\r
+#define FLASH_OPTKEY1 ((uint32_t)0xFBEAD9C8) /*!< Flash option key1 */\r
+#define FLASH_OPTKEY2 ((uint32_t)0x24252627) /*!< Flash option key2: used with FLASH_OPTKEY1 to\r
+ unlock the write access to the option byte block */\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup Timeout_definition \r
+ * @{\r
+ */ \r
+#define FLASH_ER_PRG_TIMEOUT ((uint32_t)0x8000)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+ \r
+/** \r
+ * @brief FLASH memory functions that can be executed from FLASH. \r
+ */ \r
+/* FLASH Interface configuration functions ************************************/ \r
+void FLASH_SetLatency(uint32_t FLASH_Latency);\r
+void FLASH_PrefetchBufferCmd(FunctionalState NewState);\r
+void FLASH_ReadAccess64Cmd(FunctionalState NewState);\r
+void FLASH_SLEEPPowerDownCmd(FunctionalState NewState);\r
+\r
+/* FLASH Memory Programming functions *****************************************/ \r
+void FLASH_Unlock(void);\r
+void FLASH_Lock(void);\r
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address);\r
+FLASH_Status FLASH_FastProgramWord(uint32_t Address, uint32_t Data);\r
+\r
+/* DATA EEPROM Programming functions ******************************************/ \r
+void DATA_EEPROM_Unlock(void);\r
+void DATA_EEPROM_Lock(void);\r
+void DATA_EEPROM_FixedTimeProgramCmd(FunctionalState NewState);\r
+FLASH_Status DATA_EEPROM_EraseWord(uint32_t Address);\r
+FLASH_Status DATA_EEPROM_FastProgramByte(uint32_t Address, uint8_t Data);\r
+FLASH_Status DATA_EEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data);\r
+FLASH_Status DATA_EEPROM_FastProgramWord(uint32_t Address, uint32_t Data);\r
+FLASH_Status DATA_EEPROM_ProgramByte(uint32_t Address, uint8_t Data);\r
+FLASH_Status DATA_EEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data);\r
+FLASH_Status DATA_EEPROM_ProgramWord(uint32_t Address, uint32_t Data);\r
+\r
+/* Option Bytes Programming functions *****************************************/\r
+void FLASH_OB_Unlock(void);\r
+void FLASH_OB_Lock(void);\r
+void FLASH_OB_Launch(void);\r
+FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);\r
+FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);\r
+FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);\r
+FLASH_Status FLASH_OB_BORConfig(uint8_t OB_BOR);\r
+uint8_t FLASH_OB_GetUser(void);\r
+uint32_t FLASH_OB_GetWRP(void);\r
+FlagStatus FLASH_OB_GetRDP(void);\r
+uint8_t FLASH_OB_GetBOR(void);\r
+\r
+/* Interrupts and flags management functions **********************************/ \r
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);\r
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);\r
+void FLASH_ClearFlag(uint32_t FLASH_FLAG);\r
+FLASH_Status FLASH_GetStatus(void);\r
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);\r
+\r
+/** \r
+ * @brief FLASH memory functions that should be executed from internal SRAM.\r
+ * These functions are defined inside the "stm32l1xx_flash_ramfunc.c"\r
+ * file.\r
+ */ \r
+FLASH_Status FLASH_RUNPowerDownCmd(FunctionalState NewState);\r
+FLASH_Status FLASH_ProgramHalfPage(uint32_t Address, uint32_t* pBuffer);\r
+FLASH_Status DATA_EEPROM_EraseDoubleWord(uint32_t Address);\r
+FLASH_Status DATA_EEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data);\r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_FLASH_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_gpio.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the GPIO \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_GPIO_H\r
+#define __STM32L1xx_GPIO_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup GPIO\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \\r
+ ((PERIPH) == GPIOB) || \\r
+ ((PERIPH) == GPIOC) || \\r
+ ((PERIPH) == GPIOD) || \\r
+ ((PERIPH) == GPIOE) || \\r
+ ((PERIPH) == GPIOH))\r
+\r
+/** @defgroup Configuration_Mode_enumeration \r
+ * @{\r
+ */ \r
+typedef enum\r
+{ \r
+ GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */\r
+ GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */\r
+ GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */\r
+ GPIO_Mode_AN = 0x03 /*!< GPIO Analog Mode */\r
+}GPIOMode_TypeDef;\r
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN) || ((MODE) == GPIO_Mode_OUT) || \\r
+ ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Output_type_enumeration\r
+ * @{\r
+ */ \r
+typedef enum\r
+{ GPIO_OType_PP = 0x00,\r
+ GPIO_OType_OD = 0x01\r
+}GPIOOType_TypeDef;\r
+#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Output_Maximum_frequency_enumeration \r
+ * @{\r
+ */ \r
+typedef enum\r
+{ \r
+ GPIO_Speed_400KHz = 0x00, /*!< Very Low Speed */\r
+ GPIO_Speed_2MHz = 0x01, /*!< Low Speed */\r
+ GPIO_Speed_10MHz = 0x02, /*!< Medium Speed */\r
+ GPIO_Speed_40MHz = 0x03 /*!< High Speed */\r
+}GPIOSpeed_TypeDef;\r
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_400KHz) || ((SPEED) == GPIO_Speed_2MHz) || \\r
+ ((SPEED) == GPIO_Speed_10MHz)|| ((SPEED) == GPIO_Speed_40MHz))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Configuration_Pull-Up_Pull-Down_enumeration \r
+ * @{\r
+ */ \r
+typedef enum\r
+{ GPIO_PuPd_NOPULL = 0x00,\r
+ GPIO_PuPd_UP = 0x01,\r
+ GPIO_PuPd_DOWN = 0x02\r
+}GPIOPuPd_TypeDef;\r
+#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \\r
+ ((PUPD) == GPIO_PuPd_DOWN))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Bit_SET_and_Bit_RESET_enumeration\r
+ * @{\r
+ */\r
+typedef enum\r
+{ Bit_RESET = 0,\r
+ Bit_SET\r
+}BitAction;\r
+#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** \r
+ * @brief GPIO Init structure definition\r
+ */ \r
+typedef struct\r
+{\r
+ uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.\r
+ This parameter can be any value of @ref GPIO_pins_define */\r
+\r
+ GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.\r
+ This parameter can be a value of @ref GPIOMode_TypeDef */\r
+\r
+ GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.\r
+ This parameter can be a value of @ref GPIOSpeed_TypeDef */\r
+\r
+ GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins.\r
+ This parameter can be a value of @ref GPIOOType_TypeDef */\r
+\r
+ GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins.\r
+ This parameter can be a value of @ref GPIOPuPd_TypeDef */\r
+}GPIO_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup GPIO_Exported_Constants\r
+ * @{\r
+ */\r
+ \r
+/** @defgroup GPIO_pins_define \r
+ * @{\r
+ */\r
+#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */\r
+#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */\r
+#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */\r
+#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */\r
+#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */\r
+#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */\r
+#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */\r
+#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */\r
+#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */\r
+#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */\r
+#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */\r
+#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */\r
+#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */\r
+#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */\r
+#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */\r
+#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */\r
+#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */\r
+\r
+#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00)\r
+#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \\r
+ ((PIN) == GPIO_Pin_1) || \\r
+ ((PIN) == GPIO_Pin_2) || \\r
+ ((PIN) == GPIO_Pin_3) || \\r
+ ((PIN) == GPIO_Pin_4) || \\r
+ ((PIN) == GPIO_Pin_5) || \\r
+ ((PIN) == GPIO_Pin_6) || \\r
+ ((PIN) == GPIO_Pin_7) || \\r
+ ((PIN) == GPIO_Pin_8) || \\r
+ ((PIN) == GPIO_Pin_9) || \\r
+ ((PIN) == GPIO_Pin_10) || \\r
+ ((PIN) == GPIO_Pin_11) || \\r
+ ((PIN) == GPIO_Pin_12) || \\r
+ ((PIN) == GPIO_Pin_13) || \\r
+ ((PIN) == GPIO_Pin_14) || \\r
+ ((PIN) == GPIO_Pin_15))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Pin_sources \r
+ * @{\r
+ */ \r
+#define GPIO_PinSource0 ((uint8_t)0x00)\r
+#define GPIO_PinSource1 ((uint8_t)0x01)\r
+#define GPIO_PinSource2 ((uint8_t)0x02)\r
+#define GPIO_PinSource3 ((uint8_t)0x03)\r
+#define GPIO_PinSource4 ((uint8_t)0x04)\r
+#define GPIO_PinSource5 ((uint8_t)0x05)\r
+#define GPIO_PinSource6 ((uint8_t)0x06)\r
+#define GPIO_PinSource7 ((uint8_t)0x07)\r
+#define GPIO_PinSource8 ((uint8_t)0x08)\r
+#define GPIO_PinSource9 ((uint8_t)0x09)\r
+#define GPIO_PinSource10 ((uint8_t)0x0A)\r
+#define GPIO_PinSource11 ((uint8_t)0x0B)\r
+#define GPIO_PinSource12 ((uint8_t)0x0C)\r
+#define GPIO_PinSource13 ((uint8_t)0x0D)\r
+#define GPIO_PinSource14 ((uint8_t)0x0E)\r
+#define GPIO_PinSource15 ((uint8_t)0x0F)\r
+\r
+#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \\r
+ ((PINSOURCE) == GPIO_PinSource1) || \\r
+ ((PINSOURCE) == GPIO_PinSource2) || \\r
+ ((PINSOURCE) == GPIO_PinSource3) || \\r
+ ((PINSOURCE) == GPIO_PinSource4) || \\r
+ ((PINSOURCE) == GPIO_PinSource5) || \\r
+ ((PINSOURCE) == GPIO_PinSource6) || \\r
+ ((PINSOURCE) == GPIO_PinSource7) || \\r
+ ((PINSOURCE) == GPIO_PinSource8) || \\r
+ ((PINSOURCE) == GPIO_PinSource9) || \\r
+ ((PINSOURCE) == GPIO_PinSource10) || \\r
+ ((PINSOURCE) == GPIO_PinSource11) || \\r
+ ((PINSOURCE) == GPIO_PinSource12) || \\r
+ ((PINSOURCE) == GPIO_PinSource13) || \\r
+ ((PINSOURCE) == GPIO_PinSource14) || \\r
+ ((PINSOURCE) == GPIO_PinSource15))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Alternat_function_selection_define \r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief AF 0 selection \r
+ */ \r
+#define GPIO_AF_RTC_50Hz ((uint8_t)0x00) /*!< RTC 50/60 Hz Alternate Function mapping */\r
+#define GPIO_AF_MCO ((uint8_t)0x00) /*!< MCO Alternate Function mapping */\r
+#define GPIO_AF_RTC_AF1 ((uint8_t)0x00) /*!< RTC_AF1 Alternate Function mapping */\r
+#define GPIO_AF_WKUP ((uint8_t)0x00) /*!< Wakeup (WKUP1, WKUP2 and WKUP3) Alternate Function mapping */\r
+#define GPIO_AF_SWJ ((uint8_t)0x00) /*!< SWJ (SW and JTAG) Alternate Function mapping */\r
+#define GPIO_AF_TRACE ((uint8_t)0x00) /*!< TRACE Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 1 selection \r
+ */ \r
+#define GPIO_AF_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */\r
+/** \r
+ * @brief AF 2 selection \r
+ */ \r
+#define GPIO_AF_TIM3 ((uint8_t)0x02) /*!< TIM3 Alternate Function mapping */\r
+#define GPIO_AF_TIM4 ((uint8_t)0x02) /*!< TIM4 Alternate Function mapping */\r
+/** \r
+ * @brief AF 3 selection \r
+ */ \r
+#define GPIO_AF_TIM9 ((uint8_t)0x03) /*!< TIM9 Alternate Function mapping */\r
+#define GPIO_AF_TIM10 ((uint8_t)0x03) /*!< TIM10 Alternate Function mapping */\r
+#define GPIO_AF_TIM11 ((uint8_t)0x03) /*!< TIM11 Alternate Function mapping */\r
+/** \r
+ * @brief AF 4 selection \r
+ */ \r
+#define GPIO_AF_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */\r
+#define GPIO_AF_I2C2 ((uint8_t)0x04) /*!< I2C2 Alternate Function mapping */\r
+/** \r
+ * @brief AF 5 selection \r
+ */ \r
+#define GPIO_AF_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */\r
+#define GPIO_AF_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */\r
+/** \r
+ * @brief AF 7 selection \r
+ */ \r
+#define GPIO_AF_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */\r
+#define GPIO_AF_USART2 ((uint8_t)0x07) /*!< USART2 Alternate Function mapping */\r
+#define GPIO_AF_USART3 ((uint8_t)0x07) /*!< USART3 Alternate Function mapping */\r
+/** \r
+ * @brief AF 10 selection \r
+ */ \r
+#define GPIO_AF_USB ((uint8_t)0xA) /*!< USB Full speed device Alternate Function mapping */\r
+/** \r
+ * @brief AF 11 selection \r
+ */ \r
+#define GPIO_AF_LCD ((uint8_t)0x0B) /*!< LCD Alternate Function mapping */\r
+/** \r
+ * @brief AF 14 selection \r
+ */ \r
+#define GPIO_AF_RI ((uint8_t)0x0E) /*!< RI Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 15 selection \r
+ */ \r
+#define GPIO_AF_EVENTOUT ((uint8_t)0x0F) /*!< EVENTOUT Alternate Function mapping */\r
+\r
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_MCO) || \\r
+ ((AF) == GPIO_AF_RTC_AF1) || ((AF) == GPIO_AF_WKUP) || \\r
+ ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \\r
+ ((AF) == GPIO_AF_TIM2) || ((AF)== GPIO_AF_TIM3) || \\r
+ ((AF) == GPIO_AF_TIM4) || ((AF)== GPIO_AF_TIM9) || \\r
+ ((AF) == GPIO_AF_TIM10) || ((AF)== GPIO_AF_TIM11) || \\r
+ ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \\r
+ ((AF) == GPIO_AF_SPI1) || ((AF) == GPIO_AF_SPI2) || \\r
+ ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \\r
+ ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_USB) || \\r
+ ((AF) == GPIO_AF_LCD) || ((AF) == GPIO_AF_RI) || \\r
+ ((AF) == GPIO_AF_EVENTOUT))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Legacy \r
+ * @{\r
+ */\r
+ \r
+#define GPIO_Mode_AIN GPIO_Mode_AN\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Function used to set the GPIO configuration to the default reset state ****/\r
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);\r
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);\r
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+\r
+/* GPIO Read and Write functions **********************************************/\r
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);\r
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);\r
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);\r
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);\r
+\r
+/* GPIO Alternate functions configuration functions ***************************/\r
+void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32L1xx_GPIO_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_i2c.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the I2C firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_I2C_H\r
+#define __STM32L1xx_I2C_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup I2C\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief I2C Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency.\r
+ This parameter must be set to a value lower than 400kHz */\r
+\r
+ uint16_t I2C_Mode; /*!< Specifies the I2C mode.\r
+ This parameter can be a value of @ref I2C_mode */\r
+\r
+ uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle.\r
+ This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */\r
+\r
+ uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address.\r
+ This parameter can be a 7-bit or 10-bit address. */\r
+\r
+ uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement.\r
+ This parameter can be a value of @ref I2C_acknowledgement */\r
+\r
+ uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.\r
+ This parameter can be a value of @ref I2C_acknowledged_address */\r
+}I2C_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+\r
+/** @defgroup I2C_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \\r
+ ((PERIPH) == I2C2))\r
+/** @defgroup I2C_mode \r
+ * @{\r
+ */\r
+\r
+#define I2C_Mode_I2C ((uint16_t)0x0000)\r
+#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) \r
+#define I2C_Mode_SMBusHost ((uint16_t)0x000A)\r
+#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \\r
+ ((MODE) == I2C_Mode_SMBusDevice) || \\r
+ ((MODE) == I2C_Mode_SMBusHost))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_duty_cycle_in_fast_mode \r
+ * @{\r
+ */\r
+\r
+#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */\r
+#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */\r
+#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \\r
+ ((CYCLE) == I2C_DutyCycle_2))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup I2C_acknowledgement\r
+ * @{\r
+ */\r
+\r
+#define I2C_Ack_Enable ((uint16_t)0x0400)\r
+#define I2C_Ack_Disable ((uint16_t)0x0000)\r
+#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \\r
+ ((STATE) == I2C_Ack_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_transfer_direction \r
+ * @{\r
+ */\r
+\r
+#define I2C_Direction_Transmitter ((uint8_t)0x00)\r
+#define I2C_Direction_Receiver ((uint8_t)0x01)\r
+#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \\r
+ ((DIRECTION) == I2C_Direction_Receiver))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_acknowledged_address \r
+ * @{\r
+ */\r
+\r
+#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)\r
+#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)\r
+#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \\r
+ ((ADDRESS) == I2C_AcknowledgedAddress_10bit))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup I2C_registers \r
+ * @{\r
+ */\r
+\r
+#define I2C_Register_CR1 ((uint8_t)0x00)\r
+#define I2C_Register_CR2 ((uint8_t)0x04)\r
+#define I2C_Register_OAR1 ((uint8_t)0x08)\r
+#define I2C_Register_OAR2 ((uint8_t)0x0C)\r
+#define I2C_Register_DR ((uint8_t)0x10)\r
+#define I2C_Register_SR1 ((uint8_t)0x14)\r
+#define I2C_Register_SR2 ((uint8_t)0x18)\r
+#define I2C_Register_CCR ((uint8_t)0x1C)\r
+#define I2C_Register_TRISE ((uint8_t)0x20)\r
+#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \\r
+ ((REGISTER) == I2C_Register_CR2) || \\r
+ ((REGISTER) == I2C_Register_OAR1) || \\r
+ ((REGISTER) == I2C_Register_OAR2) || \\r
+ ((REGISTER) == I2C_Register_DR) || \\r
+ ((REGISTER) == I2C_Register_SR1) || \\r
+ ((REGISTER) == I2C_Register_SR2) || \\r
+ ((REGISTER) == I2C_Register_CCR) || \\r
+ ((REGISTER) == I2C_Register_TRISE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_SMBus_alert_pin_level \r
+ * @{\r
+ */\r
+\r
+#define I2C_SMBusAlert_Low ((uint16_t)0x2000)\r
+#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)\r
+#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \\r
+ ((ALERT) == I2C_SMBusAlert_High))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_PEC_position \r
+ * @{\r
+ */\r
+\r
+#define I2C_PECPosition_Next ((uint16_t)0x0800)\r
+#define I2C_PECPosition_Current ((uint16_t)0xF7FF)\r
+#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \\r
+ ((POSITION) == I2C_PECPosition_Current))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup I2C_interrupts_definition \r
+ * @{\r
+ */\r
+\r
+#define I2C_IT_BUF ((uint16_t)0x0400)\r
+#define I2C_IT_EVT ((uint16_t)0x0200)\r
+#define I2C_IT_ERR ((uint16_t)0x0100)\r
+#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup I2C_interrupts_definition \r
+ * @{\r
+ */\r
+\r
+#define I2C_IT_SMBALERT ((uint32_t)0x01008000)\r
+#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)\r
+#define I2C_IT_PECERR ((uint32_t)0x01001000)\r
+#define I2C_IT_OVR ((uint32_t)0x01000800)\r
+#define I2C_IT_AF ((uint32_t)0x01000400)\r
+#define I2C_IT_ARLO ((uint32_t)0x01000200)\r
+#define I2C_IT_BERR ((uint32_t)0x01000100)\r
+#define I2C_IT_TXE ((uint32_t)0x06000080)\r
+#define I2C_IT_RXNE ((uint32_t)0x06000040)\r
+#define I2C_IT_STOPF ((uint32_t)0x02000010)\r
+#define I2C_IT_ADD10 ((uint32_t)0x02000008)\r
+#define I2C_IT_BTF ((uint32_t)0x02000004)\r
+#define I2C_IT_ADDR ((uint32_t)0x02000002)\r
+#define I2C_IT_SB ((uint32_t)0x02000001)\r
+\r
+#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))\r
+\r
+#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \\r
+ ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \\r
+ ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \\r
+ ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \\r
+ ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \\r
+ ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \\r
+ ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_flags_definition \r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief SR2 register flags \r
+ */\r
+\r
+#define I2C_FLAG_DUALF ((uint32_t)0x00800000)\r
+#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)\r
+#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)\r
+#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)\r
+#define I2C_FLAG_TRA ((uint32_t)0x00040000)\r
+#define I2C_FLAG_BUSY ((uint32_t)0x00020000)\r
+#define I2C_FLAG_MSL ((uint32_t)0x00010000)\r
+\r
+/** \r
+ * @brief SR1 register flags \r
+ */\r
+\r
+#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)\r
+#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)\r
+#define I2C_FLAG_PECERR ((uint32_t)0x10001000)\r
+#define I2C_FLAG_OVR ((uint32_t)0x10000800)\r
+#define I2C_FLAG_AF ((uint32_t)0x10000400)\r
+#define I2C_FLAG_ARLO ((uint32_t)0x10000200)\r
+#define I2C_FLAG_BERR ((uint32_t)0x10000100)\r
+#define I2C_FLAG_TXE ((uint32_t)0x10000080)\r
+#define I2C_FLAG_RXNE ((uint32_t)0x10000040)\r
+#define I2C_FLAG_STOPF ((uint32_t)0x10000010)\r
+#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)\r
+#define I2C_FLAG_BTF ((uint32_t)0x10000004)\r
+#define I2C_FLAG_ADDR ((uint32_t)0x10000002)\r
+#define I2C_FLAG_SB ((uint32_t)0x10000001)\r
+\r
+#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))\r
+\r
+#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \\r
+ ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \\r
+ ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \\r
+ ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \\r
+ ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \\r
+ ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \\r
+ ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \\r
+ ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \\r
+ ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \\r
+ ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \\r
+ ((FLAG) == I2C_FLAG_SB))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Events \r
+ * @{\r
+ */\r
+\r
+/**\r
+ ===============================================================================\r
+ I2C Master Events (Events grouped in order of communication) \r
+ =============================================================================== \r
+ */\r
+\r
+/** \r
+ * @brief Communication start\r
+ * \r
+ * After sending the START condition (I2C_GenerateSTART() function) the master \r
+ * has to wait for this event. It means that the Start condition has been correctly \r
+ * released on the I2C bus (the bus is free, no other devices is communicating).\r
+ * \r
+ */\r
+/* --EV5 */\r
+#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */\r
+\r
+/** \r
+ * @brief Address Acknowledge\r
+ * \r
+ * After checking on EV5 (start condition correctly released on the bus), the \r
+ * master sends the address of the slave(s) with which it will communicate \r
+ * (I2C_Send7bitAddress() function, it also determines the direction of the communication: \r
+ * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges \r
+ * his address. If an acknowledge is sent on the bus, one of the following events will \r
+ * be set:\r
+ * \r
+ * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED \r
+ * event is set.\r
+ * \r
+ * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED \r
+ * is set\r
+ * \r
+ * 3) In case of 10-Bit addressing mode, the master (just after generating the START \r
+ * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() \r
+ * function). Then master should wait on EV9. It means that the 10-bit addressing \r
+ * header has been correctly sent on the bus. Then master should send the second part of \r
+ * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master \r
+ * should wait for event EV6. \r
+ * \r
+ */\r
+\r
+/* --EV6 */\r
+#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */\r
+#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */\r
+/* --EV9 */\r
+#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */\r
+\r
+/** \r
+ * @brief Communication events\r
+ * \r
+ * If a communication is established (START condition generated and slave address \r
+ * acknowledged) then the master has to check on one of the following events for \r
+ * communication procedures:\r
+ * \r
+ * 1) Master Receiver mode: The master has to wait on the event EV7 then to read \r
+ * the data received from the slave (I2C_ReceiveData() function).\r
+ * \r
+ * 2) Master Transmitter mode: The master has to send data (I2C_SendData() \r
+ * function) then to wait on event EV8 or EV8_2.\r
+ * These two events are similar: \r
+ * - EV8 means that the data has been written in the data register and is \r
+ * being shifted out.\r
+ * - EV8_2 means that the data has been physically shifted out and output \r
+ * on the bus.\r
+ * In most cases, using EV8 is sufficient for the application.\r
+ * Using EV8_2 leads to a slower communication but ensure more reliable test.\r
+ * EV8_2 is also more suitable than EV8 for testing on the last data transmission \r
+ * (before Stop condition generation).\r
+ * \r
+ * @note In case the user software does not guarantee that this event EV7 is \r
+ * managed before the current byte end of transfer, then user may check on EV7 \r
+ * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).\r
+ * In this case the communication may be slower.\r
+ * \r
+ */\r
+\r
+/* Master RECEIVER mode -----------------------------*/ \r
+/* --EV7 */\r
+#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */\r
+\r
+/* Master TRANSMITTER mode --------------------------*/\r
+/* --EV8 */\r
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */\r
+/* --EV8_2 */\r
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */\r
+\r
+\r
+/**\r
+ ===============================================================================\r
+ I2C Slave Events (Events grouped in order of communication) \r
+ =============================================================================== \r
+ */\r
+\r
+\r
+/** \r
+ * @brief Communication start events\r
+ * \r
+ * Wait on one of these events at the start of the communication. It means that \r
+ * the I2C peripheral detected a Start condition on the bus (generated by master \r
+ * device) followed by the peripheral address. The peripheral generates an ACK \r
+ * condition on the bus (if the acknowledge feature is enabled through function \r
+ * I2C_AcknowledgeConfig()) and the events listed above are set :\r
+ * \r
+ * 1) In normal case (only one address managed by the slave), when the address \r
+ * sent by the master matches the own address of the peripheral (configured by \r
+ * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set \r
+ * (where XXX could be TRANSMITTER or RECEIVER).\r
+ * \r
+ * 2) In case the address sent by the master matches the second address of the \r
+ * peripheral (configured by the function I2C_OwnAddress2Config() and enabled \r
+ * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED \r
+ * (where XXX could be TRANSMITTER or RECEIVER) are set.\r
+ * \r
+ * 3) In case the address sent by the master is General Call (address 0x00) and \r
+ * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) \r
+ * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. \r
+ * \r
+ */\r
+\r
+/* --EV1 (all the events below are variants of EV1) */ \r
+/* 1) Case of One Single Address managed by the slave */\r
+#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */\r
+#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */\r
+\r
+/* 2) Case of Dual address managed by the slave */\r
+#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */\r
+#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */\r
+\r
+/* 3) Case of General Call enabled for the slave */\r
+#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */\r
+\r
+/** \r
+ * @brief Communication events\r
+ * \r
+ * Wait on one of these events when EV1 has already been checked and: \r
+ * \r
+ * - Slave RECEIVER mode:\r
+ * - EV2: When the application is expecting a data byte to be received. \r
+ * - EV4: When the application is expecting the end of the communication: master \r
+ * sends a stop condition and data transmission is stopped.\r
+ * \r
+ * - Slave Transmitter mode:\r
+ * - EV3: When a byte has been transmitted by the slave and the application is expecting \r
+ * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and\r
+ * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be \r
+ * used when the user software doesn't guarantee the EV3 is managed before the\r
+ * current byte end of transfer.\r
+ * - EV3_2: When the master sends a NACK in order to tell slave that data transmission \r
+ * shall end (before sending the STOP condition). In this case slave has to stop sending \r
+ * data bytes and expect a Stop condition on the bus.\r
+ * \r
+ * @note In case the user software does not guarantee that the event EV2 is \r
+ * managed before the current byte end of transfer, then user may check on EV2 \r
+ * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).\r
+ * In this case the communication may be slower.\r
+ *\r
+ */\r
+\r
+/* Slave RECEIVER mode --------------------------*/ \r
+/* --EV2 */\r
+#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */\r
+/* --EV4 */\r
+#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */\r
+\r
+/* Slave TRANSMITTER mode -----------------------*/\r
+/* --EV3 */\r
+#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */\r
+#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */\r
+/* --EV3_2 */\r
+#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */\r
+\r
+/**\r
+ ===============================================================================\r
+ End of Events Description \r
+ =============================================================================== \r
+ */\r
+\r
+#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \\r
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \\r
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \\r
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \\r
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_own_address1 \r
+ * @{\r
+ */\r
+\r
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_clock_speed \r
+ * @{\r
+ */\r
+\r
+#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Function used to set the I2C configuration to the default reset state *****/\r
+void I2C_DeInit(I2C_TypeDef* I2Cx);\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);\r
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);\r
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);\r
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);\r
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);\r
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);\r
+\r
+/* Data transfers functions ***************************************************/ \r
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);\r
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);\r
+\r
+/* PEC management functions ***************************************************/ \r
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);\r
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);\r
+\r
+/* DMA transfers management functions *****************************************/\r
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+\r
+\r
+/* Interrupts, events and flags management functions **************************/\r
+uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);\r
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);\r
+\r
+/**\r
+ * @brief\r
+ * \r
+@verbatim \r
+ ===============================================================================\r
+ I2C State Monitoring Functions \r
+ =============================================================================== \r
+ This I2C driver provides three different ways for I2C state monitoring\r
+ depending on the application requirements and constraints:\r
+ \r
+ \r
+ 1. Basic state monitoring (Using I2C_CheckEvent() function)\r
+ -----------------------------------------------------------\r
+ It compares the status registers (SR1 and SR2) content to a given event\r
+ (can be the combination of one or more flags).\r
+ It returns SUCCESS if the current status includes the given flags \r
+ and returns ERROR if one or more flags are missing in the current status.\r
+\r
+ - When to use\r
+ - This function is suitable for most applications as well as for startup \r
+ activity since the events are fully described in the product reference \r
+ manual (RM0038).\r
+ - It is also suitable for users who need to define their own events.\r
+\r
+ - Limitations\r
+ - If an error occurs (ie. error flags are set besides to the monitored \r
+ flags), the I2C_CheckEvent() function may return SUCCESS despite \r
+ the communication hold or corrupted real state. \r
+ In this case, it is advised to use error interrupts to monitor \r
+ the error events and handle them in the interrupt IRQ handler.\r
+ \r
+ @note \r
+ For error management, it is advised to use the following functions:\r
+ - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).\r
+ - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.\r
+ Where x is the peripheral instance (I2C1, I2C2 ...)\r
+ - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the \r
+ I2Cx_ER_IRQHandler() function in order to determine which error occurred.\r
+ - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() \r
+ and/or I2C_GenerateStop() in order to clear the error flag and source \r
+ and return to correct communciation status.\r
+ \r
+ \r
+ 2. Advanced state monitoring (Using the function I2C_GetLastEvent())\r
+ -------------------------------------------------------------------- \r
+ Using the function I2C_GetLastEvent() which returns the image of both status \r
+ registers in a single word (uint32_t) (Status Register 2 value is shifted left \r
+ by 16 bits and concatenated to Status Register 1).\r
+\r
+ - When to use\r
+ - This function is suitable for the same applications above but it \r
+ allows to overcome the mentioned limitation of I2C_GetFlagStatus() \r
+ function.\r
+ - The returned value could be compared to events already defined in \r
+ the library (stm32l1xx_i2c.h) or to custom values defined by user.\r
+ This function is suitable when multiple flags are monitored at the \r
+ same time.\r
+ - At the opposite of I2C_CheckEvent() function, this function allows \r
+ user to choose when an event is accepted (when all events flags are \r
+ set and no other flags are set or just when the needed flags are set \r
+ like I2C_CheckEvent() function.\r
+\r
+ - Limitations\r
+ - User may need to define his own events.\r
+ - Same remark concerning the error management is applicable for this \r
+ function if user decides to check only regular communication flags \r
+ (and ignores error flags).\r
+ \r
+ \r
+ 3. Flag-based state monitoring (Using the function I2C_GetFlagStatus())\r
+ -----------------------------------------------------------------------\r
+ \r
+ Using the function I2C_GetFlagStatus() which simply returns the status of \r
+ one single flag (ie. I2C_FLAG_RXNE ...). \r
+\r
+ - When to use\r
+ - This function could be used for specific applications or in debug \r
+ phase.\r
+ - It is suitable when only one flag checking is needed (most I2C \r
+ events are monitored through multiple flags).\r
+ - Limitations: \r
+ - When calling this function, the Status register is accessed. \r
+ Some flags are cleared when the status register is accessed. \r
+ So checking the status of one Flag, may clear other ones.\r
+ - Function may need to be called twice or more in order to monitor \r
+ one single event.\r
+ \r
+ For detailed description of Events, please refer to section I2C_Events in \r
+ stm32l1xx_i2c.h file.\r
+ \r
+@endverbatim\r
+ * \r
+ */\r
+\r
+/**\r
+ ===============================================================================\r
+ 1. Basic state monitoring \r
+ =============================================================================== \r
+ */\r
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);\r
+/**\r
+ ===============================================================================\r
+ 2. Advanced state monitoring \r
+ =============================================================================== \r
+ */\r
+uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);\r
+/**\r
+ ===============================================================================\r
+ 3. Flag-based state monitoring \r
+ =============================================================================== \r
+ */\r
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);\r
+\r
+\r
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);\r
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);\r
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32L1xx_I2C_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_iwdg.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the IWDG \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_IWDG_H\r
+#define __STM32L1xx_IWDG_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup IWDG\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup IWDG_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup IWDG_WriteAccess\r
+ * @{\r
+ */\r
+\r
+#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)\r
+#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)\r
+#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \\r
+ ((ACCESS) == IWDG_WriteAccess_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IWDG_prescaler \r
+ * @{\r
+ */\r
+\r
+#define IWDG_Prescaler_4 ((uint8_t)0x00)\r
+#define IWDG_Prescaler_8 ((uint8_t)0x01)\r
+#define IWDG_Prescaler_16 ((uint8_t)0x02)\r
+#define IWDG_Prescaler_32 ((uint8_t)0x03)\r
+#define IWDG_Prescaler_64 ((uint8_t)0x04)\r
+#define IWDG_Prescaler_128 ((uint8_t)0x05)\r
+#define IWDG_Prescaler_256 ((uint8_t)0x06)\r
+#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \\r
+ ((PRESCALER) == IWDG_Prescaler_8) || \\r
+ ((PRESCALER) == IWDG_Prescaler_16) || \\r
+ ((PRESCALER) == IWDG_Prescaler_32) || \\r
+ ((PRESCALER) == IWDG_Prescaler_64) || \\r
+ ((PRESCALER) == IWDG_Prescaler_128)|| \\r
+ ((PRESCALER) == IWDG_Prescaler_256))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IWDG_Flag \r
+ * @{\r
+ */\r
+\r
+#define IWDG_FLAG_PVU ((uint16_t)0x0001)\r
+#define IWDG_FLAG_RVU ((uint16_t)0x0002)\r
+#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))\r
+#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Prescaler and Counter configuration functions ******************************/\r
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);\r
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);\r
+void IWDG_SetReload(uint16_t Reload);\r
+void IWDG_ReloadCounter(void);\r
+\r
+/* IWDG activation function ***************************************************/\r
+void IWDG_Enable(void);\r
+\r
+/* Flag management function ***************************************************/\r
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_IWDG_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_lcd.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the LCD firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_LCD_H\r
+#define __STM32L1xx_LCD_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup LCD\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+ \r
+/** \r
+ * @brief LCD Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t LCD_Prescaler; /*!< Configures the LCD Prescaler. \r
+ This parameter can be one value of @ref LCD_Prescaler */\r
+ uint32_t LCD_Divider; /*!< Configures the LCD Divider.\r
+ This parameter can be one value of @ref LCD_Divider */\r
+ uint32_t LCD_Duty; /*!< Configures the LCD Duty.\r
+ This parameter can be one value of @ref LCD_Duty */\r
+ uint32_t LCD_Bias; /*!< Configures the LCD Bias.\r
+ This parameter can be one value of @ref LCD_Bias */ \r
+ uint32_t LCD_VoltageSource; /*!< Selects the LCD Voltage source.\r
+ This parameter can be one value of @ref LCD_Voltage_Source */\r
+}LCD_InitTypeDef;\r
+\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup LCD_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup LCD_Prescaler \r
+ * @{\r
+ */\r
+\r
+#define LCD_Prescaler_1 ((uint32_t)0x00000000) /*!< CLKPS = LCDCLK */\r
+#define LCD_Prescaler_2 ((uint32_t)0x00400000) /*!< CLKPS = LCDCLK/2 */\r
+#define LCD_Prescaler_4 ((uint32_t)0x00800000) /*!< CLKPS = LCDCLK/4 */\r
+#define LCD_Prescaler_8 ((uint32_t)0x00C00000) /*!< CLKPS = LCDCLK/8 */\r
+#define LCD_Prescaler_16 ((uint32_t)0x01000000) /*!< CLKPS = LCDCLK/16 */\r
+#define LCD_Prescaler_32 ((uint32_t)0x01400000) /*!< CLKPS = LCDCLK/32 */\r
+#define LCD_Prescaler_64 ((uint32_t)0x01800000) /*!< CLKPS = LCDCLK/64 */\r
+#define LCD_Prescaler_128 ((uint32_t)0x01C00000) /*!< CLKPS = LCDCLK/128 */\r
+#define LCD_Prescaler_256 ((uint32_t)0x02000000) /*!< CLKPS = LCDCLK/256 */\r
+#define LCD_Prescaler_512 ((uint32_t)0x02400000) /*!< CLKPS = LCDCLK/512 */\r
+#define LCD_Prescaler_1024 ((uint32_t)0x02800000) /*!< CLKPS = LCDCLK/1024 */\r
+#define LCD_Prescaler_2048 ((uint32_t)0x02C00000) /*!< CLKPS = LCDCLK/2048 */\r
+#define LCD_Prescaler_4096 ((uint32_t)0x03000000) /*!< CLKPS = LCDCLK/4096 */\r
+#define LCD_Prescaler_8192 ((uint32_t)0x03400000) /*!< CLKPS = LCDCLK/8192 */\r
+#define LCD_Prescaler_16384 ((uint32_t)0x03800000) /*!< CLKPS = LCDCLK/16384 */\r
+#define LCD_Prescaler_32768 ((uint32_t)0x03C00000) /*!< CLKPS = LCDCLK/32768 */\r
+\r
+#define IS_LCD_PRESCALER(PRESCALER) (((PRESCALER) == LCD_Prescaler_1) || \\r
+ ((PRESCALER) == LCD_Prescaler_2) || \\r
+ ((PRESCALER) == LCD_Prescaler_4) || \\r
+ ((PRESCALER) == LCD_Prescaler_8) || \\r
+ ((PRESCALER) == LCD_Prescaler_16) || \\r
+ ((PRESCALER) == LCD_Prescaler_32) || \\r
+ ((PRESCALER) == LCD_Prescaler_64) || \\r
+ ((PRESCALER) == LCD_Prescaler_128) || \\r
+ ((PRESCALER) == LCD_Prescaler_256) || \\r
+ ((PRESCALER) == LCD_Prescaler_512) || \\r
+ ((PRESCALER) == LCD_Prescaler_1024) || \\r
+ ((PRESCALER) == LCD_Prescaler_2048) || \\r
+ ((PRESCALER) == LCD_Prescaler_4096) || \\r
+ ((PRESCALER) == LCD_Prescaler_8192) || \\r
+ ((PRESCALER) == LCD_Prescaler_16384) || \\r
+ ((PRESCALER) == LCD_Prescaler_32768))\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup LCD_Divider \r
+ * @{\r
+ */\r
+\r
+#define LCD_Divider_16 ((uint32_t)0x00000000) /*!< LCD frequency = CLKPS/16 */\r
+#define LCD_Divider_17 ((uint32_t)0x00040000) /*!< LCD frequency = CLKPS/17 */\r
+#define LCD_Divider_18 ((uint32_t)0x00080000) /*!< LCD frequency = CLKPS/18 */\r
+#define LCD_Divider_19 ((uint32_t)0x000C0000) /*!< LCD frequency = CLKPS/19 */\r
+#define LCD_Divider_20 ((uint32_t)0x00100000) /*!< LCD frequency = CLKPS/20 */\r
+#define LCD_Divider_21 ((uint32_t)0x00140000) /*!< LCD frequency = CLKPS/21 */\r
+#define LCD_Divider_22 ((uint32_t)0x00180000) /*!< LCD frequency = CLKPS/22 */\r
+#define LCD_Divider_23 ((uint32_t)0x001C0000) /*!< LCD frequency = CLKPS/23 */\r
+#define LCD_Divider_24 ((uint32_t)0x00200000) /*!< LCD frequency = CLKPS/24 */\r
+#define LCD_Divider_25 ((uint32_t)0x00240000) /*!< LCD frequency = CLKPS/25 */\r
+#define LCD_Divider_26 ((uint32_t)0x00280000) /*!< LCD frequency = CLKPS/26 */\r
+#define LCD_Divider_27 ((uint32_t)0x002C0000) /*!< LCD frequency = CLKPS/27 */\r
+#define LCD_Divider_28 ((uint32_t)0x00300000) /*!< LCD frequency = CLKPS/28 */\r
+#define LCD_Divider_29 ((uint32_t)0x00340000) /*!< LCD frequency = CLKPS/29 */\r
+#define LCD_Divider_30 ((uint32_t)0x00380000) /*!< LCD frequency = CLKPS/30 */\r
+#define LCD_Divider_31 ((uint32_t)0x003C0000) /*!< LCD frequency = CLKPS/31 */\r
+\r
+#define IS_LCD_DIVIDER(DIVIDER) (((DIVIDER) == LCD_Divider_16) || \\r
+ ((DIVIDER) == LCD_Divider_17) || \\r
+ ((DIVIDER) == LCD_Divider_18) || \\r
+ ((DIVIDER) == LCD_Divider_19) || \\r
+ ((DIVIDER) == LCD_Divider_20) || \\r
+ ((DIVIDER) == LCD_Divider_21) || \\r
+ ((DIVIDER) == LCD_Divider_22) || \\r
+ ((DIVIDER) == LCD_Divider_23) || \\r
+ ((DIVIDER) == LCD_Divider_24) || \\r
+ ((DIVIDER) == LCD_Divider_25) || \\r
+ ((DIVIDER) == LCD_Divider_26) || \\r
+ ((DIVIDER) == LCD_Divider_27) || \\r
+ ((DIVIDER) == LCD_Divider_28) || \\r
+ ((DIVIDER) == LCD_Divider_29) || \\r
+ ((DIVIDER) == LCD_Divider_30) || \\r
+ ((DIVIDER) == LCD_Divider_31))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup LCD_Duty \r
+ * @{\r
+ */\r
+ \r
+#define LCD_Duty_Static ((uint32_t)0x00000000) /*!< Static duty */\r
+#define LCD_Duty_1_2 ((uint32_t)0x00000004) /*!< 1/2 duty */\r
+#define LCD_Duty_1_3 ((uint32_t)0x00000008) /*!< 1/3 duty */\r
+#define LCD_Duty_1_4 ((uint32_t)0x0000000C) /*!< 1/4 duty */\r
+#define LCD_Duty_1_8 ((uint32_t)0x00000010) /*!< 1/4 duty */\r
+\r
+#define IS_LCD_DUTY(DUTY) (((DUTY) == LCD_Duty_Static) || \\r
+ ((DUTY) == LCD_Duty_1_2) || \\r
+ ((DUTY) == LCD_Duty_1_3) || \\r
+ ((DUTY) == LCD_Duty_1_4) || \\r
+ ((DUTY) == LCD_Duty_1_8))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+\r
+/** @defgroup LCD_Bias \r
+ * @{\r
+ */\r
+ \r
+#define LCD_Bias_1_4 ((uint32_t)0x00000000) /*!< 1/4 Bias */\r
+#define LCD_Bias_1_2 LCD_CR_BIAS_0 /*!< 1/2 Bias */\r
+#define LCD_Bias_1_3 LCD_CR_BIAS_1 /*!< 1/3 Bias */\r
+\r
+#define IS_LCD_BIAS(BIAS) (((BIAS) == LCD_Bias_1_4) || \\r
+ ((BIAS) == LCD_Bias_1_2) || \\r
+ ((BIAS) == LCD_Bias_1_3))\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup LCD_Voltage_Source \r
+ * @{\r
+ */\r
+ \r
+#define LCD_VoltageSource_Internal ((uint32_t)0x00000000) /*!< Internal voltage source for the LCD */\r
+#define LCD_VoltageSource_External LCD_CR_VSEL /*!< External voltage source for the LCD */\r
+\r
+#define IS_LCD_VOLTAGE_SOURCE(SOURCE) (((SOURCE) == LCD_VoltageSource_Internal) || \\r
+ ((SOURCE) == LCD_VoltageSource_External))\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup LCD_Interrupts \r
+ * @{\r
+ */\r
+#define LCD_IT_SOF LCD_FCR_SOFIE\r
+#define LCD_IT_UDD LCD_FCR_UDDIE\r
+\r
+#define IS_LCD_IT(IT) ((((IT) & (uint32_t)0xFFFFFFF5) == 0x00) && ((IT) != 0x00))\r
+\r
+#define IS_LCD_GET_IT(IT) (((IT) == LCD_IT_SOF) || ((IT) == LCD_IT_UDD))\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LCD_PulseOnDuration \r
+ * @{\r
+ */\r
+\r
+#define LCD_PulseOnDuration_0 ((uint32_t)0x00000000) /*!< Pulse ON duration = 0 pulse */\r
+#define LCD_PulseOnDuration_1 ((uint32_t)0x00000010) /*!< Pulse ON duration = 1/CK_PS */\r
+#define LCD_PulseOnDuration_2 ((uint32_t)0x00000020) /*!< Pulse ON duration = 2/CK_PS */\r
+#define LCD_PulseOnDuration_3 ((uint32_t)0x00000030) /*!< Pulse ON duration = 3/CK_PS */\r
+#define LCD_PulseOnDuration_4 ((uint32_t)0x00000040) /*!< Pulse ON duration = 4/CK_PS */\r
+#define LCD_PulseOnDuration_5 ((uint32_t)0x00000050) /*!< Pulse ON duration = 5/CK_PS */\r
+#define LCD_PulseOnDuration_6 ((uint32_t)0x00000060) /*!< Pulse ON duration = 6/CK_PS */\r
+#define LCD_PulseOnDuration_7 ((uint32_t)0x00000070) /*!< Pulse ON duration = 7/CK_PS */\r
+\r
+#define IS_LCD_PULSE_ON_DURATION(DURATION) (((DURATION) == LCD_PulseOnDuration_0) || \\r
+ ((DURATION) == LCD_PulseOnDuration_1) || \\r
+ ((DURATION) == LCD_PulseOnDuration_2) || \\r
+ ((DURATION) == LCD_PulseOnDuration_3) || \\r
+ ((DURATION) == LCD_PulseOnDuration_4) || \\r
+ ((DURATION) == LCD_PulseOnDuration_5) || \\r
+ ((DURATION) == LCD_PulseOnDuration_6) || \\r
+ ((DURATION) == LCD_PulseOnDuration_7))\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup LCD_DeadTime \r
+ * @{\r
+ */\r
+\r
+#define LCD_DeadTime_0 ((uint32_t)0x00000000) /*!< No dead Time */\r
+#define LCD_DeadTime_1 ((uint32_t)0x00000080) /*!< One Phase between different couple of Frame */\r
+#define LCD_DeadTime_2 ((uint32_t)0x00000100) /*!< Two Phase between different couple of Frame */\r
+#define LCD_DeadTime_3 ((uint32_t)0x00000180) /*!< Three Phase between different couple of Frame */\r
+#define LCD_DeadTime_4 ((uint32_t)0x00000200) /*!< Four Phase between different couple of Frame */\r
+#define LCD_DeadTime_5 ((uint32_t)0x00000280) /*!< Five Phase between different couple of Frame */\r
+#define LCD_DeadTime_6 ((uint32_t)0x00000300) /*!< Six Phase between different couple of Frame */\r
+#define LCD_DeadTime_7 ((uint32_t)0x00000380) /*!< Seven Phase between different couple of Frame */\r
+\r
+#define IS_LCD_DEAD_TIME(TIME) (((TIME) == LCD_DeadTime_0) || \\r
+ ((TIME) == LCD_DeadTime_1) || \\r
+ ((TIME) == LCD_DeadTime_2) || \\r
+ ((TIME) == LCD_DeadTime_3) || \\r
+ ((TIME) == LCD_DeadTime_4) || \\r
+ ((TIME) == LCD_DeadTime_5) || \\r
+ ((TIME) == LCD_DeadTime_6) || \\r
+ ((TIME) == LCD_DeadTime_7))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LCD_BlinkMode \r
+ * @{\r
+ */\r
+\r
+#define LCD_BlinkMode_Off ((uint32_t)0x00000000) /*!< Blink disabled */\r
+#define LCD_BlinkMode_SEG0_COM0 ((uint32_t)0x00010000) /*!< Blink enabled on SEG[0], COM[0] (1 pixel) */\r
+#define LCD_BlinkMode_SEG0_AllCOM ((uint32_t)0x00020000) /*!< Blink enabled on SEG[0], all COM (up to \r
+ 8 pixels according to the programmed duty) */\r
+#define LCD_BlinkMode_AllSEG_AllCOM ((uint32_t)0x00030000) /*!< Blink enabled on all SEG and all COM (all pixels) */\r
+\r
+#define IS_LCD_BLINK_MODE(MODE) (((MODE) == LCD_BlinkMode_Off) || \\r
+ ((MODE) == LCD_BlinkMode_SEG0_COM0) || \\r
+ ((MODE) == LCD_BlinkMode_SEG0_AllCOM) || \\r
+ ((MODE) == LCD_BlinkMode_AllSEG_AllCOM))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup LCD_BlinkFrequency \r
+ * @{\r
+ */\r
+\r
+#define LCD_BlinkFrequency_Div8 ((uint32_t)0x00000000) /*!< The Blink frequency = fLCD/8 */\r
+#define LCD_BlinkFrequency_Div16 ((uint32_t)0x00002000) /*!< The Blink frequency = fLCD/16 */\r
+#define LCD_BlinkFrequency_Div32 ((uint32_t)0x00004000) /*!< The Blink frequency = fLCD/32 */\r
+#define LCD_BlinkFrequency_Div64 ((uint32_t)0x00006000) /*!< The Blink frequency = fLCD/64 */\r
+#define LCD_BlinkFrequency_Div128 ((uint32_t)0x00008000) /*!< The Blink frequency = fLCD/128 */\r
+#define LCD_BlinkFrequency_Div256 ((uint32_t)0x0000A000) /*!< The Blink frequency = fLCD/256 */\r
+#define LCD_BlinkFrequency_Div512 ((uint32_t)0x0000C000) /*!< The Blink frequency = fLCD/512 */\r
+#define LCD_BlinkFrequency_Div1024 ((uint32_t)0x0000E000) /*!< The Blink frequency = fLCD/1024 */\r
+\r
+#define IS_LCD_BLINK_FREQUENCY(FREQUENCY) (((FREQUENCY) == LCD_BlinkFrequency_Div8) || \\r
+ ((FREQUENCY) == LCD_BlinkFrequency_Div16) || \\r
+ ((FREQUENCY) == LCD_BlinkFrequency_Div32) || \\r
+ ((FREQUENCY) == LCD_BlinkFrequency_Div64) || \\r
+ ((FREQUENCY) == LCD_BlinkFrequency_Div128) || \\r
+ ((FREQUENCY) == LCD_BlinkFrequency_Div256) || \\r
+ ((FREQUENCY) == LCD_BlinkFrequency_Div512) || \\r
+ ((FREQUENCY) == LCD_BlinkFrequency_Div1024))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LCD_Contrast \r
+ * @{\r
+ */\r
+\r
+#define LCD_Contrast_Level_0 ((uint32_t)0x00000000) /*!< Maximum Voltage = 2.60V */\r
+#define LCD_Contrast_Level_1 ((uint32_t)0x00000400) /*!< Maximum Voltage = 2.73V */\r
+#define LCD_Contrast_Level_2 ((uint32_t)0x00000800) /*!< Maximum Voltage = 2.86V */\r
+#define LCD_Contrast_Level_3 ((uint32_t)0x00000C00) /*!< Maximum Voltage = 2.99V */\r
+#define LCD_Contrast_Level_4 ((uint32_t)0x00001000) /*!< Maximum Voltage = 3.12V */\r
+#define LCD_Contrast_Level_5 ((uint32_t)0x00001400) /*!< Maximum Voltage = 3.25V */\r
+#define LCD_Contrast_Level_6 ((uint32_t)0x00001800) /*!< Maximum Voltage = 3.38V */\r
+#define LCD_Contrast_Level_7 ((uint32_t)0x00001C00) /*!< Maximum Voltage = 3.51V */\r
+\r
+#define IS_LCD_CONTRAST(CONTRAST) (((CONTRAST) == LCD_Contrast_Level_0) || \\r
+ ((CONTRAST) == LCD_Contrast_Level_1) || \\r
+ ((CONTRAST) == LCD_Contrast_Level_2) || \\r
+ ((CONTRAST) == LCD_Contrast_Level_3) || \\r
+ ((CONTRAST) == LCD_Contrast_Level_4) || \\r
+ ((CONTRAST) == LCD_Contrast_Level_5) || \\r
+ ((CONTRAST) == LCD_Contrast_Level_6) || \\r
+ ((CONTRAST) == LCD_Contrast_Level_7))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup LCD_Flag \r
+ * @{\r
+ */\r
+\r
+#define LCD_FLAG_ENS LCD_SR_ENS\r
+#define LCD_FLAG_SOF LCD_SR_SOF\r
+#define LCD_FLAG_UDR LCD_SR_UDR\r
+#define LCD_FLAG_UDD LCD_SR_UDD\r
+#define LCD_FLAG_RDY LCD_SR_RDY\r
+#define LCD_FLAG_FCRSF LCD_SR_FCRSR\r
+\r
+#define IS_LCD_GET_FLAG(FLAG) (((FLAG) == LCD_FLAG_ENS) || ((FLAG) == LCD_FLAG_SOF) || \\r
+ ((FLAG) == LCD_FLAG_UDR) || ((FLAG) == LCD_FLAG_UDD) || \\r
+ ((FLAG) == LCD_FLAG_RDY) || ((FLAG) == LCD_FLAG_FCRSF))\r
+\r
+#define IS_LCD_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF5) == 0x00) && ((FLAG) != 0x00))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup LCD_RAMRegister \r
+ * @{\r
+ */\r
+\r
+#define LCD_RAMRegister_0 ((uint32_t)0x00000000) /*!< LCD RAM Register 0 */\r
+#define LCD_RAMRegister_1 ((uint32_t)0x00000001) /*!< LCD RAM Register 1 */\r
+#define LCD_RAMRegister_2 ((uint32_t)0x00000002) /*!< LCD RAM Register 2 */\r
+#define LCD_RAMRegister_3 ((uint32_t)0x00000003) /*!< LCD RAM Register 3 */\r
+#define LCD_RAMRegister_4 ((uint32_t)0x00000004) /*!< LCD RAM Register 4 */\r
+#define LCD_RAMRegister_5 ((uint32_t)0x00000005) /*!< LCD RAM Register 5 */\r
+#define LCD_RAMRegister_6 ((uint32_t)0x00000006) /*!< LCD RAM Register 6 */\r
+#define LCD_RAMRegister_7 ((uint32_t)0x00000007) /*!< LCD RAM Register 7 */\r
+#define LCD_RAMRegister_8 ((uint32_t)0x00000008) /*!< LCD RAM Register 8 */\r
+#define LCD_RAMRegister_9 ((uint32_t)0x00000009) /*!< LCD RAM Register 9 */\r
+#define LCD_RAMRegister_10 ((uint32_t)0x0000000A) /*!< LCD RAM Register 10 */\r
+#define LCD_RAMRegister_11 ((uint32_t)0x0000000B) /*!< LCD RAM Register 11 */\r
+#define LCD_RAMRegister_12 ((uint32_t)0x0000000C) /*!< LCD RAM Register 12 */\r
+#define LCD_RAMRegister_13 ((uint32_t)0x0000000D) /*!< LCD RAM Register 13 */\r
+#define LCD_RAMRegister_14 ((uint32_t)0x0000000E) /*!< LCD RAM Register 14 */\r
+#define LCD_RAMRegister_15 ((uint32_t)0x0000000F) /*!< LCD RAM Register 15 */\r
+\r
+#define IS_LCD_RAM_REGISTER(REGISTER) (((REGISTER) == LCD_RAMRegister_0) || \\r
+ ((REGISTER) == LCD_RAMRegister_1) || \\r
+ ((REGISTER) == LCD_RAMRegister_2) || \\r
+ ((REGISTER) == LCD_RAMRegister_3) || \\r
+ ((REGISTER) == LCD_RAMRegister_4) || \\r
+ ((REGISTER) == LCD_RAMRegister_5) || \\r
+ ((REGISTER) == LCD_RAMRegister_6) || \\r
+ ((REGISTER) == LCD_RAMRegister_7) || \\r
+ ((REGISTER) == LCD_RAMRegister_8) || \\r
+ ((REGISTER) == LCD_RAMRegister_9) || \\r
+ ((REGISTER) == LCD_RAMRegister_10) || \\r
+ ((REGISTER) == LCD_RAMRegister_11) || \\r
+ ((REGISTER) == LCD_RAMRegister_12) || \\r
+ ((REGISTER) == LCD_RAMRegister_13) || \\r
+ ((REGISTER) == LCD_RAMRegister_14) || \\r
+ ((REGISTER) == LCD_RAMRegister_15))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Function used to set the LCD configuration to the default reset state *****/\r
+void LCD_DeInit(void);\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+void LCD_Init(LCD_InitTypeDef* LCD_InitStruct);\r
+void LCD_StructInit(LCD_InitTypeDef* LCD_InitStruct);\r
+void LCD_Cmd(FunctionalState NewState);\r
+void LCD_WaitForSynchro(void);\r
+void LCD_HighDriveCmd(FunctionalState NewState);\r
+void LCD_MuxSegmentCmd(FunctionalState NewState);\r
+void LCD_PulseOnDurationConfig(uint32_t LCD_PulseOnDuration);\r
+void LCD_DeadTimeConfig(uint32_t LCD_DeadTime);\r
+void LCD_BlinkConfig(uint32_t LCD_BlinkMode, uint32_t LCD_BlinkFrequency);\r
+void LCD_ContrastConfig(uint32_t LCD_Contrast);\r
+\r
+/* LCD RAM memory write functions *********************************************/\r
+void LCD_Write(uint32_t LCD_RAMRegister, uint32_t LCD_Data);\r
+void LCD_UpdateDisplayRequest(void);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void LCD_ITConfig(uint32_t LCD_IT, FunctionalState NewState);\r
+FlagStatus LCD_GetFlagStatus(uint32_t LCD_FLAG);\r
+void LCD_ClearFlag(uint32_t LCD_FLAG);\r
+ITStatus LCD_GetITStatus(uint32_t LCD_IT);\r
+void LCD_ClearITPendingBit(uint32_t LCD_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_LCD_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_pwr.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the PWR firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_PWR_H\r
+#define __STM32L1xx_PWR_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup PWR\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup PWR_Exported_Constants\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup PVD_detection_level \r
+ * @{\r
+ */ \r
+\r
+#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0\r
+#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1\r
+#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2\r
+#define PWR_PVDLevel_3 PWR_CR_PLS_LEV3\r
+#define PWR_PVDLevel_4 PWR_CR_PLS_LEV4\r
+#define PWR_PVDLevel_5 PWR_CR_PLS_LEV5\r
+#define PWR_PVDLevel_6 PWR_CR_PLS_LEV6\r
+#define PWR_PVDLevel_7 PWR_CR_PLS_LEV7 /* External input analog voltage \r
+ (Compare internally to VREFINT) */\r
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \\r
+ ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \\r
+ ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \\r
+ ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup WakeUp_Pins \r
+ * @{\r
+ */\r
+\r
+#define PWR_WakeUpPin_1 ((uint32_t)0x00000000)\r
+#define PWR_WakeUpPin_2 ((uint32_t)0x00000004)\r
+#define PWR_WakeUpPin_3 ((uint32_t)0x00000008)\r
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUpPin_1) || \\r
+ ((PIN) == PWR_WakeUpPin_2) || \\r
+ ((PIN) == PWR_WakeUpPin_3))\r
+/**\r
+ * @}\r
+ */\r
+\r
+ \r
+/** @defgroup Voltage_Scaling_Ranges\r
+ * @{\r
+ */\r
+\r
+#define PWR_VoltageScaling_Range1 PWR_CR_VOS_0\r
+#define PWR_VoltageScaling_Range2 PWR_CR_VOS_1\r
+#define PWR_VoltageScaling_Range3 PWR_CR_VOS\r
+\r
+#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_VoltageScaling_Range1) || \\r
+ ((RANGE) == PWR_VoltageScaling_Range2) || \\r
+ ((RANGE) == PWR_VoltageScaling_Range3))\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup Regulator_state_is_Sleep_STOP_mode \r
+ * @{\r
+ */\r
+\r
+#define PWR_Regulator_ON ((uint32_t)0x00000000)\r
+#define PWR_Regulator_LowPower PWR_CR_LPSDSR\r
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \\r
+ ((REGULATOR) == PWR_Regulator_LowPower))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SLEEP_mode_entry \r
+ * @{\r
+ */\r
+\r
+#define PWR_SLEEPEntry_WFI ((uint8_t)0x01)\r
+#define PWR_SLEEPEntry_WFE ((uint8_t)0x02)\r
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE))\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup STOP_mode_entry \r
+ * @{\r
+ */\r
+\r
+#define PWR_STOPEntry_WFI ((uint8_t)0x01)\r
+#define PWR_STOPEntry_WFE ((uint8_t)0x02)\r
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Flag \r
+ * @{\r
+ */\r
+\r
+#define PWR_FLAG_WU PWR_CSR_WUF\r
+#define PWR_FLAG_SB PWR_CSR_SBF\r
+#define PWR_FLAG_PVDO PWR_CSR_PVDO\r
+#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF\r
+#define PWR_FLAG_VOS PWR_CSR_VOSF\r
+#define PWR_FLAG_REGLP PWR_CSR_REGLPF\r
+\r
+#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \\r
+ ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY) || \\r
+ ((FLAG) == PWR_FLAG_VOS) || ((FLAG) == PWR_FLAG_REGLP))\r
+\r
+#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Function used to set the PWR configuration to the default reset state ******/ \r
+void PWR_DeInit(void);\r
+\r
+/* RTC Domain Access function *************************************************/ \r
+void PWR_RTCAccessCmd(FunctionalState NewState);\r
+\r
+/* PVD configuration functions ************************************************/ \r
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);\r
+void PWR_PVDCmd(FunctionalState NewState);\r
+\r
+/* WakeUp pins configuration functions ****************************************/ \r
+void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState);\r
+\r
+/* Ultra Low Power mode configuration functions *******************************/ \r
+void PWR_FastWakeUpCmd(FunctionalState NewState);\r
+void PWR_UltraLowPowerCmd(FunctionalState NewState);\r
+\r
+/* Voltage Scaling configuration functions ************************************/ \r
+void PWR_VoltageScalingConfig(uint32_t PWR_VoltageScaling);\r
+\r
+/* Low Power modes configuration functions ************************************/ \r
+void PWR_EnterLowPowerRunMode(FunctionalState NewState);\r
+void PWR_EnterSleepMode(uint32_t PWR_Regulator, uint8_t PWR_SLEEPEntry);\r
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);\r
+void PWR_EnterSTANDBYMode(void);\r
+\r
+/* Flags management functions *************************************************/ \r
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);\r
+void PWR_ClearFlag(uint32_t PWR_FLAG);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_PWR_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_rcc.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the RCC \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_RCC_H\r
+#define __STM32L1xx_RCC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RCC\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+typedef struct\r
+{\r
+ uint32_t SYSCLK_Frequency;\r
+ uint32_t HCLK_Frequency;\r
+ uint32_t PCLK1_Frequency;\r
+ uint32_t PCLK2_Frequency;\r
+}RCC_ClocksTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup RCC_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup HSE_configuration \r
+ * @{\r
+ */\r
+\r
+#define RCC_HSE_OFF ((uint8_t)0x00)\r
+#define RCC_HSE_ON ((uint8_t)0x01)\r
+#define RCC_HSE_Bypass ((uint8_t)0x05)\r
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \\r
+ ((HSE) == RCC_HSE_Bypass))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup MSI_Clock_Range \r
+ * @{\r
+ */\r
+\r
+#define RCC_MSIRange_0 RCC_ICSCR_MSIRANGE_0 /*!< MSI = 65.536 KHz */\r
+#define RCC_MSIRange_1 RCC_ICSCR_MSIRANGE_1 /*!< MSI = 131.072 KHz */\r
+#define RCC_MSIRange_2 RCC_ICSCR_MSIRANGE_2 /*!< MSI = 262.144 KHz */\r
+#define RCC_MSIRange_3 RCC_ICSCR_MSIRANGE_3 /*!< MSI = 524.288 KHz */\r
+#define RCC_MSIRange_4 RCC_ICSCR_MSIRANGE_4 /*!< MSI = 1.048 MHz */\r
+#define RCC_MSIRange_5 RCC_ICSCR_MSIRANGE_5 /*!< MSI = 2.097 MHz */\r
+#define RCC_MSIRange_6 RCC_ICSCR_MSIRANGE_6 /*!< MSI = 4.194 MHz */\r
+\r
+#define IS_RCC_MSI_CLOCK_RANGE(RANGE) (((RANGE) == RCC_MSIRange_0) || \\r
+ ((RANGE) == RCC_MSIRange_1) || \\r
+ ((RANGE) == RCC_MSIRange_2) || \\r
+ ((RANGE) == RCC_MSIRange_3) || \\r
+ ((RANGE) == RCC_MSIRange_4) || \\r
+ ((RANGE) == RCC_MSIRange_5) || \\r
+ ((RANGE) == RCC_MSIRange_6))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup PLL_Clock_Source \r
+ * @{\r
+ */\r
+\r
+#define RCC_PLLSource_HSI ((uint8_t)0x00)\r
+#define RCC_PLLSource_HSE ((uint8_t)0x01)\r
+\r
+#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \\r
+ ((SOURCE) == RCC_PLLSource_HSE))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup PLL_Multiplication_Factor \r
+ * @{\r
+ */\r
+\r
+#define RCC_PLLMul_3 ((uint8_t)0x00)\r
+#define RCC_PLLMul_4 ((uint8_t)0x04)\r
+#define RCC_PLLMul_6 ((uint8_t)0x08)\r
+#define RCC_PLLMul_8 ((uint8_t)0x0C)\r
+#define RCC_PLLMul_12 ((uint8_t)0x10)\r
+#define RCC_PLLMul_16 ((uint8_t)0x14)\r
+#define RCC_PLLMul_24 ((uint8_t)0x18)\r
+#define RCC_PLLMul_32 ((uint8_t)0x1C)\r
+#define RCC_PLLMul_48 ((uint8_t)0x20)\r
+\r
+\r
+#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_3) || ((MUL) == RCC_PLLMul_4) || \\r
+ ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_8) || \\r
+ ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_16) || \\r
+ ((MUL) == RCC_PLLMul_24) || ((MUL) == RCC_PLLMul_32) || \\r
+ ((MUL) == RCC_PLLMul_48))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PLL_Divider_Factor \r
+ * @{\r
+ */\r
+\r
+#define RCC_PLLDiv_2 ((uint8_t)0x40)\r
+#define RCC_PLLDiv_3 ((uint8_t)0x80)\r
+#define RCC_PLLDiv_4 ((uint8_t)0xC0)\r
+\r
+\r
+#define IS_RCC_PLL_DIV(DIV) (((DIV) == RCC_PLLDiv_2) || ((DIV) == RCC_PLLDiv_3) || \\r
+ ((DIV) == RCC_PLLDiv_4))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup System_Clock_Source \r
+ * @{\r
+ */\r
+\r
+#define RCC_SYSCLKSource_MSI RCC_CFGR_SW_MSI\r
+#define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI\r
+#define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE\r
+#define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL\r
+#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_MSI) || \\r
+ ((SOURCE) == RCC_SYSCLKSource_HSI) || \\r
+ ((SOURCE) == RCC_SYSCLKSource_HSE) || \\r
+ ((SOURCE) == RCC_SYSCLKSource_PLLCLK))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup AHB_Clock_Source\r
+ * @{\r
+ */\r
+\r
+#define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1\r
+#define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2\r
+#define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4\r
+#define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8\r
+#define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16\r
+#define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64\r
+#define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128\r
+#define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256\r
+#define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512\r
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \\r
+ ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \\r
+ ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \\r
+ ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \\r
+ ((HCLK) == RCC_SYSCLK_Div512))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup APB1_APB2_Clock_Source\r
+ * @{\r
+ */\r
+\r
+#define RCC_HCLK_Div1 RCC_CFGR_PPRE1_DIV1\r
+#define RCC_HCLK_Div2 RCC_CFGR_PPRE1_DIV2\r
+#define RCC_HCLK_Div4 RCC_CFGR_PPRE1_DIV4\r
+#define RCC_HCLK_Div8 RCC_CFGR_PPRE1_DIV8\r
+#define RCC_HCLK_Div16 RCC_CFGR_PPRE1_DIV16\r
+#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \\r
+ ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \\r
+ ((PCLK) == RCC_HCLK_Div16))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+\r
+/** @defgroup RCC_Interrupt_Source \r
+ * @{\r
+ */\r
+\r
+#define RCC_IT_LSIRDY ((uint8_t)0x01)\r
+#define RCC_IT_LSERDY ((uint8_t)0x02)\r
+#define RCC_IT_HSIRDY ((uint8_t)0x04)\r
+#define RCC_IT_HSERDY ((uint8_t)0x08)\r
+#define RCC_IT_PLLRDY ((uint8_t)0x10)\r
+#define RCC_IT_MSIRDY ((uint8_t)0x20)\r
+#define RCC_IT_CSS ((uint8_t)0x80)\r
+\r
+#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))\r
+\r
+#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \\r
+ ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \\r
+ ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_MSIRDY) || \\r
+ ((IT) == RCC_IT_CSS))\r
+\r
+#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup LSE_Configuration \r
+ * @{\r
+ */\r
+\r
+#define RCC_LSE_OFF ((uint8_t)0x00)\r
+#define RCC_LSE_ON ((uint8_t)0x01)\r
+#define RCC_LSE_Bypass ((uint8_t)0x05)\r
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \\r
+ ((LSE) == RCC_LSE_Bypass))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Clock_Source\r
+ * @{\r
+ */\r
+\r
+#define RCC_RTCCLKSource_LSE RCC_CSR_RTCSEL_LSE\r
+#define RCC_RTCCLKSource_LSI RCC_CSR_RTCSEL_LSI\r
+#define RCC_RTCCLKSource_HSE_Div2 RCC_CSR_RTCSEL_HSE\r
+#define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_0)\r
+#define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_1)\r
+#define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE)\r
+#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_LSI) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div16))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup AHB_Peripherals \r
+ * @{\r
+ */\r
+\r
+#define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN\r
+#define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN\r
+#define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN\r
+#define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN\r
+#define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN\r
+#define RCC_AHBPeriph_GPIOH RCC_AHBENR_GPIOHEN\r
+#define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN\r
+#define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN\r
+#define RCC_AHBPeriph_SRAM RCC_AHBLPENR_SRAMLPEN\r
+#define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN\r
+\r
+#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFEFF6FC0) == 0x00) && ((PERIPH) != 0x00))\r
+#define IS_RCC_AHB_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0xFEFE6FC0) == 0x00) && ((PERIPH) != 0x00))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup APB2_Peripherals \r
+ * @{\r
+ */\r
+\r
+#define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN\r
+#define RCC_APB2Periph_TIM9 RCC_APB2ENR_TIM9EN\r
+#define RCC_APB2Periph_TIM10 RCC_APB2ENR_TIM10EN\r
+#define RCC_APB2Periph_TIM11 RCC_APB2ENR_TIM11EN\r
+#define RCC_APB2Periph_ADC1 RCC_APB2ENR_ADC1EN\r
+#define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN\r
+#define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN\r
+\r
+#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFADE2) == 0x00) && ((PERIPH) != 0x00))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup APB1_Peripherals \r
+ * @{\r
+ */\r
+\r
+#define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN\r
+#define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN\r
+#define RCC_APB1Periph_TIM4 RCC_APB1ENR_TIM4EN\r
+#define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN\r
+#define RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN\r
+#define RCC_APB1Periph_LCD RCC_APB1ENR_LCDEN\r
+#define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN\r
+#define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN\r
+#define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN\r
+#define RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN\r
+#define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN\r
+#define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN\r
+#define RCC_APB1Periph_USB RCC_APB1ENR_USBEN\r
+#define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN\r
+#define RCC_APB1Periph_DAC RCC_APB1ENR_DACEN\r
+#define RCC_APB1Periph_COMP RCC_APB1ENR_COMPEN\r
+\r
+#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x4F19B5C8) == 0x00) && ((PERIPH) != 0x00))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup MCO_Clock_Source\r
+ * @{\r
+ */\r
+\r
+#define RCC_MCOSource_NoClock ((uint8_t)0x00)\r
+#define RCC_MCOSource_SYSCLK ((uint8_t)0x01)\r
+#define RCC_MCOSource_HSI ((uint8_t)0x02)\r
+#define RCC_MCOSource_MSI ((uint8_t)0x03)\r
+#define RCC_MCOSource_HSE ((uint8_t)0x04)\r
+#define RCC_MCOSource_PLLCLK ((uint8_t)0x05)\r
+#define RCC_MCOSource_LSI ((uint8_t)0x06)\r
+#define RCC_MCOSource_LSE ((uint8_t)0x07)\r
+\r
+#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSource_SYSCLK) || \\r
+ ((SOURCE) == RCC_MCOSource_HSI) || ((SOURCE) == RCC_MCOSource_MSI) || \\r
+ ((SOURCE) == RCC_MCOSource_HSE) || ((SOURCE) == RCC_MCOSource_PLLCLK) || \\r
+ ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_LSE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup MCO_Output_Divider \r
+ * @{\r
+ */\r
+\r
+#define RCC_MCODiv_1 ((uint8_t)0x00)\r
+#define RCC_MCODiv_2 ((uint8_t)0x10)\r
+#define RCC_MCODiv_4 ((uint8_t)0x20)\r
+#define RCC_MCODiv_8 ((uint8_t)0x30)\r
+#define RCC_MCODiv_16 ((uint8_t)0x40)\r
+\r
+#define IS_RCC_MCO_DIV(DIV) (((DIV) == RCC_MCODiv_1) || ((DIV) == RCC_MCODiv_2) || \\r
+ ((DIV) == RCC_MCODiv_4) || ((DIV) == RCC_MCODiv_8) || \\r
+ ((DIV) == RCC_MCODiv_16))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RCC_Flag \r
+ * @{\r
+ */\r
+\r
+#define RCC_FLAG_HSIRDY ((uint8_t)0x21)\r
+#define RCC_FLAG_MSIRDY ((uint8_t)0x29)\r
+#define RCC_FLAG_HSERDY ((uint8_t)0x31)\r
+#define RCC_FLAG_PLLRDY ((uint8_t)0x39)\r
+#define RCC_FLAG_LSERDY ((uint8_t)0x49)\r
+#define RCC_FLAG_LSIRDY ((uint8_t)0x41)\r
+#define RCC_FLAG_OBLRST ((uint8_t)0x59)\r
+#define RCC_FLAG_PINRST ((uint8_t)0x5A)\r
+#define RCC_FLAG_PORRST ((uint8_t)0x5B)\r
+#define RCC_FLAG_SFTRST ((uint8_t)0x5C)\r
+#define RCC_FLAG_IWDGRST ((uint8_t)0x5D)\r
+#define RCC_FLAG_WWDGRST ((uint8_t)0x5E)\r
+#define RCC_FLAG_LPWRRST ((uint8_t)0x5F)\r
+\r
+#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \\r
+ ((FLAG) == RCC_FLAG_MSIRDY) || ((FLAG) == RCC_FLAG_PLLRDY) || \\r
+ ((FLAG) == RCC_FLAG_LSERDY) || ((FLAG) == RCC_FLAG_LSIRDY) || \\r
+ ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \\r
+ ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \\r
+ ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \\r
+ ((FLAG) == RCC_FLAG_WWDGRST))\r
+\r
+#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)\r
+#define IS_RCC_MSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3F)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Function used to set the RCC clock configuration to the default reset state */\r
+void RCC_DeInit(void);\r
+\r
+/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/\r
+void RCC_HSEConfig(uint8_t RCC_HSE);\r
+ErrorStatus RCC_WaitForHSEStartUp(void);\r
+void RCC_MSIRangeConfig(uint32_t RCC_MSIRange);\r
+void RCC_AdjustMSICalibrationValue(uint8_t MSICalibrationValue);\r
+void RCC_MSICmd(FunctionalState NewState);\r
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);\r
+void RCC_HSICmd(FunctionalState NewState);\r
+void RCC_LSEConfig(uint8_t RCC_LSE);\r
+void RCC_LSICmd(FunctionalState NewState);\r
+void RCC_PLLConfig(uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv);\r
+void RCC_PLLCmd(FunctionalState NewState);\r
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState);\r
+void RCC_MCOConfig(uint8_t RCC_MCOSource, uint8_t RCC_MCODiv);\r
+\r
+/* System, AHB and APB busses clocks configuration functions ******************/\r
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);\r
+uint8_t RCC_GetSYSCLKSource(void);\r
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK);\r
+void RCC_PCLK1Config(uint32_t RCC_HCLK);\r
+void RCC_PCLK2Config(uint32_t RCC_HCLK);\r
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);\r
+\r
+/* Peripheral clocks configuration functions **********************************/\r
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);\r
+void RCC_RTCCLKCmd(FunctionalState NewState);\r
+void RCC_RTCResetCmd(FunctionalState NewState);\r
+\r
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);\r
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);\r
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);\r
+\r
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);\r
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);\r
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);\r
+\r
+void RCC_AHBPeriphClockLPModeCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);\r
+void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);\r
+void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);\r
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);\r
+void RCC_ClearFlag(void);\r
+ITStatus RCC_GetITStatus(uint8_t RCC_IT);\r
+void RCC_ClearITPendingBit(uint8_t RCC_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_RCC_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_rtc.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the RTC firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_RTC_H\r
+#define __STM32L1xx_RTC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RTC\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief RTC Init structures definition \r
+ */ \r
+typedef struct\r
+{\r
+ uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format.\r
+ This parameter can be a value of @ref RTC_Hour_Formats */\r
+ \r
+ uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.\r
+ This parameter must be set to a value lower than 0x7F */\r
+ \r
+ uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.\r
+ This parameter must be set to a value lower than 0x1FFF */ \r
+}RTC_InitTypeDef;\r
+\r
+/** \r
+ * @brief RTC Time structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour.\r
+ This parameter must be set to a value in the 0-12 range\r
+ if the RTC_HourFormat_12 is selected or 0-23 range if\r
+ the RTC_HourFormat_24 is selected. */\r
+\r
+ uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes.\r
+ This parameter must be set to a value in the 0-59 range. */\r
+ \r
+ uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds.\r
+ This parameter must be set to a value in the 0-59 range. */\r
+\r
+ uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time.\r
+ This parameter can be a value of @ref RTC_AM_PM_Definitions */\r
+}RTC_TimeTypeDef; \r
+\r
+/** \r
+ * @brief RTC Date structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay.\r
+ This parameter can be a value of @ref RTC_WeekDay_Definitions */\r
+ \r
+ uint32_t RTC_Month; /*!< Specifies the RTC Date Month.\r
+ This parameter can be a value of @ref RTC_Month_Date_Definitions */\r
+\r
+ uint8_t RTC_Date; /*!< Specifies the RTC Date.\r
+ This parameter must be set to a value in the 1-31 range. */\r
+ \r
+ uint8_t RTC_Year; /*!< Specifies the RTC Date Year.\r
+ This parameter must be set to a value in the 0-99 range. */\r
+}RTC_DateTypeDef;\r
+\r
+/** \r
+ * @brief RTC Alarm structure definition \r
+ */\r
+typedef struct\r
+{\r
+ RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */\r
+\r
+ uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks.\r
+ This parameter can be a value of @ref RTC_AlarmMask_Definitions */\r
+\r
+ uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.\r
+ This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */\r
+ \r
+ uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.\r
+ This parameter must be set to a value in the 1-31 range \r
+ if the Alarm Date is selected.\r
+ This parameter can be a value of @ref RTC_WeekDay_Definitions \r
+ if the Alarm WeekDay is selected. */\r
+}RTC_AlarmTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup RTC_Exported_Constants\r
+ * @{\r
+ */ \r
+\r
+\r
+/** @defgroup RTC_Hour_Formats \r
+ * @{\r
+ */ \r
+#define RTC_HourFormat_24 ((uint32_t)0x00000000)\r
+#define RTC_HourFormat_12 ((uint32_t)0x00000040)\r
+#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \\r
+ ((FORMAT) == RTC_HourFormat_24))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Asynchronous_Predivider \r
+ * @{\r
+ */ \r
+#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F)\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup RTC_Synchronous_Predivider \r
+ * @{\r
+ */ \r
+#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x1FFF)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Time_Definitions \r
+ * @{\r
+ */ \r
+#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12))\r
+#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23)\r
+#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59)\r
+#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_AM_PM_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_H12_AM ((uint8_t)0x00)\r
+#define RTC_H12_PM ((uint8_t)0x40)\r
+#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Year_Date_Definitions \r
+ * @{\r
+ */ \r
+#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Month_Date_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_Month_January ((uint32_t)0x00000001)\r
+#define RTC_Month_February ((uint32_t)0x00000002)\r
+#define RTC_Month_March ((uint32_t)0x00000003)\r
+#define RTC_Month_April ((uint32_t)0x00000004)\r
+#define RTC_Month_May ((uint32_t)0x00000005)\r
+#define RTC_Month_June ((uint32_t)0x00000006)\r
+#define RTC_Month_July ((uint32_t)0x00000007)\r
+#define RTC_Month_August ((uint32_t)0x00000008)\r
+#define RTC_Month_September ((uint32_t)0x00000009)\r
+#define RTC_Month_October ((uint32_t)0x00000010)\r
+#define RTC_Month_November ((uint32_t)0x00000011)\r
+#define RTC_Month_December ((uint32_t)0x00000012)\r
+#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12))\r
+#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_WeekDay_Definitions \r
+ * @{\r
+ */ \r
+ \r
+#define RTC_Weekday_Monday ((uint32_t)0x00000001)\r
+#define RTC_Weekday_Tuesday ((uint32_t)0x00000002)\r
+#define RTC_Weekday_Wednesday ((uint32_t)0x00000003)\r
+#define RTC_Weekday_Thursday ((uint32_t)0x00000004)\r
+#define RTC_Weekday_Friday ((uint32_t)0x00000005)\r
+#define RTC_Weekday_Saturday ((uint32_t)0x00000006)\r
+#define RTC_Weekday_Sunday ((uint32_t)0x00000007)\r
+#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Tuesday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Wednesday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Thursday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Friday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Saturday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Sunday))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup RTC_Alarm_Definitions \r
+ * @{\r
+ */ \r
+#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))\r
+#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Tuesday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Wednesday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Thursday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Friday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Saturday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Sunday))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup RTC_AlarmDateWeekDay_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000) \r
+#define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000) \r
+\r
+#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \\r
+ ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup RTC_AlarmMask_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_AlarmMask_None ((uint32_t)0x00000000)\r
+#define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000) \r
+#define RTC_AlarmMask_Hours ((uint32_t)0x00800000)\r
+#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000)\r
+#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080)\r
+#define RTC_AlarmMask_All ((uint32_t)0x80808080)\r
+#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Alarms_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_Alarm_A ((uint32_t)0x00000100)\r
+#define RTC_Alarm_B ((uint32_t)0x00000200)\r
+#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B))\r
+#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Wakeup_Timer_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000)\r
+#define RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001)\r
+#define RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002)\r
+#define RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003)\r
+#define RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004)\r
+#define RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006)\r
+#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \\r
+ ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \\r
+ ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \\r
+ ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \\r
+ ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \\r
+ ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits))\r
+#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Time_Stamp_Edges_definitions \r
+ * @{\r
+ */ \r
+#define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000)\r
+#define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008)\r
+#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \\r
+ ((EDGE) == RTC_TimeStampEdge_Falling))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Output_selection_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_Output_Disable ((uint32_t)0x00000000)\r
+#define RTC_Output_AlarmA ((uint32_t)0x00200000)\r
+#define RTC_Output_AlarmB ((uint32_t)0x00400000)\r
+#define RTC_Output_WakeUp ((uint32_t)0x00600000)\r
+ \r
+#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \\r
+ ((OUTPUT) == RTC_Output_AlarmA) || \\r
+ ((OUTPUT) == RTC_Output_AlarmB) || \\r
+ ((OUTPUT) == RTC_Output_WakeUp))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Output_Polarity_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_OutputPolarity_High ((uint32_t)0x00000000)\r
+#define RTC_OutputPolarity_Low ((uint32_t)0x00100000)\r
+#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \\r
+ ((POL) == RTC_OutputPolarity_Low))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup RTC_Digital_Calibration_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_CalibSign_Positive ((uint32_t)0x00000000) \r
+#define RTC_CalibSign_Negative ((uint32_t)0x00000080)\r
+#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \\r
+ ((SIGN) == RTC_CalibSign_Negative))\r
+#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup RTC_DayLightSaving_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000)\r
+#define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000)\r
+#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \\r
+ ((SAVE) == RTC_DayLightSaving_ADD1H))\r
+\r
+#define RTC_StoreOperation_Reset ((uint32_t)0x00000000)\r
+#define RTC_StoreOperation_Set ((uint32_t)0x00040000)\r
+#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \\r
+ ((OPERATION) == RTC_StoreOperation_Set))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Tamper_Trigger_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000)\r
+#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001)\r
+#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \\r
+ ((TRIGGER) == RTC_TamperTrigger_FallingEdge))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Tamper_Pins_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_Tamper_1 RTC_TAFCR_TAMP1E\r
+#define IS_RTC_TAMPER(TAMPER) (((TAMPER) == RTC_Tamper_1))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup RTC_Output_Type_ALARM_OUT \r
+ * @{\r
+ */ \r
+#define RTC_OutputType_OpenDrain ((uint32_t)0x00000000)\r
+#define RTC_OutputType_PushPull ((uint32_t)0x00040000)\r
+#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \\r
+ ((TYPE) == RTC_OutputType_PushPull)) \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Backup_Registers_Definitions \r
+ * @{\r
+ */ \r
+\r
+#define RTC_BKP_DR0 ((uint32_t)0x00000000)\r
+#define RTC_BKP_DR1 ((uint32_t)0x00000001)\r
+#define RTC_BKP_DR2 ((uint32_t)0x00000002)\r
+#define RTC_BKP_DR3 ((uint32_t)0x00000003)\r
+#define RTC_BKP_DR4 ((uint32_t)0x00000004)\r
+#define RTC_BKP_DR5 ((uint32_t)0x00000005)\r
+#define RTC_BKP_DR6 ((uint32_t)0x00000006)\r
+#define RTC_BKP_DR7 ((uint32_t)0x00000007)\r
+#define RTC_BKP_DR8 ((uint32_t)0x00000008)\r
+#define RTC_BKP_DR9 ((uint32_t)0x00000009)\r
+#define RTC_BKP_DR10 ((uint32_t)0x0000000A)\r
+#define RTC_BKP_DR11 ((uint32_t)0x0000000B)\r
+#define RTC_BKP_DR12 ((uint32_t)0x0000000C)\r
+#define RTC_BKP_DR13 ((uint32_t)0x0000000D)\r
+#define RTC_BKP_DR14 ((uint32_t)0x0000000E)\r
+#define RTC_BKP_DR15 ((uint32_t)0x0000000F)\r
+#define RTC_BKP_DR16 ((uint32_t)0x00000010)\r
+#define RTC_BKP_DR17 ((uint32_t)0x00000011)\r
+#define RTC_BKP_DR18 ((uint32_t)0x00000012)\r
+#define RTC_BKP_DR19 ((uint32_t)0x00000013)\r
+#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \\r
+ ((BKP) == RTC_BKP_DR1) || \\r
+ ((BKP) == RTC_BKP_DR2) || \\r
+ ((BKP) == RTC_BKP_DR3) || \\r
+ ((BKP) == RTC_BKP_DR4) || \\r
+ ((BKP) == RTC_BKP_DR5) || \\r
+ ((BKP) == RTC_BKP_DR6) || \\r
+ ((BKP) == RTC_BKP_DR7) || \\r
+ ((BKP) == RTC_BKP_DR8) || \\r
+ ((BKP) == RTC_BKP_DR9) || \\r
+ ((BKP) == RTC_BKP_DR10) || \\r
+ ((BKP) == RTC_BKP_DR11) || \\r
+ ((BKP) == RTC_BKP_DR12) || \\r
+ ((BKP) == RTC_BKP_DR13) || \\r
+ ((BKP) == RTC_BKP_DR14) || \\r
+ ((BKP) == RTC_BKP_DR15) || \\r
+ ((BKP) == RTC_BKP_DR16) || \\r
+ ((BKP) == RTC_BKP_DR17) || \\r
+ ((BKP) == RTC_BKP_DR18) || \\r
+ ((BKP) == RTC_BKP_DR19))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Input_parameter_format_definitions \r
+ * @{\r
+ */ \r
+#define RTC_Format_BIN ((uint32_t)0x000000000)\r
+#define RTC_Format_BCD ((uint32_t)0x000000001)\r
+#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Flags_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000)\r
+#define RTC_FLAG_TSOVF ((uint32_t)0x00001000)\r
+#define RTC_FLAG_TSF ((uint32_t)0x00000800)\r
+#define RTC_FLAG_WUTF ((uint32_t)0x00000400)\r
+#define RTC_FLAG_ALRBF ((uint32_t)0x00000200)\r
+#define RTC_FLAG_ALRAF ((uint32_t)0x00000100)\r
+#define RTC_FLAG_INITF ((uint32_t)0x00000040)\r
+#define RTC_FLAG_RSF ((uint32_t)0x00000020)\r
+#define RTC_FLAG_INITS ((uint32_t)0x00000010)\r
+#define RTC_FLAG_WUTWF ((uint32_t)0x00000004)\r
+#define RTC_FLAG_ALRBWF ((uint32_t)0x00000002)\r
+#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001)\r
+#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \\r
+ ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \\r
+ ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \\r
+ ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \\r
+ ((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \\r
+ ((FLAG) == RTC_FLAG_TAMP1F))\r
+#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFFC0DF) == (uint32_t)RESET))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Interrupts_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_IT_TS ((uint32_t)0x00008000)\r
+#define RTC_IT_WUT ((uint32_t)0x00004000)\r
+#define RTC_IT_ALRB ((uint32_t)0x00002000)\r
+#define RTC_IT_ALRA ((uint32_t)0x00001000)\r
+#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */\r
+#define RTC_IT_TAMP1 ((uint32_t)0x00020000)\r
+\r
+#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET))\r
+#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \\r
+ ((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \\r
+ ((IT) == RTC_IT_TAMP1))\r
+#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFD0FFF) == (uint32_t)RESET))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */ \r
+\r
+/* Function used to set the RTC configuration to the default reset state *****/ \r
+ErrorStatus RTC_DeInit(void);\r
+\r
+\r
+/* Initialization and Configuration functions *********************************/ \r
+ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct);\r
+void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct);\r
+void RTC_WriteProtectionCmd(FunctionalState NewState);\r
+ErrorStatus RTC_EnterInitMode(void);\r
+void RTC_ExitInitMode(void);\r
+ErrorStatus RTC_WaitForSynchro(void);\r
+ErrorStatus RTC_RefClockCmd(FunctionalState NewState);\r
+\r
+/* Time and Date configuration functions **************************************/ \r
+ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);\r
+void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct);\r
+void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);\r
+ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);\r
+void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct);\r
+void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);\r
+\r
+/* Alarms (Alarm A and Alarm B) configuration functions **********************/ \r
+void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);\r
+void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct);\r
+void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);\r
+ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState);\r
+\r
+/* WakeUp Timer configuration functions ***************************************/ \r
+void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock);\r
+void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter);\r
+uint32_t RTC_GetWakeUpCounter(void);\r
+ErrorStatus RTC_WakeUpCmd(FunctionalState NewState);\r
+\r
+/* Daylight Saving configuration functions ************************************/ \r
+void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation);\r
+uint32_t RTC_GetStoreOperation(void);\r
+\r
+/* Output pin Configuration function ******************************************/ \r
+void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity);\r
+\r
+/* Digital Calibration configuration functions ********************************/ \r
+ErrorStatus RTC_DigitalCalibConfig(uint32_t RTC_CalibSign, uint32_t Value);\r
+ErrorStatus RTC_DigitalCalibCmd(FunctionalState NewState);\r
+void RTC_CalibOutputCmd(FunctionalState NewState);\r
+\r
+/* TimeStamp configuration functions ******************************************/ \r
+void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState);\r
+void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, \r
+ RTC_DateTypeDef* RTC_StampDateStruct);\r
+ \r
+\r
+/* Tampers configuration functions ********************************************/ \r
+void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger);\r
+void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState);\r
+\r
+/* Backup Data Registers configuration functions ******************************/ \r
+void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data);\r
+uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR);\r
+\r
+/* Output Type Config configuration functions *********************************/ \r
+void RTC_OutputTypeConfig(uint32_t RTC_OutputType);\r
+\r
+\r
+/* Interrupts and flags management functions **********************************/ \r
+void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState);\r
+FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG);\r
+void RTC_ClearFlag(uint32_t RTC_FLAG);\r
+ITStatus RTC_GetITStatus(uint32_t RTC_IT);\r
+void RTC_ClearITPendingBit(uint32_t RTC_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32L1xx_RTC_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_spi.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the SPI \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_SPI_H\r
+#define __STM32L1xx_SPI_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup SPI\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief SPI Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.\r
+ This parameter can be any combination of @ref SPI_data_direction */\r
+\r
+ uint16_t SPI_Mode; /*!< Specifies the SPI operating mode.\r
+ This parameter can be any combination of @ref SPI_mode */\r
+\r
+ uint16_t SPI_DataSize; /*!< Specifies the SPI data size.\r
+ This parameter can be any combination of @ref SPI_data_size */\r
+\r
+ uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.\r
+ This parameter can be any combination of @ref SPI_Clock_Polarity */\r
+\r
+ uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.\r
+ This parameter can be any combination of @ref SPI_Clock_Phase */\r
+\r
+ uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by\r
+ hardware (NSS pin) or by software using the SSI bit.\r
+ This parameter can be any combination of @ref SPI_Slave_Select_management */\r
+ \r
+ uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be\r
+ used to configure the transmit and receive SCK clock.\r
+ This parameter can be any combination of @ref SPI_BaudRate_Prescaler.\r
+ @note The communication clock is derived from the master\r
+ clock. The slave clock does not need to be set. */\r
+\r
+ uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.\r
+ This parameter can be any combination of @ref SPI_MSB_LSB_transmission */\r
+\r
+ uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */\r
+}SPI_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup SPI_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \\r
+ ((PERIPH) == SPI2))\r
+\r
+/** @defgroup SPI_data_direction \r
+ * @{\r
+ */\r
+ \r
+#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)\r
+#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)\r
+#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)\r
+#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)\r
+#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \\r
+ ((MODE) == SPI_Direction_2Lines_RxOnly) || \\r
+ ((MODE) == SPI_Direction_1Line_Rx) || \\r
+ ((MODE) == SPI_Direction_1Line_Tx))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_mode \r
+ * @{\r
+ */\r
+\r
+#define SPI_Mode_Master ((uint16_t)0x0104)\r
+#define SPI_Mode_Slave ((uint16_t)0x0000)\r
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \\r
+ ((MODE) == SPI_Mode_Slave))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_data_size \r
+ * @{\r
+ */\r
+\r
+#define SPI_DataSize_16b ((uint16_t)0x0800)\r
+#define SPI_DataSize_8b ((uint16_t)0x0000)\r
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \\r
+ ((DATASIZE) == SPI_DataSize_8b))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SPI_Clock_Polarity \r
+ * @{\r
+ */\r
+\r
+#define SPI_CPOL_Low ((uint16_t)0x0000)\r
+#define SPI_CPOL_High ((uint16_t)0x0002)\r
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \\r
+ ((CPOL) == SPI_CPOL_High))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Clock_Phase \r
+ * @{\r
+ */\r
+\r
+#define SPI_CPHA_1Edge ((uint16_t)0x0000)\r
+#define SPI_CPHA_2Edge ((uint16_t)0x0001)\r
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \\r
+ ((CPHA) == SPI_CPHA_2Edge))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Slave_Select_management \r
+ * @{\r
+ */\r
+\r
+#define SPI_NSS_Soft ((uint16_t)0x0200)\r
+#define SPI_NSS_Hard ((uint16_t)0x0000)\r
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \\r
+ ((NSS) == SPI_NSS_Hard))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SPI_BaudRate_Prescaler \r
+ * @{\r
+ */\r
+\r
+#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)\r
+#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)\r
+#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)\r
+#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)\r
+#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)\r
+#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)\r
+#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)\r
+#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)\r
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_4) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_8) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_16) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_32) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_64) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_128) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_256))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SPI_MSB_LSB_transmission \r
+ * @{\r
+ */\r
+\r
+#define SPI_FirstBit_MSB ((uint16_t)0x0000)\r
+#define SPI_FirstBit_LSB ((uint16_t)0x0080)\r
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \\r
+ ((BIT) == SPI_FirstBit_LSB))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_I2S_DMA_transfer_requests \r
+ * @{\r
+ */\r
+\r
+#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)\r
+#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)\r
+#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_NSS_internal_software_management \r
+ * @{\r
+ */\r
+\r
+#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)\r
+#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)\r
+#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \\r
+ ((INTERNAL) == SPI_NSSInternalSoft_Reset))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_CRC_Transmit_Receive \r
+ * @{\r
+ */\r
+\r
+#define SPI_CRC_Tx ((uint8_t)0x00)\r
+#define SPI_CRC_Rx ((uint8_t)0x01)\r
+#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_direction_transmit_receive \r
+ * @{\r
+ */\r
+\r
+#define SPI_Direction_Rx ((uint16_t)0xBFFF)\r
+#define SPI_Direction_Tx ((uint16_t)0x4000)\r
+#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \\r
+ ((DIRECTION) == SPI_Direction_Tx))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_I2S_interrupts_definition \r
+ * @{\r
+ */\r
+\r
+#define SPI_I2S_IT_TXE ((uint8_t)0x71)\r
+#define SPI_I2S_IT_RXNE ((uint8_t)0x60)\r
+#define SPI_I2S_IT_ERR ((uint8_t)0x50)\r
+#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \\r
+ ((IT) == SPI_I2S_IT_RXNE) || \\r
+ ((IT) == SPI_I2S_IT_ERR))\r
+\r
+#define SPI_I2S_IT_OVR ((uint8_t)0x56)\r
+#define SPI_IT_MODF ((uint8_t)0x55)\r
+#define SPI_IT_CRCERR ((uint8_t)0x54)\r
+\r
+#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))\r
+\r
+#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \\r
+ ((IT) == SPI_IT_CRCERR) || ((IT) == SPI_IT_MODF) || \\r
+ ((IT) == SPI_I2S_IT_OVR))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_I2S_flags_definition \r
+ * @{\r
+ */\r
+\r
+#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)\r
+#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)\r
+#define SPI_FLAG_CRCERR ((uint16_t)0x0010)\r
+#define SPI_FLAG_MODF ((uint16_t)0x0020)\r
+#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)\r
+#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)\r
+#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))\r
+#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \\r
+ ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \\r
+ ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_CRC_polynomial \r
+ * @{\r
+ */\r
+\r
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_I2S_Legacy \r
+ * @{\r
+ */\r
+\r
+#define SPI_DMAReq_Tx SPI_I2S_DMAReq_Tx\r
+#define SPI_DMAReq_Rx SPI_I2S_DMAReq_Rx\r
+#define SPI_IT_TXE SPI_I2S_IT_TXE\r
+#define SPI_IT_RXNE SPI_I2S_IT_RXNE\r
+#define SPI_IT_ERR SPI_I2S_IT_ERR\r
+#define SPI_IT_OVR SPI_I2S_IT_OVR\r
+#define SPI_FLAG_RXNE SPI_I2S_FLAG_RXNE\r
+#define SPI_FLAG_TXE SPI_I2S_FLAG_TXE\r
+#define SPI_FLAG_OVR SPI_I2S_FLAG_OVR\r
+#define SPI_FLAG_BSY SPI_I2S_FLAG_BSY\r
+#define SPI_DeInit SPI_I2S_DeInit\r
+#define SPI_ITConfig SPI_I2S_ITConfig\r
+#define SPI_DMACmd SPI_I2S_DMACmd\r
+#define SPI_SendData SPI_I2S_SendData\r
+#define SPI_ReceiveData SPI_I2S_ReceiveData\r
+#define SPI_GetFlagStatus SPI_I2S_GetFlagStatus\r
+#define SPI_ClearFlag SPI_I2S_ClearFlag\r
+#define SPI_GetITStatus SPI_I2S_GetITStatus\r
+#define SPI_ClearITPendingBit SPI_I2S_ClearITPendingBit\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Function used to set the SPI configuration to the default reset state *****/ \r
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx);\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);\r
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);\r
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);\r
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);\r
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);\r
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+\r
+/* Data transfers functions ***************************************************/ \r
+void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);\r
+uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);\r
+\r
+/* Hardware CRC Calculation functions *****************************************/\r
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+void SPI_TransmitCRC(SPI_TypeDef* SPIx);\r
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);\r
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);\r
+\r
+/* DMA transfers management functions *****************************************/\r
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);\r
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);\r
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);\r
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);\r
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32L1xx_SPI_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_syscfg.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the SYSCFG \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/*!< Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_SYSCFG_H\r
+#define __STM32L1xx_SYSCFG_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/*!< Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup SYSCFG\r
+ * @{\r
+ */ \r
+ \r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup SYSCFG_Exported_Constants\r
+ * @{\r
+ */ \r
+ \r
+/** @defgroup EXTI_Port_Sources \r
+ * @{\r
+ */ \r
+#define EXTI_PortSourceGPIOA ((uint8_t)0x00)\r
+#define EXTI_PortSourceGPIOB ((uint8_t)0x01)\r
+#define EXTI_PortSourceGPIOC ((uint8_t)0x02)\r
+#define EXTI_PortSourceGPIOD ((uint8_t)0x03)\r
+#define EXTI_PortSourceGPIOE ((uint8_t)0x04)\r
+#define EXTI_PortSourceGPIOH ((uint8_t)0x05)\r
+ \r
+#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \\r
+ ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \\r
+ ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \\r
+ ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \\r
+ ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \\r
+ ((PORTSOURCE) == EXTI_PortSourceGPIOH)) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup EXTI_Pin_sources \r
+ * @{\r
+ */ \r
+#define EXTI_PinSource0 ((uint8_t)0x00)\r
+#define EXTI_PinSource1 ((uint8_t)0x01)\r
+#define EXTI_PinSource2 ((uint8_t)0x02)\r
+#define EXTI_PinSource3 ((uint8_t)0x03)\r
+#define EXTI_PinSource4 ((uint8_t)0x04)\r
+#define EXTI_PinSource5 ((uint8_t)0x05)\r
+#define EXTI_PinSource6 ((uint8_t)0x06)\r
+#define EXTI_PinSource7 ((uint8_t)0x07)\r
+#define EXTI_PinSource8 ((uint8_t)0x08)\r
+#define EXTI_PinSource9 ((uint8_t)0x09)\r
+#define EXTI_PinSource10 ((uint8_t)0x0A)\r
+#define EXTI_PinSource11 ((uint8_t)0x0B)\r
+#define EXTI_PinSource12 ((uint8_t)0x0C)\r
+#define EXTI_PinSource13 ((uint8_t)0x0D)\r
+#define EXTI_PinSource14 ((uint8_t)0x0E)\r
+#define EXTI_PinSource15 ((uint8_t)0x0F)\r
+#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \\r
+ ((PINSOURCE) == EXTI_PinSource1) || \\r
+ ((PINSOURCE) == EXTI_PinSource2) || \\r
+ ((PINSOURCE) == EXTI_PinSource3) || \\r
+ ((PINSOURCE) == EXTI_PinSource4) || \\r
+ ((PINSOURCE) == EXTI_PinSource5) || \\r
+ ((PINSOURCE) == EXTI_PinSource6) || \\r
+ ((PINSOURCE) == EXTI_PinSource7) || \\r
+ ((PINSOURCE) == EXTI_PinSource8) || \\r
+ ((PINSOURCE) == EXTI_PinSource9) || \\r
+ ((PINSOURCE) == EXTI_PinSource10) || \\r
+ ((PINSOURCE) == EXTI_PinSource11) || \\r
+ ((PINSOURCE) == EXTI_PinSource12) || \\r
+ ((PINSOURCE) == EXTI_PinSource13) || \\r
+ ((PINSOURCE) == EXTI_PinSource14) || \\r
+ ((PINSOURCE) == EXTI_PinSource15))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SYSCFG_Memory_Remap_Config \r
+ * @{\r
+ */ \r
+#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00)\r
+#define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01)\r
+#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03)\r
+ \r
+#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \\r
+ ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \\r
+ ((REMAP) == SYSCFG_MemoryRemap_SRAM))\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup RI_Resistor\r
+ * @{\r
+ */\r
+\r
+#define RI_Resistor_10KPU COMP_CSR_10KPU\r
+#define RI_Resistor_400KPU COMP_CSR_400KPU\r
+#define RI_Resistor_10KPD COMP_CSR_10KPD\r
+#define RI_Resistor_400KPD COMP_CSR_400KPD\r
+\r
+#define IS_RI_RESISTOR(RESISTOR) (((RESISTOR) == COMP_CSR_10KPU) || \\r
+ ((RESISTOR) == COMP_CSR_400KPU) || \\r
+ ((RESISTOR) == COMP_CSR_10KPD) || \\r
+ ((RESISTOR) == COMP_CSR_400KPD))\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RI_InputCapture\r
+ * @{\r
+ */ \r
+ \r
+#define RI_InputCapture_IC1 RI_ICR_IC1 /*!< Input Capture 1 */\r
+#define RI_InputCapture_IC2 RI_ICR_IC2 /*!< Input Capture 2 */\r
+#define RI_InputCapture_IC3 RI_ICR_IC3 /*!< Input Capture 3 */\r
+#define RI_InputCapture_IC4 RI_ICR_IC4 /*!< Input Capture 4 */\r
+\r
+#define IS_RI_INPUTCAPTURE(INPUTCAPTURE) ((((INPUTCAPTURE) & (uint32_t)0xFFC2FFFF) == 0x00) && ((INPUTCAPTURE) != (uint32_t)0x00))\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup TIM_Select\r
+ * @{\r
+ */ \r
+ \r
+#define TIM_Select_None ((uint32_t)0x00000000) /*!< None selected */\r
+#define TIM_Select_TIM2 ((uint32_t)0x00010000) /*!< Timer 2 selected */\r
+#define TIM_Select_TIM3 ((uint32_t)0x00020000) /*!< Timer 3 selected */\r
+#define TIM_Select_TIM4 ((uint32_t)0x00030000) /*!< Timer 4 selected */\r
+\r
+#define IS_RI_TIM(TIM) (((TIM) == TIM_Select_None) || \\r
+ ((TIM) == TIM_Select_TIM2) || \\r
+ ((TIM) == TIM_Select_TIM3) || \\r
+ ((TIM) == TIM_Select_TIM4))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup RI_InputCaptureRouting\r
+ * @{\r
+ */ \r
+ /* TIMx_IC1 TIMx_IC2 TIMx_IC3 TIMx_IC4 */ \r
+#define RI_InputCaptureRouting_0 ((uint32_t)0x00000000) /* PA0 PA1 PA2 PA3 */\r
+#define RI_InputCaptureRouting_1 ((uint32_t)0x00000001) /* PA4 PA5 PA6 PA7 */\r
+#define RI_InputCaptureRouting_2 ((uint32_t)0x00000002) /* PA8 PA9 PA10 PA11 */\r
+#define RI_InputCaptureRouting_3 ((uint32_t)0x00000003) /* PA12 PA13 PA14 PA15 */\r
+#define RI_InputCaptureRouting_4 ((uint32_t)0x00000004) /* PC0 PC1 PC2 PC3 */\r
+#define RI_InputCaptureRouting_5 ((uint32_t)0x00000005) /* PC4 PC5 PC6 PC7 */\r
+#define RI_InputCaptureRouting_6 ((uint32_t)0x00000006) /* PC8 PC9 PC10 PC11 */\r
+#define RI_InputCaptureRouting_7 ((uint32_t)0x00000007) /* PC12 PC13 PC14 PC15 */\r
+#define RI_InputCaptureRouting_8 ((uint32_t)0x00000008) /* PD0 PD1 PD2 PD3 */\r
+#define RI_InputCaptureRouting_9 ((uint32_t)0x00000009) /* PD4 PD5 PD6 PD7 */\r
+#define RI_InputCaptureRouting_10 ((uint32_t)0x0000000A) /* PD8 PD9 PD10 PD11 */\r
+#define RI_InputCaptureRouting_11 ((uint32_t)0x0000000B) /* PD12 PD13 PD14 PD15 */\r
+#define RI_InputCaptureRouting_12 ((uint32_t)0x0000000C) /* PE0 PE1 PE2 PE3 */\r
+#define RI_InputCaptureRouting_13 ((uint32_t)0x0000000D) /* PE4 PE5 PE6 PE7 */\r
+#define RI_InputCaptureRouting_14 ((uint32_t)0x0000000E) /* PE8 PE9 PE10 PE11 */\r
+#define RI_InputCaptureRouting_15 ((uint32_t)0x0000000F) /* PE12 PE13 PE14 PE15 */\r
+\r
+#define IS_RI_INPUTCAPTURE_ROUTING(ROUTING) (((ROUTING) == RI_InputCaptureRouting_0) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_1) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_2) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_3) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_4) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_5) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_6) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_7) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_8) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_9) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_10) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_11) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_12) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_13) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_14) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_15))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RI_IOSwitch\r
+ * @{\r
+ */ \r
+ \r
+/* ASCR1 I/O switch: bit 31 is set to '1' to indicate that the mask is in ASCR1 register */\r
+#define RI_IOSwitch_CH0 ((uint32_t)0x80000001)\r
+#define RI_IOSwitch_CH1 ((uint32_t)0x80000002)\r
+#define RI_IOSwitch_CH2 ((uint32_t)0x80000004)\r
+#define RI_IOSwitch_CH3 ((uint32_t)0x80000008)\r
+#define RI_IOSwitch_CH4 ((uint32_t)0x80000010)\r
+#define RI_IOSwitch_CH5 ((uint32_t)0x80000020)\r
+#define RI_IOSwitch_CH6 ((uint32_t)0x80000040)\r
+#define RI_IOSwitch_CH7 ((uint32_t)0x80000080)\r
+#define RI_IOSwitch_CH8 ((uint32_t)0x80000100)\r
+#define RI_IOSwitch_CH9 ((uint32_t)0x80000200)\r
+#define RI_IOSwitch_CH10 ((uint32_t)0x80000400)\r
+#define RI_IOSwitch_CH11 ((uint32_t)0x80000800)\r
+#define RI_IOSwitch_CH12 ((uint32_t)0x80001000)\r
+#define RI_IOSwitch_CH13 ((uint32_t)0x80002000)\r
+#define RI_IOSwitch_CH14 ((uint32_t)0x80004000)\r
+#define RI_IOSwitch_CH15 ((uint32_t)0x80008000)\r
+#define RI_IOSwitch_CH18 ((uint32_t)0x80040000)\r
+#define RI_IOSwitch_CH19 ((uint32_t)0x80080000)\r
+#define RI_IOSwitch_CH20 ((uint32_t)0x80100000)\r
+#define RI_IOSwitch_CH21 ((uint32_t)0x80200000)\r
+#define RI_IOSwitch_CH22 ((uint32_t)0x80400000)\r
+#define RI_IOSwitch_CH23 ((uint32_t)0x80800000)\r
+#define RI_IOSwitch_CH24 ((uint32_t)0x81000000)\r
+#define RI_IOSwitch_CH25 ((uint32_t)0x82000000)\r
+#define RI_IOSwitch_VCOMP ((uint32_t)0x84000000) /* VCOMP is an internal switch used to connect \r
+ selected channel to COMP1 non inverting input */\r
+\r
+/* ASCR2 IO switch: bit 31 is set to '0' to indicate that the mask is in ASCR2 register */ \r
+#define RI_IOSwitch_GR10_1 ((uint32_t)0x00000001)\r
+#define RI_IOSwitch_GR10_2 ((uint32_t)0x00000002)\r
+#define RI_IOSwitch_GR10_3 ((uint32_t)0x00000004)\r
+#define RI_IOSwitch_GR10_4 ((uint32_t)0x00000008)\r
+#define RI_IOSwitch_GR6_1 ((uint32_t)0x00000010)\r
+#define RI_IOSwitch_GR6_2 ((uint32_t)0x00000020)\r
+#define RI_IOSwitch_GR5_1 ((uint32_t)0x00000040)\r
+#define RI_IOSwitch_GR5_2 ((uint32_t)0x00000080)\r
+#define RI_IOSwitch_GR5_3 ((uint32_t)0x00000100)\r
+#define RI_IOSwitch_GR4_1 ((uint32_t)0x00000200)\r
+#define RI_IOSwitch_GR4_2 ((uint32_t)0x00000400)\r
+#define RI_IOSwitch_GR4_3 ((uint32_t)0x00000800)\r
+\r
+#define IS_RI_IOSWITCH(IOSWITCH) (((IOSWITCH) == RI_IOSwitch_CH0) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH1) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH2) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH3) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH4) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH5) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH6) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH7) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH8) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH9) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH10) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH11) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH12) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH13) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH14) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH15) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH18) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH19) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH20) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH21) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH22) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH23) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH24) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH25) || \\r
+ ((IOSWITCH) == RI_IOSwitch_VCOMP) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR10_1) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR10_2) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR10_3) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR10_4) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR6_1) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR6_2) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR5_1) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR5_2) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR5_3) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR4_1) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR4_2) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR4_3))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RI_Port\r
+ * @{\r
+ */\r
+\r
+#define RI_PortA ((uint8_t)0x01) /*!< GPIOA selected */\r
+#define RI_PortB ((uint8_t)0x02) /*!< GPIOB selected */\r
+#define RI_PortC ((uint8_t)0x03) /*!< GPIOC selected */\r
+#define RI_PortD ((uint8_t)0x04) /*!< GPIOD selected */\r
+#define RI_PortE ((uint8_t)0x05) /*!< GPIOE selected */\r
+\r
+#define IS_RI_PORT(PORT) (((PORT) == RI_PortA) || \\r
+ ((PORT) == RI_PortB) || \\r
+ ((PORT) == RI_PortC) || \\r
+ ((PORT) == RI_PortD) || \\r
+ ((PORT) == RI_PortE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RI_Pin define \r
+ * @{\r
+ */\r
+#define RI_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */\r
+#define RI_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */\r
+#define RI_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */\r
+#define RI_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */\r
+#define RI_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */\r
+#define RI_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */\r
+#define RI_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */\r
+#define RI_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */\r
+#define RI_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */\r
+#define RI_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */\r
+#define RI_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */\r
+#define RI_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */\r
+#define RI_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */\r
+#define RI_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */\r
+#define RI_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */\r
+#define RI_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */\r
+#define RI_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */\r
+\r
+#define IS_RI_PIN(PIN) ((PIN) != (uint16_t)0x00)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Function used to set the RTC configuration to the default reset state *****/\r
+void SYSCFG_DeInit(void);\r
+void SYSCFG_RIDeInit(void);\r
+\r
+/* SYSCFG Initialization and Configuration functions **************************/ \r
+void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap);\r
+void SYSCFG_USBPuCmd(FunctionalState NewState);\r
+void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);\r
+\r
+/* RI Initialization and Configuration functions ******************************/ \r
+void SYSCFG_RITIMSelect(uint32_t TIM_Select);\r
+void SYSCFG_RITIMInputCaptureConfig(uint32_t RI_InputCapture, uint32_t RI_InputCaptureRouting);\r
+void SYSCFG_RIResistorConfig(uint32_t RI_Resistor, FunctionalState NewState);\r
+void SYSCFG_RISwitchControlModeCmd(FunctionalState NewState);\r
+void SYSCFG_RIIOSwitchConfig(uint32_t RI_IOSwitch, FunctionalState NewState);\r
+void SYSCFG_RIHysteresisConfig(uint8_t RI_Port, uint16_t RI_Pin,\r
+ FunctionalState NewState);\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32L1xx_SYSCFG_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_tim.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the TIM firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_TIM_H\r
+#define __STM32L1xx_TIM_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup TIM\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief TIM Time Base Init structure definition\r
+ * @note This structure is used with all TIMx except for TIM6 and TIM7. \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.\r
+ This parameter can be a number between 0x0000 and 0xFFFF */\r
+\r
+ uint16_t TIM_CounterMode; /*!< Specifies the counter mode.\r
+ This parameter can be a value of @ref TIM_Counter_Mode */\r
+\r
+ uint16_t TIM_Period; /*!< Specifies the period value to be loaded into the active\r
+ Auto-Reload Register at the next update event.\r
+ This parameter must be a number between 0x0000 and 0xFFFF. */ \r
+\r
+ uint16_t TIM_ClockDivision; /*!< Specifies the clock division.\r
+ This parameter can be a value of @ref TIM_Clock_Division_CKD */\r
+\r
+} TIM_TimeBaseInitTypeDef; \r
+\r
+/** \r
+ * @brief TIM Output Compare Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint16_t TIM_OCMode; /*!< Specifies the TIM mode.\r
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */\r
+\r
+ uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.\r
+ This parameter can be a value of @ref TIM_Output_Compare_state */\r
+\r
+ uint16_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. \r
+ This parameter can be a number between 0x0000 and 0xFFFF */\r
+\r
+ uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.\r
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */\r
+\r
+} TIM_OCInitTypeDef;\r
+\r
+/** \r
+ * @brief TIM Input Capture Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+\r
+ uint16_t TIM_Channel; /*!< Specifies the TIM channel.\r
+ This parameter can be a value of @ref TIM_Channel */\r
+\r
+ uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
+\r
+ uint16_t TIM_ICSelection; /*!< Specifies the input.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */\r
+\r
+ uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
+\r
+ uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.\r
+ This parameter can be a number between 0x0 and 0xF */\r
+} TIM_ICInitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+ \r
+/** @defgroup TIM_Exported_constants \r
+ * @{\r
+ */\r
+\r
+#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) || \\r
+ ((PERIPH) == TIM6) || \\r
+ ((PERIPH) == TIM7) || \\r
+ ((PERIPH) == TIM9) || \\r
+ ((PERIPH) == TIM10) || \\r
+ ((PERIPH) == TIM11))\r
+\r
+/* LIST1: TIM2, TIM3, TIM4, TIM9, TIM10 and TIM11 */\r
+#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) || \\r
+ ((PERIPH) == TIM9) || \\r
+ ((PERIPH) == TIM10) || \\r
+ ((PERIPH) == TIM11))\r
+\r
+/* LIST3: TIM2, TIM3 and TIM4 */\r
+#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4))\r
+\r
+/* LIST2: TIM2, TIM3, TIM4 and TIM9 */\r
+#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) ||\\r
+ ((PERIPH) == TIM9))\r
+\r
+/* LIST5: TIM2, TIM3, TIM4, TIM6, TIM7 and TIM9 */\r
+#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) ||\\r
+ ((PERIPH) == TIM6) || \\r
+ ((PERIPH) == TIM7) ||\\r
+ ((PERIPH) == TIM9))\r
+\r
+/* LIST4: TIM2, TIM3, TIM4, TIM6 and TIM7 */\r
+#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) ||\\r
+ ((PERIPH) == TIM6) || \\r
+ ((PERIPH) == TIM7))\r
+\r
+/* LIST6: TIM9, TIM10 and TIM11 */\r
+#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM9) || \\r
+ ((PERIPH) == TIM10) ||\\r
+ ((PERIPH) == TIM11))\r
+\r
+\r
+\r
+/** @defgroup TIM_Output_Compare_and_PWM_modes \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCMode_Timing ((uint16_t)0x0000)\r
+#define TIM_OCMode_Active ((uint16_t)0x0010)\r
+#define TIM_OCMode_Inactive ((uint16_t)0x0020)\r
+#define TIM_OCMode_Toggle ((uint16_t)0x0030)\r
+#define TIM_OCMode_PWM1 ((uint16_t)0x0060)\r
+#define TIM_OCMode_PWM2 ((uint16_t)0x0070)\r
+#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \\r
+ ((MODE) == TIM_OCMode_Active) || \\r
+ ((MODE) == TIM_OCMode_Inactive) || \\r
+ ((MODE) == TIM_OCMode_Toggle)|| \\r
+ ((MODE) == TIM_OCMode_PWM1) || \\r
+ ((MODE) == TIM_OCMode_PWM2))\r
+#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \\r
+ ((MODE) == TIM_OCMode_Active) || \\r
+ ((MODE) == TIM_OCMode_Inactive) || \\r
+ ((MODE) == TIM_OCMode_Toggle)|| \\r
+ ((MODE) == TIM_OCMode_PWM1) || \\r
+ ((MODE) == TIM_OCMode_PWM2) || \\r
+ ((MODE) == TIM_ForcedAction_Active) || \\r
+ ((MODE) == TIM_ForcedAction_InActive))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_One_Pulse_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_OPMode_Single ((uint16_t)0x0008)\r
+#define TIM_OPMode_Repetitive ((uint16_t)0x0000)\r
+#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \\r
+ ((MODE) == TIM_OPMode_Repetitive))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Channel \r
+ * @{\r
+ */\r
+\r
+#define TIM_Channel_1 ((uint16_t)0x0000)\r
+#define TIM_Channel_2 ((uint16_t)0x0004)\r
+#define TIM_Channel_3 ((uint16_t)0x0008)\r
+#define TIM_Channel_4 ((uint16_t)0x000C)\r
+\r
+#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \\r
+ ((CHANNEL) == TIM_Channel_2) || \\r
+ ((CHANNEL) == TIM_Channel_3) || \\r
+ ((CHANNEL) == TIM_Channel_4))\r
+ \r
+#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \\r
+ ((CHANNEL) == TIM_Channel_2))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Clock_Division_CKD \r
+ * @{\r
+ */\r
+\r
+#define TIM_CKD_DIV1 ((uint16_t)0x0000)\r
+#define TIM_CKD_DIV2 ((uint16_t)0x0100)\r
+#define TIM_CKD_DIV4 ((uint16_t)0x0200)\r
+#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \\r
+ ((DIV) == TIM_CKD_DIV2) || \\r
+ ((DIV) == TIM_CKD_DIV4))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Counter_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_CounterMode_Up ((uint16_t)0x0000)\r
+#define TIM_CounterMode_Down ((uint16_t)0x0010)\r
+#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)\r
+#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)\r
+#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)\r
+#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \\r
+ ((MODE) == TIM_CounterMode_Down) || \\r
+ ((MODE) == TIM_CounterMode_CenterAligned1) || \\r
+ ((MODE) == TIM_CounterMode_CenterAligned2) || \\r
+ ((MODE) == TIM_CounterMode_CenterAligned3))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_Polarity \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCPolarity_High ((uint16_t)0x0000)\r
+#define TIM_OCPolarity_Low ((uint16_t)0x0002)\r
+#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \\r
+ ((POLARITY) == TIM_OCPolarity_Low))\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup TIM_Output_Compare_state\r
+ * @{\r
+ */\r
+\r
+#define TIM_OutputState_Disable ((uint16_t)0x0000)\r
+#define TIM_OutputState_Enable ((uint16_t)0x0001)\r
+#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \\r
+ ((STATE) == TIM_OutputState_Enable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup TIM_Capture_Compare_state \r
+ * @{\r
+ */\r
+\r
+#define TIM_CCx_Enable ((uint16_t)0x0001)\r
+#define TIM_CCx_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \\r
+ ((CCX) == TIM_CCx_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Input_Capture_Polarity \r
+ * @{\r
+ */\r
+\r
+#define TIM_ICPolarity_Rising ((uint16_t)0x0000)\r
+#define TIM_ICPolarity_Falling ((uint16_t)0x0002)\r
+#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)\r
+#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \\r
+ ((POLARITY) == TIM_ICPolarity_Falling)|| \\r
+ ((POLARITY) == TIM_ICPolarity_BothEdge))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Input_Capture_Selection \r
+ * @{\r
+ */\r
+\r
+#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be \r
+ connected to IC1, IC2, IC3 or IC4, respectively */\r
+#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be\r
+ connected to IC2, IC1, IC4 or IC3, respectively. */\r
+#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */\r
+#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \\r
+ ((SELECTION) == TIM_ICSelection_IndirectTI) || \\r
+ ((SELECTION) == TIM_ICSelection_TRC))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Input_Capture_Prescaler \r
+ * @{\r
+ */\r
+\r
+#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */\r
+#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */\r
+#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */\r
+#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */\r
+#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \\r
+ ((PRESCALER) == TIM_ICPSC_DIV2) || \\r
+ ((PRESCALER) == TIM_ICPSC_DIV4) || \\r
+ ((PRESCALER) == TIM_ICPSC_DIV8))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_interrupt_sources \r
+ * @{\r
+ */\r
+\r
+#define TIM_IT_Update ((uint16_t)0x0001)\r
+#define TIM_IT_CC1 ((uint16_t)0x0002)\r
+#define TIM_IT_CC2 ((uint16_t)0x0004)\r
+#define TIM_IT_CC3 ((uint16_t)0x0008)\r
+#define TIM_IT_CC4 ((uint16_t)0x0010)\r
+#define TIM_IT_Trigger ((uint16_t)0x0040)\r
+#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFFA0) == 0x0000) && ((IT) != 0x0000))\r
+\r
+#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \\r
+ ((IT) == TIM_IT_CC1) || \\r
+ ((IT) == TIM_IT_CC2) || \\r
+ ((IT) == TIM_IT_CC3) || \\r
+ ((IT) == TIM_IT_CC4) || \\r
+ ((IT) == TIM_IT_Trigger))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_DMA_Base_address \r
+ * @{\r
+ */\r
+\r
+#define TIM_DMABase_CR1 ((uint16_t)0x0000)\r
+#define TIM_DMABase_CR2 ((uint16_t)0x0001)\r
+#define TIM_DMABase_SMCR ((uint16_t)0x0002)\r
+#define TIM_DMABase_DIER ((uint16_t)0x0003)\r
+#define TIM_DMABase_SR ((uint16_t)0x0004)\r
+#define TIM_DMABase_EGR ((uint16_t)0x0005)\r
+#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)\r
+#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)\r
+#define TIM_DMABase_CCER ((uint16_t)0x0008)\r
+#define TIM_DMABase_CNT ((uint16_t)0x0009)\r
+#define TIM_DMABase_PSC ((uint16_t)0x000A)\r
+#define TIM_DMABase_ARR ((uint16_t)0x000B)\r
+#define TIM_DMABase_RCR ((uint16_t)0x000C)\r
+#define TIM_DMABase_CCR1 ((uint16_t)0x000D)\r
+#define TIM_DMABase_CCR2 ((uint16_t)0x000E)\r
+#define TIM_DMABase_CCR3 ((uint16_t)0x000F)\r
+#define TIM_DMABase_CCR4 ((uint16_t)0x0010)\r
+#define TIM_DMABase_DCR ((uint16_t)0x0012)\r
+#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \\r
+ ((BASE) == TIM_DMABase_CR2) || \\r
+ ((BASE) == TIM_DMABase_SMCR) || \\r
+ ((BASE) == TIM_DMABase_DIER) || \\r
+ ((BASE) == TIM_DMABase_SR) || \\r
+ ((BASE) == TIM_DMABase_EGR) || \\r
+ ((BASE) == TIM_DMABase_CCMR1) || \\r
+ ((BASE) == TIM_DMABase_CCMR2) || \\r
+ ((BASE) == TIM_DMABase_CCER) || \\r
+ ((BASE) == TIM_DMABase_CNT) || \\r
+ ((BASE) == TIM_DMABase_PSC) || \\r
+ ((BASE) == TIM_DMABase_ARR) || \\r
+ ((BASE) == TIM_DMABase_CCR1) || \\r
+ ((BASE) == TIM_DMABase_CCR2) || \\r
+ ((BASE) == TIM_DMABase_CCR3) || \\r
+ ((BASE) == TIM_DMABase_CCR4) || \\r
+ ((BASE) == TIM_DMABase_DCR)) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_DMA_Burst_Length \r
+ * @{\r
+ */\r
+\r
+#define TIM_DMABurstLength_1Byte ((uint16_t)0x0000)\r
+#define TIM_DMABurstLength_2Bytes ((uint16_t)0x0100)\r
+#define TIM_DMABurstLength_3Bytes ((uint16_t)0x0200)\r
+#define TIM_DMABurstLength_4Bytes ((uint16_t)0x0300)\r
+#define TIM_DMABurstLength_5Bytes ((uint16_t)0x0400)\r
+#define TIM_DMABurstLength_6Bytes ((uint16_t)0x0500)\r
+#define TIM_DMABurstLength_7Bytes ((uint16_t)0x0600)\r
+#define TIM_DMABurstLength_8Bytes ((uint16_t)0x0700)\r
+#define TIM_DMABurstLength_9Bytes ((uint16_t)0x0800)\r
+#define TIM_DMABurstLength_10Bytes ((uint16_t)0x0900)\r
+#define TIM_DMABurstLength_11Bytes ((uint16_t)0x0A00)\r
+#define TIM_DMABurstLength_12Bytes ((uint16_t)0x0B00)\r
+#define TIM_DMABurstLength_13Bytes ((uint16_t)0x0C00)\r
+#define TIM_DMABurstLength_14Bytes ((uint16_t)0x0D00)\r
+#define TIM_DMABurstLength_15Bytes ((uint16_t)0x0E00)\r
+#define TIM_DMABurstLength_16Bytes ((uint16_t)0x0F00)\r
+#define TIM_DMABurstLength_17Bytes ((uint16_t)0x1000)\r
+#define TIM_DMABurstLength_18Bytes ((uint16_t)0x1100)\r
+#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Byte) || \\r
+ ((LENGTH) == TIM_DMABurstLength_2Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_3Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_4Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_5Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_6Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_7Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_8Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_9Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_10Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_11Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_12Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_13Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_14Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_15Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_16Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_17Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_18Bytes))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_DMA_sources \r
+ * @{\r
+ */\r
+\r
+#define TIM_DMA_Update ((uint16_t)0x0100)\r
+#define TIM_DMA_CC1 ((uint16_t)0x0200)\r
+#define TIM_DMA_CC2 ((uint16_t)0x0400)\r
+#define TIM_DMA_CC3 ((uint16_t)0x0800)\r
+#define TIM_DMA_CC4 ((uint16_t)0x1000)\r
+#define TIM_DMA_Trigger ((uint16_t)0x4000)\r
+#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xA0FF) == 0x0000) && ((SOURCE) != 0x0000))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_External_Trigger_Prescaler \r
+ * @{\r
+ */\r
+\r
+#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)\r
+#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)\r
+#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)\r
+#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)\r
+#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \\r
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \\r
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \\r
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV8))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Internal_Trigger_Selection \r
+ * @{\r
+ */\r
+\r
+#define TIM_TS_ITR0 ((uint16_t)0x0000)\r
+#define TIM_TS_ITR1 ((uint16_t)0x0010)\r
+#define TIM_TS_ITR2 ((uint16_t)0x0020)\r
+#define TIM_TS_ITR3 ((uint16_t)0x0030)\r
+#define TIM_TS_TI1F_ED ((uint16_t)0x0040)\r
+#define TIM_TS_TI1FP1 ((uint16_t)0x0050)\r
+#define TIM_TS_TI2FP2 ((uint16_t)0x0060)\r
+#define TIM_TS_ETRF ((uint16_t)0x0070)\r
+#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \\r
+ ((SELECTION) == TIM_TS_ITR1) || \\r
+ ((SELECTION) == TIM_TS_ITR2) || \\r
+ ((SELECTION) == TIM_TS_ITR3) || \\r
+ ((SELECTION) == TIM_TS_TI1F_ED) || \\r
+ ((SELECTION) == TIM_TS_TI1FP1) || \\r
+ ((SELECTION) == TIM_TS_TI2FP2) || \\r
+ ((SELECTION) == TIM_TS_ETRF))\r
+#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \\r
+ ((SELECTION) == TIM_TS_ITR1) || \\r
+ ((SELECTION) == TIM_TS_ITR2) || \\r
+ ((SELECTION) == TIM_TS_ITR3))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_TIx_External_Clock_Source \r
+ * @{\r
+ */\r
+\r
+#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)\r
+#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)\r
+#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_External_Trigger_Polarity \r
+ * @{\r
+ */ \r
+#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)\r
+#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)\r
+#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \\r
+ ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Prescaler_Reload_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)\r
+#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)\r
+#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \\r
+ ((RELOAD) == TIM_PSCReloadMode_Immediate))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Forced_Action \r
+ * @{\r
+ */\r
+\r
+#define TIM_ForcedAction_Active ((uint16_t)0x0050)\r
+#define TIM_ForcedAction_InActive ((uint16_t)0x0040)\r
+#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \\r
+ ((ACTION) == TIM_ForcedAction_InActive))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Encoder_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)\r
+#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)\r
+#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)\r
+#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \\r
+ ((MODE) == TIM_EncoderMode_TI2) || \\r
+ ((MODE) == TIM_EncoderMode_TI12))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup TIM_Event_Source \r
+ * @{\r
+ */\r
+\r
+#define TIM_EventSource_Update ((uint16_t)0x0001)\r
+#define TIM_EventSource_CC1 ((uint16_t)0x0002)\r
+#define TIM_EventSource_CC2 ((uint16_t)0x0004)\r
+#define TIM_EventSource_CC3 ((uint16_t)0x0008)\r
+#define TIM_EventSource_CC4 ((uint16_t)0x0010)\r
+#define TIM_EventSource_Trigger ((uint16_t)0x0040)\r
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFFA0) == 0x0000) && ((SOURCE) != 0x0000)) \r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Update_Source \r
+ * @{\r
+ */\r
+\r
+#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow\r
+ or the setting of UG bit, or an update generation\r
+ through the slave mode controller. */\r
+#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */\r
+#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \\r
+ ((SOURCE) == TIM_UpdateSource_Regular))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_Preload_State \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCPreload_Enable ((uint16_t)0x0008)\r
+#define TIM_OCPreload_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \\r
+ ((STATE) == TIM_OCPreload_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_Fast_State \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCFast_Enable ((uint16_t)0x0004)\r
+#define TIM_OCFast_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \\r
+ ((STATE) == TIM_OCFast_Disable))\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_Clear_State \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCClear_Enable ((uint16_t)0x0080)\r
+#define TIM_OCClear_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \\r
+ ((STATE) == TIM_OCClear_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Trigger_Output_Source \r
+ * @{\r
+ */\r
+\r
+#define TIM_TRGOSource_Reset ((uint16_t)0x0000)\r
+#define TIM_TRGOSource_Enable ((uint16_t)0x0010)\r
+#define TIM_TRGOSource_Update ((uint16_t)0x0020)\r
+#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)\r
+#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)\r
+#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)\r
+#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)\r
+#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)\r
+#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \\r
+ ((SOURCE) == TIM_TRGOSource_Enable) || \\r
+ ((SOURCE) == TIM_TRGOSource_Update) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC1) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC1Ref) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC2Ref) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC3Ref) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC4Ref))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Slave_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_SlaveMode_Reset ((uint16_t)0x0004)\r
+#define TIM_SlaveMode_Gated ((uint16_t)0x0005)\r
+#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)\r
+#define TIM_SlaveMode_External1 ((uint16_t)0x0007)\r
+#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \\r
+ ((MODE) == TIM_SlaveMode_Gated) || \\r
+ ((MODE) == TIM_SlaveMode_Trigger) || \\r
+ ((MODE) == TIM_SlaveMode_External1))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Master_Slave_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)\r
+#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \\r
+ ((STATE) == TIM_MasterSlaveMode_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup TIM_Flags \r
+ * @{\r
+ */\r
+\r
+#define TIM_FLAG_Update ((uint16_t)0x0001)\r
+#define TIM_FLAG_CC1 ((uint16_t)0x0002)\r
+#define TIM_FLAG_CC2 ((uint16_t)0x0004)\r
+#define TIM_FLAG_CC3 ((uint16_t)0x0008)\r
+#define TIM_FLAG_CC4 ((uint16_t)0x0010)\r
+#define TIM_FLAG_Trigger ((uint16_t)0x0040)\r
+#define TIM_FLAG_CC1OF ((uint16_t)0x0200)\r
+#define TIM_FLAG_CC2OF ((uint16_t)0x0400)\r
+#define TIM_FLAG_CC3OF ((uint16_t)0x0800)\r
+#define TIM_FLAG_CC4OF ((uint16_t)0x1000)\r
+#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \\r
+ ((FLAG) == TIM_FLAG_CC1) || \\r
+ ((FLAG) == TIM_FLAG_CC2) || \\r
+ ((FLAG) == TIM_FLAG_CC3) || \\r
+ ((FLAG) == TIM_FLAG_CC4) || \\r
+ ((FLAG) == TIM_FLAG_Trigger) || \\r
+ ((FLAG) == TIM_FLAG_CC1OF) || \\r
+ ((FLAG) == TIM_FLAG_CC2OF) || \\r
+ ((FLAG) == TIM_FLAG_CC3OF) || \\r
+ ((FLAG) == TIM_FLAG_CC4OF))\r
+#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE1A0) == 0x0000) && ((TIM_FLAG) != 0x0000)) \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Input_Capture_Filer_Value \r
+ * @{\r
+ */\r
+\r
+#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_External_Trigger_Filter \r
+ * @{\r
+ */\r
+\r
+#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_OCReferenceClear \r
+ * @{\r
+ */\r
+#define TIM_OCReferenceClear_ETRF ((uint16_t)0x0008)\r
+#define TIM_OCReferenceClear_OCREFCLR ((uint16_t)0x0000)\r
+#define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \\r
+ ((SOURCE) == TIM_OCReferenceClear_OCREFCLR)) \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Remap \r
+ * @{\r
+ */\r
+\r
+#define TIM9_GPIO ((uint16_t)0x0000)\r
+#define TIM9_LSE ((uint16_t)0x0001)\r
+\r
+#define TIM10_GPIO ((uint16_t)0x0000)\r
+#define TIM10_LSI ((uint16_t)0x0001)\r
+#define TIM10_LSE ((uint16_t)0x0002)\r
+#define TIM10_RTC ((uint16_t)0x0003)\r
+\r
+#define TIM11_GPIO ((uint16_t)0x0000)\r
+#define TIM11_MSI ((uint16_t)0x0001)\r
+#define TIM11_HSE_RTC ((uint16_t)0x0002)\r
+\r
+#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM9_GPIO)||\\r
+ ((TIM_REMAP) == TIM9_LSE)||\\r
+ ((TIM_REMAP) == TIM10_GPIO)||\\r
+ ((TIM_REMAP) == TIM10_LSI)||\\r
+ ((TIM_REMAP) == TIM10_LSE)||\\r
+ ((TIM_REMAP) == TIM10_RTC)||\\r
+ ((TIM_REMAP) == TIM11_GPIO)||\\r
+ ((TIM_REMAP) == TIM11_MSI)||\\r
+ ((TIM_REMAP) == TIM11_HSE_RTC)) \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */ \r
+\r
+/* TimeBase management ********************************************************/\r
+void TIM_DeInit(TIM_TypeDef* TIMx);\r
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);\r
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);\r
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);\r
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);\r
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);\r
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);\r
+uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);\r
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);\r
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);\r
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);\r
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);\r
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+\r
+/* Output Compare management **************************************************/\r
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);\r
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);\r
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);\r
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);\r
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);\r
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
+void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear);\r
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);\r
+\r
+/* Input Capture management ***************************************************/\r
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);\r
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);\r
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);\r
+uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);\r
+uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);\r
+uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);\r
+uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);\r
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
+\r
+/* Interrupts, DMA and flags management ***************************************/\r
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);\r
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);\r
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);\r
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);\r
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);\r
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);\r
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);\r
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);\r
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+\r
+/* Clocks management **********************************************************/\r
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx);\r
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);\r
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,\r
+ uint16_t TIM_ICPolarity, uint16_t ICFilter);\r
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
+ uint16_t ExtTRGFilter);\r
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, \r
+ uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);\r
+\r
+\r
+/* Synchronization management *************************************************/\r
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);\r
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);\r
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);\r
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);\r
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
+ uint16_t ExtTRGFilter);\r
+\r
+/* Specific interface management **********************************************/ \r
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,\r
+ uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);\r
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+\r
+/* Specific remapping management **********************************************/\r
+void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32L1xx_TIM_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_usart.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the USART \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_USART_H\r
+#define __STM32L1xx_USART_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup USART\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/ \r
+\r
+/** \r
+ * @brief USART Init Structure definition \r
+ */ \r
+ \r
+typedef struct\r
+{\r
+ uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.\r
+ The baud rate is computed using the following formula:\r
+ - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))\r
+ - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */\r
+\r
+ uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.\r
+ This parameter can be a value of @ref USART_Word_Length */\r
+\r
+ uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.\r
+ This parameter can be a value of @ref USART_Stop_Bits */\r
+\r
+ uint16_t USART_Parity; /*!< Specifies the parity mode.\r
+ This parameter can be a value of @ref USART_Parity\r
+ @note When parity is enabled, the computed parity is inserted\r
+ at the MSB position of the transmitted data (9th bit when\r
+ the word length is set to 9 data bits; 8th bit when the\r
+ word length is set to 8 data bits). */\r
+ \r
+ uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.\r
+ This parameter can be a value of @ref USART_Mode */\r
+\r
+ uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled\r
+ or disabled.\r
+ This parameter can be a value of @ref USART_Hardware_Flow_Control */\r
+} USART_InitTypeDef;\r
+\r
+/** \r
+ * @brief USART Clock Init Structure definition \r
+ */ \r
+ \r
+typedef struct\r
+{\r
+\r
+ uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.\r
+ This parameter can be a value of @ref USART_Clock */\r
+\r
+ uint16_t USART_CPOL; /*!< Specifies the steady state value of the serial clock.\r
+ This parameter can be a value of @ref USART_Clock_Polarity */\r
+\r
+ uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.\r
+ This parameter can be a value of @ref USART_Clock_Phase */\r
+\r
+ uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted\r
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.\r
+ This parameter can be a value of @ref USART_Last_Bit */\r
+} USART_ClockInitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup USART_Exported_Constants\r
+ * @{\r
+ */ \r
+ \r
+#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \\r
+ ((PERIPH) == USART2) || \\r
+ ((PERIPH) == USART3))\r
+\r
+/** @defgroup USART_Word_Length \r
+ * @{\r
+ */ \r
+ \r
+#define USART_WordLength_8b ((uint16_t)0x0000)\r
+#define USART_WordLength_9b ((uint16_t)0x1000)\r
+ \r
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \\r
+ ((LENGTH) == USART_WordLength_9b))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Stop_Bits \r
+ * @{\r
+ */ \r
+ \r
+#define USART_StopBits_1 ((uint16_t)0x0000)\r
+#define USART_StopBits_0_5 ((uint16_t)0x1000)\r
+#define USART_StopBits_2 ((uint16_t)0x2000)\r
+#define USART_StopBits_1_5 ((uint16_t)0x3000)\r
+#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \\r
+ ((STOPBITS) == USART_StopBits_0_5) || \\r
+ ((STOPBITS) == USART_StopBits_2) || \\r
+ ((STOPBITS) == USART_StopBits_1_5))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Parity \r
+ * @{\r
+ */ \r
+ \r
+#define USART_Parity_No ((uint16_t)0x0000)\r
+#define USART_Parity_Even ((uint16_t)0x0400)\r
+#define USART_Parity_Odd ((uint16_t)0x0600) \r
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \\r
+ ((PARITY) == USART_Parity_Even) || \\r
+ ((PARITY) == USART_Parity_Odd))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Mode \r
+ * @{\r
+ */ \r
+ \r
+#define USART_Mode_Rx ((uint16_t)0x0004)\r
+#define USART_Mode_Tx ((uint16_t)0x0008)\r
+#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Hardware_Flow_Control \r
+ * @{\r
+ */ \r
+#define USART_HardwareFlowControl_None ((uint16_t)0x0000)\r
+#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)\r
+#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)\r
+#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)\r
+#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\\r
+ (((CONTROL) == USART_HardwareFlowControl_None) || \\r
+ ((CONTROL) == USART_HardwareFlowControl_RTS) || \\r
+ ((CONTROL) == USART_HardwareFlowControl_CTS) || \\r
+ ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Clock \r
+ * @{\r
+ */ \r
+#define USART_Clock_Disable ((uint16_t)0x0000)\r
+#define USART_Clock_Enable ((uint16_t)0x0800)\r
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \\r
+ ((CLOCK) == USART_Clock_Enable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Clock_Polarity \r
+ * @{\r
+ */\r
+ \r
+#define USART_CPOL_Low ((uint16_t)0x0000)\r
+#define USART_CPOL_High ((uint16_t)0x0400)\r
+#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Clock_Phase\r
+ * @{\r
+ */\r
+\r
+#define USART_CPHA_1Edge ((uint16_t)0x0000)\r
+#define USART_CPHA_2Edge ((uint16_t)0x0200)\r
+#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Last_Bit\r
+ * @{\r
+ */\r
+\r
+#define USART_LastBit_Disable ((uint16_t)0x0000)\r
+#define USART_LastBit_Enable ((uint16_t)0x0100)\r
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \\r
+ ((LASTBIT) == USART_LastBit_Enable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Interrupt_definition \r
+ * @{\r
+ */\r
+ \r
+#define USART_IT_PE ((uint16_t)0x0028)\r
+#define USART_IT_TXE ((uint16_t)0x0727)\r
+#define USART_IT_TC ((uint16_t)0x0626)\r
+#define USART_IT_RXNE ((uint16_t)0x0525)\r
+#define USART_IT_IDLE ((uint16_t)0x0424)\r
+#define USART_IT_LBD ((uint16_t)0x0846)\r
+#define USART_IT_CTS ((uint16_t)0x096A)\r
+#define USART_IT_ERR ((uint16_t)0x0060)\r
+#define USART_IT_ORE ((uint16_t)0x0360)\r
+#define USART_IT_NE ((uint16_t)0x0260)\r
+#define USART_IT_FE ((uint16_t)0x0160)\r
+#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \\r
+ ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \\r
+ ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \\r
+ ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))\r
+#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \\r
+ ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \\r
+ ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \\r
+ ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \\r
+ ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))\r
+#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \\r
+ ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_DMA_Requests \r
+ * @{\r
+ */\r
+\r
+#define USART_DMAReq_Tx ((uint16_t)0x0080)\r
+#define USART_DMAReq_Rx ((uint16_t)0x0040)\r
+#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_WakeUp_methods\r
+ * @{\r
+ */\r
+\r
+#define USART_WakeUp_IdleLine ((uint16_t)0x0000)\r
+#define USART_WakeUp_AddressMark ((uint16_t)0x0800)\r
+#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \\r
+ ((WAKEUP) == USART_WakeUp_AddressMark))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_LIN_Break_Detection_Length \r
+ * @{\r
+ */\r
+ \r
+#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)\r
+#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)\r
+#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \\r
+ (((LENGTH) == USART_LINBreakDetectLength_10b) || \\r
+ ((LENGTH) == USART_LINBreakDetectLength_11b))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_IrDA_Low_Power \r
+ * @{\r
+ */\r
+\r
+#define USART_IrDAMode_LowPower ((uint16_t)0x0004)\r
+#define USART_IrDAMode_Normal ((uint16_t)0x0000)\r
+#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \\r
+ ((MODE) == USART_IrDAMode_Normal))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Flags \r
+ * @{\r
+ */\r
+\r
+#define USART_FLAG_CTS ((uint16_t)0x0200)\r
+#define USART_FLAG_LBD ((uint16_t)0x0100)\r
+#define USART_FLAG_TXE ((uint16_t)0x0080)\r
+#define USART_FLAG_TC ((uint16_t)0x0040)\r
+#define USART_FLAG_RXNE ((uint16_t)0x0020)\r
+#define USART_FLAG_IDLE ((uint16_t)0x0010)\r
+#define USART_FLAG_ORE ((uint16_t)0x0008)\r
+#define USART_FLAG_NE ((uint16_t)0x0004)\r
+#define USART_FLAG_FE ((uint16_t)0x0002)\r
+#define USART_FLAG_PE ((uint16_t)0x0001)\r
+#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \\r
+ ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \\r
+ ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \\r
+ ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \\r
+ ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))\r
+ \r
+#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))\r
+\r
+#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x003D0901))\r
+#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)\r
+#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */ \r
+\r
+/* Function used to set the USART configuration to the default reset state ***/ \r
+void USART_DeInit(USART_TypeDef* USARTx);\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);\r
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct);\r
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);\r
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);\r
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);\r
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+\r
+/* Data transfers functions ***************************************************/ \r
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);\r
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx);\r
+\r
+/* Multi-Processor Communication functions ************************************/\r
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);\r
+void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);\r
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+\r
+/* LIN mode functions *********************************************************/\r
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);\r
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_SendBreak(USART_TypeDef* USARTx);\r
+\r
+/* Half-duplex mode function **************************************************/\r
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+\r
+/* Smartcard mode functions ***************************************************/\r
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);\r
+\r
+/* IrDA mode functions ********************************************************/\r
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);\r
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+\r
+/* DMA transfers management functions *****************************************/\r
+void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);\r
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);\r
+void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);\r
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);\r
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_USART_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_wwdg.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the WWDG \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_WWDG_H\r
+#define __STM32L1xx_WWDG_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup WWDG\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup WWDG_Exported_Constants\r
+ * @{\r
+ */ \r
+ \r
+/** @defgroup WWDG_Prescaler \r
+ * @{\r
+ */ \r
+ \r
+#define WWDG_Prescaler_1 ((uint32_t)0x00000000)\r
+#define WWDG_Prescaler_2 ((uint32_t)0x00000080)\r
+#define WWDG_Prescaler_4 ((uint32_t)0x00000100)\r
+#define WWDG_Prescaler_8 ((uint32_t)0x00000180)\r
+#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \\r
+ ((PRESCALER) == WWDG_Prescaler_2) || \\r
+ ((PRESCALER) == WWDG_Prescaler_4) || \\r
+ ((PRESCALER) == WWDG_Prescaler_8))\r
+#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)\r
+#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+/* Function used to set the WWDG configuration to the default reset state ****/ \r
+void WWDG_DeInit(void);\r
+\r
+/* Prescaler, Refresh window and Counter configuration functions **************/\r
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);\r
+void WWDG_SetWindowValue(uint8_t WindowValue);\r
+void WWDG_EnableIT(void);\r
+void WWDG_SetCounter(uint8_t Counter);\r
+\r
+/* WWDG activation functions **************************************************/\r
+void WWDG_Enable(uint8_t Counter);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+FlagStatus WWDG_GetFlagStatus(void);\r
+void WWDG_ClearFlag(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_WWDG_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file misc.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides all the miscellaneous firmware functions (add-on\r
+ * to CMSIS functions).\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "misc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup MISC \r
+ * @brief MISC driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup MISC_Private_Functions\r
+ * @{\r
+ */\r
+/**\r
+ *\r
+@verbatim \r
+ *******************************************************************************\r
+ Interrupts configuration functions\r
+ ******************************************************************************* \r
+ \r
+ This section provide functions allowing to configure the NVIC interrupts (IRQ).\r
+ The Cortex-M3 exceptions are managed by CMSIS functions.\r
+ \r
+ 1. Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig() function\r
+ according to the following table.\r
+ \r
+ The table below gives the allowed values of the pre-emption priority and subpriority according\r
+ to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function\r
+ ============================================================================================================================\r
+ NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description\r
+ ============================================================================================================================\r
+ NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority\r
+ | | | 4 bits for subpriority\r
+ ----------------------------------------------------------------------------------------------------------------------------\r
+ NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority\r
+ | | | 3 bits for subpriority\r
+ ---------------------------------------------------------------------------------------------------------------------------- \r
+ NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority\r
+ | | | 2 bits for subpriority\r
+ ---------------------------------------------------------------------------------------------------------------------------- \r
+ NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority\r
+ | | | 1 bits for subpriority\r
+ ---------------------------------------------------------------------------------------------------------------------------- \r
+ NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority\r
+ | | | 0 bits for subpriority \r
+ ============================================================================================================================ \r
+\r
+\r
+ 2. Enable and Configure the priority of the selected IRQ Channels. \r
+\r
+@note When the NVIC_PriorityGroup_0 is selected, it will no any nested interrupt,\r
+ the IRQ priority will be managed only by subpriority.\r
+ The sub-priority is only used to sort pending exception priorities, \r
+ and does not affect active exceptions.\r
+\r
+@note Lower priority values gives higher priority.\r
+\r
+@note Priority Order:\r
+ 1. Lowest Preemption priority\r
+ 2. Lowest Subpriority\r
+ 3. Lowest hardware priority (IRQn position)\r
+ \r
+@endverbatim\r
+*/\r
+\r
+/**\r
+ * @brief Configures the priority grouping: pre-emption priority and subpriority.\r
+ * @param NVIC_PriorityGroup: specifies the priority grouping bits length. \r
+ * This parameter can be one of the following values:\r
+ * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority\r
+ * 4 bits for subpriority\r
+ * @note When NVIC_PriorityGroup_0 is selected, it will no be any nested \r
+ * interrupt. This interrupts priority is managed only with subpriority. \r
+ * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority\r
+ * 3 bits for subpriority\r
+ * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority\r
+ * 2 bits for subpriority\r
+ * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority\r
+ * 1 bits for subpriority\r
+ * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority\r
+ * 0 bits for subpriority\r
+ * @retval None\r
+ */\r
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));\r
+ \r
+ /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */\r
+ SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the NVIC peripheral according to the specified\r
+ * parameters in the NVIC_InitStruct.\r
+ * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()\r
+ * function should be called before. \r
+ * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains\r
+ * the configuration information for the specified NVIC peripheral.\r
+ * @retval None\r
+ */\r
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)\r
+{\r
+ uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));\r
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); \r
+ assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));\r
+ \r
+ if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)\r
+ {\r
+ /* Compute the Corresponding IRQ Priority --------------------------------*/ \r
+ tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;\r
+ tmppre = (0x4 - tmppriority);\r
+ tmpsub = tmpsub >> tmppriority;\r
+\r
+ tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;\r
+ tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;\r
+ tmppriority = tmppriority << 0x04;\r
+ \r
+ NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;\r
+ \r
+ /* Enable the Selected IRQ Channels --------------------------------------*/\r
+ NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =\r
+ (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Selected IRQ Channels -------------------------------------*/\r
+ NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =\r
+ (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sets the vector table location and Offset.\r
+ * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.\r
+ * This parameter can be one of the following values:\r
+ * @arg NVIC_VectTab_RAM\r
+ * @arg NVIC_VectTab_FLASH\r
+ * @param Offset: Vector Table base offset field. This value must be a multiple of 0x200.\r
+ * @retval None\r
+ */\r
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));\r
+ assert_param(IS_NVIC_OFFSET(Offset)); \r
+ \r
+ SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);\r
+}\r
+\r
+/**\r
+ * @brief Selects the condition for the system to enter low power mode.\r
+ * @param LowPowerMode: Specifies the new mode for the system to enter low power mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg NVIC_LP_SEVONPEND\r
+ * @arg NVIC_LP_SLEEPDEEP\r
+ * @arg NVIC_LP_SLEEPONEXIT\r
+ * @param NewState: new state of LP condition. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_LP(LowPowerMode));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ SCB->SCR |= LowPowerMode;\r
+ }\r
+ else\r
+ {\r
+ SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the SysTick clock source.\r
+ * @param SysTick_CLKSource: specifies the SysTick clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.\r
+ * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.\r
+ * @retval None\r
+ */\r
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));\r
+ \r
+ if (SysTick_CLKSource == SysTick_CLKSource_HCLK)\r
+ {\r
+ SysTick->CTRL |= SysTick_CLKSource_HCLK;\r
+ }\r
+ else\r
+ {\r
+ SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_adc.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Analog to Digital Convertor (ADC) peripheral: \r
+ * - Initialization and Configuration\r
+ * - Power saving\r
+ * - Analog Watchdog configuration \r
+ * - Temperature Sensor & Vrefint (Voltage Reference internal) management \r
+ * - Regular Channels Configuration\r
+ * - Regular Channels DMA Configuration\r
+ * - Injected channels Configuration \r
+ * - Interrupts and flags management \r
+ * \r
+ * @verbatim\r
+ * \r
+ * =================================================================== \r
+ * How to use this driver\r
+ * =================================================================== \r
+ * - Configure the ADC Prescaler, conversion resolution and data \r
+ * alignment using the ADC_Init() function.\r
+ * - Activate the ADC peripheral using ADC_Cmd() function. \r
+ *\r
+ * Regular channels group configuration\r
+ * ==================================== \r
+ * - To configure the ADC regular channels group features, use \r
+ * ADC_Init() and ADC_RegularChannelConfig() functions.\r
+ * - To activate the continuous mode, use the ADC_continuousModeCmd()\r
+ * function.\r
+ * - To configurate and activate the Discontinuous mode, use the \r
+ * ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions. \r
+ * - To read the ADC converted values, use the ADC_GetConversionValue()\r
+ * function.\r
+ *\r
+ * DMA for Regular channels group features configuration\r
+ * ====================================================== \r
+ * - To enable the DMA mode for regular channels group, use the \r
+ * ADC_DMACmd() function.\r
+ * - To enable the generation of DMA requests continuously at the end\r
+ * of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd() \r
+ * function. \r
+ \r
+ * Injected channels group configuration\r
+ * ===================================== \r
+ * - To configure the ADC Injected channels group features, use \r
+ * ADC_InjectedChannelConfig() and ADC_InjectedSequencerLengthConfig()\r
+ * functions.\r
+ * - To activate the continuous mode, use the ADC_continuousModeCmd()\r
+ * function.\r
+ * - To activate the Injected Discontinuous mode, use the \r
+ * ADC_InjectedDiscModeCmd() function. \r
+ * - To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd() \r
+ * function. \r
+ * - To read the ADC converted values, use the ADC_GetInjectedConversionValue() \r
+ * function.\r
+ * \r
+ * @endverbatim\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_adc.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ADC \r
+ * @brief ADC driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* ADC DISCNUM mask */\r
+#define CR1_DISCNUM_RESET ((uint32_t)0xFFFF1FFF)\r
+ \r
+/* ADC AWDCH mask */\r
+#define CR1_AWDCH_RESET ((uint32_t)0xFFFFFFE0) \r
+ \r
+/* ADC Analog watchdog enable mode mask */\r
+#define CR1_AWDMODE_RESET ((uint32_t)0xFF3FFDFF)\r
+ \r
+/* CR1 register Mask */\r
+#define CR1_CLEAR_MASK ((uint32_t)0xFCFFFEFF) \r
+ \r
+/* ADC DELAY mask */ \r
+#define CR2_DELS_RESET ((uint32_t)0xFFFFFF0F)\r
+ \r
+/* ADC JEXTEN mask */\r
+#define CR2_JEXTEN_RESET ((uint32_t)0xFFCFFFFF)\r
+ \r
+/* ADC JEXTSEL mask */\r
+#define CR2_JEXTSEL_RESET ((uint32_t)0xFFF0FFFF)\r
+ \r
+/* CR2 register Mask */\r
+#define CR2_CLEAR_MASK ((uint32_t)0xC0FFF7FD)\r
+\r
+/* ADC SQx mask */\r
+#define SQR5_SQ_SET ((uint32_t)0x0000001F) \r
+#define SQR4_SQ_SET ((uint32_t)0x0000001F) \r
+#define SQR3_SQ_SET ((uint32_t)0x0000001F) \r
+#define SQR2_SQ_SET ((uint32_t)0x0000001F) \r
+#define SQR1_SQ_SET ((uint32_t)0x0000001F)\r
+\r
+/* ADC L Mask */\r
+#define SQR1_L_RESET ((uint32_t)0xFE0FFFFF) \r
+\r
+/* ADC JSQx mask */\r
+#define JSQR_JSQ_SET ((uint32_t)0x0000001F) \r
+ \r
+/* ADC JL mask */\r
+#define JSQR_JL_SET ((uint32_t)0x00300000) \r
+#define JSQR_JL_RESET ((uint32_t)0xFFCFFFFF) \r
+\r
+/* ADC SMPx mask */\r
+#define SMPR1_SMP_SET ((uint32_t)0x00000007) \r
+#define SMPR2_SMP_SET ((uint32_t)0x00000007)\r
+#define SMPR3_SMP_SET ((uint32_t)0x00000007) \r
+\r
+/* ADC JDRx registers offset */\r
+#define JDR_OFFSET ((uint8_t)0x30) \r
+ \r
+/* ADC CCR register Mask */\r
+#define CR_CLEAR_MASK ((uint32_t)0xFFFCFFFF) \r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup ADC_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ADC_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Initialization and Configuration functions\r
+ =============================================================================== \r
+ This section provides functions allowing to:\r
+ - Initialize and configure the ADC Prescaler\r
+ - ADC Conversion Resolution (12bit..6bit)\r
+ - Scan Conversion Mode (multichannels or one channel) for regular group\r
+ - ADC Continuous Conversion Mode (Continuous or Single conversion) for regular group\r
+ - External trigger Edge and source of regular group, \r
+ - Converted data alignment (left or right)\r
+ - The number of ADC conversions that will be done using the sequencer for regular channel group\r
+ - Enable or disable the ADC peripheral\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes ADC1 peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void ADC_DeInit(ADC_TypeDef* ADCx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ \r
+ /* Enable ADC1 reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);\r
+ /* Release ADC1 from reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Initializes the ADCx peripheral according to the specified parameters\r
+ * in the ADC_InitStruct.\r
+ * @note This function is used to configure the global features of the ADC ( \r
+ * Resolution and Data Alignment), however, the rest of the configuration\r
+ * parameters are specific to the regular channels group (scan mode \r
+ * activation, continuous mode activation, External trigger source and \r
+ * edge, number of conversion in the regular channels group sequencer). \r
+ * @param ADCx: where x can be 1 to select the ADC peripheral.\r
+ * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains \r
+ * the configuration information for the specified ADC peripheral.\r
+ * @retval None\r
+ */\r
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) \r
+{\r
+ uint32_t tmpreg1 = 0;\r
+ uint8_t tmpreg2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution)); \r
+ assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));\r
+ assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); \r
+ assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge)); \r
+ assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); \r
+ assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); \r
+ assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfConversion));\r
+ \r
+ /*---------------------------- ADCx CR1 Configuration -----------------*/\r
+ /* Get the ADCx CR1 value */\r
+ tmpreg1 = ADCx->CR1;\r
+ /* Clear RES and SCAN bits */ \r
+ tmpreg1 &= CR1_CLEAR_MASK;\r
+ /* Configure ADCx: scan conversion mode and resolution */\r
+ /* Set SCAN bit according to ADC_ScanConvMode value */\r
+ /* Set RES bit according to ADC_Resolution value */ \r
+ tmpreg1 |= (uint32_t)(((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8) | ADC_InitStruct->ADC_Resolution);\r
+ /* Write to ADCx CR1 */\r
+ ADCx->CR1 = tmpreg1;\r
+ \r
+ /*---------------------------- ADCx CR2 Configuration -----------------*/\r
+ /* Get the ADCx CR2 value */\r
+ tmpreg1 = ADCx->CR2;\r
+ /* Clear CONT, ALIGN, EXTEN and EXTSEL bits */\r
+ tmpreg1 &= CR2_CLEAR_MASK;\r
+ /* Configure ADCx: external trigger event and edge, data alignment and continuous conversion mode */\r
+ /* Set ALIGN bit according to ADC_DataAlign value */\r
+ /* Set EXTEN bits according to ADC_ExternalTrigConvEdge value */ \r
+ /* Set EXTSEL bits according to ADC_ExternalTrigConv value */\r
+ /* Set CONT bit according to ADC_ContinuousConvMode value */\r
+ tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | \r
+ ADC_InitStruct->ADC_ExternalTrigConvEdge | ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));\r
+ /* Write to ADCx CR2 */\r
+ ADCx->CR2 = tmpreg1;\r
+ \r
+ /*---------------------------- ADCx SQR1 Configuration -----------------*/\r
+ /* Get the ADCx SQR1 value */\r
+ tmpreg1 = ADCx->SQR1;\r
+ /* Clear L bits */\r
+ tmpreg1 &= SQR1_L_RESET;\r
+ /* Configure ADCx: regular channel sequence length */\r
+ /* Set L bits according to ADC_NbrOfConversion value */ \r
+ tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfConversion - (uint8_t)1);\r
+ tmpreg1 |= ((uint32_t)tmpreg2 << 20);\r
+ /* Write to ADCx SQR1 */\r
+ ADCx->SQR1 = tmpreg1;\r
+}\r
+\r
+/**\r
+ * @brief Fills each ADC_InitStruct member with its default value.\r
+ * @note This function is used to initialize the global features of the ADC ( \r
+ * Resolution and Data Alignment), however, the rest of the configuration\r
+ * parameters are specific to the regular channels group (scan mode \r
+ * activation, continuous mode activation, External trigger source and \r
+ * edge, number of conversion in the regular channels group sequencer). \r
+ * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will \r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) \r
+{\r
+ /* Reset ADC init structure parameters values */\r
+ /* Initialize the ADC_Resolution member */\r
+ ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b;\r
+\r
+ /* Initialize the ADC_ScanConvMode member */\r
+ ADC_InitStruct->ADC_ScanConvMode = DISABLE;\r
+\r
+ /* Initialize the ADC_ContinuousConvMode member */\r
+ ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;\r
+\r
+ /* Initialize the ADC_ExternalTrigConvEdge member */\r
+ ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;\r
+\r
+ /* Initialize the ADC_ExternalTrigConv member */\r
+ ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T2_CC2;\r
+\r
+ /* Initialize the ADC_DataAlign member */\r
+ ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;\r
+\r
+ /* Initialize the ADC_NbrOfConversion member */\r
+ ADC_InitStruct->ADC_NbrOfConversion = 1;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the ADCs peripherals according to the specified parameters\r
+ * in the ADC_CommonInitStruct.\r
+ * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure \r
+ * that contains the configuration information (Prescaler) for ADC1 peripheral.\r
+ * @retval None\r
+ */\r
+void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct) \r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_PRESCALER(ADC_CommonInitStruct->ADC_Prescaler));\r
+\r
+ /*---------------------------- ADC CCR Configuration -----------------*/\r
+ /* Get the ADC CCR value */\r
+ tmpreg = ADC->CCR;\r
+\r
+ /* Clear ADCPRE bit */ \r
+ tmpreg &= CR_CLEAR_MASK;\r
+ \r
+ /* Configure ADCx: ADC prescaler according to ADC_Prescaler */ \r
+ tmpreg |= (uint32_t)(ADC_CommonInitStruct->ADC_Prescaler); \r
+ \r
+ /* Write to ADC CCR */\r
+ ADC->CCR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Fills each ADC_CommonInitStruct member with its default value.\r
+ * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure\r
+ * which will be initialized.\r
+ * @retval None\r
+ */\r
+void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct) \r
+{\r
+ /* Reset ADC init structure parameters values */\r
+ /* Initialize the ADC_Prescaler member */\r
+ ADC_CommonInitStruct->ADC_Prescaler = ADC_Prescaler_Div1;\r
+\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified ADC peripheral.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param NewState: new state of the ADCx peripheral. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the ADON bit to wake up the ADC from power down mode */\r
+ ADCx->CR2 |= (uint32_t)ADC_CR2_ADON;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC peripheral */\r
+ ADCx->CR2 &= (uint32_t)(~ADC_CR2_ADON);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Group2 Power saving functions\r
+ * @brief Power saving functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Power saving functions\r
+ =============================================================================== \r
+\r
+ This section provides functions allowing to reduce power consumption.\r
+ The two function must be combined to get the maximal benefits:\r
+ When the ADC frequency is higher than the CPU one, it is recommended to \r
+ 1. Insert a freeze delay : \r
+ ==> using ADC_DelaySelectionConfig(ADC1, ADC_DelayLength_Freeze);\r
+ 2. Enable the power down in Idle and Delay phases :\r
+ ==> using ADC_PowerDownCmd(ADC1, ADC_PowerDown_Idle_Delay, ENABLE);\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the ADC Power Down during Delay and/or Idle phase.\r
+ * @note ADC power-on and power-off can be managed by hardware to cut the \r
+ * consumption when the ADC is not converting. \r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_PowerDown: The ADC power down configuration. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_PowerDown_Delay: ADC is powered down during delay phase \r
+ * @arg ADC_PowerDown_Idle: ADC is powered down during Idle phase \r
+ * @arg ADC_PowerDown_Idle_Delay: ADC is powered down during Delay and Idle phases\r
+ * @note The ADC can be powered down: \r
+ * - During the hardware delay insertion (using the ADC_PowerDown_Delay\r
+ * parameter) \r
+ * => The ADC is powered up again at the end of the delay. \r
+ * - During the ADC is waiting for a trigger event ( using the \r
+ * ADC_PowerDown_Idle parameter) \r
+ * => The ADC is powered up at the next trigger event.\r
+ * - During the hardware delay insertion or the ADC is waiting for a \r
+ * trigger event (using the ADC_PowerDown_Idle_Delay parameter) \r
+ * => The ADC is powered up only at the end of the delay and at the \r
+ * next trigger event. \r
+ * @param NewState: new state of the ADCx power down. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_PowerDownCmd(ADC_TypeDef* ADCx, uint32_t ADC_PowerDown, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_ADC_POWER_DOWN(ADC_PowerDown));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the ADC power-down during Delay and/or Idle phase */\r
+ ADCx->CR1 |= ADC_PowerDown;\r
+ }\r
+ else\r
+ {\r
+ /* Disable The ADC power-down during Delay and/or Idle phase */\r
+ ADCx->CR1 &= (uint32_t)~ADC_PowerDown;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Defines the length of the delay which is applied after a conversion \r
+ * or a sequence of conversion.\r
+ * @note When the CPU clock is not fast enough to manage the data rate, a \r
+ * Hardware delay can be introduced between ADC conversions to reduce \r
+ * this data rate. \r
+ * @note The Hardware delay is inserted after :\r
+ * - each regular conversion\r
+ * - after each sequence of injected conversions\r
+ * @note No Hardware delay is inserted between conversions of different groups.\r
+ * @note When the hardware delay is not enough, the Freeze Delay Mode can be \r
+ * selected and a new conversion can start only if all the previous data \r
+ * of the same group have been treated:\r
+ * - for a regular conversion: once the ADC conversion data register has \r
+ * been read (using ADC_GetConversionValue() function) or if the EOC \r
+ * Flag has been cleared (using ADC_ClearFlag() function).\r
+ * - for an injected conversion: when the JEOC bit has been cleared \r
+ * (using ADC_ClearFlag() function).\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_DelayLength: The length of delay which is applied after a \r
+ * conversion or a sequence of conversion. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_DelayLength_None: No delay \r
+ * @arg ADC_DelayLength_Freeze: Delay until the converted data has been read.\r
+ * @arg ADC_DelayLength_7Cycles: Delay length equal to 7 APB clock cycles\r
+ * @arg ADC_DelayLength_15Cycles: Delay length equal to 15 APB clock cycles \r
+ * @arg ADC_DelayLength_31Cycles: Delay length equal to 31 APB clock cycles \r
+ * @arg ADC_DelayLength_63Cycles: Delay length equal to 63 APB clock cycles \r
+ * @arg ADC_DelayLength_127Cycles: Delay length equal to 127 APB clock cycles \r
+ * @arg ADC_DelayLength_255Cycles: Delay length equal to 255 APB clock cycles \r
+ * @retval None\r
+ */\r
+void ADC_DelaySelectionConfig(ADC_TypeDef* ADCx, uint8_t ADC_DelayLength)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_DELAY_LENGTH(ADC_DelayLength));\r
+\r
+ /* Get the old register value */ \r
+ tmpreg = ADCx->CR2;\r
+ /* Clear the old delay length */\r
+ tmpreg &= CR2_DELS_RESET;\r
+ /* Set the delay length */\r
+ tmpreg |= ADC_DelayLength;\r
+ /* Store the new register value */\r
+ ADCx->CR2 = tmpreg;\r
+\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Group3 Analog Watchdog configuration functions\r
+ * @brief Analog Watchdog configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Analog Watchdog configuration functions\r
+ =============================================================================== \r
+\r
+ This section provides functions allowing to configure the Analog Watchdog\r
+ (AWD) feature in the ADC.\r
+ \r
+ A typical configuration Analog Watchdog is done following these steps :\r
+ 1. the ADC guarded channel(s) is (are) selected using the \r
+ ADC_AnalogWatchdogSingleChannelConfig() function.\r
+ 2. The Analog watchdog lower and higher threshold are configured using the \r
+ ADC_AnalogWatchdogThresholdsConfig() function.\r
+ 3. The Analog watchdog is enabled and configured to enable the check, on one\r
+ or more channels, using the ADC_AnalogWatchdogCmd() function.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Enables or disables the analog watchdog on single/all regular\r
+ * or injected channels\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration.\r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single \r
+ * regular channel\r
+ * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single \r
+ * injected channel\r
+ * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a \r
+ * single regular or injected channel \r
+ * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular \r
+ * channel\r
+ * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected \r
+ * channel\r
+ * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all \r
+ * regular and injected channels\r
+ * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog\r
+ * @retval None \r
+ */\r
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));\r
+\r
+ /* Get the old register value */\r
+ tmpreg = ADCx->CR1;\r
+ /* Clear AWDEN, JAWDEN and AWDSGL bits */ \r
+ tmpreg &= CR1_AWDMODE_RESET;\r
+ /* Set the analog watchdog enable mode */\r
+ tmpreg |= ADC_AnalogWatchdog;\r
+ /* Store the new register value */\r
+ ADCx->CR1 = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Configures the high and low thresholds of the analog watchdog. \r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param HighThreshold: the ADC analog watchdog High threshold value.\r
+ * This parameter must be a 12bit value.\r
+ * @param LowThreshold: the ADC analog watchdog Low threshold value.\r
+ * This parameter must be a 12bit value.\r
+ * @retval None\r
+ */\r
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,\r
+ uint16_t LowThreshold)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_THRESHOLD(HighThreshold));\r
+ assert_param(IS_ADC_THRESHOLD(LowThreshold));\r
+\r
+ /* Set the ADCx high threshold */\r
+ ADCx->HTR = HighThreshold;\r
+ /* Set the ADCx low threshold */\r
+ ADCx->LTR = LowThreshold;\r
+}\r
+\r
+/**\r
+ * @brief Configures the analog watchdog guarded single channel\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_Channel: the ADC channel to configure for the analog watchdog. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_Channel_0: ADC Channel0 selected\r
+ * @arg ADC_Channel_1: ADC Channel1 selected\r
+ * @arg ADC_Channel_2: ADC Channel2 selected\r
+ * @arg ADC_Channel_3: ADC Channel3 selected\r
+ * @arg ADC_Channel_4: ADC Channel4 selected\r
+ * @arg ADC_Channel_5: ADC Channel5 selected\r
+ * @arg ADC_Channel_6: ADC Channel6 selected\r
+ * @arg ADC_Channel_7: ADC Channel7 selected\r
+ * @arg ADC_Channel_8: ADC Channel8 selected\r
+ * @arg ADC_Channel_9: ADC Channel9 selected\r
+ * @arg ADC_Channel_10: ADC Channel10 selected\r
+ * @arg ADC_Channel_11: ADC Channel11 selected\r
+ * @arg ADC_Channel_12: ADC Channel12 selected\r
+ * @arg ADC_Channel_13: ADC Channel13 selected\r
+ * @arg ADC_Channel_14: ADC Channel14 selected\r
+ * @arg ADC_Channel_15: ADC Channel15 selected\r
+ * @arg ADC_Channel_16: ADC Channel16 selected\r
+ * @arg ADC_Channel_17: ADC Channel17 selected\r
+ * @arg ADC_Channel_18: ADC Channel18 selected\r
+ * @arg ADC_Channel_19: ADC Channel19 selected\r
+ * @arg ADC_Channel_20: ADC Channel20 selected\r
+ * @arg ADC_Channel_21: ADC Channel21 selected\r
+ * @arg ADC_Channel_22: ADC Channel22 selected\r
+ * @arg ADC_Channel_23: ADC Channel23 selected\r
+ * @arg ADC_Channel_24: ADC Channel24 selected\r
+ * @arg ADC_Channel_25: ADC Channel25 selected\r
+ * @retval None\r
+ */\r
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));\r
+\r
+ /* Get the old register value */\r
+ tmpreg = ADCx->CR1;\r
+ /* Clear the Analog watchdog channel select bits */\r
+ tmpreg &= CR1_AWDCH_RESET;\r
+ /* Set the Analog watchdog channel */\r
+ tmpreg |= ADC_Channel;\r
+ /* Store the new register value */\r
+ ADCx->CR1 = tmpreg;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Group4 Temperature Sensor & Vrefint (Voltage Reference internal) management function\r
+ * @brief Temperature Sensor & Vrefint (Voltage Reference internal) management function \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Temperature Sensor & Vrefint (Voltage Reference internal) management function\r
+ =============================================================================== \r
+\r
+ This section provides a function allowing to enable/ disable the internal \r
+ connections between the ADC and the Temperature Sensor and the Vrefint source.\r
+ \r
+ A typical configuration to get the Temperature sensor and Vrefint channels \r
+ voltages or is done following these steps :\r
+ 1. Enable the internal connection of Temperature sensor and Vrefint sources \r
+ with the ADC channels using ADC_TempSensorVrefintCmd() function. \r
+ 2. select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint using \r
+ ADC_RegularChannelConfig() or ADC_InjectedChannelConfig() functions \r
+ 3. Get the voltage values, using ADC_GetConversionValue() or \r
+ ADC_GetInjectedConversionValue().\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Enables or disables the temperature sensor and Vrefint channel.\r
+ * @param NewState: new state of the temperature sensor and Vref int channels.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_TempSensorVrefintCmd(FunctionalState NewState) \r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the temperature sensor and Vrefint channel*/\r
+ ADC->CCR |= (uint32_t)ADC_CCR_TSVREFE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the temperature sensor and Vrefint channel*/\r
+ ADC->CCR &= (uint32_t)(~ADC_CCR_TSVREFE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Group5 Regular Channels Configuration functions\r
+ * @brief Regular Channels Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Regular Channels Configuration functions\r
+ =============================================================================== \r
+\r
+ This section provides functions allowing to manage the ADC regular channels,\r
+ it is composed of 2 sub sections : \r
+ \r
+ 1. Configuration and management functions for regular channels: This subsection \r
+ provides functions allowing to configure the ADC regular channels : \r
+ - Configure the rank in the regular group sequencer for each channel\r
+ - Configure the sampling time for each channel\r
+ - select the conversion Trigger for regular channels\r
+ - select the desired EOC event behavior configuration\r
+ - Activate the continuous Mode (*)\r
+ - Activate the Discontinuous Mode \r
+ Please Note that the following features for regular channels are configurated\r
+ using the ADC_Init() function : \r
+ - scan mode activation \r
+ - continuous mode activation (**) \r
+ - External trigger source \r
+ - External trigger edge \r
+ - number of conversion in the regular channels group sequencer.\r
+ \r
+ @note : (*) and (**) are performing the same configuration\r
+ \r
+ 2. Get the conversion data: This subsection provides an important function in \r
+ the ADC peripheral since it returns the converted data of the current \r
+ regular channel. When the Conversion value is read, the EOC Flag is \r
+ automatically cleared.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures for the selected ADC regular channel its corresponding\r
+ * rank in the sequencer and its sampling time.\r
+ * @param ADCx: where x can be 1 to select the ADC peripheral.\r
+ * @param ADC_Channel: the ADC channel to configure. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_Channel_0: ADC Channel0 selected\r
+ * @arg ADC_Channel_1: ADC Channel1 selected\r
+ * @arg ADC_Channel_2: ADC Channel2 selected\r
+ * @arg ADC_Channel_3: ADC Channel3 selected\r
+ * @arg ADC_Channel_4: ADC Channel4 selected\r
+ * @arg ADC_Channel_5: ADC Channel5 selected\r
+ * @arg ADC_Channel_6: ADC Channel6 selected\r
+ * @arg ADC_Channel_7: ADC Channel7 selected\r
+ * @arg ADC_Channel_8: ADC Channel8 selected\r
+ * @arg ADC_Channel_9: ADC Channel9 selected\r
+ * @arg ADC_Channel_10: ADC Channel10 selected\r
+ * @arg ADC_Channel_11: ADC Channel11 selected\r
+ * @arg ADC_Channel_12: ADC Channel12 selected\r
+ * @arg ADC_Channel_13: ADC Channel13 selected\r
+ * @arg ADC_Channel_14: ADC Channel14 selected\r
+ * @arg ADC_Channel_15: ADC Channel15 selected\r
+ * @arg ADC_Channel_16: ADC Channel16 selected\r
+ * @arg ADC_Channel_17: ADC Channel17 selected\r
+ * @arg ADC_Channel_18: ADC Channel18 selected \r
+ * @arg ADC_Channel_19: ADC Channel19 selected\r
+ * @arg ADC_Channel_20: ADC Channel20 selected\r
+ * @arg ADC_Channel_21: ADC Channel21 selected\r
+ * @arg ADC_Channel_22: ADC Channel22 selected\r
+ * @arg ADC_Channel_23: ADC Channel23 selected\r
+ * @arg ADC_Channel_24: ADC Channel24 selected\r
+ * @arg ADC_Channel_25: ADC Channel25 selected\r
+ * @param Rank: The rank in the regular group sequencer. This parameter\r
+ * must be between 1 to 26.\r
+ * @param ADC_SampleTime: The sample time value to be set for the selected \r
+ * channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_SampleTime_4Cycles: Sample time equal to 4 cycles \r
+ * @arg ADC_SampleTime_9Cycles: Sample time equal to 9 cycles\r
+ * @arg ADC_SampleTime_16Cycles: Sample time equal to 16 cycles\r
+ * @arg ADC_SampleTime_24Cycles: Sample time equal to 24 cycles \r
+ * @arg ADC_SampleTime_48Cycles: Sample time equal to 48 cycles \r
+ * @arg ADC_SampleTime_96Cycles: Sample time equal to 96 cycles \r
+ * @arg ADC_SampleTime_192Cycles: Sample time equal to 192 cycles \r
+ * @arg ADC_SampleTime_384Cycles: Sample time equal to 384 cycles \r
+ * @retval None\r
+ */\r
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)\r
+{\r
+ uint32_t tmpreg1 = 0, tmpreg2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));\r
+ assert_param(IS_ADC_REGULAR_RANK(Rank));\r
+ assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));\r
+\r
+ /* if ADC_Channel_20 ... ADC_Channel_25 is selected */\r
+ if (ADC_Channel > ADC_Channel_19)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SMPR1;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 20));\r
+ /* Clear the old sample time */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 20));\r
+ /* Set the new sample time */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SMPR1 = tmpreg1;\r
+ }\r
+ \r
+ /* if ADC_Channel_10 ... ADC_Channel_19 is selected */\r
+ else if (ADC_Channel > ADC_Channel_9)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SMPR2;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SMPR2_SMP_SET << (3 * (ADC_Channel - 10));\r
+ /* Clear the old sample time */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));\r
+ /* Set the new sample time */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SMPR2 = tmpreg1;\r
+ }\r
+ \r
+ else /* ADC_Channel include in ADC_Channel_[0..9] */\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SMPR3;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SMPR3_SMP_SET << (3 * ADC_Channel);\r
+ /* Clear the old sample time */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);\r
+ /* Set the new sample time */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SMPR3 = tmpreg1;\r
+ }\r
+ /* For Rank 1 to 6 */\r
+ if (Rank < 7)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SQR5;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SQR5_SQ_SET << (5 * (Rank - 1));\r
+ /* Clear the old SQx bits for the selected rank */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));\r
+ /* Set the SQx bits for the selected rank */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SQR5 = tmpreg1;\r
+ }\r
+ /* For Rank 7 to 12 */\r
+ else if (Rank < 13)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SQR4;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SQR4_SQ_SET << (5 * (Rank - 7));\r
+ /* Clear the old SQx bits for the selected rank */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));\r
+ /* Set the SQx bits for the selected rank */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SQR4 = tmpreg1;\r
+ } \r
+ /* For Rank 13 to 18 */\r
+ else if (Rank < 19)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SQR3;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SQR3_SQ_SET << (5 * (Rank - 13));\r
+ /* Clear the old SQx bits for the selected rank */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));\r
+ /* Set the SQx bits for the selected rank */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SQR3 = tmpreg1;\r
+ }\r
+ \r
+ /* For Rank 19 to 24 */\r
+ else if (Rank < 25)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SQR2;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SQR2_SQ_SET << (5 * (Rank - 19));\r
+ /* Clear the old SQx bits for the selected rank */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 19));\r
+ /* Set the SQx bits for the selected rank */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SQR2 = tmpreg1;\r
+ } \r
+ \r
+ /* For Rank 25 to 27 */\r
+ else\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SQR1;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SQR1_SQ_SET << (5 * (Rank - 25));\r
+ /* Clear the old SQx bits for the selected rank */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 25));\r
+ /* Set the SQx bits for the selected rank */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SQR1 = tmpreg1;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables the selected ADC software start conversion of the regular channels.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @retval None\r
+ */\r
+void ADC_SoftwareStartConv(ADC_TypeDef* ADCx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+\r
+ /* Enable the selected ADC conversion for regular group */\r
+ ADCx->CR2 |= (uint32_t)ADC_CR2_SWSTART;\r
+}\r
+\r
+/**\r
+ * @brief Gets the selected ADC Software start regular conversion Status.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @retval The new state of ADC software start conversion (SET or RESET).\r
+ */\r
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+\r
+ /* Check the status of SWSTART bit */\r
+ if ((ADCx->CR2 & ADC_CR2_SWSTART) != (uint32_t)RESET)\r
+ {\r
+ /* SWSTART bit is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* SWSTART bit is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the SWSTART bit status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the EOC on each regular channel conversion\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param NewState: new state of the selected ADC EOC flag rising\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC EOC rising on each regular channel conversion */\r
+ ADCx->CR2 |= ADC_CR2_EOCS;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC EOC rising on each regular channel conversion */\r
+ ADCx->CR2 &= (uint32_t)~ADC_CR2_EOCS;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the ADC continuous conversion mode \r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param NewState: new state of the selected ADC continuous conversion mode\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC continuous conversion mode */\r
+ ADCx->CR2 |= (uint32_t)ADC_CR2_CONT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC continuous conversion mode */\r
+ ADCx->CR2 &= (uint32_t)(~ADC_CR2_CONT);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the discontinuous mode for the selected ADC regular\r
+ * group channel.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param Number: specifies the discontinuous mode regular channel count value. \r
+ * This number must be between 1 and 8.\r
+ * @retval None\r
+ */\r
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)\r
+{\r
+ uint32_t tmpreg1 = 0;\r
+ uint32_t tmpreg2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number));\r
+\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->CR1;\r
+ /* Clear the old discontinuous mode channel count */\r
+ tmpreg1 &= CR1_DISCNUM_RESET;\r
+ /* Set the discontinuous mode channel count */\r
+ tmpreg2 = Number - 1;\r
+ tmpreg1 |= tmpreg2 << 13;\r
+ /* Store the new register value */\r
+ ADCx->CR1 = tmpreg1;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the discontinuous mode on regular group\r
+ * channel for the specified ADC\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param NewState: new state of the selected ADC discontinuous mode on regular \r
+ * group channel. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC regular discontinuous mode */\r
+ ADCx->CR1 |= (uint32_t)ADC_CR1_DISCEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC regular discontinuous mode */\r
+ ADCx->CR1 &= (uint32_t)(~ADC_CR1_DISCEN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the last ADCx conversion result data for regular channel. \r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @retval The Data conversion value.\r
+ */\r
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+\r
+ /* Return the selected ADC conversion value */\r
+ return (uint16_t) ADCx->DR;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Group6 Regular Channels DMA Configuration functions\r
+ * @brief Regular Channels DMA Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Regular Channels DMA Configuration functions\r
+ =============================================================================== \r
+\r
+ This section provides functions allowing to configure the DMA for ADC regular \r
+ channels.\r
+ Since converted regular channel values are stored into a unique data register, \r
+ it is useful to use DMA for conversion of more than one regular channel. This \r
+ avoids the loss of the data already stored in the ADC Data register. \r
+ \r
+ When the DMA mode is enabled (using the ADC_DMACmd() function), after each\r
+ conversion of a regular channel, a DMA request is generated.\r
+ \r
+ Depending on the "DMA disable selection" configuration (using the \r
+ ADC_DMARequestAfterLastTransferCmd() function), at the end of the last DMA \r
+ transfer, two possibilities are allowed:\r
+ - No new DMA request is issued to the DMA controller (feature DISABLED) \r
+ - Requests can continue to be generated (feature ENABLED).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified ADC DMA request.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param NewState: new state of the selected ADC DMA transfer.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_DMA_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC DMA request */\r
+ ADCx->CR2 |= (uint32_t)ADC_CR2_DMA;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC DMA request */\r
+ ADCx->CR2 &= (uint32_t)(~ADC_CR2_DMA);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables the ADC DMA request after last transfer (Single-ADC mode) \r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param NewState: new state of the selected ADC EOC flag rising\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC DMA request after last transfer */\r
+ ADCx->CR2 |= ADC_CR2_DDS;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC DMA request after last transfer */\r
+ ADCx->CR2 &= (uint32_t)~ADC_CR2_DDS;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Group7 Injected channels Configuration functions\r
+ * @brief Injected channels Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Injected channels Configuration functions\r
+ =============================================================================== \r
+\r
+ This section provide functions allowing to configure the ADC Injected channels,\r
+ it is composed of 2 sub sections : \r
+ \r
+ 1. Configuration functions for Injected channels: This subsection provides \r
+ functions allowing to configure the ADC injected channels : \r
+ - Configure the rank in the injected group sequencer for each channel\r
+ - Configure the sampling time for each channel \r
+ - Activate the Auto injected Mode \r
+ - Activate the Discontinuous Mode \r
+ - scan mode activation \r
+ - External/software trigger source \r
+ - External trigger edge \r
+ - injected channels sequencer.\r
+ \r
+ 2. Get the Specified Injected channel conversion data: This subsection \r
+ provides an important function in the ADC peripheral since it returns the \r
+ converted data of the specific injected channel.\r
+\r
+@endverbatim\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @brief Configures for the selected ADC injected channel its corresponding\r
+ * rank in the sequencer and its sample time.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_Channel: the ADC channel to configure. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_Channel_0: ADC Channel0 selected\r
+ * @arg ADC_Channel_1: ADC Channel1 selected\r
+ * @arg ADC_Channel_2: ADC Channel2 selected\r
+ * @arg ADC_Channel_3: ADC Channel3 selected\r
+ * @arg ADC_Channel_4: ADC Channel4 selected\r
+ * @arg ADC_Channel_5: ADC Channel5 selected\r
+ * @arg ADC_Channel_6: ADC Channel6 selected\r
+ * @arg ADC_Channel_7: ADC Channel7 selected\r
+ * @arg ADC_Channel_8: ADC Channel8 selected\r
+ * @arg ADC_Channel_9: ADC Channel9 selected\r
+ * @arg ADC_Channel_10: ADC Channel10 selected\r
+ * @arg ADC_Channel_11: ADC Channel11 selected\r
+ * @arg ADC_Channel_12: ADC Channel12 selected\r
+ * @arg ADC_Channel_13: ADC Channel13 selected\r
+ * @arg ADC_Channel_14: ADC Channel14 selected\r
+ * @arg ADC_Channel_15: ADC Channel15 selected\r
+ * @arg ADC_Channel_16: ADC Channel16 selected\r
+ * @arg ADC_Channel_17: ADC Channel17 selected\r
+ * @arg ADC_Channel_18: ADC Channel18 selected \r
+ * @arg ADC_Channel_19: ADC Channel19 selected\r
+ * @arg ADC_Channel_20: ADC Channel20 selected\r
+ * @arg ADC_Channel_21: ADC Channel21 selected\r
+ * @arg ADC_Channel_22: ADC Channel22 selected\r
+ * @arg ADC_Channel_23: ADC Channel23 selected\r
+ * @arg ADC_Channel_24: ADC Channel24 selected\r
+ * @arg ADC_Channel_25: ADC Channel25 selected\r
+ * @param Rank: The rank in the injected group sequencer. This parameter\r
+ * must be between 1 to 4.\r
+ * @param ADC_SampleTime: The sample time value to be set for the selected \r
+ * channel. This parameter can be one of the following values:\r
+ * @arg ADC_SampleTime_4Cycles: Sample time equal to 4 cycles \r
+ * @arg ADC_SampleTime_9Cycles: Sample time equal to 9 cycles\r
+ * @arg ADC_SampleTime_16Cycles: Sample time equal to 16 cycles\r
+ * @arg ADC_SampleTime_24Cycles: Sample time equal to 24 cycles \r
+ * @arg ADC_SampleTime_48Cycles: Sample time equal to 48 cycles \r
+ * @arg ADC_SampleTime_96Cycles: Sample time equal to 96 cycles \r
+ * @arg ADC_SampleTime_192Cycles: Sample time equal to 192 cycles \r
+ * @arg ADC_SampleTime_384Cycles: Sample time equal to 384 cycles \r
+ * @retval None\r
+ */\r
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)\r
+{\r
+ uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));\r
+ assert_param(IS_ADC_INJECTED_RANK(Rank));\r
+ assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));\r
+ \r
+ /* if ADC_Channel_20 ... ADC_Channel_25 is selected */\r
+ if (ADC_Channel > ADC_Channel_19)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SMPR1;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 20));\r
+ /* Clear the old sample time */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 20));\r
+ /* Set the new sample time */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SMPR1 = tmpreg1;\r
+ }\r
+ \r
+ /* if ADC_Channel_10 ... ADC_Channel_19 is selected */\r
+ else if (ADC_Channel > ADC_Channel_9)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SMPR2;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SMPR2_SMP_SET << (3 * (ADC_Channel - 10));\r
+ /* Clear the old sample time */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));\r
+ /* Set the new sample time */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SMPR2 = tmpreg1;\r
+ }\r
+ \r
+ else /* ADC_Channel include in ADC_Channel_[0..9] */\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SMPR3;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SMPR3_SMP_SET << (3 * ADC_Channel);\r
+ /* Clear the old sample time */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);\r
+ /* Set the new sample time */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SMPR3 = tmpreg1;\r
+ }\r
+ \r
+ /* Rank configuration */\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->JSQR;\r
+ /* Get JL value: Number = JL+1 */\r
+ tmpreg3 = (tmpreg1 & JSQR_JL_SET)>> 20;\r
+ /* Calculate the mask to clear: ((Rank-1)+(4- (JL+1))) */ \r
+ tmpreg2 = JSQR_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));\r
+ /* Clear the old JSQx bits for the selected rank */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set: ((Rank-1)+(4- (JL+1))) */ \r
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));\r
+ /* Set the JSQx bits for the selected rank */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->JSQR = tmpreg1;\r
+}\r
+\r
+/**\r
+ * @brief Configures the sequencer length for injected channels\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param Length: The sequencer length. \r
+ * This parameter must be a number between 1 to 4.\r
+ * @retval None\r
+ */\r
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length)\r
+{\r
+ uint32_t tmpreg1 = 0;\r
+ uint32_t tmpreg2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_INJECTED_LENGTH(Length));\r
+ \r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->JSQR;\r
+ /* Clear the old injected sequence length JL bits */\r
+ tmpreg1 &= JSQR_JL_RESET;\r
+ /* Set the injected sequence length JL bits */\r
+ tmpreg2 = Length - 1; \r
+ tmpreg1 |= tmpreg2 << 20;\r
+ /* Store the new register value */\r
+ ADCx->JSQR = tmpreg1;\r
+}\r
+\r
+/**\r
+ * @brief Set the injected channels conversion value offset\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_InjectedChannel: the ADC injected channel to set its offset. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_InjectedChannel_1: Injected Channel1 selected\r
+ * @arg ADC_InjectedChannel_2: Injected Channel2 selected\r
+ * @arg ADC_InjectedChannel_3: Injected Channel3 selected\r
+ * @arg ADC_InjectedChannel_4: Injected Channel4 selected\r
+ * @param Offset: the offset value for the selected ADC injected channel\r
+ * This parameter must be a 12bit value.\r
+ * @retval None\r
+ */\r
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));\r
+ assert_param(IS_ADC_OFFSET(Offset)); \r
+ \r
+ tmp = (uint32_t)ADCx;\r
+ tmp += ADC_InjectedChannel;\r
+ \r
+ /* Set the selected injected channel data offset */\r
+ *(__IO uint32_t *) tmp = (uint32_t)Offset;\r
+}\r
+\r
+/**\r
+ * @brief Configures the ADCx external trigger for injected channels conversion.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected \r
+ * conversion. This parameter can be one of the following values: \r
+ * @arg ADC_ExternalTrigInjecConv_T9_CC1: Timer9 capture compare1 selected \r
+ * @arg ADC_ExternalTrigInjecConv_T9_TRGO: Timer9 TRGO event selected \r
+ * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected \r
+ * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected\r
+ * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected \r
+ * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected \r
+ * @arg ADC_ExternalTrigInjecConv_T4_CC1: Timer4 capture compare1 selected \r
+ * @arg ADC_ExternalTrigInjecConv_T4_CC2: Timer4 capture compare2 selected \r
+ * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected \r
+ * @arg ADC_ExternalTrigInjecConv_T10_CC1: Timer10 capture compare1 selected\r
+ * @arg ADC_ExternalTrigInjecConv_T7_TRGO: Timer7 TRGO event selected \r
+ * @arg ADC_ExternalTrigInjecConv_Ext_IT15: External interrupt line 15 event selected \r
+ * @retval None\r
+ */\r
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));\r
+\r
+ /* Get the old register value */\r
+ tmpreg = ADCx->CR2;\r
+ /* Clear the old external event selection for injected group */\r
+ tmpreg &= CR2_JEXTSEL_RESET;\r
+ /* Set the external event selection for injected group */\r
+ tmpreg |= ADC_ExternalTrigInjecConv;\r
+ /* Store the new register value */\r
+ ADCx->CR2 = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Configures the ADCx external trigger edge for injected channels conversion.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_ExternalTrigInjecConvEdge: specifies the ADC external trigger\r
+ * edge to start injected conversion. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_ExternalTrigConvEdge_None: external trigger disabled for \r
+ * injected conversion\r
+ * @arg ADC_ExternalTrigConvEdge_Rising: detection on rising edge\r
+ * @arg ADC_ExternalTrigConvEdge_Falling: detection on falling edge\r
+ * @arg ADC_External ADC_ExternalTrigConvEdge_RisingFalling: detection on \r
+ * both rising and falling edge\r
+ * @retval None\r
+ */\r
+void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(ADC_ExternalTrigInjecConvEdge));\r
+\r
+ /* Get the old register value */\r
+ tmpreg = ADCx->CR2;\r
+ /* Clear the old external trigger edge for injected group */\r
+ tmpreg &= CR2_JEXTEN_RESET;\r
+ /* Set the new external trigger edge for injected group */\r
+ tmpreg |= ADC_ExternalTrigInjecConvEdge;\r
+ /* Store the new register value */\r
+ ADCx->CR2 = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables the selected ADC software start conversion of the injected \r
+ * channels.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @retval None\r
+ */\r
+void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ /* Enable the selected ADC conversion for injected group */\r
+ ADCx->CR2 |= (uint32_t)ADC_CR2_JSWSTART;\r
+}\r
+\r
+/**\r
+ * @brief Gets the selected ADC Software start injected conversion Status.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @retval The new state of ADC software start injected conversion (SET or RESET).\r
+ */\r
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+\r
+ /* Check the status of JSWSTART bit */\r
+ if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET)\r
+ {\r
+ /* JSWSTART bit is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* JSWSTART bit is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the JSWSTART bit status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the selected ADC automatic injected group\r
+ * conversion after regular one.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param NewState: new state of the selected ADC auto injected\r
+ * conversion. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC automatic injected group conversion */\r
+ ADCx->CR1 |= (uint32_t)ADC_CR1_JAUTO;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC automatic injected group conversion */\r
+ ADCx->CR1 &= (uint32_t)(~ADC_CR1_JAUTO);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the discontinuous mode for injected group\r
+ * channel for the specified ADC\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param NewState: new state of the selected ADC discontinuous mode\r
+ * on injected group channel. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC injected discontinuous mode */\r
+ ADCx->CR1 |= (uint32_t)ADC_CR1_JDISCEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC injected discontinuous mode */\r
+ ADCx->CR1 &= (uint32_t)(~ADC_CR1_JDISCEN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the ADC injected channel conversion result\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_InjectedChannel: the converted ADC injected channel.\r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_InjectedChannel_1: Injected Channel1 selected\r
+ * @arg ADC_InjectedChannel_2: Injected Channel2 selected\r
+ * @arg ADC_InjectedChannel_3: Injected Channel3 selected\r
+ * @arg ADC_InjectedChannel_4: Injected Channel4 selected\r
+ * @retval The Data conversion value.\r
+ */\r
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));\r
+\r
+ tmp = (uint32_t)ADCx;\r
+ tmp += ADC_InjectedChannel + JDR_OFFSET;\r
+ \r
+ /* Returns the selected injected channel conversion data value */\r
+ return (uint16_t) (*(__IO uint32_t*) tmp); \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Group8 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Interrupts and flags management functions\r
+ =============================================================================== \r
+\r
+ This section provides functions allowing to configure the ADC Interrupts and get \r
+ the status and clear flags and Interrupts pending bits.\r
+ \r
+ The ADC provide 4 Interrupts sources and 9 Flags which can be divided into 3 groups:\r
+ \r
+ I. Flags and Interrupts for ADC regular channels\r
+ =================================================\r
+ Flags :\r
+ ---------- \r
+ 1. ADC_FLAG_OVR : Overrun detection when regular converted data are lost\r
+\r
+ 2. ADC_FLAG_EOC : Regular channel end of conversion + to indicate (depending \r
+ on EOCS bit, managed by ADC_EOCOnEachRegularChannelCmd() ) the end of :\r
+ ==> a regular CHANNEL conversion \r
+ ==> sequence of regular GROUP conversions .\r
+\r
+ 3. ADC_FLAG_STRT: Regular channel start + to indicate when regular CHANNEL \r
+ conversion starts.\r
+ \r
+ 4. ADC_FLAG_RCNR: Regular channel not ready+ to indicate if a new regular \r
+ conversion can be launched\r
+ \r
+ Interrupts :\r
+ ------------\r
+ 1. ADC_IT_OVR \r
+ 2. ADC_IT_EOC \r
+ \r
+ \r
+ II. Flags and Interrupts for ADC Injected channels\r
+ =================================================\r
+ Flags :\r
+ ---------- \r
+ 1. ADC_FLAG_JEOC : Injected channel end of conversion+ to indicate at \r
+ the end of injected GROUP conversion \r
+ \r
+ 2. ADC_FLAG_JSTRT: Injected channel start + to indicate hardware when \r
+ injected GROUP conversion starts.\r
+\r
+ 3. ADC_FLAG_JCNR: Injected channel not ready + to indicate if a new \r
+ injected conversion can be launched.\r
+\r
+ Interrupts :\r
+ ------------\r
+ 1. ADC_IT_JEOC \r
+\r
+ III. General Flags and Interrupts for the ADC\r
+ ================================================= \r
+ Flags :\r
+ ---------- \r
+ 1. ADC_FLAG_AWD: Analog watchdog + to indicate if the converted voltage \r
+ crosses the programmed thresholds values.\r
+ \r
+ 2. ADC_FLAG_ADONS: ADC ON status + to indicate if the ADC is ready to convert.\r
+ \r
+ Interrupts :\r
+ ------------\r
+ 1. ADC_IT_AWD \r
+\r
+@endverbatim\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @brief Enables or disables the specified ADC interrupts.\r
+ * @param ADCx: where x can be 1 to select the ADC peripheral.\r
+ * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_IT_EOC: End of conversion interrupt \r
+ * @arg ADC_IT_AWD: Analog watchdog interrupt \r
+ * @arg ADC_IT_JEOC: End of injected conversion interrupt \r
+ * @arg ADC_IT_OVR: overrun interrupt \r
+ * @param NewState: new state of the specified ADC interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState) \r
+{\r
+ uint32_t itmask = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_ADC_IT(ADC_IT)); \r
+\r
+ /* Get the ADC IT index */\r
+ itmask = (uint8_t)ADC_IT;\r
+ itmask = (uint32_t)0x01 << itmask; \r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC interrupts */\r
+ ADCx->CR1 |= itmask;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC interrupts */\r
+ ADCx->CR1 &= (~(uint32_t)itmask);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified ADC flag is set or not.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_FLAG: specifies the flag to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_FLAG_AWD: Analog watchdog flag\r
+ * @arg ADC_FLAG_EOC: End of conversion flag\r
+ * @arg ADC_FLAG_JEOC: End of injected group conversion flag\r
+ * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag\r
+ * @arg ADC_FLAG_STRT: Start of regular group conversion flag\r
+ * @arg ADC_FLAG_OVR: Overrun flag \r
+ * @arg ADC_FLAG_ADONS: ADC ON status \r
+ * @arg ADC_FLAG_RCNR: Regular channel not ready \r
+ * @arg ADC_FLAG_JCNR: Injected channel not ready \r
+ * @retval The new state of ADC_FLAG (SET or RESET).\r
+ */\r
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint16_t ADC_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_GET_FLAG(ADC_FLAG));\r
+\r
+ /* Check the status of the specified ADC flag */\r
+ if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET)\r
+ {\r
+ /* ADC_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* ADC_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the ADC_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the ADCx's pending flags.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_FLAG: specifies the flag to clear. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg ADC_FLAG_AWD: Analog watchdog flag\r
+ * @arg ADC_FLAG_EOC: End of conversion flag\r
+ * @arg ADC_FLAG_JEOC: End of injected group conversion flag\r
+ * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag\r
+ * @arg ADC_FLAG_STRT: Start of regular group conversion flag\r
+ * @arg ADC_FLAG_OVR: overrun flag \r
+ * @retval None\r
+ */\r
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint16_t ADC_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));\r
+\r
+ /* Clear the selected ADC flags */\r
+ ADCx->SR = ~(uint32_t)ADC_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified ADC interrupt has occurred or not.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_IT: specifies the ADC interrupt source to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_IT_EOC: End of conversion interrupt \r
+ * @arg ADC_IT_AWD: Analog watchdog interrupt \r
+ * @arg ADC_IT_JEOC: End of injected conversion interrupt \r
+ * @arg ADC_IT_OVR: Overrun interrupt \r
+ * @retval The new state of ADC_IT (SET or RESET).\r
+ */\r
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t itmask = 0, enablestatus = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_IT(ADC_IT));\r
+\r
+ /* Get the ADC IT index */\r
+ itmask = (uint32_t)((uint32_t)ADC_IT >> 8);\r
+\r
+ /* Get the ADC_IT enable bit status */\r
+ enablestatus = (ADCx->CR1 & ((uint32_t)0x01 << (uint8_t)ADC_IT)); \r
+\r
+ /* Check the status of the specified ADC interrupt */\r
+ if (((uint32_t)(ADCx->SR & (uint32_t)itmask) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))\r
+ { \r
+ /* ADC_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* ADC_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the ADC_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the ADCx\92s interrupt pending bits.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_IT: specifies the ADC interrupt pending bit to clear.\r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_IT_EOC: End of conversion interrupt \r
+ * @arg ADC_IT_AWD: Analog watchdog interrupt \r
+ * @arg ADC_IT_JEOC: End of injected conversion interrupt \r
+ * @arg ADC_IT_OVR: Overrun interrupt \r
+ * @retval None\r
+ */\r
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT)\r
+{\r
+ uint8_t itmask = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_IT(ADC_IT)); \r
+\r
+ /* Get the ADC IT index */\r
+ itmask = (uint8_t)(ADC_IT >> 8);\r
+\r
+ /* Clear the selected ADC interrupt pending bits */\r
+ ADCx->SR = ~(uint32_t)itmask;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_comp.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the comparators (COMP1 and COMP2) peripheral: \r
+ * - Comparators configuration\r
+ * - Window mode control\r
+ * - Internal Reference Voltage (VREFINT) output\r
+ *\r
+ * @verbatim\r
+ *\r
+ * ===================================================================\r
+ * How to use this driver\r
+ * ===================================================================\r
+ * \r
+ * The device integrates two analog comparators COMP1 and COMP2: \r
+ * - COMP1 is a fixed threshold (VREFINT) that shares the non inverting\r
+ * input with the ADC channels.\r
+ *\r
+ * - COMP2 is a rail-to-rail comparator whose the inverting input \r
+ * can be selected among: DAC_OUT1, DAC_OUT2, 1/4 VREFINT,\r
+ * 1/2 VERFINT, 3/4 VREFINT, VREFINT, PB3 and whose the output\r
+ * can be redirected to embedded timers: TIM2, TIM3, TIM4, TIM10\r
+ *\r
+ * - The two comparators COMP1 and COMP2 can be combined in window\r
+ * mode.\r
+ *\r
+ * @note\r
+ * 1- Comparator APB clock must be enabled to get write access\r
+ * to comparator register using\r
+ * RCC_APB1PeriphClockCmd(RCC_APB1Periph_COMP, ENABLE);\r
+ *\r
+ * 2- COMP1 comparator and ADC can't be used at the same time since\r
+ * they share the same ADC switch matrix (analog switches).\r
+ *\r
+ * 3- When an I/O is used as comparator input, the corresponding GPIO \r
+ * registers should be configured in analog mode.\r
+ *\r
+ * 4- Comparators outputs (CMP1OUT and CMP2OUT) are not mapped on\r
+ * GPIO pin. They are only internal.\r
+ * To get the comparator output level, use COMP_GetOutputLevel()\r
+ *\r
+ * 5- COMP1 and COMP2 outputs are internally connected to EXTI Line 21\r
+ * and EXTI Line 22 respectively.\r
+ * Interrupts can be used by configuring the EXTI Line using the \r
+ * EXTI peripheral driver.\r
+ *\r
+ * 6- After enabling the comparator (COMP1 or COMP2), user should wait\r
+ * for start-up time (tSTART) to get right output levels.\r
+ * Please refer to product datasheet for more information on tSTART. \r
+ *\r
+ * 7- Comparators cannot be used to exit the device from Sleep or Stop \r
+ * mode when the internal reference voltage is switched off using \r
+ * the PWR_UltraLowPowerCmd() function (ULP bit in the PWR_CR register).\r
+ *\r
+ * @endverbatim\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_comp.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup COMP \r
+ * @brief COMP driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup COMP_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup COMP_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Initialization and Configuration functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Deinitializes COMP peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void COMP_DeInit(void)\r
+{\r
+ COMP->CSR = ((uint32_t)0x00000000); /*!< Set COMP->CSR to reset value */\r
+}\r
+\r
+/**\r
+ * @brief Initializes the COMP2 peripheral according to the specified parameters\r
+ * in the COMP_InitStruct:\r
+ * - COMP_InvertingInput specify the inverting input of COMP2\r
+ * - COMP_OutputSelect connect the output of COMP2 to selected timer\r
+ * input (Input capture / Output Compare Reference Clear)\r
+ * - COMP_Speed configures COMP2 speed for optimum speed/consumption ratio\r
+ * @note This function configures only COMP2.\r
+ * @note COMP2 comparator is enabled as soon as the INSEL[2:0] bits are \r
+ * different from "000".\r
+ * @param COMP_InitStruct: pointer to an COMP_InitTypeDef structure that contains \r
+ * the configuration information for the specified COMP peripheral.\r
+ * @retval None\r
+ */\r
+void COMP_Init(COMP_InitTypeDef* COMP_InitStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_COMP_INVERTING_INPUT(COMP_InitStruct->COMP_InvertingInput));\r
+ assert_param(IS_COMP_OUTPUT(COMP_InitStruct->COMP_OutputSelect));\r
+ assert_param(IS_COMP_SPEED(COMP_InitStruct->COMP_Speed));\r
+\r
+ /*!< Get the COMP CSR value */\r
+ tmpreg = COMP->CSR;\r
+\r
+ /*!< Clear the INSEL[2:0], OUTSEL[1:0] and SPEED bits */ \r
+ tmpreg &= (uint32_t) (~(uint32_t) (COMP_CSR_OUTSEL | COMP_CSR_INSEL | COMP_CSR_SPEED));\r
+ \r
+ /*!< Configure COMP: speed, inversion input selection and output redirection */\r
+ /*!< Set SPEED bit according to COMP_InitStruct->COMP_Speed value */\r
+ /*!< Set INSEL bits according to COMP_InitStruct->COMP_InvertingInput value */ \r
+ /*!< Set OUTSEL bits according to COMP_InitStruct->COMP_OutputSelect value */ \r
+ tmpreg |= (uint32_t)((COMP_InitStruct->COMP_Speed | COMP_InitStruct->COMP_InvertingInput \r
+ | COMP_InitStruct->COMP_OutputSelect));\r
+\r
+ /*!< The COMP2 comparator is enabled as soon as the INSEL[2:0] bits value are \r
+ different from "000" */\r
+ /*!< Write to COMP_CSR register */\r
+ COMP->CSR = tmpreg; \r
+}\r
+\r
+/**\r
+ * @brief Enable or disable the COMP1 peripheral.\r
+ * After enabling COMP1, the following functions should be called to \r
+ * connect the selected GPIO input to COMP1 non inverting input:\r
+ * - Enable switch control mode using SYSCFG_RISwitchControlModeCmd()\r
+ * - Close VCOMP switch using SYSCFG_RIIOSwitchConfig()\r
+ * - Close the I/O switch number n corresponding to the I/O \r
+ * using SYSCFG_RIIOSwitchConfig()\r
+ * @param NewState: new state of the COMP1 peripheral.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note This function enables/disables only the COMP1.\r
+ * @retval None\r
+ */\r
+void COMP_Cmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameter */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the COMP1 */\r
+ COMP->CSR |= (uint32_t) COMP_CSR_CMP1EN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the COMP1 */\r
+ COMP->CSR &= (uint32_t)(~COMP_CSR_CMP1EN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Return the output level (high or low) of the selected comparator:\r
+ * - Comparator output is low when the non-inverting input is at a lower\r
+ * voltage than the inverting input\r
+ * - Comparator output is high when the non-inverting input is at a higher\r
+ * voltage than the inverting input\r
+ * @note Comparators outputs aren't available on GPIO (outputs levels are \r
+ * only internal). The COMP1 and COMP2 outputs are connected internally \r
+ * to the EXTI Line 21 and Line 22 respectively. \r
+ * @param COMP_Selection: the selected comparator. \r
+ * This parameter can be one of the following values:\r
+ * @arg COMP_Selection_COMP1: COMP1 selected\r
+ * @arg COMP_Selection_COMP2: COMP2 selected \r
+ * @retval Returns the selected comparator output level.\r
+ */\r
+uint8_t COMP_GetOutputLevel(uint32_t COMP_Selection)\r
+{\r
+ uint8_t compout = 0x0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));\r
+\r
+ /* Check if Comparator 1 is selected */\r
+ if(COMP_Selection == COMP_Selection_COMP1)\r
+ {\r
+ /* Check if comparator 1 output level is high */\r
+ if((COMP->CSR & COMP_CSR_CMP1OUT) != (uint8_t) RESET)\r
+ {\r
+ /* Get Comparator 1 output level */\r
+ compout = (uint8_t) COMP_OutputLevel_High;\r
+ }\r
+ /* comparator 1 output level is low */\r
+ else\r
+ {\r
+ /* Get Comparator 1 output level */\r
+ compout = (uint8_t) COMP_OutputLevel_Low;\r
+ }\r
+ }\r
+ /* Comparator 2 is selected */\r
+ else\r
+ {\r
+ /* Check if comparator 2 output level is high */\r
+ if((COMP->CSR & COMP_CSR_CMP2OUT) != (uint8_t) RESET)\r
+ {\r
+ /* Get Comparator output level */\r
+ compout = (uint8_t) COMP_OutputLevel_High;\r
+ }\r
+ /* comparator 2 output level is low */\r
+ else\r
+ {\r
+ /* Get Comparator 2 output level */\r
+ compout = (uint8_t) COMP_OutputLevel_Low;\r
+ }\r
+ }\r
+ /* Return the comparator output level */\r
+ return (uint8_t)(compout);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup COMP_Group2 Window mode control function\r
+ * @brief Window mode control function \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Window mode control function\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the window mode.\r
+ * In window mode:\r
+ * - COMP1 inverting input is fixed to VREFINT defining the first\r
+ * threshold\r
+ * - COMP2 inverting input is configurable (DAC_OUT1, DAC_OUT2, VREFINT\r
+ * sub-multiples, PB3) defining the second threshold\r
+ * - COMP1 and COMP2 non inverting inputs are connected together.\r
+ * @note In window mode, only the Group 6 (PB4 or PB5) can be used as\r
+ * non-inverting inputs.\r
+ * param NewState: new state of the window mode. \r
+ * This parameter can be ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void COMP_WindowCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the window mode */\r
+ COMP->CSR |= (uint32_t) COMP_CSR_WNDWE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the window mode */\r
+ COMP->CSR &= (uint32_t)(~COMP_CSR_WNDWE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup COMP_Group3 Internal Reference Voltage output function\r
+ * @brief Internal Reference Voltage (VREFINT) output function \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Internal Reference Voltage (VREFINT) output function\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the output of internal reference voltage (VREFINT).\r
+ * The VREFINT output can be routed to any I/O in group 3: CH8 (PB0) or\r
+ * CH9 (PB1).\r
+ * To correctly use this function, the SYSCFG_RIIOSwitchConfig() function\r
+ * should be called after.\r
+ * @param NewState: new state of the Vrefint output.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void COMP_VrefintOutputCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the output of internal reference voltage */\r
+ COMP->CSR |= (uint32_t) COMP_CSR_VREFOUTEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the output of internal reference voltage */\r
+ COMP->CSR &= (uint32_t) (~COMP_CSR_VREFOUTEN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_crc.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides all the CRC firmware functions.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_crc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CRC \r
+ * @brief CRC driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup CRC_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Resets the CRC Data register (DR).\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void CRC_ResetDR(void)\r
+{\r
+ /* Reset CRC generator */\r
+ CRC->CR = CRC_CR_RESET;\r
+}\r
+\r
+/**\r
+ * @brief Computes the 32-bit CRC of a given data word(32-bit).\r
+ * @param Data: data word(32-bit) to compute its CRC\r
+ * @retval 32-bit CRC\r
+ */\r
+uint32_t CRC_CalcCRC(uint32_t Data)\r
+{\r
+ CRC->DR = Data;\r
+ \r
+ return (CRC->DR);\r
+}\r
+\r
+/**\r
+ * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).\r
+ * @param pBuffer: pointer to the buffer containing the data to be computed\r
+ * @param BufferLength: length of the buffer to be computed \r
+ * @retval 32-bit CRC\r
+ */\r
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)\r
+{\r
+ uint32_t index = 0;\r
+ \r
+ for(index = 0; index < BufferLength; index++)\r
+ {\r
+ CRC->DR = pBuffer[index];\r
+ }\r
+ return (CRC->DR);\r
+}\r
+\r
+/**\r
+ * @brief Returns the current CRC value.\r
+ * @param None\r
+ * @retval 32-bit CRC\r
+ */\r
+uint32_t CRC_GetCRC(void)\r
+{\r
+ return (CRC->DR);\r
+}\r
+\r
+/**\r
+ * @brief Stores a 8-bit data in the Independent Data(ID) register.\r
+ * @param IDValue: 8-bit value to be stored in the ID register \r
+ * @retval None\r
+ */\r
+void CRC_SetIDRegister(uint8_t IDValue)\r
+{\r
+ CRC->IDR = IDValue;\r
+}\r
+\r
+/**\r
+ * @brief Returns the 8-bit data stored in the Independent Data(ID) register\r
+ * @param None\r
+ * @retval 8-bit value of the ID register \r
+ */\r
+uint8_t CRC_GetIDRegister(void)\r
+{\r
+ return (CRC->IDR);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_dac.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Digital-to-Analog Converter (DAC) peripheral: \r
+ * - DAC channels configuration: trigger, output buffer, data format\r
+ * - DMA management \r
+ * - Interrupts and flags management\r
+ *\r
+ * @verbatim\r
+ * \r
+ * ===================================================================\r
+ * DAC Peripheral features\r
+ * ===================================================================\r
+ * The device integrates two 12-bit Digital Analog Converters that can \r
+ * be used independently or simultaneously (dual mode):\r
+ * 1- DAC channel1 with DAC_OUT1 (PA4) as output\r
+ * 1- DAC channel2 with DAC_OUT2 (PA5) as output\r
+ *\r
+ * Digital to Analog conversion can be non-triggered using DAC_Trigger_None\r
+ * and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register using \r
+ * DAC_SetChannel1Data()/DAC_SetChannel2Data.\r
+ * \r
+ * Digital to Analog conversion can be triggered by:\r
+ * 1- External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.\r
+ * The used pin (GPIOx_Pin9) must be configured in input mode.\r
+ *\r
+ * 2- Timers TRGO: TIM2, TIM4, TIM6, TIM7 and TIM9 \r
+ * (DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...)\r
+ * The timer TRGO event should be selected using TIM_SelectOutputTrigger()\r
+ *\r
+ * 3- Software using DAC_Trigger_Software\r
+ *\r
+ * Each DAC channel integrates an output buffer that can be used to \r
+ * reduce the output impedance, and to drive external loads directly\r
+ * without having to add an external operational amplifier.\r
+ * To enable, the output buffer use \r
+ * DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;\r
+ * \r
+ * Refer to the device datasheet for more details about output impedance\r
+ * value with and without output buffer.\r
+ *\r
+ * Both DAC channels can be used to generate\r
+ * 1- Noise wave using DAC_WaveGeneration_Noise\r
+ * 2- Triangle wave using DAC_WaveGeneration_Triangle\r
+ * \r
+ * Wave generation can be disabled using DAC_WaveGeneration_None\r
+ *\r
+ * The DAC data format can be:\r
+ * 1- 8-bit right alignment using DAC_Align_8b_R\r
+ * 2- 12-bit left alignment using DAC_Align_12b_L\r
+ * 3- 12-bit right alignment using DAC_Align_12b_R\r
+ *\r
+ * The analog output voltage on each DAC channel pin is determined\r
+ * by the following equation: DAC_OUTx = VREF+ * DOR / 4095\r
+ * with DOR is the Data Output Register\r
+ * VEF+ is the input voltage reference (refer to the device datasheet)\r
+ * e.g. To set DAC_OUT1 to 0.7V, use\r
+ * DAC_SetChannel1Data(DAC_Align_12b_R, 868);\r
+ * Assuming that VREF+ = 3.3, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V\r
+ *\r
+ * A DMA1 request can be generated when an external trigger (but not\r
+ * a software trigger) occurs if DMA1 requests are enabled using\r
+ * DAC_DMACmd()\r
+ * DMA1 requests are mapped as following:\r
+ * 1- DAC channel1 is mapped on DMA1 channel3 which must be already \r
+ * configured\r
+ * 2- DAC channel2 is mapped on DMA1 channel4 which must be already \r
+ * configured\r
+ *\r
+ * =================================================================== \r
+ * How to use this driver \r
+ * =================================================================== \r
+ * - DAC APB clock must be enabled to get write access to DAC\r
+ * registers using\r
+ * RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE)\r
+ * - Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.\r
+ * - Configure the DAC channel using DAC_Init()\r
+ * - Enable the DAC channel using DAC_Cmd()\r
+ * \r
+ * @endverbatim\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_dac.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DAC \r
+ * @brief DAC driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* CR register Mask */\r
+#define CR_CLEAR_MASK ((uint32_t)0x00000FFE)\r
+\r
+/* DAC Dual Channels SWTRIG masks */\r
+#define DUAL_SWTRIG_SET ((uint32_t)0x00000003)\r
+#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC)\r
+\r
+/* DHR registers offsets */\r
+#define DHR12R1_OFFSET ((uint32_t)0x00000008)\r
+#define DHR12R2_OFFSET ((uint32_t)0x00000014)\r
+#define DHR12RD_OFFSET ((uint32_t)0x00000020)\r
+\r
+/* DOR register offset */\r
+#define DOR_OFFSET ((uint32_t)0x0000002C)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup DAC_Private_Functions\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup DAC_Group1 DAC channels configuration\r
+ * @brief DAC channels configuration: trigger, output buffer, data format \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ DAC channels configuration: trigger, output buffer, data format\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the DAC peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void DAC_DeInit(void)\r
+{\r
+ /* Enable DAC reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);\r
+ /* Release DAC from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DAC peripheral according to the specified \r
+ * parameters in the DAC_InitStruct.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that\r
+ * contains the configuration information for the specified DAC channel.\r
+ * DAC_Trigger selects the trigger source: EXTI Line 9, TIM2, TIM4....\r
+ * DAC_WaveGeneration selects the waveform to be generated: noise, triangle\r
+ * DAC_LFSRUnmask_TriangleAmplitude \r
+ * defines the LFSR when noise waveform is selected by DAC_WaveGeneration\r
+ * or defines the amplitude of the triangle waveform when it is \r
+ * selected by DAC_WaveGeneration\r
+ * DAC_OutputBuffer enables/disables the output buffer on DAC_OUTx\r
+ * @retval None\r
+ */\r
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)\r
+{\r
+ uint32_t tmpreg1 = 0, tmpreg2 = 0;\r
+\r
+ /* Check the DAC parameters */\r
+ assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));\r
+ assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));\r
+ assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));\r
+ assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));\r
+\r
+/*---------------------------- DAC CR Configuration --------------------------*/\r
+ /* Get the DAC CR value */\r
+ tmpreg1 = DAC->CR;\r
+ /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */\r
+ tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);\r
+ /* Configure for the selected DAC channel: buffer output, trigger, wave generation,\r
+ mask/amplitude for wave generation */\r
+ /* Set TSELx and TENx bits according to DAC_Trigger value */\r
+ /* Set WAVEx bits according to DAC_WaveGeneration value */\r
+ /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ \r
+ /* Set BOFFx bit according to DAC_OutputBuffer value */ \r
+ tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |\r
+ DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);\r
+ /* Calculate CR register value depending on DAC_Channel */\r
+ tmpreg1 |= tmpreg2 << DAC_Channel;\r
+ /* Write to DAC CR */\r
+ DAC->CR = tmpreg1;\r
+}\r
+\r
+/**\r
+ * @brief Fills each DAC_InitStruct member with its default value.\r
+ * @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will \r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)\r
+{\r
+/*--------------- Reset DAC init structure parameters values -----------------*/\r
+ /* Initialize the DAC_Trigger member */\r
+ DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;\r
+ /* Initialize the DAC_WaveGeneration member */\r
+ DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;\r
+ /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */\r
+ DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;\r
+ /* Initialize the DAC_OutputBuffer member */\r
+ DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified DAC channel.\r
+ * @param DAC_Channel: The selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param NewState: new state of the DAC channel. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note When the DAC channel is enabled the trigger source can no more\r
+ * be modified.\r
+ * @retval None\r
+ */\r
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DAC channel */\r
+ DAC->CR |= (DAC_CR_EN1 << DAC_Channel);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DAC channel */\r
+ DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the selected DAC channel software trigger.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param NewState: new state of the selected DAC channel software trigger.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable software trigger for the selected DAC channel */\r
+ DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);\r
+ }\r
+ else\r
+ {\r
+ /* Disable software trigger for the selected DAC channel */\r
+ DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables simultaneously the two DAC channels software\r
+ * triggers.\r
+ * @param NewState: new state of the DAC channels software triggers.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable software trigger for both DAC channels */\r
+ DAC->SWTRIGR |= DUAL_SWTRIG_SET;\r
+ }\r
+ else\r
+ {\r
+ /* Disable software trigger for both DAC channels */\r
+ DAC->SWTRIGR &= DUAL_SWTRIG_RESET;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the selected DAC channel wave generation.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_Wave: Specifies the wave type to enable or disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Wave_Noise: noise wave generation\r
+ * @arg DAC_Wave_Triangle: triangle wave generation\r
+ * @param NewState: new state of the selected DAC channel wave generation.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note \r
+ * @retval None\r
+ */\r
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_DAC_WAVE(DAC_Wave)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected wave generation for the selected DAC channel */\r
+ DAC->CR |= DAC_Wave << DAC_Channel;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected wave generation for the selected DAC channel */\r
+ DAC->CR &= ~(DAC_Wave << DAC_Channel);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Set the specified data holding register value for DAC channel1.\r
+ * @param DAC_Align: Specifies the data alignment for DAC channel1.\r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Align_8b_R: 8bit right data alignment selected\r
+ * @arg DAC_Align_12b_L: 12bit left data alignment selected\r
+ * @arg DAC_Align_12b_R: 12bit right data alignment selected\r
+ * @param Data : Data to be loaded in the selected data holding register.\r
+ * @retval None\r
+ */\r
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)\r
+{ \r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_ALIGN(DAC_Align));\r
+ assert_param(IS_DAC_DATA(Data));\r
+ \r
+ tmp = (uint32_t)DAC_BASE; \r
+ tmp += DHR12R1_OFFSET + DAC_Align;\r
+\r
+ /* Set the DAC channel1 selected data holding register */\r
+ *(__IO uint32_t *) tmp = Data;\r
+}\r
+\r
+/**\r
+ * @brief Set the specified data holding register value for DAC channel2.\r
+ * @param DAC_Align: Specifies the data alignment for DAC channel2.\r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Align_8b_R: 8bit right data alignment selected\r
+ * @arg DAC_Align_12b_L: 12bit left data alignment selected\r
+ * @arg DAC_Align_12b_R: 12bit right data alignment selected\r
+ * @param Data : Data to be loaded in the selected data holding register.\r
+ * @retval None\r
+ */\r
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_ALIGN(DAC_Align));\r
+ assert_param(IS_DAC_DATA(Data));\r
+ \r
+ tmp = (uint32_t)DAC_BASE;\r
+ tmp += DHR12R2_OFFSET + DAC_Align;\r
+\r
+ /* Set the DAC channel2 selected data holding register */\r
+ *(__IO uint32_t *)tmp = Data;\r
+}\r
+\r
+/**\r
+ * @brief Set the specified data holding register value for dual channel DAC.\r
+ * @param DAC_Align: Specifies the data alignment for dual channel DAC.\r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Align_8b_R: 8bit right data alignment selected\r
+ * @arg DAC_Align_12b_L: 12bit left data alignment selected\r
+ * @arg DAC_Align_12b_R: 12bit right data alignment selected\r
+ * @param Data2: Data for DAC Channel2 to be loaded in the selected data \r
+ * holding register.\r
+ * @param Data1: Data for DAC Channel1 to be loaded in the selected data \r
+ * holding register.\r
+ * @note In dual mode, a unique register access is required to write in both\r
+ * DAC channels at the same time.\r
+ * @retval None\r
+ */\r
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)\r
+{\r
+ uint32_t data = 0, tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_ALIGN(DAC_Align));\r
+ assert_param(IS_DAC_DATA(Data1));\r
+ assert_param(IS_DAC_DATA(Data2));\r
+ \r
+ /* Calculate and set dual DAC data holding register value */\r
+ if (DAC_Align == DAC_Align_8b_R)\r
+ {\r
+ data = ((uint32_t)Data2 << 8) | Data1; \r
+ }\r
+ else\r
+ {\r
+ data = ((uint32_t)Data2 << 16) | Data1;\r
+ }\r
+ \r
+ tmp = (uint32_t)DAC_BASE;\r
+ tmp += DHR12RD_OFFSET + DAC_Align;\r
+\r
+ /* Set the dual DAC selected data holding register */\r
+ *(__IO uint32_t *)tmp = data;\r
+}\r
+\r
+/**\r
+ * @brief Returns the last data output value of the selected DAC channel.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @retval The selected DAC channel data output value.\r
+ */\r
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ \r
+ tmp = (uint32_t) DAC_BASE ;\r
+ tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);\r
+ \r
+ /* Returns the DAC channel data output register value */\r
+ return (uint16_t) (*(__IO uint32_t*) tmp);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Group2 DMA management functions\r
+ * @brief DMA management functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ DMA management functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified DAC channel DMA request.\r
+ * When enabled DMA1 is generated when an external trigger (EXTI Line9,\r
+ * TIM2, TIM4, TIM6, TIM7 or TIM9 but not a software trigger) occurs\r
+ * @param DAC_Channel: the selected DAC channel.\r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param NewState: new state of the selected DAC channel DMA request.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * The DAC channel1 (channel2) is mapped on DMA1 channel3 (channel4) which \r
+ * must be already configured. \r
+ * @retval None\r
+ */\r
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DAC channel DMA request */\r
+ DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DAC channel DMA request */\r
+ DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel));\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Group3 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Interrupts and flags management functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified DAC interrupts.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. \r
+ * This parameter can be the following values:\r
+ * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask\r
+ * @note The DMA underrun occurs when a second external trigger arrives before\r
+ * the acknowledgement for the first external trigger is received (first request).\r
+ * @param NewState: new state of the specified DAC interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */ \r
+void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) \r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_DAC_IT(DAC_IT)); \r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DAC interrupts */\r
+ DAC->CR |= (DAC_IT << DAC_Channel);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DAC interrupts */\r
+ DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified DAC flag is set or not.\r
+ * @param DAC_Channel: thee selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_FLAG: specifies the flag to check. \r
+ * This parameter can be only of the following value:\r
+ * @arg DAC_FLAG_DMAUDR: DMA underrun flag\r
+ * @note The DMA underrun occurs when a second external trigger arrives before\r
+ * the acknowledgement for the first external trigger is received (first request).\r
+ * @retval The new state of DAC_FLAG (SET or RESET).\r
+ */\r
+FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_DAC_FLAG(DAC_FLAG));\r
+\r
+ /* Check the status of the specified DAC flag */\r
+ if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)\r
+ {\r
+ /* DAC_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* DAC_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the DAC_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the DAC channel's pending flags.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_FLAG: specifies the flag to clear. \r
+ * This parameter can be of the following value:\r
+ * @arg DAC_FLAG_DMAUDR: DMA underrun flag \r
+ * @retval None\r
+ */\r
+void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_DAC_FLAG(DAC_FLAG));\r
+\r
+ /* Clear the selected DAC flags */\r
+ DAC->SR = (DAC_FLAG << DAC_Channel);\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified DAC interrupt has occurred or not.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_IT: specifies the DAC interrupt source to check. \r
+ * This parameter can be the following values:\r
+ * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask\r
+ * @note The DMA underrun occurs when a second external trigger arrives before\r
+ * the acknowledgement for the first external trigger is received (first request).\r
+ * @retval The new state of DAC_IT (SET or RESET).\r
+ */\r
+ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t enablestatus = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_DAC_IT(DAC_IT));\r
+\r
+ /* Get the DAC_IT enable bit status */\r
+ enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;\r
+ \r
+ /* Check the status of the specified DAC interrupt */\r
+ if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)\r
+ {\r
+ /* DAC_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* DAC_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the DAC_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the DAC channel\92s interrupt pending bits.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_IT: specifies the DAC interrupt pending bit to clear.\r
+ * This parameter can be the following values:\r
+ * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask \r
+ * @retval None\r
+ */\r
+void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_DAC_IT(DAC_IT)); \r
+\r
+ /* Clear the selected DAC interrupt pending bits */\r
+ DAC->SR = (DAC_IT << DAC_Channel);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_dbgmcu.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides all the DBGMCU firmware functions.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_dbgmcu.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DBGMCU \r
+ * @brief DBGMCU driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup DBGMCU_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Returns the device revision identifier.\r
+ * @param None\r
+ * @retval Device revision identifier\r
+ */\r
+uint32_t DBGMCU_GetREVID(void)\r
+{\r
+ return(DBGMCU->IDCODE >> 16);\r
+}\r
+\r
+/**\r
+ * @brief Returns the device identifier.\r
+ * @param None\r
+ * @retval Device identifier\r
+ */\r
+uint32_t DBGMCU_GetDEVID(void)\r
+{\r
+ return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);\r
+}\r
+\r
+/**\r
+ * @brief Configures low power mode behavior when the MCU is in Debug mode.\r
+ * @param DBGMCU_Periph: specifies the low power mode.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode \r
+ * @arg DBGMCU_STOP: Keep debugger connection during STOP mode \r
+ * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode \r
+ * @param NewState: new state of the specified low power mode in Debug mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ DBGMCU->CR |= DBGMCU_Periph;\r
+ }\r
+ else\r
+ {\r
+ DBGMCU->CR &= ~DBGMCU_Periph;\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configures APB1 peripheral behavior when the MCU is in Debug mode.\r
+ * @param DBGMCU_Periph: specifies the APB1 peripheral.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted \r
+ * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted \r
+ * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted\r
+ * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted\r
+ * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted\r
+ * @arg DBGMCU_RTC_STOP: RTC Wakeup counter stopped when Core is halted \r
+ * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted\r
+ * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted\r
+ * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is \r
+ * halted\r
+ * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is \r
+ * halted \r
+ * @param NewState: new state of the specified APB1 peripheral in Debug mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ DBGMCU->APB1FZ |= DBGMCU_Periph;\r
+ }\r
+ else\r
+ {\r
+ DBGMCU->APB1FZ &= ~DBGMCU_Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures APB2 peripheral behavior when the MCU is in Debug mode.\r
+ * @param DBGMCU_Periph: specifies the APB2 peripheral.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted \r
+ * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted \r
+ * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted \r
+ * @param NewState: new state of the specified APB2 peripheral in Debug mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ DBGMCU->APB2FZ |= DBGMCU_Periph;\r
+ }\r
+ else\r
+ {\r
+ DBGMCU->APB2FZ &= ~DBGMCU_Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_dma.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Direct Memory Access controller (DMA): \r
+ * - Initialization and Configuration\r
+ * - Data Counter\r
+ * - Interrupts and flags management\r
+ * \r
+ * @verbatim\r
+ * \r
+ * =================================================================== \r
+ * How to use this driver\r
+ * =================================================================== \r
+ * 1. Enable The DMA controller clock using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE)\r
+ * function for DMA1 or using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA2, ENABLE)\r
+ * function for DMA2.\r
+ *\r
+ * 2. Enable and configure the peripheral to be connected to the DMA channel\r
+ * (except for internal SRAM / FLASH memories: no initialization is \r
+ * necessary). \r
+ * \r
+ * 3. For a given Channel, program the Source and Destination addresses, \r
+ * the transfer Direction, the Buffer Size, the Peripheral and Memory\r
+ * Incrementation mode and Data Size, the Circular or Normal mode, \r
+ * the channel transfer Priority and the Memory-to-Memory transfer \r
+ * mode (if needed) using the DMA_Init() function.\r
+ *\r
+ * 4. Enable the NVIC and the corresponding interrupt(s) using the function \r
+ * DMA_ITConfig() if you need to use DMA interrupts. \r
+ *\r
+ * 5. Enable the DMA channel using the DMA_Cmd() function. \r
+ * \r
+ * 6. Activate the needed channel Request using PPP_DMACmd() function for\r
+ * any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...)\r
+ * The function allowing this operation is provided in each PPP peripheral\r
+ * driver (ie. SPI_DMACmd for SPI peripheral). \r
+ *\r
+ * 7. Optionally, you can configure the number of data to be transferred\r
+ * when the channel is disabled (ie. after each Transfer Complete event\r
+ * or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter().\r
+ * And you can get the number of remaining data to be transferred using \r
+ * the function DMA_GetCurrDataCounter() at run time (when the DMA channel is\r
+ * enabled and running). \r
+ * \r
+ * 8. To control DMA events you can use one of the following \r
+ * two methods:\r
+ * a- Check on DMA channel flags using the function DMA_GetFlagStatus(). \r
+ * b- Use DMA interrupts through the function DMA_ITConfig() at initialization\r
+ * phase and DMA_GetITStatus() function into interrupt routines in\r
+ * communication phase. \r
+ * After checking on a flag you should clear it using DMA_ClearFlag()\r
+ * function. And after checking on an interrupt event you should \r
+ * clear it using DMA_ClearITPendingBit() function. \r
+ * \r
+ * @endverbatim\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_dma.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMA \r
+ * @brief DMA driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+\r
+/* DMA1 Channelx interrupt pending bit masks */\r
+#define DMA1_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))\r
+#define DMA1_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))\r
+#define DMA1_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))\r
+#define DMA1_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))\r
+#define DMA1_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))\r
+#define DMA1_CHANNEL6_IT_MASK ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))\r
+#define DMA1_CHANNEL7_IT_MASK ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))\r
+\r
+/* DMA FLAG mask */\r
+#define FLAG_MASK ((uint32_t)0x10000000)\r
+\r
+/* DMA registers Masks */\r
+#define CCR_CLEAR_MASK ((uint32_t)0xFFFF800F)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+\r
+/** @defgroup DMA_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMA_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Initialization and Configuration functions\r
+ =============================================================================== \r
+\r
+ This subsection provides functions allowing to initialize the DMA channel source\r
+ and destination addresses, incrementation and data sizes, transfer direction, \r
+ buffer size, circular/normal mode selection, memory-to-memory mode selection \r
+ and channel priority value.\r
+ \r
+ The DMA_Init() function follows the DMA configuration procedures as described in\r
+ reference manual (RM0038).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Deinitializes the DMAy Channelx registers to their default reset\r
+ * values.\r
+ * @param DMAy_Channelx: where y can be 1 to select the DMA and\r
+ * x can be 1 to 7 for DMA1 to select the DMA Channel.\r
+ * @retval None\r
+ */\r
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
+\r
+ /* Disable the selected DMAy Channelx */\r
+ DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);\r
+\r
+ /* Reset DMAy Channelx control register */\r
+ DMAy_Channelx->CCR = 0;\r
+ \r
+ /* Reset DMAy Channelx remaining bytes register */\r
+ DMAy_Channelx->CNDTR = 0;\r
+ \r
+ /* Reset DMAy Channelx peripheral address register */\r
+ DMAy_Channelx->CPAR = 0;\r
+ \r
+ /* Reset DMAy Channelx memory address register */\r
+ DMAy_Channelx->CMAR = 0;\r
+ \r
+ if (DMAy_Channelx == DMA1_Channel1)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel1 */\r
+ DMA1->IFCR |= DMA1_CHANNEL1_IT_MASK;\r
+ }\r
+ else if (DMAy_Channelx == DMA1_Channel2)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel2 */\r
+ DMA1->IFCR |= DMA1_CHANNEL2_IT_MASK;\r
+ }\r
+ else if (DMAy_Channelx == DMA1_Channel3)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel3 */\r
+ DMA1->IFCR |= DMA1_CHANNEL3_IT_MASK;\r
+ }\r
+ else if (DMAy_Channelx == DMA1_Channel4)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel4 */\r
+ DMA1->IFCR |= DMA1_CHANNEL4_IT_MASK;\r
+ }\r
+ else if (DMAy_Channelx == DMA1_Channel5)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel5 */\r
+ DMA1->IFCR |= DMA1_CHANNEL5_IT_MASK;\r
+ }\r
+ else if (DMAy_Channelx == DMA1_Channel6)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel6 */\r
+ DMA1->IFCR |= DMA1_CHANNEL6_IT_MASK;\r
+ }\r
+ else\r
+ {\r
+ if (DMAy_Channelx == DMA1_Channel7)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel7 */\r
+ DMA1->IFCR |= DMA1_CHANNEL7_IT_MASK; \r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DMAy Channelx according to the specified\r
+ * parameters in the DMA_InitStruct.\r
+ * @param DMAy_Channelx: where y can be 1 to select the DMA and\r
+ * x can be 1 to 7 for DMA1 to select the DMA Channel.\r
+ * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that\r
+ * contains the configuration information for the specified DMA Channel.\r
+ * @retval None\r
+ */\r
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
+ assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));\r
+ assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));\r
+ assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));\r
+ assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); \r
+ assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));\r
+ assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));\r
+ assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));\r
+ assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));\r
+ assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));\r
+\r
+/*--------------------------- DMAy Channelx CCR Configuration -----------------*/\r
+ /* Get the DMAy_Channelx CCR value */\r
+ tmpreg = DMAy_Channelx->CCR;\r
+ /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */\r
+ tmpreg &= CCR_CLEAR_MASK;\r
+ /* Configure DMAy Channelx: data transfer, data size, priority level and mode */\r
+ /* Set DIR bit according to DMA_DIR value */\r
+ /* Set CIRC bit according to DMA_Mode value */\r
+ /* Set PINC bit according to DMA_PeripheralInc value */\r
+ /* Set MINC bit according to DMA_MemoryInc value */\r
+ /* Set PSIZE bits according to DMA_PeripheralDataSize value */\r
+ /* Set MSIZE bits according to DMA_MemoryDataSize value */\r
+ /* Set PL bits according to DMA_Priority value */\r
+ /* Set the MEM2MEM bit according to DMA_M2M value */\r
+ tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |\r
+ DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |\r
+ DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |\r
+ DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;\r
+\r
+ /* Write to DMAy Channelx CCR */\r
+ DMAy_Channelx->CCR = tmpreg;\r
+\r
+/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/\r
+ /* Write to DMAy Channelx CNDTR */\r
+ DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;\r
+\r
+/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/\r
+ /* Write to DMAy Channelx CPAR */\r
+ DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;\r
+\r
+/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/\r
+ /* Write to DMAy Channelx CMAR */\r
+ DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;\r
+}\r
+\r
+/**\r
+ * @brief Fills each DMA_InitStruct member with its default value.\r
+ * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will\r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)\r
+{\r
+/*-------------- Reset DMA init structure parameters values ------------------*/\r
+ /* Initialize the DMA_PeripheralBaseAddr member */\r
+ DMA_InitStruct->DMA_PeripheralBaseAddr = 0;\r
+ /* Initialize the DMA_MemoryBaseAddr member */\r
+ DMA_InitStruct->DMA_MemoryBaseAddr = 0;\r
+ /* Initialize the DMA_DIR member */\r
+ DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;\r
+ /* Initialize the DMA_BufferSize member */\r
+ DMA_InitStruct->DMA_BufferSize = 0;\r
+ /* Initialize the DMA_PeripheralInc member */\r
+ DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;\r
+ /* Initialize the DMA_MemoryInc member */\r
+ DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;\r
+ /* Initialize the DMA_PeripheralDataSize member */\r
+ DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;\r
+ /* Initialize the DMA_MemoryDataSize member */\r
+ DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;\r
+ /* Initialize the DMA_Mode member */\r
+ DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;\r
+ /* Initialize the DMA_Priority member */\r
+ DMA_InitStruct->DMA_Priority = DMA_Priority_Low;\r
+ /* Initialize the DMA_M2M member */\r
+ DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified DMAy Channelx.\r
+ * @param DMAy_Channelx: where y can be 1 to select the DMA and\r
+ * x can be 1 to 7 for DMA1 to select the DMA Channel.\r
+ * @param NewState: new state of the DMAy Channelx. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DMAy Channelx */\r
+ DMAy_Channelx->CCR |= DMA_CCR1_EN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DMAy Channelx */\r
+ DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Group2 Data Counter functions\r
+ * @brief Data Counter functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Data Counter functions\r
+ =============================================================================== \r
+\r
+ This subsection provides function allowing to configure and read the buffer size\r
+ (number of data to be transferred). \r
+\r
+ The DMA data counter can be written only when the DMA channel is disabled \r
+ (ie. after transfer complete event).\r
+\r
+ The following function can be used to write the Channel data counter value:\r
+ - void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);\r
+\r
+@note It is advised to use this function rather than DMA_Init() in situations where\r
+ only the Data buffer needs to be reloaded.\r
+\r
+ The DMA data counter can be read to indicate the number of remaining transfers for\r
+ the relative DMA channel. This counter is decremented at the end of each data \r
+ transfer and when the transfer is complete: \r
+ - If Normal mode is selected: the counter is set to 0.\r
+ - If Circular mode is selected: the counter is reloaded with the initial value\r
+ (configured before enabling the DMA channel)\r
+ \r
+ The following function can be used to read the Channel data counter value:\r
+ - uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sets the number of data units in the current DMAy Channelx transfer.\r
+ * @param DMAy_Channelx: where y can be 1 to select the DMA and\r
+ * x can be 1 to 7 for DMA1 to select the DMA Channel.\r
+ * @param DataNumber: The number of data units in the current DMAy Channelx\r
+ * transfer. \r
+ * @note This function can only be used when the DMAy_Channelx is disabled. \r
+ * @retval None.\r
+ */\r
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
+ \r
+/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/\r
+ /* Write to DMAy Channelx CNDTR */\r
+ DMAy_Channelx->CNDTR = DataNumber; \r
+}\r
+\r
+/**\r
+ * @brief Returns the number of remaining data units in the current\r
+ * DMAy Channelx transfer.\r
+ * @param DMAy_Channelx: where y can be 1 to select the DMA and\r
+ * x can be 1 to 7 for DMA1 to select the DMA Channel.\r
+ * @retval The number of remaining data units in the current DMAy Channelx\r
+ * transfer.\r
+ */\r
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
+ /* Return the number of remaining data units for DMAy Channelx */\r
+ return ((uint16_t)(DMAy_Channelx->CNDTR));\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Group3 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Interrupts and flags management functions\r
+ =============================================================================== \r
+\r
+ This subsection provides functions allowing to configure the DMA Interrupts \r
+ sources and check or clear the flags or pending bits status.\r
+ The user should identify which mode will be used in his application to manage the\r
+ DMA controller events: Polling mode or Interrupt mode. \r
+ \r
+ Polling Mode\r
+ =============\r
+ Each DMA channel can be managed through 4 event Flags:\r
+ (y : DMA Controller number \r
+ x : DMA channel number )\r
+ 1. DMAy_FLAG_TCx : to indicate that a Transfer Complete event occurred\r
+ 2. DMAy_FLAG_HTx : to indicate that a Half-Transfer Complete event occured\r
+ 3. DMAy_FLAG_TEx : to indicate that a Transfer Error occured.\r
+ 4. DMAy_FLAG_GLx : to indicate that at least one of the events described \r
+ above occured. \r
+\r
+@note Clearing DMAy_FLAG_GLx results in clearing all other pending flags of the \r
+ same channel (DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).\r
+\r
+ In this Mode it is advised to use the following functions:\r
+ - FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);\r
+ - void DMA_ClearFlag(uint32_t DMA_FLAG);\r
+\r
+ Interrupt Mode\r
+ ===============\r
+ Each DMA channel can be managed through 4 Interrupts:\r
+\r
+ Interrupt Source\r
+ ----------------\r
+ 1. DMA_IT_TC: specifies the interrupt source for the Transfer Complete event. \r
+ 2. DMA_IT_HT : specifies the interrupt source for the Half-transfer Complete event.\r
+ 3. DMA_IT_TE : specifies the interrupt source for the transfer errors event.\r
+ 4. DMA_IT_GL : to indicate that at least one of the interrupts described \r
+ above occurred. \r
+\r
+@note Clearing DMA_IT_GL interrupt results in clearing all other interrupts of the \r
+ same channel (DMA_IT_TCx, DMA_IT_HT and DMA_IT_TE).\r
+ \r
+ In this Mode it is advised to use the following functions:\r
+ - void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);\r
+ - ITStatus DMA_GetITStatus(uint32_t DMA_IT);\r
+ - void DMA_ClearITPendingBit(uint32_t DMA_IT);\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified DMAy Channelx interrupts.\r
+ * @param DMAy_Channelx: where y can be 1 to select the DMA and\r
+ * x can be 1 to 7 for DMA1 to select the DMA Channel.\r
+ * @param DMA_IT: specifies the DMA interrupts sources to be enabled\r
+ * or disabled. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg DMA_IT_TC: Transfer complete interrupt mask\r
+ * @arg DMA_IT_HT: Half transfer interrupt mask\r
+ * @arg DMA_IT_TE: Transfer error interrupt mask\r
+ * @param NewState: new state of the specified DMA interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
+ assert_param(IS_DMA_CONFIG_IT(DMA_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DMA interrupts */\r
+ DMAy_Channelx->CCR |= DMA_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DMA interrupts */\r
+ DMAy_Channelx->CCR &= ~DMA_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified DMAy Channelx flag is set or not.\r
+ * @param DMA_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.\r
+ * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.\r
+ * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.\r
+ * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.\r
+ * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.\r
+ * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.\r
+ * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.\r
+ * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.\r
+ * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.\r
+ * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.\r
+ * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.\r
+ * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.\r
+ * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.\r
+ * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.\r
+ * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.\r
+ * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.\r
+ * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.\r
+ * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.\r
+ * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.\r
+ * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.\r
+ * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.\r
+ * \r
+ * @note\r
+ * The Global flag (DMAy_FLAG_GLx) is set whenever any of the other flags \r
+ * relative to the same channel is set (Transfer Complete, Half-transfer \r
+ * Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or \r
+ * DMAy_FLAG_TEx). \r
+ * \r
+ * @retval The new state of DMA_FLAG (SET or RESET).\r
+ */\r
+FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_GET_FLAG(DMA_FLAG));\r
+\r
+ /* Calculate the used DMA */\r
+ if ((DMA_FLAG & FLAG_MASK) == (uint32_t)RESET)\r
+ {\r
+ /* Get DMA1 ISR register value */\r
+ tmpreg = DMA1->ISR ;\r
+ }\r
+\r
+ /* Check the status of the specified DMA flag */\r
+ if ((tmpreg & DMA_FLAG) != (uint32_t)RESET)\r
+ {\r
+ /* DMA_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* DMA_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ \r
+ /* Return the DMA_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the DMAy Channelx's pending flags.\r
+ * @param DMA_FLAG: specifies the flag to clear.\r
+ * This parameter can be any combination (for the same DMA) of the following values:\r
+ * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.\r
+ * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.\r
+ * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.\r
+ * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.\r
+ * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.\r
+ * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.\r
+ * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.\r
+ * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.\r
+ * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.\r
+ * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.\r
+ * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.\r
+ * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.\r
+ * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.\r
+ * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.\r
+ * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.\r
+ * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.\r
+ * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.\r
+ * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.\r
+ * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.\r
+ * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.\r
+ * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.\r
+ * \r
+ * @note\r
+ * Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags\r
+ * relative to the same channel (Transfer Complete, Half-transfer Complete and \r
+ * Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx). \r
+ * \r
+ * @retval None\r
+ */\r
+void DMA_ClearFlag(uint32_t DMA_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));\r
+\r
+ if ((DMA_FLAG & FLAG_MASK) == (uint32_t)RESET)\r
+ {\r
+ /* Clear the selected DMA flags */\r
+ DMA1->IFCR = DMA_FLAG;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.\r
+ * @param DMA_IT: specifies the DMA interrupt source to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.\r
+ * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.\r
+ * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.\r
+ * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.\r
+ * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.\r
+ * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.\r
+ * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.\r
+ * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.\r
+ * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.\r
+ * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.\r
+ * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.\r
+ * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.\r
+ * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.\r
+ * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.\r
+ * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.\r
+ * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.\r
+ * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.\r
+ * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.\r
+ * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.\r
+ * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.\r
+ * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.\r
+ * \r
+ * @note\r
+ * The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other \r
+ * interrupts relative to the same channel is set (Transfer Complete, \r
+ * Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx, \r
+ * DMAy_IT_HTx or DMAy_IT_TEx). \r
+ * \r
+ * @retval The new state of DMA_IT (SET or RESET).\r
+ */\r
+ITStatus DMA_GetITStatus(uint32_t DMA_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_GET_IT(DMA_IT));\r
+\r
+ /* Calculate the used DMA */\r
+ if ((DMA_IT & FLAG_MASK) == (uint32_t)RESET)\r
+ {\r
+ /* Get DMA1 ISR register value */\r
+ tmpreg = DMA1->ISR ;\r
+ }\r
+\r
+ /* Check the status of the specified DMA interrupt */\r
+ if ((tmpreg & DMA_IT) != (uint32_t)RESET)\r
+ {\r
+ /* DMA_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* DMA_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the DMA_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the DMAy Channelx\92s interrupt pending bits.\r
+ * @param DMA_IT: specifies the DMA interrupt pending bit to clear.\r
+ * This parameter can be any combination (for the same DMA) of the following values:\r
+ * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.\r
+ * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.\r
+ * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.\r
+ * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.\r
+ * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.\r
+ * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.\r
+ * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.\r
+ * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.\r
+ * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.\r
+ * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.\r
+ * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.\r
+ * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.\r
+ * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.\r
+ * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.\r
+ * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.\r
+ * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.\r
+ * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.\r
+ * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.\r
+ * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.\r
+ * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.\r
+ * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.\r
+ * \r
+ * @note\r
+ * Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other \r
+ * interrupts relative to the same channel (Transfer Complete, Half-transfer \r
+ * Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and \r
+ * DMAy_IT_TEx). \r
+ * \r
+ * @retval None\r
+ */\r
+void DMA_ClearITPendingBit(uint32_t DMA_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_CLEAR_IT(DMA_IT));\r
+\r
+ /* Calculate the used DMA */\r
+ if ((DMA_IT & FLAG_MASK) == (uint32_t)RESET)\r
+ {\r
+ /* Clear the selected DMA interrupt pending bits */\r
+ DMA1->IFCR = DMA_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_exti.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the EXTI peripheral: \r
+ * - Initialization and Configuration\r
+ * - Interrupts and flags management\r
+ *\r
+ * @verbatim \r
+ * \r
+ * ===================================================================\r
+ * EXTI features\r
+ * ===================================================================\r
+ * \r
+ * External interrupt/event lines are mapped as following:\r
+ * 1- All available GPIO pins are connected to the 16 external \r
+ * interrupt/event lines from EXTI0 to EXTI15.\r
+ * 2- EXTI line 16 is connected to the PVD output\r
+ * 3- EXTI line 17 is connected to the RTC Alarm event\r
+ * 4- EXTI line 18 is connected to the USB Device FS wakeup event\r
+ * 5- EXTI line 19 is connected to the RTC Tamper and TimeStamp events\r
+ * 6- EXTI line 20 is connected to the RTC Wakeup event\r
+ * 7- EXTI line 21 is connected to the Comparator 1 wakeup event \r
+ * 8- EXTI line 22 is connected to the Comparator 2 wakeup event\r
+ *\r
+ * ===================================================================\r
+ * How to use this driver\r
+ * =================================================================== \r
+ * \r
+ * In order to use an I/O pin as an external interrupt source, follow\r
+ * steps below:\r
+ * 1- Configure the I/O in input mode using GPIO_Init()\r
+ * 2- Select the input source pin for the EXTI line using \r
+ * SYSCFG_EXTILineConfig()\r
+ * 3- Select the mode(interrupt, event) and configure the trigger \r
+ * selection (Rising, falling or both) using EXTI_Init()\r
+ * 4- Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init()\r
+ * \r
+ *@note SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx\r
+ * registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);\r
+ * \r
+ * @endverbatim \r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_exti.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup EXTI \r
+ * @brief EXTI driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup EXTI_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup EXTI_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Initialization and Configuration functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the EXTI peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void EXTI_DeInit(void)\r
+{\r
+ EXTI->IMR = 0x00000000;\r
+ EXTI->EMR = 0x00000000;\r
+ EXTI->RTSR = 0x00000000; \r
+ EXTI->FTSR = 0x00000000; \r
+ EXTI->PR = 0x007FFFFF;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the EXTI peripheral according to the specified\r
+ * parameters in the EXTI_InitStruct.\r
+ * EXTI_Line specifies the EXTI line (EXTI0....EXTI22) \r
+ * EXTI_Mode specifies which EXTI line is used as interrupt or an event\r
+ * EXTI_Trigger selects the trigger. When the trigger occurs, interrupt\r
+ * pending bit will be set\r
+ * EXTI_LineCmd controls (Enable/Disable) the EXTI line\r
+ * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure\r
+ * that contains the configuration information for the EXTI peripheral.\r
+ * @retval None\r
+ */\r
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)\r
+{\r
+ uint32_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));\r
+ assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));\r
+ assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); \r
+ assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));\r
+\r
+ tmp = (uint32_t)EXTI_BASE;\r
+ \r
+ if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)\r
+ {\r
+ /* Clear EXTI line configuration */\r
+ EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;\r
+ EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;\r
+ \r
+ tmp += EXTI_InitStruct->EXTI_Mode;\r
+\r
+ *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;\r
+\r
+ /* Clear Rising Falling edge configuration */\r
+ EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;\r
+ EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;\r
+ \r
+ /* Select the trigger for the selected external interrupts */\r
+ if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)\r
+ {\r
+ /* Rising Falling edge */\r
+ EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;\r
+ EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;\r
+ }\r
+ else\r
+ {\r
+ tmp = (uint32_t)EXTI_BASE;\r
+ tmp += EXTI_InitStruct->EXTI_Trigger;\r
+\r
+ *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ tmp += EXTI_InitStruct->EXTI_Mode;\r
+\r
+ /* Disable the selected external lines */\r
+ *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Fills each EXTI_InitStruct member with its reset value.\r
+ * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will\r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)\r
+{\r
+ EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;\r
+ EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;\r
+ EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;\r
+ EXTI_InitStruct->EXTI_LineCmd = DISABLE;\r
+}\r
+\r
+/**\r
+ * @brief Generates a Software interrupt on selected EXTI line.\r
+ * @param EXTI_Line: specifies the EXTI line on which the software interrupt\r
+ * will be generated.\r
+ * This parameter can be any combination of EXTI_Linex where x can be (0..22).\r
+ * @retval None\r
+ */\r
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_EXTI_LINE(EXTI_Line));\r
+ \r
+ EXTI->SWIER |= EXTI_Line;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup EXTI_Group2 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Interrupts and flags management functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Checks whether the specified EXTI line flag is set or not.\r
+ * @param EXTI_Line: specifies the EXTI line flag to check.\r
+ * This parameter can be:\r
+ * @arg EXTI_Linex: External interrupt line x where x(0..22)\r
+ * @retval The new state of EXTI_Line (SET or RESET).\r
+ */\r
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_GET_EXTI_LINE(EXTI_Line));\r
+ \r
+ if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the EXTI\92s line pending flags.\r
+ * @param EXTI_Line: specifies the EXTI lines flags to clear.\r
+ * This parameter can be any combination of EXTI_Linex where x can be (0..22).\r
+ * @retval None\r
+ */\r
+void EXTI_ClearFlag(uint32_t EXTI_Line)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_EXTI_LINE(EXTI_Line));\r
+ \r
+ EXTI->PR = EXTI_Line;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified EXTI line is asserted or not.\r
+ * @param EXTI_Line: specifies the EXTI line to check.\r
+ * This parameter can be:\r
+ * @arg EXTI_Linex: External interrupt line x where x(0..22)\r
+ * @retval The new state of EXTI_Line (SET or RESET).\r
+ */\r
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t enablestatus = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_GET_EXTI_LINE(EXTI_Line));\r
+ \r
+ enablestatus = EXTI->IMR & EXTI_Line;\r
+ if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the EXTI\92s line pending bits.\r
+ * @param EXTI_Line: specifies the EXTI lines to clear.\r
+ * This parameter can be any combination of EXTI_Linex where x can be (0..22).\r
+ * @retval None\r
+ */\r
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_EXTI_LINE(EXTI_Line));\r
+ \r
+ EXTI->PR = EXTI_Line;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_flash.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides all the Flash firmware functions. These functions \r
+ * can be executed from Internal FLASH or Internal SRAM memories. \r
+ * The functions that should be called from SRAM are defined inside \r
+ * the "stm32l1xx_flash_ramfunc.c" file.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the FLASH peripheral:\r
+ * - FLASH Interface configuration\r
+ * - FLASH Memory Programming\r
+ * - DATA EEPROM Programming\r
+ * - Option Bytes Programming\r
+ * - Interrupts and flags management\r
+ * \r
+ * @verbatim\r
+ * \r
+ * ===================================================================\r
+ * How to use this driver\r
+ * ===================================================================\r
+ * \r
+ * This driver provides functions to configure and program the Flash \r
+ * memory of all STM32L1xx devices\r
+ * These functions are split in 5 groups\r
+ * \r
+ * 1. FLASH Interface configuration functions: this group includes \r
+ * the management of following features:\r
+ * - Set the latency\r
+ * - Enable/Disable the prefetch buffer\r
+ * - Enable/Disable the 64 bit Read Access \r
+ * - Enable/Disable the RUN PowerDown mode\r
+ * - Enable/Disable the SLEEP PowerDown mode \r
+ * \r
+ * 2. FLASH Memory Programming functions: this group includes all \r
+ * needed functions to erase and program the main memory:\r
+ * - Lock and Unlock the Flash interface.\r
+ * - Erase function: Erase Page.\r
+ * - Program functions: Fast Word and Half Page(should be \r
+ * executed from internal SRAM).\r
+ * \r
+ * 3. DATA EEPROM Programming functions: this group includes all \r
+ * needed functions to erase and program the DATA EEPROM memory:\r
+ * - Lock and Unlock the DATA EEPROM interface.\r
+ * - Erase function: Erase Word, erase Double Word (should be \r
+ * executed from internal SRAM).\r
+ * - Program functions: Fast Program Byte, Fast Program Half-Word, \r
+ * FastProgramWord, Program Byte, Program Half-Word, \r
+ * Program Word and Program Double-Word (should be executed \r
+ * from internal SRAM).\r
+ * \r
+ * 4. FLASH Option Bytes Programming functions: this group includes \r
+ * all needed functions to:\r
+ * - Lock and Unlock the Flash Option bytes. \r
+ * - Set/Reset the write protection\r
+ * - Set the Read protection Level\r
+ * - Set the BOR level\r
+ * - Program the user option Bytes \r
+ * - Launch the Option Bytes loader\r
+ * - Get the Write protection\r
+ * - Get the read protection status\r
+ * - Get the BOR level\r
+ * - Get the user option bytes \r
+ * \r
+ * 5. FLASH Interrupts and flag management functions: this group \r
+ * includes all needed functions to:\r
+ * - Enable/Disable the flash interrupt sources\r
+ * - Get flags status\r
+ * - Clear flags\r
+ * - Get Flash operation status\r
+ * - Wait for last flash operation \r
+ * \r
+ * @endverbatim\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_flash.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FLASH \r
+ * @brief FLASH driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+ \r
+/* FLASH Mask */\r
+#define RDPRT_MASK ((uint32_t)0x00000002)\r
+#define WRP01_MASK ((uint32_t)0x0000FFFF)\r
+#define WRP23_MASK ((uint32_t)0xFFFF0000)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+ \r
+/** @defgroup FLASH_Private_Functions\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup FLASH_Group1 FLASH Interface configuration functions\r
+ * @brief FLASH Interface configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ FLASH Interface configuration functions\r
+ =============================================================================== \r
+\r
+ FLASH_Interface configuration_Functions, includes the following functions:\r
+ - void FLASH_SetLatency(uint32_t FLASH_Latency):\r
+ To correctly read data from Flash memory, the number of wait states (LATENCY) \r
+ must be correctly programmed according to the frequency of the CPU clock \r
+ (HCLK) and the supply voltage of the device.\r
+ ---------------------------------------------------------------- \r
+ | Wait states | HCLK clock frequency (MHz) |\r
+ | |------------------------------------------------| \r
+ | (Latency) | voltage range | voltage range | \r
+ | | 1.65 V - 3.6 V | 2.0 V - 3.6 V |\r
+ | |----------------|---------------|---------------| \r
+ | | VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V |\r
+ |-------------- |----------------|---------------|---------------| \r
+ |0WS(1CPU cycle)|0 < HCLK <= 2 |0 < HCLK <= 8 |0 < HCLK <= 16 |\r
+ |---------------|----------------|---------------|---------------| \r
+ |1WS(2CPU cycle)|2 < HCLK <= 4 |8 < HCLK <= 16 |16 < HCLK <= 32| \r
+ ---------------------------------------------------------------- \r
+ \r
+ - void FLASH_PrefetchBufferCmd(FunctionalState NewState);\r
+ - void FLASH_ReadAccess64Cmd(FunctionalState NewState);\r
+ - void FLASH_RUNPowerDownCmd(FunctionalState NewState);\r
+ - void FLASH_SLEEPPowerDownCmd(FunctionalState NewState);\r
+ - void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);\r
+ \r
+ Here below the allowed configuration of Latency, 64Bit access and prefetch buffer\r
+ -------------------------------------------------------------------------------- \r
+ | | ACC64 = 0 | ACC64 = 1 |\r
+ | Latency |----------------|---------------|---------------|---------------| \r
+ | | PRFTEN = 0 | PRFTEN = 1 | PRFTEN = 0 | PRFTEN = 1 | \r
+ |---------------|----------------|---------------|---------------|---------------| \r
+ |0WS(1CPU cycle)| YES | NO | YES | YES |\r
+ |---------------|----------------|---------------|---------------|---------------| \r
+ |1WS(2CPU cycle)| NO | NO | YES | YES | \r
+ -------------------------------------------------------------------------------- \r
+ All these functions don't need the unlock sequence.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sets the code latency value.\r
+ * @param FLASH_Latency: specifies the FLASH Latency value.\r
+ * This parameter can be one of the following values:\r
+ * @arg FLASH_Latency_0: FLASH Zero Latency cycle\r
+ * @arg FLASH_Latency_1: FLASH One Latency cycle\r
+ * @retval None\r
+ */\r
+void FLASH_SetLatency(uint32_t FLASH_Latency)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_LATENCY(FLASH_Latency));\r
+ \r
+ /* Read the ACR register */\r
+ tmpreg = FLASH->ACR; \r
+ \r
+ /* Sets the Latency value */\r
+ tmpreg &= (uint32_t) (~((uint32_t)FLASH_ACR_LATENCY));\r
+ tmpreg |= FLASH_Latency;\r
+ \r
+ /* Write the ACR register */\r
+ FLASH->ACR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Prefetch Buffer.\r
+ * @param NewState: new state of the FLASH prefetch buffer.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @retval None\r
+ */\r
+void FLASH_PrefetchBufferCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if(NewState != DISABLE)\r
+ {\r
+ FLASH->ACR |= FLASH_ACR_PRFTEN;\r
+ }\r
+ else\r
+ {\r
+ FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_PRFTEN));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables read access to flash by 64 bits.\r
+ * @param NewState: new state of the FLASH read access mode.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @note - If this bit is set, the Read access 64 bit is used.\r
+ * - If this bit is reset, the Read access 32 bit is used.\r
+ * @note - This bit cannot be written at the same time as the LATENCY and \r
+ * PRFTEN bits. \r
+ * - To reset this bit, the LATENCY should be zero wait state and the \r
+ * prefetch off.\r
+ * @retval None\r
+ */\r
+void FLASH_ReadAccess64Cmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if(NewState != DISABLE)\r
+ {\r
+ FLASH->ACR |= FLASH_ACR_ACC64;\r
+ }\r
+ else\r
+ {\r
+ FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_ACC64));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enable or disable the power down mode during Sleep mode.\r
+ * @note This function is used to power down the FLASH when the system is in SLEEP LP mode. \r
+ * @param NewState: new state of the power down mode during sleep mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void FLASH_SLEEPPowerDownCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the SLEEP_PD bit to put Flash in power down mode during sleep mode */\r
+ FLASH->ACR |= FLASH_ACR_SLEEP_PD;\r
+ }\r
+ else\r
+ {\r
+ /* Clear the SLEEP_PD bit in to put Flash in idle mode during sleep mode */\r
+ FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_SLEEP_PD));\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Group2 FLASH Memory Programming functions\r
+ * @brief FLASH Memory Programming functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ FLASH Memory Programming functions\r
+ =============================================================================== \r
+\r
+ The FLASH Memory Programming functions, includes the following functions:\r
+ - void FLASH_Unlock(void);\r
+ - void FLASH_Lock(void);\r
+ - FLASH_Status FLASH_ErasePage(uint32_t Page_Address);\r
+ - FLASH_Status FLASH_FastProgramWord(uint32_t Address, uint32_t Data);\r
+ \r
+ Any operation of erase or program should follow these steps:\r
+\r
+ 1. Call the FLASH_Unlock() function to enable the flash control register and \r
+ program memory access\r
+\r
+ 2. Call the desired function to erase page or program data\r
+\r
+ 3. Call the FLASH_Lock() to disable the flash program memory access \r
+ (recommended to protect the FLASH memory against possible unwanted operation)\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Unlocks the FLASH control register and program memory access.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void FLASH_Unlock(void)\r
+{\r
+ if((FLASH->PECR & FLASH_PECR_PRGLOCK) != RESET)\r
+ {\r
+ /* Unlocking the data memory and FLASH_PECR register access */\r
+ DATA_EEPROM_Unlock();\r
+ \r
+ /* Unlocking the program memory access */\r
+ FLASH->PRGKEYR = FLASH_PRGKEY1;\r
+ FLASH->PRGKEYR = FLASH_PRGKEY2; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Locks the Program memory access.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void FLASH_Lock(void)\r
+{\r
+ /* Set the PRGLOCK Bit to lock the program memory access */\r
+ FLASH->PECR |= FLASH_PECR_PRGLOCK;\r
+}\r
+\r
+/**\r
+ * @brief Erases a specified page in program memory.\r
+ * @note - To correctly run this function, the FLASH_Unlock() function\r
+ * must be called before.\r
+ * - Call the FLASH_Lock() to disable the flash memory access \r
+ * (recommended to protect the FLASH memory against possible unwanted operation) \r
+ * @param Page_Address: The page address in program memory to be erased.\r
+ * @note A Page is erased in the Program memory only if the address to load \r
+ * is the start address of a page (multiple of 256 bytes). \r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(Page_Address));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* If the previous operation is completed, proceed to erase the page */\r
+\r
+ /* Set the ERASE bit */\r
+ FLASH->PECR |= FLASH_PECR_ERASE;\r
+\r
+ /* Set PROG bit */\r
+ FLASH->PECR |= FLASH_PECR_PROG;\r
+ \r
+ /* Write 00000000h to the first word of the program page to erase */\r
+ *(__IO uint32_t *)Page_Address = 0x00000000;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+\r
+ /* If the erase operation is completed, disable the ERASE and PROG bits */\r
+ FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG);\r
+ FLASH->PECR &= (uint32_t)(~FLASH_PECR_ERASE); \r
+ } \r
+ /* Return the Erase Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Programs a word at a specified address in program memory.\r
+ * @note - To correctly run this function, the FLASH_Unlock() function\r
+ * must be called before.\r
+ * - Call the FLASH_Lock() to disable the flash memory access \r
+ * (recommended to protect the FLASH memory against possible unwanted operation) \r
+ * @param Address: specifies the address to be written.\r
+ * @param Data: specifies the data to be written.\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
+ */\r
+FLASH_Status FLASH_FastProgramWord(uint32_t Address, uint32_t Data)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* If the previous operation is completed, proceed to program the new word */ \r
+ *(__IO uint32_t *)Address = Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); \r
+ }\r
+ /* Return the Write Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FLASH_Group3 DATA EEPROM Programming functions\r
+ * @brief DATA EEPROM Programming functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ DATA EEPROM Programming functions\r
+ =============================================================================== \r
+\r
+ The DATA_EEPROM Programming_Functions, includes the following functions:\r
+ - void DATA_EEPROM_Unlock(void);\r
+ - void DATA_EEPROM_Lock(void);\r
+ - FLASH_Status DATA_EEPROM_EraseWord(uint32_t Address);\r
+ - FLASH_Status DATA_EEPROM_FastProgramByte(uint32_t Address, uint8_t Data);\r
+ - FLASH_Status DATA_EEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data);\r
+ - FLASH_Status DATA_EEPROM_FastProgramWord(uint32_t Address, uint32_t Data);\r
+ - FLASH_Status DATA_EEPROM_ProgramByte(uint32_t Address, uint8_t Data);\r
+ - FLASH_Status DATA_EEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data);\r
+ - FLASH_Status DATA_EEPROM_ProgramWord(uint32_t Address, uint32_t Data);\r
+ \r
+ Any operation of erase or program should follow these steps:\r
+\r
+ 1. Call the DATA_EEPROM_Unlock() function to enable the data EEPROM access\r
+ and Flash program erase control register access.\r
+\r
+ 2. Call the desired function to erase or program data\r
+\r
+ 3. Call the DATA_EEPROM_Lock() to disable the data EEPROM access\r
+ and Flash program erase control register access(recommended\r
+ to protect the DATA_EEPROM against possible unwanted operation)\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Unlocks the data memory and FLASH_PECR register access.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void DATA_EEPROM_Unlock(void)\r
+{\r
+ if((FLASH->PECR & FLASH_PECR_PELOCK) != RESET)\r
+ { \r
+ /* Unlocking the Data memory and FLASH_PECR register access*/\r
+ FLASH->PEKEYR = FLASH_PEKEY1;\r
+ FLASH->PEKEYR = FLASH_PEKEY2;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Locks the Data memory and FLASH_PECR register access.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void DATA_EEPROM_Lock(void)\r
+{\r
+ /* Set the PELOCK Bit to lock the data memory and FLASH_PECR register access */\r
+ FLASH->PECR |= FLASH_PECR_PELOCK;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables DATA EEPROM fixed Time programming (2*Tprog).\r
+ * @param NewState: new state of the DATA EEPROM fixed Time programming mode.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @retval None\r
+ */\r
+void DATA_EEPROM_FixedTimeProgramCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if(NewState != DISABLE)\r
+ {\r
+ FLASH->PECR |= (uint32_t)FLASH_PECR_FTDW;\r
+ }\r
+ else\r
+ {\r
+ FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Erase a word in data memory.\r
+ * @param Address: specifies the address to be erased\r
+ * @note1 - A data memory word is erased in the data memory only if the address \r
+ * to load is the start address of a word (multiple of a word).\r
+ * @note2 - To correctly run this function, the DATA_EEPROM_Unlock() function\r
+ * must be called before.\r
+ * - Call the DATA_EEPROM_Lock() to he data EEPROM access\r
+ * and Flash program erase control register access(recommended to protect \r
+ * the DATA_EEPROM against possible unwanted operation) \r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status DATA_EEPROM_EraseWord(uint32_t Address)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_DATA_ADDRESS(Address));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* Write "00000000h" to valid address in the data memory" */\r
+ *(__IO uint32_t *) Address = 0x00000000;\r
+ }\r
+ \r
+ /* Return the erase status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Write a Byte at a specified address in data memory.\r
+ * @note - To correctly run this function, the DATA_EEPROM_Unlock() function\r
+ * must be called before.\r
+ * - Call the DATA_EEPROM_Lock() to he data EEPROM access\r
+ * and Flash program erase control register access(recommended to protect \r
+ * the DATA_EEPROM against possible unwanted operation) \r
+ * @param Address: specifies the address to be written.\r
+ * @param Data: specifies the data to be written.\r
+ * @note This function assumes that the is data word is already erased. \r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
+ */\r
+FLASH_Status DATA_EEPROM_FastProgramByte(uint32_t Address, uint8_t Data)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ uint32_t tmp = 0, tmpaddr = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_DATA_ADDRESS(Address)); \r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* Clear the FTDW bit */\r
+ FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW));\r
+ \r
+ if(Data != (uint8_t)0x00) \r
+ {\r
+ /* If the previous operation is completed, proceed to write the new Data */ \r
+ *(__IO uint8_t *)Address = Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); \r
+ }\r
+ else\r
+ {\r
+ tmpaddr = Address & 0xFFFFFFFC;\r
+ tmp = * (__IO uint32_t *) tmpaddr;\r
+ tmpaddr = 0xFF << ((uint32_t) (0x8 * (Address & 0x3)));\r
+ tmp &= ~tmpaddr;\r
+ status = DATA_EEPROM_EraseWord(Address & 0xFFFFFFFC);\r
+ status = DATA_EEPROM_FastProgramWord((Address & 0xFFFFFFFC), tmp); \r
+ } \r
+ }\r
+ /* Return the Write Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Writes a half word at a specified address in data memory.\r
+ * @note - To correctly run this function, the DATA_EEPROM_Unlock() function\r
+ * must be called before.\r
+ * - Call the DATA_EEPROM_Lock() to he data EEPROM access\r
+ * and Flash program erase control register access(recommended to protect \r
+ * the DATA_EEPROM against possible unwanted operation) \r
+ * @param Address: specifies the address to be written.\r
+ * @param Data: specifies the data to be written.\r
+ * @note This function assumes that the is data word is already erased. \r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
+ */\r
+FLASH_Status DATA_EEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ uint32_t tmp = 0, tmpaddr = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_DATA_ADDRESS(Address));\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* Clear the FTDW bit */\r
+ FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW));\r
+ \r
+ if(Data != (uint16_t)0x0000) \r
+ {\r
+ /* If the previous operation is completed, proceed to write the new data */ \r
+ *(__IO uint16_t *)Address = Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ }\r
+ else\r
+ {\r
+ if((Address & 0x3) != 0x3)\r
+ { \r
+ tmpaddr = Address & 0xFFFFFFFC;\r
+ tmp = * (__IO uint32_t *) tmpaddr;\r
+ tmpaddr = 0xFFFF << ((uint32_t) (0x8 * (Address & 0x3)));\r
+ tmp &= ~tmpaddr; \r
+ status = DATA_EEPROM_EraseWord(Address & 0xFFFFFFFC);\r
+ status = DATA_EEPROM_FastProgramWord((Address & 0xFFFFFFFC), tmp); \r
+ }\r
+ else\r
+ {\r
+ DATA_EEPROM_FastProgramByte(Address, 0x00);\r
+ DATA_EEPROM_FastProgramByte(Address + 1, 0x00); \r
+ } \r
+ } \r
+ } \r
+ /* Return the Write Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Programs a word at a specified address in data memory.\r
+ * @note - To correctly run this function, the DATA_EEPROM_Unlock() function\r
+ * must be called before.\r
+ * - Call the DATA_EEPROM_Lock() to the data EEPROM access\r
+ * and Flash program erase control register access(recommended to protect \r
+ * the DATA_EEPROM against possible unwanted operation) \r
+ * @param Address: specifies the address to be written.\r
+ * @param Data: specifies the data to be written.\r
+ * @note This function assumes that the is data word is already erased. \r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
+ */\r
+FLASH_Status DATA_EEPROM_FastProgramWord(uint32_t Address, uint32_t Data)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_DATA_ADDRESS(Address));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* Clear the FTDW bit */\r
+ FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW));\r
+ \r
+ /* If the previous operation is completed, proceed to program the new data */ \r
+ *(__IO uint32_t *)Address = Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); \r
+ }\r
+ /* Return the Write Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Write a Byte at a specified address in data memory without erase.\r
+ * @note - To correctly run this function, the DATA_EEPROM_Unlock() function\r
+ * must be called before.\r
+ * - Call the DATA_EEPROM_Lock() to he data EEPROM access\r
+ * and Flash program erase control register access(recommended to protect \r
+ * the DATA_EEPROM against possible unwanted operation) \r
+ * @note The function DATA_EEPROM_FixedTimeProgramCmd() can be called before \r
+ * this function to configure the Fixed Time Programming. \r
+ * @param Address: specifies the address to be written.\r
+ * @param Data: specifies the data to be written.\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
+ */\r
+FLASH_Status DATA_EEPROM_ProgramByte(uint32_t Address, uint8_t Data)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ uint32_t tmp = 0, tmpaddr = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_DATA_ADDRESS(Address)); \r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ if(Data != (uint8_t) 0x00)\r
+ { \r
+ *(__IO uint8_t *)Address = Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+\r
+ }\r
+ else\r
+ {\r
+ tmpaddr = Address & 0xFFFFFFFC;\r
+ tmp = * (__IO uint32_t *) tmpaddr;\r
+ tmpaddr = 0xFF << ((uint32_t) (0x8 * (Address & 0x3)));\r
+ tmp &= ~tmpaddr; \r
+ status = DATA_EEPROM_EraseWord(Address & 0xFFFFFFFC);\r
+ status = DATA_EEPROM_FastProgramWord((Address & 0xFFFFFFFC), tmp); \r
+ } \r
+ }\r
+ /* Return the Write Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Writes a half word at a specified address in data memory without erase.\r
+ * @note - To correctly run this function, the DATA_EEPROM_Unlock() function\r
+ * must be called before.\r
+ * - Call the DATA_EEPROM_Lock() to he data EEPROM access\r
+ * and Flash program erase control register access(recommended to protect \r
+ * the DATA_EEPROM against possible unwanted operation)\r
+ * @note The function DATA_EEPROM_FixedTimeProgramCmd() can be called before \r
+ * this function to configure the Fixed Time Programming \r
+ * @param Address: specifies the address to be written.\r
+ * @param Data: specifies the data to be written.\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
+ */\r
+FLASH_Status DATA_EEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ uint32_t tmp = 0, tmpaddr = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_DATA_ADDRESS(Address));\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ if(Data != (uint16_t)0x0000)\r
+ {\r
+ *(__IO uint16_t *)Address = Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); \r
+ }\r
+ else\r
+ {\r
+ if((Address & 0x3) != 0x3)\r
+ {\r
+ tmpaddr = Address & 0xFFFFFFFC;\r
+ tmp = * (__IO uint32_t *) tmpaddr;\r
+ tmpaddr = 0xFFFF << ((uint32_t) (0x8 * (Address & 0x3)));\r
+ tmp &= ~tmpaddr; \r
+ status = DATA_EEPROM_EraseWord(Address & 0xFFFFFFFC);\r
+ status = DATA_EEPROM_FastProgramWord((Address & 0xFFFFFFFC), tmp); \r
+ }\r
+ else\r
+ {\r
+ DATA_EEPROM_FastProgramByte(Address, 0x00);\r
+ DATA_EEPROM_FastProgramByte(Address + 1, 0x00); \r
+ } \r
+ } \r
+ } \r
+ /* Return the Write Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Programs a word at a specified address in data memory without erase.\r
+ * @note - To correctly run this function, the DATA_EEPROM_Unlock() function\r
+ * must be called before.\r
+ * - Call the DATA_EEPROM_Lock() to he data EEPROM access\r
+ * and Flash program erase control register access(recommended to protect \r
+ * the DATA_EEPROM against possible unwanted operation) \r
+ * @note The function DATA_EEPROM_FixedTimeProgramCmd() can be called before \r
+ * this function to configure the Fixed Time Programming. \r
+ * @param Address: specifies the address to be written.\r
+ * @param Data: specifies the data to be written.\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
+ */\r
+FLASH_Status DATA_EEPROM_ProgramWord(uint32_t Address, uint32_t Data)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_DATA_ADDRESS(Address));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ *(__IO uint32_t *)Address = Data;\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); \r
+ }\r
+ /* Return the Write Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Group4 Option Bytes Programming functions\r
+ * @brief Option Bytes Programming functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Option Bytes Programming functions\r
+ =============================================================================== \r
+\r
+ The FLASH_Option Bytes Programming_functions, includes the following functions:\r
+ - void FLASH_OB_Unlock(void);\r
+ - void FLASH_OB_Lock(void);\r
+ - void FLASH_OB_Launch(void);\r
+ - FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);\r
+ - FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);\r
+ - FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);\r
+ - FLASH_Status FLASH_OB_BORConfig(uint8_t OB_BOR);\r
+ - uint8_t FLASH_OB_GetUser(void);\r
+ - uint32_t FLASH_OB_GetWRP(void);\r
+ - FlagStatus FLASH_OB_GetRDP(void);\r
+ - uint8_t FLASH_OB_GetBOR(void);\r
+ \r
+ Any operation of erase or program should follow these steps:\r
+ \r
+ 1. Call the FLASH_OB_Unlock() function to enable the Flash option control register access\r
+ \r
+ 2. Call one or several functions to program the desired option bytes \r
+ - void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) => to Enable/Disable \r
+ the desired sector write protection\r
+ - void FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read Protection Level\r
+ - void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) => to configure \r
+ the user option Bytes: IWDG, STOP and the Standby.\r
+ - void FLASH_OB_BORConfig(uint8_t OB_BOR) => to Set the BOR level \r
+ - FLASH_Status FLASH_ProgramOTP(uint32_t Address, uint32_t Data) => to program the OTP bytes \r
+ \r
+ 3. Once all needed option bytes to be programmed are correctly written, call the\r
+ FLASH_OB_Launch(void) function to launch the Option Bytes programming process. \r
+ \r
+ 4. Call the FLASH_OB_Lock() to disable the Flash option control register access (recommended\r
+ to protect the option Bytes against possible unwanted operations)\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Unlocks the option bytes block access.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void FLASH_OB_Unlock(void)\r
+{\r
+ if((FLASH->PECR & FLASH_PECR_OPTLOCK) != RESET)\r
+ {\r
+ /* Unlocking the data memory and FLASH_PECR register access */\r
+ DATA_EEPROM_Unlock();\r
+ \r
+ /* Unlocking the option bytes block access */\r
+ FLASH->OPTKEYR = FLASH_OPTKEY1;\r
+ FLASH->OPTKEYR = FLASH_OPTKEY2;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Locks the option bytes block access.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void FLASH_OB_Lock(void)\r
+{\r
+ /* Set the OPTLOCK Bit to lock the option bytes block access */\r
+ FLASH->PECR |= FLASH_PECR_OPTLOCK;\r
+}\r
+\r
+/**\r
+ * @brief Launch the option byte loading.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void FLASH_OB_Launch(void)\r
+{\r
+ /* Set the OBL_Launch bit to lauch the option byte loading */\r
+ FLASH->PECR |= FLASH_PECR_OBL_LAUNCH;\r
+}\r
+\r
+/**\r
+ * @brief Write protects the desired pages\r
+ * @note - To correctly run this function, the FLASH_OB_Unlock() function\r
+ * must be called before.\r
+ * - Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes \r
+ * (recommended to protect the FLASH memory against possible unwanted operation) \r
+ * @param OB_WRP: specifies the address of the pages to be write protected.\r
+ * This parameter can be:\r
+ * @arg value between OB_WRP_Pages0to15 and OB_WRP_Pages496to511\r
+ * @arg OB_WRP_AllPages\r
+ * @param NewState: new state of the specified FLASH Pages Wtite protection.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)\r
+{\r
+ uint32_t WRP01_Data = 0, WRP23_Data = 0;\r
+ \r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ uint32_t tmp1 = 0, tmp2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_OB_WRP(OB_WRP));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ if (NewState != DISABLE)\r
+ {\r
+ WRP01_Data = (uint16_t)(((OB_WRP & WRP01_MASK) | OB->WRP01));\r
+ WRP23_Data = (uint16_t)((((OB_WRP & WRP23_MASK)>>16 | OB->WRP23))); \r
+ tmp1 = (uint32_t)(~(WRP01_Data) << 16)|(WRP01_Data);\r
+ OB->WRP01 = tmp1;\r
+ \r
+ tmp2 = (uint32_t)(~(WRP23_Data) << 16)|(WRP23_Data);\r
+ OB->WRP23 = tmp2; \r
+ } \r
+ \r
+ else\r
+ {\r
+ WRP01_Data = (uint16_t)(~OB_WRP & (WRP01_MASK & OB->WRP01));\r
+ WRP23_Data = (uint16_t)((((~OB_WRP & WRP23_MASK)>>16 & OB->WRP23))); \r
+\r
+ tmp1 = (uint32_t)((~WRP01_Data) << 16)|(WRP01_Data);\r
+ OB->WRP01 = tmp1;\r
+ \r
+ tmp2 = (uint32_t)((~WRP23_Data) << 16)|(WRP23_Data);\r
+ OB->WRP23 = tmp2;\r
+ }\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ }\r
+\r
+ /* Return the write protection operation Status */\r
+ return status; \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the read out protection.\r
+ * @note - To correctly run this function, the FLASH_OB_Unlock() function\r
+ * must be called before.\r
+ * - Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes \r
+ * (recommended to protect the FLASH memory against possible unwanted operation) \r
+ * @param FLASH_ReadProtection_Level: specifies the read protection level. \r
+ * This parameter can be:\r
+ * @arg OB_RDP_Level_0: No protection\r
+ * @arg OB_RDP_Level_1: Read protection of the memory \r
+ * @arg OB_RDP_Level_2: Chip protection\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ uint8_t tmp1 = 0;\r
+ uint32_t tmp2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_OB_RDP(OB_RDP));\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ /* calculate the option byte to write */\r
+ tmp1 = (uint8_t)(~(OB_RDP ));\r
+ tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16)) | ((uint32_t)OB_RDP));\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ { \r
+ /* program read protection level */\r
+ OB->RDP = tmp2;\r
+ }\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ /* Return the Read protection operation Status */\r
+ return status; \r
+}\r
+\r
+/**\r
+ * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.\r
+ * @note - To correctly run this function, the FLASH_OB_Unlock() function\r
+ * must be called before.\r
+ * - Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes \r
+ * (recommended to protect the FLASH memory against possible unwanted operation) \r
+ * @param OB_IWDG: Selects the WDG mode\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_IWDG_SW: Software WDG selected\r
+ * @arg OB_IWDG_HW: Hardware WDG selected\r
+ * @param OB_STOP: Reset event when entering STOP mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_STOP_NoRST: No reset generated when entering in STOP\r
+ * @arg OB_STOP_RST: Reset generated when entering in STOP\r
+ * @param OB_STDBY: Reset event when entering Standby mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY\r
+ * @arg OB_STDBY_RST: Reset generated when entering in STANDBY\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE; \r
+ uint32_t tmp = 0, tmp1 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));\r
+ assert_param(IS_OB_STOP_SOURCE(OB_STOP));\r
+ assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));\r
+\r
+ /* Get the User Option byte register */\r
+ tmp1 = (FLASH->OBR & 0x000F0000) >> 16;\r
+ \r
+ /* Calculate the user option byte to write */ \r
+ tmp = (uint32_t)(((uint32_t)~((uint32_t)((uint32_t)(OB_IWDG) | (uint32_t)(OB_STOP) | (uint32_t)(OB_STDBY) | tmp1))) << ((uint32_t)0x10));\r
+ tmp |= ((uint32_t)(OB_IWDG) | ((uint32_t)OB_STOP) | (uint32_t)(OB_STDBY) | tmp1);\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ { \r
+ /* Write the User Option Byte */ \r
+ OB->USER = tmp; \r
+ }\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ /* Return the Option Byte program Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Programs the FLASH brownout reset threshold level Option Byte.\r
+ * @note - To correctly run this function, the FLASH_OB_Unlock() function\r
+ * must be called before.\r
+ * - Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes \r
+ * (recommended to protect the FLASH memory against possible unwanted operation) \r
+ * @param OB_BOR: Selects the brownout reset threshold level\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_BOR_OFF: BOR is disabled at power down, the reset is asserted when the VDD \r
+ * power supply reaches the PDR(Power Down Reset) threshold (1.5V)\r
+ * @arg OB_BOR_LEVEL1: BOR Reset threshold levels for 1.7V - 1.8V VDD power supply\r
+ * @arg OB_BOR_LEVEL2: BOR Reset threshold levels for 1.9V - 2.0V VDD power supply\r
+ * @arg OB_BOR_LEVEL3: BOR Reset threshold levels for 2.3V - 2.4V VDD power supply\r
+ * @arg OB_BOR_LEVEL4: BOR Reset threshold levels for 2.55V - 2.65V VDD power supply\r
+ * @arg OB_BOR_LEVEL5: BOR Reset threshold levels for 2.8V - 2.9V VDD power supply\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_OB_BORConfig(uint8_t OB_BOR)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ uint32_t tmp = 0, tmp1 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_OB_BOR_LEVEL(OB_BOR));\r
+\r
+ /* Get the User Option byte register */\r
+ tmp1 = (FLASH->OBR & 0x00700000) >> 16;\r
+ \r
+ /* Calculate the option byte to write */\r
+ tmp = (uint32_t)~(OB_BOR | tmp1)<<16;\r
+ tmp |= (OB_BOR | tmp1);\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ { \r
+ /* Write the BOR Option Byte */ \r
+ OB->USER = tmp; \r
+ }\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ /* Return the Option Byte program Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Returns the FLASH User Option Bytes values.\r
+ * @param None\r
+ * @retval The FLASH User Option Bytes .\r
+ */\r
+uint8_t FLASH_OB_GetUser(void)\r
+{\r
+ /* Return the User Option Byte */\r
+ return (uint8_t)(FLASH->OBR >> 20);\r
+}\r
+\r
+/**\r
+ * @brief Returns the FLASH Write Protection Option Bytes value.\r
+ * @param None\r
+ * @retval The FLASH Write Protection Option Bytes value\r
+ */\r
+uint32_t FLASH_OB_GetWRP(void)\r
+{\r
+ /* Return the FLASH write protection Register value */\r
+ return (uint32_t)(FLASH->WRPR);\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the FLASH Read out Protection Status is set or not.\r
+ * @param None\r
+ * @retval FLASH ReadOut Protection Status(SET or RESET)\r
+ */\r
+FlagStatus FLASH_OB_GetRDP(void)\r
+{\r
+ FlagStatus readstatus = RESET;\r
+ \r
+ if ((uint8_t)(FLASH->OBR) != (uint8_t)OB_RDP_Level_0)\r
+ {\r
+ readstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ readstatus = RESET;\r
+ }\r
+ return readstatus;\r
+}\r
+\r
+/**\r
+ * @brief Returns the FLASH BOR level.\r
+ * @param None\r
+ * @retval The FLASH User Option Bytes .\r
+ */\r
+uint8_t FLASH_OB_GetBOR(void)\r
+{\r
+ /* Return the BOR level */\r
+ return (uint8_t)((FLASH->OBR & (uint32_t)0x000F0000) >> 16);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Group5 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Interrupts and flags management functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified FLASH interrupts.\r
+ * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or \r
+ * disabled.\r
+ * This parameter can be any combination of the following values: \r
+ * @arg FLASH_IT_EOP: FLASH end of programming Interrupt\r
+ * @arg FLASH_IT_ERR: FLASH Error Interrupt \r
+ * @retval None \r
+ */\r
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_IT(FLASH_IT)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if(NewState != DISABLE)\r
+ {\r
+ /* Enable the interrupt sources */\r
+ FLASH->PECR |= FLASH_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the interrupt sources */\r
+ FLASH->PECR &= ~(uint32_t)FLASH_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified FLASH flag is set or not.\r
+ * @param FLASH_FLAG: specifies the FLASH flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag \r
+ * @arg FLASH_FLAG_EOP: FLASH End of Operation flag\r
+ * @arg FLASH_FLAG_READY: FLASH Ready flag after low power mode\r
+ * @arg FLASH_FLAG_ENDHV: FLASH End of high voltage flag\r
+ * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag \r
+ * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag\r
+ * @arg FLASH_FLAG_SIZERR: FLASH size error flag \r
+ * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag \r
+ * @retval The new state of FLASH_FLAG (SET or RESET).\r
+ */\r
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG));\r
+\r
+ if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the new state of FLASH_FLAG (SET or RESET) */\r
+ return bitstatus; \r
+}\r
+\r
+/**\r
+ * @brief Clears the FLASH\92s pending flags.\r
+ * @param FLASH_FLAG: specifies the FLASH flags to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg FLASH_FLAG_EOP: FLASH End of Operation flag\r
+ * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag \r
+ * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag \r
+ * @arg FLASH_FLAG_SIZERR: FLASH size error flag \r
+ * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag \r
+ * @retval None\r
+ */\r
+void FLASH_ClearFlag(uint32_t FLASH_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG));\r
+ \r
+ /* Clear the flags */\r
+ FLASH->SR = FLASH_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Returns the FLASH Status.\r
+ * @param None\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP or FLASH_COMPLETE.\r
+ */\r
+FLASH_Status FLASH_GetStatus(void)\r
+{\r
+ FLASH_Status FLASHstatus = FLASH_COMPLETE;\r
+ \r
+ if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) \r
+ {\r
+ FLASHstatus = FLASH_BUSY;\r
+ }\r
+ else \r
+ { \r
+ if((FLASH->SR & (uint32_t)FLASH_FLAG_WRPERR)!= (uint32_t)0x00)\r
+ { \r
+ FLASHstatus = FLASH_ERROR_WRP;\r
+ }\r
+ else \r
+ {\r
+ if((FLASH->SR & (uint32_t)0xFEF0) != (uint32_t)0x00)\r
+ {\r
+ FLASHstatus = FLASH_ERROR_PROGRAM; \r
+ }\r
+ else\r
+ {\r
+ FLASHstatus = FLASH_COMPLETE;\r
+ }\r
+ }\r
+ }\r
+ /* Return the FLASH Status */\r
+ return FLASHstatus;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Waits for a FLASH operation to complete or a TIMEOUT to occur.\r
+ * @param Timeout: FLASH programming Timeout\r
+ * @retval FLASH Status: The returned value can be: FLASH_BUSY, \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)\r
+{ \r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ \r
+ /* Check for the FLASH Status */\r
+ status = FLASH_GetStatus();\r
+ \r
+ /* Wait for a FLASH operation to complete or a TIMEOUT to occur */\r
+ while((status == FLASH_BUSY) && (Timeout != 0x00))\r
+ {\r
+ status = FLASH_GetStatus();\r
+ Timeout--;\r
+ }\r
+ \r
+ if(Timeout == 0x00 )\r
+ {\r
+ status = FLASH_TIMEOUT;\r
+ }\r
+ /* Return the operation status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+ /**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_flash_ramfunc.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides all the Flash firmware functions which should be\r
+ * executed from the internal SRAM. This file should be placed in \r
+ * internal SRAM. \r
+ * Other FLASH memory functions that can be used from the FLASH are \r
+ * defined in the "stm32l1xx_flash.c" file. \r
+ * @verbatim \r
+ * \r
+ * ARM Compiler\r
+ * ------------\r
+ * RAM functions are defined using the toolchain options. \r
+ * Functions that are be executed in RAM should reside in a separate\r
+ * source module. Using the 'Options for File' dialog you can simply change\r
+ * the 'Code / Const' area of a module to a memory space in physical RAM.\r
+ * Available memory areas are declared in the 'Target' tab of the \r
+ * 'Options for Target' dialog.\r
+ * \r
+ * ICCARM Compiler\r
+ * ---------------\r
+ * RAM functions are defined using a specific toolchain keyword "__ramfunc". \r
+ * \r
+ * GNU Compiler\r
+ * ------------\r
+ * RAM functions are defined using a specific toolchain attribute\r
+ * "__attribute__((section(".data")))".\r
+ * \r
+ * TASKING Compiler\r
+ * ----------------\r
+ * RAM functions are defined using a specific toolchain pragma. This \r
+ * pragma is defined inside this file. \r
+ * \r
+ * @endverbatim \r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_flash.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FLASH \r
+ * @brief FLASH driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+static __RAM_FUNC GetStatus(void);\r
+static __RAM_FUNC WaitForLastOperation(uint32_t Timeout);\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+ \r
+/** @defgroup FLASH_Private_Functions\r
+ * @{\r
+ */ \r
+\r
+/** @addtogroup FLASH_Group1\r
+ *\r
+@verbatim \r
+@endverbatim\r
+ * @{\r
+ */ \r
+#if defined ( __TASKING__ )\r
+#pragma section_code_init on\r
+#endif\r
+\r
+/**\r
+ * @brief Enable or disable the power down mode during RUN mode.\r
+ * @note: This function can be used only when the user code is running from Internal SRAM\r
+ * @param NewState: new state of the power down mode during RUN mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+__RAM_FUNC FLASH_RUNPowerDownCmd(FunctionalState NewState)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Unlock the RUN_PD bit */\r
+ FLASH->PDKEYR = FLASH_PDKEY1;\r
+ FLASH->PDKEYR = FLASH_PDKEY2;\r
+ \r
+ /* Set the RUN_PD bit in FLASH_ACR register to put Flash in power down mode */\r
+ FLASH->ACR |= (uint32_t)FLASH_ACR_RUN_PD;\r
+\r
+ if((FLASH->ACR & FLASH_ACR_RUN_PD) != FLASH_ACR_RUN_PD)\r
+ {\r
+ status = FLASH_ERROR_PROGRAM;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Clear the RUN_PD bit in FLASH_ACR register to put Flash in idle mode */\r
+ FLASH->ACR &= (uint32_t)(~(uint32_t)FLASH_ACR_RUN_PD);\r
+ }\r
+\r
+ /* Return the Write Status */\r
+ return status; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup FLASH_Group2\r
+ *\r
+@verbatim \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Programs a half page in program memory.\r
+ * @param Address: specifies the address to be written.\r
+ * @param pBuffer: pointer to the buffer containing the data to be written to \r
+ * the half page.\r
+ * @note - To correctly run this function, the FLASH_Unlock() function\r
+ * must be called before.\r
+ * - Call the FLASH_Lock() to disable the flash memory access \r
+ * (recommended to protect the FLASH memory against possible unwanted operation)\r
+ * @note Half page write is possible only from SRAM.\r
+ * @note If there are more than 32 words to write, after 32 words another \r
+ * Half Page programming operation starts and has to be finished.\r
+ * @note A half page is written to the program memory only if the first \r
+ * address to load is the start address of a half page (multiple of 128 \r
+ * bytes) and the 31 remaining words to load are in the same half page.\r
+ * @note During the Program memory half page write all read operations are \r
+ * forbidden (this includes DMA read operations and debugger read \r
+ * operations such as breakpoints, periodic updates, etc.)\r
+ * @note If a PGAERR is set during a Program memory half page write, the \r
+ * complete write operation is aborted. Software should then reset the \r
+ * FPRG and PROG/DATA bits and restart the write operation from the \r
+ * beginning. \r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
+ */\r
+__RAM_FUNC FLASH_ProgramHalfPage(uint32_t Address, uint32_t* pBuffer)\r
+{\r
+ uint32_t count = 0; \r
+ \r
+ FLASH_Status status = FLASH_COMPLETE;\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the previous operation is completed, proceed to program the new \r
+ half page */\r
+ FLASH->PECR |= FLASH_PECR_FPRG;\r
+ FLASH->PECR |= FLASH_PECR_PROG;\r
+ \r
+ /* Write one half page directly with 32 different words */\r
+ while(count < 32)\r
+ {\r
+ *(__IO uint32_t*) (Address + (4 * count)) = *(pBuffer++);\r
+ count ++; \r
+ }\r
+ /* Wait for last operation to be completed */\r
+ status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ /* if the write operation is completed, disable the PROG and FPRG bits */\r
+ FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG);\r
+ FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG);\r
+ }\r
+ /* Return the Write Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup FLASH_Group3\r
+ *\r
+@verbatim \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Erase a double word in data memory.\r
+ * @param Address: specifies the address to be erased\r
+ * @note - To correctly run this function, the DATA_EEPROM_Unlock() function\r
+ * must be called before.\r
+ * - Call the DATA_EEPROM_Lock() to he data EEPROM access\r
+ * and Flash program erase control register access(recommended to protect \r
+ * the DATA_EEPROM against possible unwanted operation) \r
+ * @note Data memory double word erase is possible only from SRAM.\r
+ * @note A double word is erased to the data memory only if the first address \r
+ * to load is the start address of a double word (multiple of 8 bytes) \r
+ * @note During the Data memory double word erase, all read operations are \r
+ * forbidden (this includes DMA read operations and debugger read \r
+ * operations such as breakpoints, periodic updates, etc.) \r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+\r
+__RAM_FUNC DATA_EEPROM_EraseDoubleWord(uint32_t Address)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* If the previous operation is completed, proceed to erase the next double word */\r
+ /* Set the ERASE bit */\r
+ FLASH->PECR |= FLASH_PECR_ERASE;\r
+\r
+ /* Set DATA bit */\r
+ FLASH->PECR |= FLASH_PECR_DATA;\r
+ \r
+ /* Write 00000000h to the 2 words to erase */\r
+ *(__IO uint64_t *)Address = 0x00000000;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ /* If the erase operation is completed, disable the ERASE and DATA bits */\r
+ FLASH->PECR &= (uint32_t)(~FLASH_PECR_ERASE);\r
+ FLASH->PECR &= (uint32_t)(~FLASH_PECR_DATA);\r
+ } \r
+ /* Return the erase status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Write a double word in data memory without erase.\r
+ * @param Address: specifies the address to be written.\r
+ * @param Data: specifies the data to be written.\r
+ * @note - To correctly run this function, the DATA_EEPROM_Unlock() function\r
+ * must be called before.\r
+ * - Call the DATA_EEPROM_Lock() to he data EEPROM access\r
+ * and Flash program erase control register access(recommended to protect \r
+ * the DATA_EEPROM against possible unwanted operation) \r
+ * @note Data memory double word write is possible only from SRAM.\r
+ * @note A data memory double word is written to the data memory only if the \r
+ * first address to load is the start address of a double word (multiple \r
+ * of double word). \r
+ * @note During the Data memory double word write, all read operations are \r
+ * forbidden (this includes DMA read operations and debugger read \r
+ * operations such as breakpoints, periodic updates, etc.) \r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
+ */ \r
+__RAM_FUNC DATA_EEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* If the previous operation is completed, proceed to program the new data*/\r
+ FLASH->PECR |= FLASH_PECR_FPRG;\r
+ FLASH->PECR |= FLASH_PECR_DATA;\r
+ \r
+ /* Write the 2 words */ \r
+ *(__IO uint32_t *)Address = (uint32_t) Data;\r
+ Address += 4;\r
+ *(__IO uint32_t *)Address = (uint32_t) (Data >> 32);\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ /* If the write operation is completed, disable the FPRG and DATA bits */\r
+ FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG);\r
+ FLASH->PECR &= (uint32_t)(~FLASH_PECR_DATA); \r
+ }\r
+ /* Return the Write Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief Returns the FLASH Status.\r
+ * @param None\r
+ * @retval FLASH Status: The returned value can be: FLASH_BUSY, \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP or FLASH_COMPLETE\r
+ */\r
+static __RAM_FUNC GetStatus(void)\r
+{\r
+ FLASH_Status FLASHstatus = FLASH_COMPLETE;\r
+ \r
+ if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) \r
+ {\r
+ FLASHstatus = FLASH_BUSY;\r
+ }\r
+ else \r
+ { \r
+ if((FLASH->SR & (uint32_t)FLASH_FLAG_WRPERR)!= (uint32_t)0x00)\r
+ { \r
+ FLASHstatus = FLASH_ERROR_WRP;\r
+ }\r
+ else \r
+ {\r
+ if((FLASH->SR & (uint32_t)0xFEF0) != (uint32_t)0x00)\r
+ {\r
+ FLASHstatus = FLASH_ERROR_PROGRAM; \r
+ }\r
+ else\r
+ {\r
+ FLASHstatus = FLASH_COMPLETE;\r
+ }\r
+ }\r
+ }\r
+ /* Return the FLASH Status */\r
+ return FLASHstatus;\r
+}\r
+\r
+/**\r
+ * @brief Waits for a FLASH operation to complete or a TIMEOUT to occur.\r
+ * @param Timeout: FLASH programming Timeout\r
+ * @retval FLASH Status: The returned value can be: FLASH_BUSY, \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or \r
+ * FLASH_TIMEOUT.\r
+ */\r
+static __RAM_FUNC WaitForLastOperation(uint32_t Timeout)\r
+{ \r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ \r
+ /* Check for the FLASH Status */\r
+ status = GetStatus();\r
+ \r
+ /* Wait for a FLASH operation to complete or a TIMEOUT to occur */\r
+ while((status == FLASH_BUSY) && (Timeout != 0x00))\r
+ {\r
+ status = GetStatus();\r
+ Timeout--;\r
+ }\r
+ \r
+ if(Timeout == 0x00 )\r
+ {\r
+ status = FLASH_TIMEOUT;\r
+ }\r
+ /* Return the operation status */\r
+ return status;\r
+}\r
+\r
+#if defined ( __TASKING__ )\r
+#pragma section_code_init restore\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+ /**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_gpio.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the GPIO peripheral: \r
+ * - Initialization and Configuration\r
+ * - GPIO Read and Write\r
+ * - GPIO Alternate functions configuration\r
+ * \r
+ * @verbatim\r
+ *\r
+ * ===================================================================\r
+ * How to use this driver\r
+ * =================================================================== \r
+ * 1. Enable the GPIO AHB clock using RCC_AHBPeriphClockCmd()\r
+ * \r
+ * 2. Configure the GPIO pin(s) using GPIO_Init()\r
+ * Four possible configuration are available for each pin:\r
+ * - Input: Floating, Pull-up, Pull-down.\r
+ * - Output: Push-Pull (Pull-up, Pull-down or no Pull)\r
+ * Open Drain (Pull-up, Pull-down or no Pull).\r
+ * In output mode, the speed is configurable: Very Low, Low,\r
+ * Medium or High.\r
+ * - Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull)\r
+ * Open Drain (Pull-up, Pull-down or no Pull).\r
+ * - Analog: required mode when a pin is to be used as ADC channel,\r
+ * DAC output or comparator input.\r
+ * \r
+ * 3- Peripherals alternate function:\r
+ * - For ADC, DAC and comparators, configure the desired pin in \r
+ * analog mode using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN\r
+ * - For other peripherals (TIM, USART...):\r
+ * - Connect the pin to the desired peripherals' Alternate \r
+ * Function (AF) using GPIO_PinAFConfig() function\r
+ * - Configure the desired pin in alternate function mode using\r
+ * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF\r
+ * - Select the type, pull-up/pull-down and output speed via \r
+ * GPIO_PuPd, GPIO_OType and GPIO_Speed members\r
+ * - Call GPIO_Init() function\r
+ * \r
+ * 4. To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()\r
+ * \r
+ * 5. To set/reset the level of a pin configured in output mode use\r
+ * GPIO_SetBits()/GPIO_ResetBits()\r
+ * \r
+ * 6. During and just after reset, the alternate functions are not \r
+ * active and the GPIO pins are configured in input floating mode\r
+ * (except JTAG pins).\r
+ *\r
+ * 7. The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as \r
+ * general-purpose (PC14 and PC15, respectively) when the LSE\r
+ * oscillator is off. The LSE has priority over the GPIO function.\r
+ *\r
+ * 8. The HSE oscillator pins OSC_IN/OSC_OUT can be used as \r
+ * general-purpose PH0 and PH1, respectively, when the HSE \r
+ * oscillator is off. The HSE has priority over the GPIO function.\r
+ * \r
+ * @endverbatim \r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_gpio.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup GPIO \r
+ * @brief GPIO driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup GPIO_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup GPIO_Group1 Initialization and Configuration\r
+ * @brief Initialization and Configuration\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Initialization and Configuration\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the GPIOx peripheral registers to their default reset \r
+ * values.\r
+ * By default, The GPIO pins are configured in input floating mode\r
+ * (except JTAG pins).\r
+ * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+ * @retval None\r
+ */\r
+void GPIO_DeInit(GPIO_TypeDef* GPIOx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+\r
+ if(GPIOx == GPIOA)\r
+ {\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, ENABLE);\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, DISABLE); \r
+ }\r
+ else if(GPIOx == GPIOB)\r
+ {\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, ENABLE);\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, DISABLE);\r
+ }\r
+ else if(GPIOx == GPIOC)\r
+ {\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, ENABLE);\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, DISABLE);\r
+ }\r
+ else if(GPIOx == GPIOD)\r
+ {\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, ENABLE);\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, DISABLE);\r
+ }\r
+ else if(GPIOx == GPIOE)\r
+ {\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, ENABLE);\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, DISABLE);\r
+ }\r
+ else\r
+ {\r
+ if(GPIOx == GPIOH)\r
+ {\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOH, ENABLE);\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOH, DISABLE);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the GPIOx peripheral according to the specified \r
+ * parameters in the GPIO_InitStruct.\r
+ * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+ * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that \r
+ * contains the configuration information for the specified GPIO\r
+ * peripheral.\r
+ * GPIO_Pin: selects the pin to be configured: GPIO_Pin_0 -> GPIO_Pin_15\r
+ * GPIO_Mode: selects the mode of the pin: \r
+ * - Input mode: GPIO_Mode_IN\r
+ * - Output mode: GPIO_Mode_OUT\r
+ * - Alternate Function mode: GPIO_Mode_AF\r
+ * - Analog mode: GPIO_Mode_AN\r
+ * GPIO_Speed: selects the speed of the pin if configured in Output:\r
+ * - Very Low: GPIO_Speed_400KHz\r
+ * - Low: GPIO_Speed_2MHz\r
+ * - Medium: GPIO_Speed_10MHz\r
+ * - High: GPIO_Speed_40MHz\r
+ * GPIO_OType: selects the Output type (if the selected mode is output):\r
+ * - Push-pull: GPIO_OType_PP\r
+ * - Open Drain: GPIO_OType_OD\r
+ * GPIO_PuPd: configures the Pull-up/Pull-down resistor on the pin:\r
+ * - pull-up: GPIO_PuPd_UP\r
+ * - pull-down: GPIO_PuPd_DOWN\r
+ * - Neither pull-up nor Pull-down: GPIO_PuPd_NOPULL\r
+ * @retval None\r
+ */\r
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)\r
+{\r
+ uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));\r
+ assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));\r
+ assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));\r
+\r
+ /* -------------------------Configure the port pins---------------- */\r
+ /*-- GPIO Mode Configuration --*/\r
+ for (pinpos = 0x00; pinpos < 0x10; pinpos++)\r
+ {\r
+ pos = ((uint32_t)0x01) << pinpos;\r
+\r
+ /* Get the port pins position */\r
+ currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;\r
+\r
+ if (currentpin == pos)\r
+ {\r
+ GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2));\r
+\r
+ GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));\r
+\r
+ if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))\r
+ {\r
+ /* Check Speed mode parameters */\r
+ assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));\r
+\r
+ /* Speed mode configuration */\r
+ GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));\r
+ GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));\r
+\r
+ /*Check Output mode parameters */\r
+ assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));\r
+\r
+ /* Output mode configuration */\r
+ GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ;\r
+ GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));\r
+ }\r
+\r
+ /* Pull-up Pull down resistor configuration */\r
+ GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));\r
+ GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Fills each GPIO_InitStruct member with its default value.\r
+ * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will \r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)\r
+{\r
+ /* Reset GPIO init structure parameters values */\r
+ GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;\r
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;\r
+ GPIO_InitStruct->GPIO_Speed = GPIO_Speed_400KHz;\r
+ GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;\r
+ GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;\r
+}\r
+\r
+/**\r
+ * @brief Locks GPIO Pins configuration registers.\r
+ * The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,\r
+ * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.\r
+ * The configuration of the locked GPIO pins can no longer be modified\r
+ * until the next reset.\r
+ * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bit to be written.\r
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
+ * @retval None\r
+ */\r
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ uint32_t tmp = 0x00010000;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+ \r
+ tmp |= GPIO_Pin;\r
+ /* Set LCKK bit */\r
+ GPIOx->LCKR = tmp;\r
+ /* Reset LCKK bit */\r
+ GPIOx->LCKR = GPIO_Pin;\r
+ /* Set LCKK bit */\r
+ GPIOx->LCKR = tmp;\r
+ /* Read LCKK bit*/\r
+ tmp = GPIOx->LCKR;\r
+ /* Read LCKK bit*/\r
+ tmp = GPIOx->LCKR;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Group2 GPIO Read and Write\r
+ * @brief GPIO Read and Write\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ GPIO Read and Write\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Reads the specified input port pin.\r
+ * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bit to read.\r
+ * This parameter can be GPIO_Pin_x where x can be (0..15).\r
+ * @retval The input port pin value.\r
+ */\r
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ uint8_t bitstatus = 0x00;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));\r
+\r
+ if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)\r
+ {\r
+ bitstatus = (uint8_t)Bit_SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = (uint8_t)Bit_RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Reads the specified GPIO input data port.\r
+ * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+ * @retval GPIO input data port value.\r
+ */\r
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ \r
+ return ((uint16_t)GPIOx->IDR);\r
+}\r
+\r
+/**\r
+ * @brief Reads the specified output data port bit.\r
+ * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: Specifies the port bit to read.\r
+ * This parameter can be GPIO_Pin_x where x can be (0..15).\r
+ * @retval The output port pin value.\r
+ */\r
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ uint8_t bitstatus = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));\r
+ \r
+ if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)\r
+ {\r
+ bitstatus = (uint8_t)Bit_SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = (uint8_t)Bit_RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Reads the specified GPIO output data port.\r
+ * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+ * @retval GPIO output data port value.\r
+ */\r
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ \r
+ return ((uint16_t)GPIOx->ODR);\r
+}\r
+\r
+/**\r
+ * @brief Sets the selected data port bits.\r
+ * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bits to be written.\r
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
+ * @note This functions uses GPIOx_BSRR register to allow atomic read/modify \r
+ * accesses. In this way, there is no risk of an IRQ occurring between\r
+ * the read and the modify access.\r
+ * @retval None\r
+ */\r
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+ \r
+ GPIOx->BSRRL = GPIO_Pin;\r
+}\r
+\r
+/**\r
+ * @brief Clears the selected data port bits.\r
+ * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bits to be written.\r
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
+ * @note This functions uses GPIOx_BSRR register to allow atomic read/modify \r
+ * accesses. In this way, there is no risk of an IRQ occurring between\r
+ * the read and the modify access.\r
+ * @retval None\r
+ */\r
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+ \r
+ GPIOx->BSRRH = GPIO_Pin;\r
+}\r
+\r
+/**\r
+ * @brief Sets or clears the selected data port bit.\r
+ * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bit to be written.\r
+ * This parameter can be one of GPIO_Pin_x where x can be (0..15).\r
+ * @param BitVal: specifies the value to be written to the selected bit.\r
+ * This parameter can be one of the BitAction enum values:\r
+ * @arg Bit_RESET: to clear the port pin\r
+ * @arg Bit_SET: to set the port pin\r
+ * @retval None\r
+ */\r
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));\r
+ assert_param(IS_GPIO_BIT_ACTION(BitVal));\r
+ \r
+ if (BitVal != Bit_RESET)\r
+ {\r
+ GPIOx->BSRRL = GPIO_Pin;\r
+ }\r
+ else\r
+ {\r
+ GPIOx->BSRRH = GPIO_Pin ;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Writes data to the specified GPIO data port.\r
+ * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+ * @param PortVal: specifies the value to be written to the port output data \r
+ * register.\r
+ * @retval None\r
+ */\r
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ \r
+ GPIOx->ODR = PortVal;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Group3 GPIO Alternate functions configuration functions\r
+ * @brief GPIO Alternate functions configuration functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ GPIO Alternate functions configuration functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Changes the mapping of the specified pin.\r
+ * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+ * @param GPIO_PinSource: specifies the pin for the Alternate function.\r
+ * This parameter can be GPIO_PinSourcex where x can be (0..15).\r
+ * @param GPIO_AFSelection: selects the pin to used as Alternat function.\r
+ * This parameter can be one of the following values:\r
+ * @arg GPIO_AF_RTC_50Hz: RTC 50/60 Hz synchronization\r
+ * @arg GPIO_AF_MCO: Microcontroller clock output\r
+ * @arg GPIO_AF_RTC_AF1: Time stamp, Tamper, Alarm A out, Alarm B out,\r
+ * 512 Hz clock output (with an LSE oscillator of 32.768 kHz)\r
+ * @arg GPIO_AF_WKUP: wakeup\r
+ * @arg GPIO_AF_SWJ: SWJ (SW and JTAG)\r
+ * @arg GPIO_AF_TRACE\r
+ * @arg GPIO_AF_TIM2\r
+ * @arg GPIO_AF_TIM3\r
+ * @arg GPIO_AF_TIM4\r
+ * @arg GPIO_AF_TIM9\r
+ * @arg GPIO_AF_TIM10\r
+ * @arg GPIO_AF_TIM11\r
+ * @arg GPIO_AF_I2C1\r
+ * @arg GPIO_AF_I2C2\r
+ * @arg GPIO_AF_SPI1\r
+ * @arg GPIO_AF_SPI2\r
+ * @arg GPIO_AF_USART1\r
+ * @arg GPIO_AF_USART2\r
+ * @arg GPIO_AF_USART3\r
+ * @arg GPIO_AF_USB\r
+ * @arg GPIO_AF_LCD\r
+ * @arg GPIO_AF_RI\r
+ * @arg GPIO_AF_EVENTOUT: Cortex-M3 EVENTOUT signal\r
+ * @note: The pin should already been configured in Alternate Function mode(AF)\r
+ * using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF\r
+ * @note: Please refer to the Alternate function mapping table in the device \r
+ * datasheet for the detailed mapping of the system and peripherals\92\r
+ * alternate function I/O pins. \r
+ * @note: EVENTOUT is not mapped on PH0, PH1 and PH2. \r
+ * @retval None\r
+ */\r
+void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)\r
+{\r
+ uint32_t temp = 0x00;\r
+ uint32_t temp_2 = 0x00;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));\r
+ assert_param(IS_GPIO_AF(GPIO_AF));\r
+ \r
+ temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;\r
+ GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;\r
+ temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;\r
+ GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_i2c.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Inter-integrated circuit (I2C)\r
+ * - Initialization and Configuration\r
+ * - Data transfers\r
+ * - PEC management\r
+ * - DMA transfers management\r
+ * - Interrupts, events and flags management \r
+ * \r
+ * @verbatim\r
+ * \r
+ * ===================================================================\r
+ * How to use this driver\r
+ * ===================================================================\r
+ * 1. Enable peripheral clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2Cx, ENABLE)\r
+ * function for I2C1 or I2C2.\r
+ *\r
+ * 2. Enable SDA, SCL and SMBA (when used) GPIO clocks using \r
+ * RCC_AHBPeriphClockCmd() function. \r
+ *\r
+ * 3. Peripherals alternate function: \r
+ * - Connect the pin to the desired peripherals' Alternate \r
+ * Function (AF) using GPIO_PinAFConfig() function\r
+ * - Configure the desired pin in alternate function by:\r
+ * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF\r
+ * - Select the type, pull-up/pull-down and output speed via \r
+ * GPIO_PuPd, GPIO_OType and GPIO_Speed members\r
+ * - Call GPIO_Init() function\r
+ * \r
+ * 4. Program the Mode, duty cycle , Own address, Ack, Speed and Acknowledged\r
+ * Address using the I2C_Init() function.\r
+ *\r
+ * 5. Optionally you can enable/configure the following parameters without\r
+ * re-initialization (i.e there is no need to call again I2C_Init() function):\r
+ * - Enable the acknowledge feature using I2C_AcknowledgeConfig() function\r
+ * - Enable the dual addressing mode using I2C_DualAddressCmd() function\r
+ * - Enable the general call using the I2C_GeneralCallCmd() function\r
+ * - Enable the clock stretching using I2C_StretchClockCmd() function\r
+ * - Enable the fast mode duty cycle using the I2C_FastModeDutyCycleConfig()\r
+ * function\r
+ * - Enable the PEC Calculation using I2C_CalculatePEC() function\r
+ * - For SMBus Mode: \r
+ * - Enable the Address Resolution Protocol (ARP) using I2C_ARPCmd() function\r
+ * - Configure the SMBusAlert pin using I2C_SMBusAlertConfig() function\r
+ *\r
+ * 6. Enable the NVIC and the corresponding interrupt using the function \r
+ * I2C_ITConfig() if you need to use interrupt mode. \r
+ *\r
+ * 7. When using the DMA mode \r
+ * - Configure the DMA using DMA_Init() function\r
+ * - Active the needed channel Request using I2C_DMACmd() or\r
+ I2C_DMALastTransferCmd() function\r
+ * \r
+ * 8. Enable the I2C using the I2C_Cmd() function.\r
+ * \r
+ * 9. Enable the DMA using the DMA_Cmd() function when using DMA mode in the \r
+ * transfers. \r
+ *\r
+ * @endverbatim\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_i2c.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup I2C \r
+ * @brief I2C driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+\r
+#define CR1_CLEAR_MASK ((uint16_t)0xFBF5) /*<! I2C registers Masks */\r
+#define FLAG_MASK ((uint32_t)0x00FFFFFF) /*<! I2C FLAG mask */\r
+#define ITEN_MASK ((uint32_t)0x07000000) /*<! I2C Interrupt Enable mask */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup I2C_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup I2C_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Initialization and Configuration functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the I2Cx peripheral registers to their default reset values.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @retval None\r
+ */\r
+void I2C_DeInit(I2C_TypeDef* I2Cx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+\r
+ if (I2Cx == I2C1)\r
+ {\r
+ /* Enable I2C1 reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);\r
+ /* Release I2C1 from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);\r
+ }\r
+ else\r
+ {\r
+ /* Enable I2C2 reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);\r
+ /* Release I2C2 from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the I2Cx peripheral according to the specified \r
+ * parameters in the I2C_InitStruct.\r
+ * @note To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency \r
+ * (I2C peripheral input clock) must be a multiple of 10 MHz. \r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that\r
+ * contains the configuration information for the specified I2C peripheral.\r
+ * @retval None\r
+ */\r
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)\r
+{\r
+ uint16_t tmpreg = 0, freqrange = 0;\r
+ uint16_t result = 0x04;\r
+ uint32_t pclk1 = 8000000;\r
+ RCC_ClocksTypeDef rcc_clocks;\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed));\r
+ assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));\r
+ assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle));\r
+ assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));\r
+ assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack));\r
+ assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));\r
+\r
+/*---------------------------- I2Cx CR2 Configuration ------------------------*/\r
+ /* Get the I2Cx CR2 value */\r
+ tmpreg = I2Cx->CR2;\r
+ /* Clear frequency FREQ[5:0] bits */\r
+ tmpreg &= (uint16_t)~((uint16_t)I2C_CR2_FREQ);\r
+ /* Get pclk1 frequency value */\r
+ RCC_GetClocksFreq(&rcc_clocks);\r
+ pclk1 = rcc_clocks.PCLK1_Frequency;\r
+ /* Set frequency bits depending on pclk1 value */\r
+ freqrange = (uint16_t)(pclk1 / 1000000);\r
+ tmpreg |= freqrange;\r
+ /* Write to I2Cx CR2 */\r
+ I2Cx->CR2 = tmpreg;\r
+\r
+/*---------------------------- I2Cx CCR Configuration ------------------------*/\r
+ /* Disable the selected I2C peripheral to configure TRISE */\r
+ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE);\r
+ /* Reset tmpreg value */\r
+ /* Clear F/S, DUTY and CCR[11:0] bits */\r
+ tmpreg = 0;\r
+\r
+ /* Configure speed in standard mode */\r
+ if (I2C_InitStruct->I2C_ClockSpeed <= 100000)\r
+ {\r
+ /* Standard mode speed calculate */\r
+ result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));\r
+ /* Test if CCR value is under 0x4*/\r
+ if (result < 0x04)\r
+ {\r
+ /* Set minimum allowed value */\r
+ result = 0x04; \r
+ }\r
+ /* Set speed value for standard mode */\r
+ tmpreg |= result; \r
+ /* Set Maximum Rise Time for standard mode */\r
+ I2Cx->TRISE = freqrange + 1; \r
+ }\r
+ /* Configure speed in fast mode */\r
+ /* To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency (I2C peripheral\r
+ input clock) must be a multiple of 10 MHz */\r
+ else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/\r
+ {\r
+ if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)\r
+ {\r
+ /* Fast mode speed calculate: Tlow/Thigh = 2 */\r
+ result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));\r
+ }\r
+ else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/\r
+ {\r
+ /* Fast mode speed calculate: Tlow/Thigh = 16/9 */\r
+ result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));\r
+ /* Set DUTY bit */\r
+ result |= I2C_DutyCycle_16_9;\r
+ }\r
+\r
+ /* Test if CCR value is under 0x1*/\r
+ if ((result & I2C_CCR_CCR) == 0)\r
+ {\r
+ /* Set minimum allowed value */\r
+ result |= (uint16_t)0x0001; \r
+ }\r
+ /* Set speed value and set F/S bit for fast mode */\r
+ tmpreg |= (uint16_t)(result | I2C_CCR_FS);\r
+ /* Set Maximum Rise Time for fast mode */\r
+ I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); \r
+ }\r
+\r
+ /* Write to I2Cx CCR */\r
+ I2Cx->CCR = tmpreg;\r
+ /* Enable the selected I2C peripheral */\r
+ I2Cx->CR1 |= I2C_CR1_PE;\r
+\r
+/*---------------------------- I2Cx CR1 Configuration ------------------------*/\r
+ /* Get the I2Cx CR1 value */\r
+ tmpreg = I2Cx->CR1;\r
+ /* Clear ACK, SMBTYPE and SMBUS bits */\r
+ tmpreg &= CR1_CLEAR_MASK;\r
+ /* Configure I2Cx: mode and acknowledgement */\r
+ /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */\r
+ /* Set ACK bit according to I2C_Ack value */\r
+ tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);\r
+ /* Write to I2Cx CR1 */\r
+ I2Cx->CR1 = tmpreg;\r
+\r
+/*---------------------------- I2Cx OAR1 Configuration -----------------------*/\r
+ /* Set I2Cx Own Address1 and acknowledged address */\r
+ I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);\r
+}\r
+\r
+/**\r
+ * @brief Fills each I2C_InitStruct member with its default value.\r
+ * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)\r
+{\r
+/*---------------- Reset I2C init structure parameters values ----------------*/\r
+ /* initialize the I2C_ClockSpeed member */\r
+ I2C_InitStruct->I2C_ClockSpeed = 5000;\r
+ /* Initialize the I2C_Mode member */\r
+ I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;\r
+ /* Initialize the I2C_DutyCycle member */\r
+ I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;\r
+ /* Initialize the I2C_OwnAddress1 member */\r
+ I2C_InitStruct->I2C_OwnAddress1 = 0;\r
+ /* Initialize the I2C_Ack member */\r
+ I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;\r
+ /* Initialize the I2C_AcknowledgedAddress member */\r
+ I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C peripheral.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2Cx peripheral. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C peripheral */\r
+ I2Cx->CR1 |= I2C_CR1_PE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C peripheral */\r
+ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Generates I2Cx communication START condition.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C START condition generation.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None.\r
+ */\r
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Generate a START condition */\r
+ I2Cx->CR1 |= I2C_CR1_START;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the START condition generation */\r
+ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_START);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Generates I2Cx communication STOP condition.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C STOP condition generation.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None.\r
+ */\r
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Generate a STOP condition */\r
+ I2Cx->CR1 |= I2C_CR1_STOP;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the STOP condition generation */\r
+ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_STOP);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C acknowledge feature.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C Acknowledgement.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None.\r
+ */\r
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the acknowledgement */\r
+ I2Cx->CR1 |= I2C_CR1_ACK;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the acknowledgement */\r
+ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ACK);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the specified I2C own address2.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param Address: specifies the 7bit I2C own address2.\r
+ * @retval None.\r
+ */\r
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address)\r
+{\r
+ uint16_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+\r
+ /* Get the old register value */\r
+ tmpreg = I2Cx->OAR2;\r
+\r
+ /* Reset I2Cx Own address2 bit [7:1] */\r
+ tmpreg &= (uint16_t)~((uint16_t)I2C_OAR2_ADD2);\r
+\r
+ /* Set I2Cx Own address2 */\r
+ tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);\r
+\r
+ /* Store the new register value */\r
+ I2Cx->OAR2 = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C dual addressing mode.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C dual addressing mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable dual addressing mode */\r
+ I2Cx->OAR2 |= I2C_OAR2_ENDUAL;\r
+ }\r
+ else\r
+ {\r
+ /* Disable dual addressing mode */\r
+ I2Cx->OAR2 &= (uint16_t)~((uint16_t)I2C_OAR2_ENDUAL);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C general call feature.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C General call.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable generall call */\r
+ I2Cx->CR1 |= I2C_CR1_ENGC;\r
+ }\r
+ else\r
+ {\r
+ /* Disable generall call */\r
+ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENGC);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C software reset.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C software reset.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Peripheral under reset */\r
+ I2Cx->CR1 |= I2C_CR1_SWRST;\r
+ }\r
+ else\r
+ {\r
+ /* Peripheral not under reset */\r
+ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_SWRST);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Drives the SMBusAlert pin high or low for the specified I2C.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_SMBusAlert: specifies SMBAlert pin level. \r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low\r
+ * @arg I2C_SMBusAlert_High: SMBAlert pin driven high\r
+ * @retval None\r
+ */\r
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert));\r
+ if (I2C_SMBusAlert == I2C_SMBusAlert_Low)\r
+ {\r
+ /* Drive the SMBusAlert pin Low */\r
+ I2Cx->CR1 |= I2C_SMBusAlert_Low;\r
+ }\r
+ else\r
+ {\r
+ /* Drive the SMBusAlert pin High */\r
+ I2Cx->CR1 &= I2C_SMBusAlert_High;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C ARP.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2Cx ARP. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C ARP */\r
+ I2Cx->CR1 |= I2C_CR1_ENARP;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C ARP */\r
+ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENARP);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C Clock stretching.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2Cx Clock stretching.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState == DISABLE)\r
+ {\r
+ /* Enable the selected I2C Clock stretching */\r
+ I2Cx->CR1 |= I2C_CR1_NOSTRETCH;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C Clock stretching */\r
+ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_NOSTRETCH);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the specified I2C fast mode duty cycle.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_DutyCycle: specifies the fast mode duty cycle.\r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2\r
+ * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9\r
+ * @retval None\r
+ */\r
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle));\r
+ if (I2C_DutyCycle != I2C_DutyCycle_16_9)\r
+ {\r
+ /* I2C fast mode Tlow/Thigh=2 */\r
+ I2Cx->CCR &= I2C_DutyCycle_2;\r
+ }\r
+ else\r
+ {\r
+ /* I2C fast mode Tlow/Thigh=16/9 */\r
+ I2Cx->CCR |= I2C_DutyCycle_16_9;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Transmits the address byte to select the slave device.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param Address: specifies the slave address which will be transmitted\r
+ * @param I2C_Direction: specifies whether the I2C device will be a\r
+ * Transmitter or a Receiver. This parameter can be one of the following values\r
+ * @arg I2C_Direction_Transmitter: Transmitter mode\r
+ * @arg I2C_Direction_Receiver: Receiver mode\r
+ * @retval None.\r
+ */\r
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_DIRECTION(I2C_Direction));\r
+ /* Test on the direction to set/reset the read/write bit */\r
+ if (I2C_Direction != I2C_Direction_Transmitter)\r
+ {\r
+ /* Set the address bit0 for read */\r
+ Address |= I2C_OAR1_ADD0;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the address bit0 for write */\r
+ Address &= (uint8_t)~((uint8_t)I2C_OAR1_ADD0);\r
+ }\r
+ /* Send the address */\r
+ I2Cx->DR = Address;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Group2 Data transfers functions\r
+ * @brief Data transfers functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Data transfers functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sends a data byte through the I2Cx peripheral.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param Data: Byte to be transmitted..\r
+ * @retval None\r
+ */\r
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ /* Write in the DR register the data to be sent */\r
+ I2Cx->DR = Data;\r
+}\r
+\r
+/**\r
+ * @brief Returns the most recent received data by the I2Cx peripheral.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @retval The value of the received data.\r
+ */\r
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ /* Return the data in the DR register */\r
+ return (uint8_t)I2Cx->DR;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Group3 PEC management functions\r
+ * @brief PEC management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ PEC management functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C PEC transfer.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C PEC transmission.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C PEC transmission */\r
+ I2Cx->CR1 |= I2C_CR1_PEC;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C PEC transmission */\r
+ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PEC);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the specified I2C PEC position.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_PECPosition: specifies the PEC position. \r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_PECPosition_Next: indicates that the next byte is PEC\r
+ * @arg I2C_PECPosition_Current: indicates that current byte is PEC\r
+ * @retval None\r
+ */\r
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition));\r
+ if (I2C_PECPosition == I2C_PECPosition_Next)\r
+ {\r
+ /* Next byte in shift register is PEC */\r
+ I2Cx->CR1 |= I2C_PECPosition_Next;\r
+ }\r
+ else\r
+ {\r
+ /* Current byte in shift register is PEC */\r
+ I2Cx->CR1 &= I2C_PECPosition_Current;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the PEC value calculation of the transferred bytes.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2Cx PEC value calculation.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C PEC calculation */\r
+ I2Cx->CR1 |= I2C_CR1_ENPEC;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C PEC calculation */\r
+ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENPEC);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the PEC value for the specified I2C.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @retval The PEC value.\r
+ */\r
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ /* Return the selected I2C PEC value */\r
+ return ((I2Cx->SR2) >> 8);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Group4 DMA transfers management functions\r
+ * @brief DMA transfers management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ DMA transfers management functions\r
+ =============================================================================== \r
+ This section provides functions allowing to configure the I2C DMA channels \r
+ requests.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C DMA requests.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C DMA transfer.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C DMA requests */\r
+ I2Cx->CR2 |= I2C_CR2_DMAEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C DMA requests */\r
+ I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_DMAEN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Specifies that the next DMA transfer is the last one.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C DMA last transfer.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Next DMA transfer is the last transfer */\r
+ I2Cx->CR2 |= I2C_CR2_LAST;\r
+ }\r
+ else\r
+ {\r
+ /* Next DMA transfer is not the last transfer */\r
+ I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_LAST);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Group5 Interrupts events and flags management functions\r
+ * @brief Interrupts, events and flags management functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Interrupts, events and flags management functions\r
+ =============================================================================== \r
+ This section provides functions allowing to configure the I2C Interrupts \r
+ sources and check or clear the flags or pending bits status.\r
+ The user should identify which mode will be used in his application to manage \r
+ the communication: Polling mode, Interrupt mode or DMA mode. \r
+\r
+ ===============================================================================\r
+ I2C State Monitoring Functions \r
+ =============================================================================== \r
+ This I2C driver provides three different ways for I2C state monitoring\r
+ depending on the application requirements and constraints:\r
+ \r
+ \r
+ 1. Basic state monitoring (Using I2C_CheckEvent() function)\r
+ -----------------------------------------------------------\r
+ It compares the status registers (SR1 and SR2) content to a given event\r
+ (can be the combination of one or more flags).\r
+ It returns SUCCESS if the current status includes the given flags \r
+ and returns ERROR if one or more flags are missing in the current status.\r
+\r
+ - When to use\r
+ - This function is suitable for most applications as well as for startup \r
+ activity since the events are fully described in the product reference \r
+ manual (RM0038).\r
+ - It is also suitable for users who need to define their own events.\r
+\r
+ - Limitations\r
+ - If an error occurs (ie. error flags are set besides to the monitored \r
+ flags), the I2C_CheckEvent() function may return SUCCESS despite \r
+ the communication hold or corrupted real state. \r
+ In this case, it is advised to use error interrupts to monitor \r
+ the error events and handle them in the interrupt IRQ handler.\r
+ \r
+ @note \r
+ For error management, it is advised to use the following functions:\r
+ - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).\r
+ - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.\r
+ Where x is the peripheral instance (I2C1, I2C2 ...)\r
+ - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the \r
+ I2Cx_ER_IRQHandler() function in order to determine which error occurred.\r
+ - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() \r
+ and/or I2C_GenerateStop() in order to clear the error flag and source \r
+ and return to correct communication status.\r
+ \r
+ \r
+ 2. Advanced state monitoring (Using the function I2C_GetLastEvent())\r
+ -------------------------------------------------------------------- \r
+ Using the function I2C_GetLastEvent() which returns the image of both status \r
+ registers in a single word (uint32_t) (Status Register 2 value is shifted left \r
+ by 16 bits and concatenated to Status Register 1).\r
+\r
+ - When to use\r
+ - This function is suitable for the same applications above but it \r
+ allows to overcome the mentioned limitation of I2C_GetFlagStatus() \r
+ function.\r
+ - The returned value could be compared to events already defined in \r
+ the library (stm32l1xx_i2c.h) or to custom values defined by user.\r
+ This function is suitable when multiple flags are monitored at the \r
+ same time.\r
+ - At the opposite of I2C_CheckEvent() function, this function allows \r
+ user to choose when an event is accepted (when all events flags are \r
+ set and no other flags are set or just when the needed flags are set \r
+ like I2C_CheckEvent() function.\r
+\r
+ - Limitations\r
+ - User may need to define his own events.\r
+ - Same remark concerning the error management is applicable for this \r
+ function if user decides to check only regular communication flags \r
+ (and ignores error flags).\r
+ \r
+ \r
+ 3. Flag-based state monitoring (Using the function I2C_GetFlagStatus())\r
+ -----------------------------------------------------------------------\r
+ \r
+ Using the function I2C_GetFlagStatus() which simply returns the status of \r
+ one single flag (ie. I2C_FLAG_RXNE ...). \r
+\r
+ - When to use\r
+ - This function could be used for specific applications or in debug \r
+ phase.\r
+ - It is suitable when only one flag checking is needed (most I2C \r
+ events are monitored through multiple flags).\r
+ - Limitations: \r
+ - When calling this function, the Status register is accessed. \r
+ Some flags are cleared when the status register is accessed. \r
+ So checking the status of one Flag, may clear other ones.\r
+ - Function may need to be called twice or more in order to monitor \r
+ one single event.\r
+ \r
+ For detailed description of Events, please refer to section I2C_Events in \r
+ stm32l1xx_i2c.h file.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Reads the specified I2C register and returns its value.\r
+ * @param I2C_Register: specifies the register to read.\r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_Register_CR1: CR1 register.\r
+ * @arg I2C_Register_CR2: CR2 register.\r
+ * @arg I2C_Register_OAR1: OAR1 register.\r
+ * @arg I2C_Register_OAR2: OAR2 register.\r
+ * @arg I2C_Register_DR: DR register.\r
+ * @arg I2C_Register_SR1: SR1 register.\r
+ * @arg I2C_Register_SR2: SR2 register.\r
+ * @arg I2C_Register_CCR: CCR register.\r
+ * @arg I2C_Register_TRISE: TRISE register.\r
+ * @retval The value of the read register.\r
+ */\r
+uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_REGISTER(I2C_Register));\r
+\r
+ tmp = (uint32_t) I2Cx;\r
+ tmp += I2C_Register;\r
+\r
+ /* Return the selected register value */\r
+ return (*(__IO uint16_t *) tmp);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C interrupts.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg I2C_IT_BUF: Buffer interrupt mask\r
+ * @arg I2C_IT_EVT: Event interrupt mask\r
+ * @arg I2C_IT_ERR: Error interrupt mask\r
+ * @param NewState: new state of the specified I2C interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_I2C_CONFIG_IT(I2C_IT));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C interrupts */\r
+ I2Cx->CR2 |= I2C_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C interrupts */\r
+ I2Cx->CR2 &= (uint16_t)~I2C_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ ===============================================================================\r
+ 1. Basic state monitoring \r
+ =============================================================================== \r
+ */\r
+\r
+/**\r
+ * @brief Checks whether the last I2Cx Event is equal to the one passed\r
+ * as parameter.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_EVENT: specifies the event to be checked. \r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : EV1\r
+ * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : EV1\r
+ * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED : EV1\r
+ * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED : EV1\r
+ * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : EV1\r
+ * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2\r
+ * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) : EV2\r
+ * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) : EV2\r
+ * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3\r
+ * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) : EV3\r
+ * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) : EV3\r
+ * @arg I2C_EVENT_SLAVE_ACK_FAILURE : EV3_2\r
+ * @arg I2C_EVENT_SLAVE_STOP_DETECTED : EV4\r
+ * @arg I2C_EVENT_MASTER_MODE_SELECT : EV5\r
+ * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : EV6 \r
+ * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : EV6\r
+ * @arg I2C_EVENT_MASTER_BYTE_RECEIVED : EV7\r
+ * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING : EV8\r
+ * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8_2\r
+ * @arg I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9\r
+ * \r
+ * @note: For detailed description of Events, please refer to section \r
+ * I2C_Events in stm32l1xx_i2c.h file.\r
+ * \r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: Last event is equal to the I2C_EVENT\r
+ * - ERROR: Last event is different from the I2C_EVENT\r
+ */\r
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT)\r
+{\r
+ uint32_t lastevent = 0;\r
+ uint32_t flag1 = 0, flag2 = 0;\r
+ ErrorStatus status = ERROR;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_EVENT(I2C_EVENT));\r
+\r
+ /* Read the I2Cx status register */\r
+ flag1 = I2Cx->SR1;\r
+ flag2 = I2Cx->SR2;\r
+ flag2 = flag2 << 16;\r
+\r
+ /* Get the last event value from I2C status register */\r
+ lastevent = (flag1 | flag2) & FLAG_MASK;\r
+\r
+ /* Check whether the last event contains the I2C_EVENT */\r
+ if ((lastevent & I2C_EVENT) == I2C_EVENT)\r
+ {\r
+ /* SUCCESS: last event is equal to I2C_EVENT */\r
+ status = SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ /* ERROR: last event is different from I2C_EVENT */\r
+ status = ERROR;\r
+ }\r
+ /* Return status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ ===============================================================================\r
+ 2. Advanced state monitoring \r
+ =============================================================================== \r
+ */\r
+\r
+/**\r
+ * @brief Returns the last I2Cx Event.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * \r
+ * @note: For detailed description of Events, please refer to section \r
+ * I2C_Events in stm32l1xx_i2c.h file.\r
+ * \r
+ * @retval The last event\r
+ */\r
+uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx)\r
+{\r
+ uint32_t lastevent = 0;\r
+ uint32_t flag1 = 0, flag2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+\r
+ /* Read the I2Cx status register */\r
+ flag1 = I2Cx->SR1;\r
+ flag2 = I2Cx->SR2;\r
+ flag2 = flag2 << 16;\r
+\r
+ /* Get the last event value from I2C status register */\r
+ lastevent = (flag1 | flag2) & FLAG_MASK;\r
+\r
+ /* Return status */\r
+ return lastevent;\r
+}\r
+\r
+/**\r
+ ===============================================================================\r
+ 3. Flag-based state monitoring \r
+ =============================================================================== \r
+ */\r
+\r
+/**\r
+ * @brief Checks whether the specified I2C flag is set or not.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_FLAG: specifies the flag to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_FLAG_DUALF: Dual flag (Slave mode)\r
+ * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode)\r
+ * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)\r
+ * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode)\r
+ * @arg I2C_FLAG_TRA: Transmitter/Receiver flag\r
+ * @arg I2C_FLAG_BUSY: Bus busy flag\r
+ * @arg I2C_FLAG_MSL: Master/Slave flag\r
+ * @arg I2C_FLAG_SMBALERT: SMBus Alert flag\r
+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag\r
+ * @arg I2C_FLAG_PECERR: PEC error in reception flag\r
+ * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)\r
+ * @arg I2C_FLAG_AF: Acknowledge failure flag\r
+ * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)\r
+ * @arg I2C_FLAG_BERR: Bus error flag\r
+ * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter)\r
+ * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag\r
+ * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode)\r
+ * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)\r
+ * @arg I2C_FLAG_BTF: Byte transfer finished flag\r
+ * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) \93ADSL\94\r
+ * Address matched flag (Slave mode)\94ENDAD\94\r
+ * @arg I2C_FLAG_SB: Start bit flag (Master mode)\r
+ * @retval The new state of I2C_FLAG (SET or RESET).\r
+ */\r
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ __IO uint32_t i2creg = 0, i2cxbase = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_GET_FLAG(I2C_FLAG));\r
+\r
+ /* Get the I2Cx peripheral base address */\r
+ i2cxbase = (uint32_t)I2Cx;\r
+ \r
+ /* Read flag register index */\r
+ i2creg = I2C_FLAG >> 28;\r
+ \r
+ /* Get bit[23:0] of the flag */\r
+ I2C_FLAG &= FLAG_MASK;\r
+ \r
+ if(i2creg != 0)\r
+ {\r
+ /* Get the I2Cx SR1 register address */\r
+ i2cxbase += 0x14;\r
+ }\r
+ else\r
+ {\r
+ /* Flag in I2Cx SR2 Register */\r
+ I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);\r
+ /* Get the I2Cx SR2 register address */\r
+ i2cxbase += 0x18;\r
+ }\r
+ \r
+ if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)\r
+ {\r
+ /* I2C_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* I2C_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ \r
+ /* Return the I2C_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the I2Cx's pending flags.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_FLAG: specifies the flag to clear. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg I2C_FLAG_SMBALERT: SMBus Alert flag\r
+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag\r
+ * @arg I2C_FLAG_PECERR: PEC error in reception flag\r
+ * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)\r
+ * @arg I2C_FLAG_AF: Acknowledge failure flag\r
+ * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)\r
+ * @arg I2C_FLAG_BERR: Bus error flag\r
+ * \r
+ * @note\r
+ * - STOPF (STOP detection) is cleared by software sequence: a read operation \r
+ * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation \r
+ * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).\r
+ * - ADD10 (10-bit header sent) is cleared by software sequence: a read \r
+ * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the \r
+ * second byte of the address in DR register.\r
+ * - BTF (Byte Transfer Finished) is cleared by software sequence: a read \r
+ * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a \r
+ * read/write to I2C_DR register (I2C_SendData()).\r
+ * - ADDR (Address sent) is cleared by software sequence: a read operation to \r
+ * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to \r
+ * I2C_SR2 register ((void)(I2Cx->SR2)).\r
+ * - SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1\r
+ * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR\r
+ * register (I2C_SendData()).\r
+ * @retval None\r
+ */\r
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)\r
+{\r
+ uint32_t flagpos = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));\r
+ /* Get the I2C flag position */\r
+ flagpos = I2C_FLAG & FLAG_MASK;\r
+ /* Clear the selected I2C flag */\r
+ I2Cx->SR1 = (uint16_t)~flagpos;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified I2C interrupt has occurred or not.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_IT: specifies the interrupt source to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_IT_SMBALERT: SMBus Alert flag\r
+ * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag\r
+ * @arg I2C_IT_PECERR: PEC error in reception flag\r
+ * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode)\r
+ * @arg I2C_IT_AF: Acknowledge failure flag\r
+ * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode)\r
+ * @arg I2C_IT_BERR: Bus error flag\r
+ * @arg I2C_IT_TXE: Data register empty flag (Transmitter)\r
+ * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag\r
+ * @arg I2C_IT_STOPF: Stop detection flag (Slave mode)\r
+ * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode)\r
+ * @arg I2C_IT_BTF: Byte transfer finished flag\r
+ * @arg I2C_IT_ADDR: Address sent flag (Master mode) \93ADSL\94\r
+ * Address matched flag (Slave mode)\94ENDAD\94\r
+ * @arg I2C_IT_SB: Start bit flag (Master mode)\r
+ * @retval The new state of I2C_IT (SET or RESET).\r
+ */\r
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t enablestatus = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_GET_IT(I2C_IT));\r
+\r
+ /* Check if the interrupt source is enabled or not */\r
+ enablestatus = (uint32_t)(((I2C_IT & ITEN_MASK) >> 16) & (I2Cx->CR2)) ;\r
+ \r
+ /* Get bit[23:0] of the flag */\r
+ I2C_IT &= FLAG_MASK;\r
+\r
+ /* Check the status of the specified I2C flag */\r
+ if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus)\r
+ {\r
+ /* I2C_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* I2C_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the I2C_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the I2Cx\92s interrupt pending bits.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_IT: specifies the interrupt pending bit to clear. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg I2C_IT_SMBALERT: SMBus Alert interrupt\r
+ * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt\r
+ * @arg I2C_IT_PECERR: PEC error in reception interrupt\r
+ * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode)\r
+ * @arg I2C_IT_AF: Acknowledge failure interrupt\r
+ * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode)\r
+ * @arg I2C_IT_BERR: Bus error interrupt\r
+ * \r
+ * @note\r
+ * - STOPF (STOP detection) is cleared by software sequence: a read operation \r
+ * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to \r
+ * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).\r
+ * - ADD10 (10-bit header sent) is cleared by software sequence: a read \r
+ * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second \r
+ * byte of the address in I2C_DR register.\r
+ * - BTF (Byte Transfer Finished) is cleared by software sequence: a read \r
+ * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a \r
+ * read/write to I2C_DR register (I2C_SendData()).\r
+ * - ADDR (Address sent) is cleared by software sequence: a read operation to \r
+ * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to \r
+ * I2C_SR2 register ((void)(I2Cx->SR2)).\r
+ * - SB (Start Bit) is cleared by software sequence: a read operation to \r
+ * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to \r
+ * I2C_DR register (I2C_SendData()).\r
+ * @retval None\r
+ */\r
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)\r
+{\r
+ uint32_t flagpos = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_CLEAR_IT(I2C_IT));\r
+ /* Get the I2C flag position */\r
+ flagpos = I2C_IT & FLAG_MASK;\r
+ /* Clear the selected I2C flag */\r
+ I2Cx->SR1 = (uint16_t)~flagpos;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+\r
+\r
+\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_iwdg.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Independent watchdog (IWDG) peripheral: \r
+ * - Prescaler and Counter configuration\r
+ * - IWDG activation\r
+ * - Flag management\r
+ *\r
+ * @verbatim \r
+ * \r
+ * ===================================================================\r
+ * IWDG features\r
+ * ===================================================================\r
+ * \r
+ * The IWDG can be started by either software or hardware (configurable\r
+ * through option byte).\r
+ * \r
+ * The IWDG is clocked by its own dedicated low-speed clock (LSI) and\r
+ * thus stays active even if the main clock fails.\r
+ * Once the IWDG is started, the LSI is forced ON and cannot be disabled\r
+ * (LSI cannot be disabled too), and the counter starts counting down from \r
+ * the reset value of 0xFFF. When it reaches the end of count value (0x000)\r
+ * a system reset is generated.\r
+ * The IWDG counter should be reloaded at regular intervals to prevent\r
+ * an MCU reset.\r
+ * \r
+ * The IWDG is implemented in the VDD voltage domain that is still functional\r
+ * in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY) \r
+ * \r
+ * IWDGRST flag in RCC_CSR register can be used to inform when a IWDG\r
+ * reset occurs\r
+ * \r
+ * Min-max timeout value @37KHz (LSI): ~108us / ~28.3s\r
+ * The IWDG timeout may vary due to LSI frequency dispersion. STM32L1xx\r
+ * devices provide the capability to measure the LSI frequency (LSI clock\r
+ * connected internally to TIM10 CH1 input capture). The measured value\r
+ * can be used to have an IWDG timeout with an acceptable accuracy. \r
+ * For more information, please refer to the STM32L1xx Reference manual\r
+ * \r
+ * \r
+ * ===================================================================\r
+ * How to use this driver\r
+ * ===================================================================\r
+ * 1. Enable write access to IWDG_PR and IWDG_RLR registers using\r
+ * IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function\r
+ * \r
+ * 2. Configure the IWDG prescaler using IWDG_SetPrescaler() function\r
+ * \r
+ * 3. Configure the IWDG counter value using IWDG_SetReload() function.\r
+ * This value will be loaded in the IWDG counter each time the counter\r
+ * is reloaded, then the IWDG will start counting down from this value.\r
+ * \r
+ * 4. Start the IWDG using IWDG_Enable() function, when the IWDG is used\r
+ * in software mode (no need to enable the LSI, it will be enabled\r
+ * by hardware)\r
+ * \r
+ * 5. Then the application program must reload the IWDG counter at regular\r
+ * intervals during normal operation to prevent an MCU reset, using\r
+ * IWDG_ReloadCounter() function. \r
+ * \r
+ * @endverbatim\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_iwdg.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup IWDG \r
+ * @brief IWDG driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* ---------------------- IWDG registers bit mask ----------------------------*/\r
+/* KR register bit mask */\r
+#define KR_KEY_RELOAD ((uint16_t)0xAAAA)\r
+#define KR_KEY_ENABLE ((uint16_t)0xCCCC)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup IWDG_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions\r
+ * @brief Prescaler and Counter configuration functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Prescaler and Counter configuration functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.\r
+ * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.\r
+ * This parameter can be one of the following values:\r
+ * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers\r
+ * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers\r
+ * @retval None\r
+ */\r
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));\r
+ IWDG->KR = IWDG_WriteAccess;\r
+}\r
+\r
+/**\r
+ * @brief Sets IWDG Prescaler value.\r
+ * @param IWDG_Prescaler: specifies the IWDG Prescaler value.\r
+ * This parameter can be one of the following values:\r
+ * @arg IWDG_Prescaler_4: IWDG prescaler set to 4\r
+ * @arg IWDG_Prescaler_8: IWDG prescaler set to 8\r
+ * @arg IWDG_Prescaler_16: IWDG prescaler set to 16\r
+ * @arg IWDG_Prescaler_32: IWDG prescaler set to 32\r
+ * @arg IWDG_Prescaler_64: IWDG prescaler set to 64\r
+ * @arg IWDG_Prescaler_128: IWDG prescaler set to 128\r
+ * @arg IWDG_Prescaler_256: IWDG prescaler set to 256\r
+ * @retval None\r
+ */\r
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));\r
+ IWDG->PR = IWDG_Prescaler;\r
+}\r
+\r
+/**\r
+ * @brief Sets IWDG Reload value.\r
+ * @param Reload: specifies the IWDG Reload value.\r
+ * This parameter must be a number between 0 and 0x0FFF.\r
+ * @retval None\r
+ */\r
+void IWDG_SetReload(uint16_t Reload)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_IWDG_RELOAD(Reload));\r
+ IWDG->RLR = Reload;\r
+}\r
+\r
+/**\r
+ * @brief Reloads IWDG counter with value defined in the reload register\r
+ * (write access to IWDG_PR and IWDG_RLR registers disabled).\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void IWDG_ReloadCounter(void)\r
+{\r
+ IWDG->KR = KR_KEY_RELOAD;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IWDG_Group2 IWDG activation function\r
+ * @brief IWDG activation function \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ IWDG activation function\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void IWDG_Enable(void)\r
+{\r
+ IWDG->KR = KR_KEY_ENABLE;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IWDG_Group3 Flag management function \r
+ * @brief Flag management function \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Flag management function \r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Checks whether the specified IWDG flag is set or not.\r
+ * @param IWDG_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg IWDG_FLAG_PVU: Prescaler Value Update on going\r
+ * @arg IWDG_FLAG_RVU: Reload Value Update on going\r
+ * @retval The new state of IWDG_FLAG (SET or RESET).\r
+ */\r
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_IWDG_FLAG(IWDG_FLAG));\r
+ if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the flag status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_lcd.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the LCD controller (LCD) peripheral: \r
+ * - Initialization and configuration\r
+ * - LCD RAM memory write\r
+ * - Interrupts and flags management \r
+ * \r
+ * @verbatim\r
+ * \r
+ * =================================================================== \r
+ * LCD Clock\r
+ * =================================================================== \r
+ * LCDCLK is the same as RTCCLK. \r
+ * To configure the RTCCLK/LCDCLK, proceed as follows:\r
+ * - Enable the Power Controller (PWR) APB1 interface clock using the\r
+ * RCC_APB1PeriphClockCmd() function.\r
+ * - Enable access to RTC domain using the PWR_RTCAccessCmd() function.\r
+ * - Select the RTC clock source using the RCC_RTCCLKConfig() function. \r
+ * \r
+ * The frequency generator allows you to achieve various LCD frame rates \r
+ * starting from an LCD input clock frequency (LCDCLK) which can vary \r
+ * from 32 kHz up to 1 MHz.\r
+ * \r
+ * =================================================================== \r
+ * LCD and low power modes\r
+ * =================================================================== \r
+ * The LCD still active during STOP mode.\r
+ * \r
+ * ===================================================================\r
+ * How to use this driver\r
+ * =================================================================== \r
+ * 1. Enable LCD clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_LCD, ENABLE) function\r
+ * \r
+ * 2. Configure the LCD prescaler, divider, duty, bias and voltage source\r
+ * using LCD_Init() function \r
+ * \r
+ * 3. Optionally you can enable/configure:\r
+ * - LCD High Drive using the LCD_HighDriveCmd() function\r
+ * - LCD High Drive using the LCD_MuxSegmentCmd() function \r
+ * - LCD Pulse ON Duration using the LCD_PulseOnDurationConfig() function\r
+ * - LCD Dead Time using the LCD_DeadTimeConfig() function \r
+ * - The LCD Blink mode and frequency using the LCD_BlinkConfig() function\r
+ * - The LCD Contrast using the LCD_ContrastConfig() function \r
+ *\r
+ * 4. Call the LCD_WaitForSynchro() function to wait for LCD_FCR register\r
+ * synchronization.\r
+ * \r
+ * 5. Call the LCD_Cmd() to enable the LCD controller\r
+ * \r
+ * 6. Wait until the LCD Controller status is enabled and the step-up\r
+ * converter is ready using the LCD_GetFlagStatus() and\r
+ * LCD_FLAG_ENS and LCD_FLAG_RDY flags. \r
+ * \r
+ * 7. Write to the LCD RAM memory using the LCD_Write() function.\r
+ * \r
+ * 8. Request an update display using the LCD_UpdateDisplayRequest()\r
+ * function.\r
+ * \r
+ * 9. Wait until the update display is finished by checking the UDD\r
+ * flag status using the LCD_GetFlagStatus(LCD_FLAG_UDD)\r
+ * \r
+ * \r
+ * @endverbatim\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_lcd.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup LCD \r
+ * @brief LCD driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* ------------ LCD registers bit address in the alias region --------------- */\r
+#define LCD_OFFSET (LCD_BASE - PERIPH_BASE)\r
+\r
+/* --- CR Register ---*/\r
+\r
+/* Alias word address of LCDEN bit */\r
+#define CR_OFFSET (LCD_OFFSET + 0x00)\r
+#define LCDEN_BitNumber 0x00\r
+#define CR_LCDEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (LCDEN_BitNumber * 4))\r
+\r
+/* Alias word address of MUX_SEG bit */\r
+#define MUX_SEG_BitNumber 0x07\r
+#define CR_MUX_SEG_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MUX_SEG_BitNumber * 4))\r
+\r
+\r
+/* --- FCR Register ---*/\r
+\r
+/* Alias word address of HD bit */\r
+#define FCR_OFFSET (LCD_OFFSET + 0x04)\r
+#define HD_BitNumber 0x00\r
+#define FCR_HD_BB (PERIPH_BB_BASE + (FCR_OFFSET * 32) + (HD_BitNumber * 4))\r
+\r
+/* --- SR Register ---*/\r
+\r
+/* Alias word address of UDR bit */\r
+#define SR_OFFSET (LCD_OFFSET + 0x08)\r
+#define UDR_BitNumber 0x02\r
+#define SR_UDR_BB (PERIPH_BB_BASE + (SR_OFFSET * 32) + (UDR_BitNumber * 4))\r
+\r
+#define FCR_MASK ((uint32_t)0xFC03FFFF) /* LCD FCR Mask */\r
+#define CR_MASK ((uint32_t)0xFFFFFF81) /* LCD CR Mask */\r
+#define PON_MASK ((uint32_t)0xFFFFFF8F) /* LCD PON Mask */\r
+#define DEAD_MASK ((uint32_t)0xFFFFFC7F) /* LCD DEAD Mask */\r
+#define BLINK_MASK ((uint32_t)0xFFFC1FFF) /* LCD BLINK Mask */\r
+#define CONTRAST_MASK ((uint32_t)0xFFFFE3FF) /* LCD CONTRAST Mask */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup LCD_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup LCD_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Initialization and Configuration functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the LCD peripheral registers to their default reset \r
+ * values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void LCD_DeInit(void)\r
+{\r
+ /* Enable LCD reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_LCD, ENABLE);\r
+ /* Release LCD from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_LCD, DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Initializes the LCD peripheral according to the specified parameters \r
+ * in the LCD_InitStruct.\r
+ * @note This function can be used only when the LCD is disabled. \r
+ * @param LCD_InitStruct: pointer to a LCD_InitTypeDef structure that contains \r
+ * the configuration information for the specified LCD peripheral.\r
+ * @retval None\r
+ */\r
+void LCD_Init(LCD_InitTypeDef* LCD_InitStruct)\r
+{\r
+ /* Check function parameters */\r
+ assert_param(IS_LCD_PRESCALER(LCD_InitStruct->LCD_Prescaler));\r
+ assert_param(IS_LCD_DIVIDER(LCD_InitStruct->LCD_Divider));\r
+ assert_param(IS_LCD_DUTY(LCD_InitStruct->LCD_Duty));\r
+ assert_param(IS_LCD_BIAS(LCD_InitStruct->LCD_Bias)); \r
+ assert_param(IS_LCD_VOLTAGE_SOURCE(LCD_InitStruct->LCD_VoltageSource));\r
+\r
+ LCD->FCR &= (uint32_t)FCR_MASK;\r
+ LCD->FCR |= (uint32_t)(LCD_InitStruct->LCD_Prescaler | LCD_InitStruct->LCD_Divider);\r
+\r
+ LCD_WaitForSynchro();\r
+\r
+ LCD->CR &= (uint32_t)CR_MASK;\r
+ LCD->CR |= (uint32_t)(LCD_InitStruct->LCD_Duty | LCD_InitStruct->LCD_Bias | \\r
+ LCD_InitStruct->LCD_VoltageSource);\r
+\r
+}\r
+\r
+/**\r
+ * @brief Fills each LCD_InitStruct member with its default value.\r
+ * @param LCD_InitStruct: pointer to a LCD_InitTypeDef structure which will \r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void LCD_StructInit(LCD_InitTypeDef* LCD_InitStruct)\r
+{\r
+/*--------------- Reset LCD init structure parameters values -----------------*/\r
+ LCD_InitStruct->LCD_Prescaler = LCD_Prescaler_1; /*!< Initialize the LCD_Prescaler member */\r
+ \r
+ LCD_InitStruct->LCD_Divider = LCD_Divider_16; /*!< Initialize the LCD_Divider member */\r
+ \r
+ LCD_InitStruct->LCD_Duty = LCD_Duty_Static; /*!< Initialize the LCD_Duty member */\r
+ \r
+ LCD_InitStruct->LCD_Bias = LCD_Bias_1_4; /*!< Initialize the LCD_Bias member */\r
+ \r
+ LCD_InitStruct->LCD_VoltageSource = LCD_VoltageSource_Internal; /*!< Initialize the LCD_VoltageSource member */\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the LCD Controller.\r
+ * @param NewState: new state of the LCD peripheral.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void LCD_Cmd(FunctionalState NewState)\r
+{\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(__IO uint32_t *) CR_LCDEN_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Waits until the LCD FCR register is synchronized in the LCDCLK domain.\r
+ * This function must be called after any write operation to LCD_FCR register.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void LCD_WaitForSynchro(void)\r
+{\r
+ /* Loop until FCRSF flag is set */\r
+ while ((LCD->SR & LCD_FLAG_FCRSF) == (uint32_t)RESET)\r
+ {\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the low resistance divider. Displays with high \r
+ * internal resistance may need a longer drive time to achieve \r
+ * satisfactory contrast. This function is useful in this case if some \r
+ * additional power consumption can be tolerated.\r
+ * @note When this mode is enabled, the PulseOn Duration (PON) have to be \r
+ * programmed to 1/CK_PS (LCD_PulseOnDuration_1). \r
+ * @param NewState: new state of the low resistance divider.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void LCD_HighDriveCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(__IO uint32_t *) FCR_HD_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Mux Segment.\r
+ * @note This function can be used only when the LCD is disabled. \r
+ * @param NewState: new state of the Mux Segment.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void LCD_MuxSegmentCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(__IO uint32_t *) CR_MUX_SEG_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Configures the LCD pulses on duration.\r
+ * @param LCD_PulseOnDuration: specifies the LCD pulse on duration in terms of \r
+ * CK_PS (prescaled LCD clock period) pulses.\r
+ * This parameter can be one of the following values:\r
+ * @arg LCD_PulseOnDuration_0: 0 pulse\r
+ * @arg LCD_PulseOnDuration_1: Pulse ON duration = 1/CK_PS\r
+ * @arg LCD_PulseOnDuration_2: Pulse ON duration = 2/CK_PS\r
+ * @arg LCD_PulseOnDuration_3: Pulse ON duration = 3/CK_PS\r
+ * @arg LCD_PulseOnDuration_4: Pulse ON duration = 4/CK_PS\r
+ * @arg LCD_PulseOnDuration_5: Pulse ON duration = 5/CK_PS\r
+ * @arg LCD_PulseOnDuration_6: Pulse ON duration = 6/CK_PS\r
+ * @arg LCD_PulseOnDuration_7: Pulse ON duration = 7/CK_PS\r
+ * @retval None\r
+ */\r
+void LCD_PulseOnDurationConfig(uint32_t LCD_PulseOnDuration)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LCD_PULSE_ON_DURATION(LCD_PulseOnDuration));\r
+\r
+ LCD->FCR &= (uint32_t)PON_MASK;\r
+ LCD->FCR |= (uint32_t)(LCD_PulseOnDuration);\r
+}\r
+\r
+/**\r
+ * @brief Configures the LCD dead time.\r
+ * @param LCD_DeadTime: specifies the LCD dead time.\r
+ * This parameter can be one of the following values:\r
+ * @arg LCD_DeadTime_0: No dead Time\r
+ * @arg LCD_DeadTime_1: One Phase between different couple of Frame\r
+ * @arg LCD_DeadTime_2: Two Phase between different couple of Frame\r
+ * @arg LCD_DeadTime_3: Three Phase between different couple of Frame\r
+ * @arg LCD_DeadTime_4: Four Phase between different couple of Frame\r
+ * @arg LCD_DeadTime_5: Five Phase between different couple of Frame\r
+ * @arg LCD_DeadTime_6: Six Phase between different couple of Frame \r
+ * @arg LCD_DeadTime_7: Seven Phase between different couple of Frame\r
+ * @retval None\r
+ */\r
+void LCD_DeadTimeConfig(uint32_t LCD_DeadTime)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LCD_DEAD_TIME(LCD_DeadTime));\r
+\r
+ LCD->FCR &= (uint32_t)DEAD_MASK;\r
+ LCD->FCR |= (uint32_t)(LCD_DeadTime);\r
+}\r
+\r
+/**\r
+ * @brief Configures the LCD Blink mode and Blink frequency.\r
+ * @param LCD_BlinkMode: specifies the LCD blink mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg LCD_BlinkMode_Off: Blink disabled\r
+ * @arg LCD_BlinkMode_SEG0_COM0: Blink enabled on SEG[0], COM[0] (1 pixel)\r
+ * @arg LCD_BlinkMode_SEG0_AllCOM: Blink enabled on SEG[0], all COM (up to 8 \r
+ * pixels according to the programmed duty)\r
+ * @arg LCD_BlinkMode_AllSEG_AllCOM: Blink enabled on all SEG and all COM \r
+ * (all pixels)\r
+ * @param LCD_BlinkFrequency: specifies the LCD blink frequency.\r
+ * This parameter can be one of the following values:\r
+ * @arg LCD_BlinkFrequency_Div8: The Blink frequency = fLcd/8\r
+ * @arg LCD_BlinkFrequency_Div16: The Blink frequency = fLcd/16\r
+ * @arg LCD_BlinkFrequency_Div32: The Blink frequency = fLcd/32\r
+ * @arg LCD_BlinkFrequency_Div64: The Blink frequency = fLcd/64 \r
+ * @arg LCD_BlinkFrequency_Div128: The Blink frequency = fLcd/128\r
+ * @arg LCD_BlinkFrequency_Div256: The Blink frequency = fLcd/256\r
+ * @arg LCD_BlinkFrequency_Div512: The Blink frequency = fLcd/512\r
+ * @arg LCD_BlinkFrequency_Div1024: The Blink frequency = fLcd/1024\r
+ * @retval None\r
+ */\r
+void LCD_BlinkConfig(uint32_t LCD_BlinkMode, uint32_t LCD_BlinkFrequency)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LCD_BLINK_MODE(LCD_BlinkMode));\r
+ assert_param(IS_LCD_BLINK_FREQUENCY(LCD_BlinkFrequency));\r
+ \r
+ LCD->FCR &= (uint32_t)BLINK_MASK;\r
+ LCD->FCR |= (uint32_t)(LCD_BlinkMode | LCD_BlinkFrequency);\r
+}\r
+\r
+/**\r
+ * @brief Configures the LCD Contrast.\r
+ * @param LCD_Contrast: specifies the LCD Contrast.\r
+ * This parameter can be one of the following values:\r
+ * @arg LCD_Contrast_Level_0: Maximum Voltage = 2.60V\r
+ * @arg LCD_Contrast_Level_1: Maximum Voltage = 2.73V\r
+ * @arg LCD_Contrast_Level_2: Maximum Voltage = 2.86V\r
+ * @arg LCD_Contrast_Level_3: Maximum Voltage = 2.99V\r
+ * @arg LCD_Contrast_Level_4: Maximum Voltage = 3.12V\r
+ * @arg LCD_Contrast_Level_5: Maximum Voltage = 3.25V\r
+ * @arg LCD_Contrast_Level_6: Maximum Voltage = 3.38V\r
+ * @arg LCD_Contrast_Level_7: Maximum Voltage = 3.51V\r
+ * @retval None\r
+ */\r
+void LCD_ContrastConfig(uint32_t LCD_Contrast)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LCD_CONTRAST(LCD_Contrast));\r
+\r
+ LCD->FCR &= (uint32_t)CONTRAST_MASK;\r
+ LCD->FCR |= (uint32_t)(LCD_Contrast);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LCD_Group2 LCD RAM memory write functions\r
+ * @brief LCD RAM memory write functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ LCD RAM memory write functions\r
+ =============================================================================== \r
+\r
+ Using its double buffer memory the LCD controller ensures the coherency of the \r
+ displayed information without having to use interrupts to control LCD_RAM \r
+ modification.\r
+ The application software can access the first buffer level (LCD_RAM) through \r
+ the APB interface. Once it has modified the LCD_RAM, it sets the UDR flag in \r
+ the LCD_SR register using the LCD_UpdateDisplayRequest() function.\r
+ This UDR flag (update display request) requests the updated information to be \r
+ moved into the second buffer level (LCD_DISPLAY).\r
+ This operation is done synchronously with the frame (at the beginning of the \r
+ next frame), until the update is completed, the LCD_RAM is write protected and \r
+ the UDR flag stays high.\r
+ Once the update is completed another flag (UDD - Update Display Done) is set and\r
+ generates an interrupt if the UDDIE bit in the LCD_FCR register is set.\r
+ The time it takes to update LCD_DISPLAY is, in the worst case, one odd and one \r
+ even frame.\r
+ The update will not occur (UDR = 1 and UDD = 0) until the display is \r
+ enabled (LCDEN = 1).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Writes a word in the specific LCD RAM.\r
+ * @param LCD_RAMRegister: specifies the LCD Contrast.\r
+ * This parameter can be one of the following values:\r
+ * @arg LCD_RAMRegister_0: LCD RAM Register 0\r
+ * @arg LCD_RAMRegister_1: LCD RAM Register 1\r
+ * @arg LCD_RAMRegister_2: LCD RAM Register 2\r
+ * @arg LCD_RAMRegister_3: LCD RAM Register 3\r
+ * @arg LCD_RAMRegister_4: LCD RAM Register 4\r
+ * @arg LCD_RAMRegister_5: LCD RAM Register 5\r
+ * @arg LCD_RAMRegister_6: LCD RAM Register 6 \r
+ * @arg LCD_RAMRegister_7: LCD RAM Register 7 \r
+ * @arg LCD_RAMRegister_8: LCD RAM Register 8\r
+ * @arg LCD_RAMRegister_9: LCD RAM Register 9\r
+ * @arg LCD_RAMRegister_10: LCD RAM Register 10\r
+ * @arg LCD_RAMRegister_11: LCD RAM Register 11\r
+ * @arg LCD_RAMRegister_12: LCD RAM Register 12 \r
+ * @arg LCD_RAMRegister_13: LCD RAM Register 13 \r
+ * @arg LCD_RAMRegister_14: LCD RAM Register 14 \r
+ * @arg LCD_RAMRegister_15: LCD RAM Register 15 \r
+ * @param LCD_Data: specifies LCD Data Value to be written.\r
+ * @retval None\r
+ */\r
+void LCD_Write(uint32_t LCD_RAMRegister, uint32_t LCD_Data)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LCD_RAM_REGISTER(LCD_RAMRegister));\r
+\r
+ /* Copy data bytes to RAM register */\r
+ LCD->RAM[LCD_RAMRegister] = (uint32_t)LCD_Data;\r
+}\r
+\r
+/**\r
+ * @brief Enables the Update Display Request.\r
+ * @note Each time software modifies the LCD_RAM it must set the UDR bit to \r
+ * transfer the updated data to the second level buffer. \r
+ * The UDR bit stays set until the end of the update and during this \r
+ * time the LCD_RAM is write protected. \r
+ * @note When the display is disabled, the update is performed for all \r
+ * LCD_DISPLAY locations.\r
+ * When the display is enabled, the update is performed only for locations \r
+ * for which commons are active (depending on DUTY). For example if \r
+ * DUTY = 1/2, only the LCD_DISPLAY of COM0 and COM1 will be updated. \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void LCD_UpdateDisplayRequest(void)\r
+{\r
+ *(__IO uint32_t *) SR_UDR_BB = (uint32_t)0x01;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LCD_Group3 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Interrupts and flags management functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified LCD interrupts.\r
+ * @param LCD_IT: specifies the LCD interrupts sources to be enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg LCD_IT_SOF: Start of Frame Interrupt\r
+ * @arg LCD_IT_UDD: Update Display Done Interrupt\r
+ * @param NewState: new state of the specified LCD interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void LCD_ITConfig(uint32_t LCD_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LCD_IT(LCD_IT)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ LCD->FCR |= LCD_IT;\r
+ }\r
+ else\r
+ {\r
+ LCD->FCR &= (uint32_t)~LCD_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified LCD flag is set or not.\r
+ * @param LCD_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg LCD_FLAG_ENS: LCD Enabled flag. It indicates the LCD controller status.\r
+ * @note The ENS bit is set immediately when the LCDEN bit in the LCD_CR \r
+ * goes from 0 to 1. On deactivation it reflects the real status of \r
+ * LCD so it becomes 0 at the end of the last displayed frame. \r
+ * @arg LCD_FLAG_SOF: Start of Frame flag. This flag is set by hardware at \r
+ * the beginning of a new frame, at the same time as the display data is \r
+ * updated.\r
+ * @arg LCD_FLAG_UDR: Update Display Request flag.\r
+ * @arg LCD_FLAG_UDD: Update Display Done flag. \r
+ * @arg LCD_FLAG_RDY: Step_up converter Ready flag. It indicates the status \r
+ * of the step-up converter.\r
+ * @arg LCD_FLAG_FCRSF: LCD Frame Control Register Synchronization Flag. \r
+ * This flag is set by hardware each time the LCD_FCR register is updated \r
+ * in the LCDCLK domain. \r
+ * @retval The new state of LCD_FLAG (SET or RESET).\r
+ */\r
+FlagStatus LCD_GetFlagStatus(uint32_t LCD_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_LCD_GET_FLAG(LCD_FLAG));\r
+ \r
+ if ((LCD->SR & LCD_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the LCD's pending flags.\r
+ * @param LCD_FLAG: specifies the flag to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg LCD_FLAG_SOF: Start of Frame Interrupt\r
+ * @arg LCD_FLAG_UDD: Update Display Done Interrupt\r
+ * @retval None\r
+ */\r
+void LCD_ClearFlag(uint32_t LCD_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LCD_CLEAR_FLAG(LCD_FLAG));\r
+ \r
+ /* Clear the corresponding LCD flag */\r
+ LCD->CLR = (uint32_t)LCD_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified RTC interrupt has occurred or not.\r
+ * @param RTC_IT: specifies the RTC interrupts sources to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg LCD_IT_SOF: Start of Frame Interrupt\r
+ * @arg LCD_IT_UDD: Update Display Done Interrupt.\r
+ * @note If the device is in STOP mode (PCLK not provided) UDD will not \r
+ * generate an interrupt even if UDDIE = 1. \r
+ * If the display is not enabled the UDD interrupt will never occur. \r
+ * @retval The new state of the LCD_IT (SET or RESET).\r
+ */\r
+ITStatus LCD_GetITStatus(uint32_t LCD_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_LCD_GET_IT(LCD_IT));\r
+ \r
+ if ((LCD->SR & LCD_IT) != (uint16_t)RESET) \r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ \r
+ if (((LCD->FCR & LCD_IT) != (uint16_t)RESET) && (bitstatus != (uint32_t)RESET))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the LCD's interrupt pending bits.\r
+ * @param LCD_IT: specifies the interrupt pending bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg LCD_IT_SOF: Start of Frame Interrupt\r
+ * @arg LCD_IT_UDD: Update Display Done Interrupt\r
+ * @retval None\r
+ */\r
+void LCD_ClearITPendingBit(uint32_t LCD_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LCD_IT(LCD_IT));\r
+ \r
+ /* Clear the corresponding LCD pending bit */\r
+ LCD->CLR = (uint32_t)LCD_IT;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_pwr.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Power Controller (PWR) peripheral: \r
+ * - RTC Domain Access\r
+ * - PVD configuration\r
+ * - WakeUp pins configuration\r
+ * - Ultra Low Power mode configuration\r
+ * - Voltage Scaling configuration\r
+ * - Low Power modes configuration\r
+ * - Flags management\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_pwr.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWR \r
+ * @brief PWR driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* --------- PWR registers bit address in the alias region ---------- */\r
+#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)\r
+\r
+/* --- CR Register ---*/\r
+\r
+/* Alias word address of DBP bit */\r
+#define CR_OFFSET (PWR_OFFSET + 0x00)\r
+#define DBP_BitNumber 0x08\r
+#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))\r
+\r
+/* Alias word address of PVDE bit */\r
+#define PVDE_BitNumber 0x04\r
+#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))\r
+\r
+/* Alias word address of ULP bit */\r
+#define ULP_BitNumber 0x09\r
+#define CR_ULP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ULP_BitNumber * 4))\r
+\r
+/* Alias word address of FWU bit */\r
+#define FWU_BitNumber 0x0A\r
+#define CR_FWU_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FWU_BitNumber * 4))\r
+\r
+/* --- CSR Register ---*/\r
+\r
+/* Alias word address of EWUP bit */\r
+#define CSR_OFFSET (PWR_OFFSET + 0x04)\r
+#define EWUP_BitNumber 0x08\r
+#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))\r
+\r
+/* ------------------ PWR registers bit mask ------------------------ */\r
+\r
+/* CR register bit mask */\r
+#define CR_DS_MASK ((uint32_t)0xFFFFFFFC)\r
+#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)\r
+#define CR_VOS_MASK ((uint32_t)0xFFFFE7FF)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup PWR_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWR_Group1 RTC Domain Access function \r
+ * @brief RTC Domain Access function \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ RTC Domain Access function \r
+ =============================================================================== \r
+\r
+ After reset, the RTC Registers (RCC CSR Register, RTC registers and RTC backup \r
+ registers) are protected against possible stray write accesses.\r
+ To enable access to RTC domain use the PWR_RTCAccessCmd(ENABLE) function.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the PWR peripheral registers to their default reset values.\r
+ * @note Before calling this function, the VOS[1:0] bits should be configured \r
+ * to "10" and the system frequency has to be configured accordingly. \r
+ * To configure the VOS[1:0] bits, use the PWR_VoltageScalingConfig()\r
+ * function. \r
+ * @note ULP and FWU bits are not reset by this function. \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void PWR_DeInit(void)\r
+{\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables access to the RTC and backup registers.\r
+ * @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the \r
+ * RTC Domain Access should be kept enabled.\r
+ * @param NewState: new state of the access to the RTC and backup registers.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void PWR_RTCAccessCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Group2 PVD configuration functions\r
+ * @brief PVD configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ PVD configuration functions\r
+ =============================================================================== \r
+\r
+ - The PVD is used to monitor the VDD power supply by comparing it to a threshold\r
+ selected by the PVD Level (PLS[2:0] bits in the PWR_CR).\r
+ - The PVD can use an external input analog voltage (PVD_IN) which is compared \r
+ internally to VREFINT. The PVD_IN (PB7) has to be configured in Analog mode \r
+ when PWR_PVDLevel_7 is selected (PLS[2:0] = 111).\r
+ - A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the \r
+ PVD threshold. This event is internally connected to the EXTI line16\r
+ and can generate an interrupt if enabled through the EXTI registers.\r
+ - The PVD is stopped in Standby mode.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).\r
+ * @param PWR_PVDLevel: specifies the PVD detection level\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_PVDLevel_0: PVD detection level set to 1.9V\r
+ * @arg PWR_PVDLevel_1: PVD detection level set to 2.1V\r
+ * @arg PWR_PVDLevel_2: PVD detection level set to 2.3V\r
+ * @arg PWR_PVDLevel_3: PVD detection level set to 2.5V\r
+ * @arg PWR_PVDLevel_4: PVD detection level set to 2.7V\r
+ * @arg PWR_PVDLevel_5: PVD detection level set to 2.9V\r
+ * @arg PWR_PVDLevel_6: PVD detection level set to 3.1V\r
+ * @arg PWR_PVDLevel_7: External input analog voltage (Compare internally to VREFINT)\r
+ * @retval None\r
+ */\r
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));\r
+ \r
+ tmpreg = PWR->CR;\r
+ \r
+ /* Clear PLS[7:5] bits */\r
+ tmpreg &= CR_PLS_MASK;\r
+ \r
+ /* Set PLS[7:5] bits according to PWR_PVDLevel value */\r
+ tmpreg |= PWR_PVDLevel;\r
+ \r
+ /* Store the new value */\r
+ PWR->CR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Power Voltage Detector(PVD).\r
+ * @param NewState: new state of the PVD.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void PWR_PVDCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Group3 WakeUp pins configuration functions\r
+ * @brief WakeUp pins configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ WakeUp pins configuration functions\r
+ =============================================================================== \r
+\r
+ - WakeUp pins are used to wakeup the system from Standby mode. These pins are \r
+ forced in input pull down configuration and are active on rising edges.\r
+ - There are three WakeUp pins: WakeUp Pin 1 on PA.00, WakeUp Pin 2 on PC.13 and\r
+ WakeUp Pin 3 on PE.06.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the WakeUp Pin functionality.\r
+ * @param PWR_WakeUpPin: specifies the WakeUpPin.\r
+ * This parameter can be: PWR_WakeUpPin_1, PWR_WakeUpPin_2 or PWR_WakeUpPin_3.\r
+ * @param NewState: new state of the WakeUp Pin functionality.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_WAKEUP_PIN(PWR_WakeUpPin));\r
+ \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ tmp = CSR_EWUP_BB + PWR_WakeUpPin;\r
+ \r
+ *(__IO uint32_t *) (tmp) = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Group4 Ultra Low Power mode configuration functions\r
+ * @brief Ultra Low Power mode configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Ultra Low Power mode configuration functions\r
+ =============================================================================== \r
+\r
+ - The internal voltage reference consumption is not negligible, in particular \r
+ in Stop and Standby mode. To reduce power consumption, use the PWR_UltraLowPowerCmd()\r
+ function (ULP bit (Ultra low power) in the PWR_CR register) to disable the \r
+ internal voltage reference. However, in this case, when exiting from the \r
+ Stop/Standby mode, the functions managed through the internal voltage reference \r
+ are not reliable during the internal voltage reference startup time (up to 3 ms).\r
+ To reduce the wakeup time, the device can exit from Stop/Standby mode without \r
+ waiting for the internal voltage reference startup time. This is performed \r
+ by using the PWR_FastWakeUpCmd() function (setting the FWU bit (Fast\r
+ wakeup) in the PWR_CR register) before entering Stop/Standby mode.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the Fast WakeUp from Ultra Low Power mode.\r
+ * @param NewState: new state of the Fast WakeUp functionality.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void PWR_FastWakeUpCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(__IO uint32_t *) CR_FWU_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Ultra Low Power mode.\r
+ * @param NewState: new state of the Ultra Low Power mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void PWR_UltraLowPowerCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(__IO uint32_t *) CR_ULP_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Group5 Voltage Scaling configuration functions\r
+ * @brief Voltage Scaling configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Voltage Scaling configuration functions\r
+ =============================================================================== \r
+\r
+ - The dynamic voltage scaling is a power management technique which consists in \r
+ increasing or decreasing the voltage used for the digital peripherals (VCORE), \r
+ according to the circumstances.\r
+ \r
+ Depending on the device voltage range, the maximum frequency and FLASH wait\r
+ state should be adapted accordingly:\r
+ \r
+ +------------------------------------------------------------------+ \r
+ | Wait states | HCLK clock frequency (MHz) |\r
+ | |------------------------------------------------| \r
+ | (Latency) | voltage range | voltage range | \r
+ | | 1.65 V - 3.6 V | 2.0 V - 3.6 V |\r
+ | |----------------|---------------|---------------|\r
+ | | Range 3 | Range 2 | Range 1 |\r
+ | | VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V |\r
+ |---------------- |----------------|---------------|---------------| \r
+ | 0WS(1CPU cycle) |0 < HCLK <= 2 |0 < HCLK <= 8 |0 < HCLK <= 16 |\r
+ |-----------------|----------------|---------------|---------------| \r
+ | 1WS(2CPU cycle) |2 < HCLK <= 4 |8 < HCLK <= 16 |16 < HCLK <= 32|\r
+ |-----------------|----------------|---------------|---------------| \r
+ | CPU Performance | Low | Medium | High |\r
+ |-----__----------|----------------|---------------|---------------| \r
+ |Power Performance| High | Medium | Low | \r
+ +------------------------------------------------------------------+ \r
+\r
+ - To modify the Product voltage range, user application has to:\r
+ - Check VDD to identify which ranges are allowed (see table above)\r
+ - Check the PWR_FLAG_VOSF (Voltage Scaling update ongoing) using the PWR_GetFlagStatus() \r
+ function and wait until it is reset.\r
+ - Configure the Voltage range using the PWR_VoltageScalingConfig() function.\r
+\r
+ - When VCORE range 1 is selected and VDD drops below 2.0 V, the application must\r
+ reconfigure the system:\r
+ - Detect that VDD drops below 2.0 V using the PVD Level 1\r
+ - Adapt the clock frequency to the voltage range that will be selected at next step\r
+ - Select the required voltage range\r
+ - When VCORE range 2 or range 3 is selected and VDD drops below 2.0 V, no system\r
+ reconfiguration is required.\r
+ \r
+ - When VDD is above 2.0 V, any of the 3 voltage ranges can be selected\r
+ - When the voltage range is above the targeted voltage range (e.g. from range \r
+ 1 to 2):\r
+ - Adapt the clock frequency to the lower voltage range that will be selected \r
+ at next step.\r
+ - Select the required voltage range.\r
+ - When the voltage range is below the targeted voltage range (e.g. from range \r
+ 3 to 1):\r
+ - Select the required voltage range.\r
+ - Tune the clock frequency if needed.\r
+ \r
+ - When VDD is below 2.0 V, only range 2 and 3 can be selected:\r
+ - From range 2 to range 3\r
+ - Adapt the clock frequency to voltage range 3.\r
+ - Select voltage range 3.\r
+ - From range 3 to range 2\r
+ - Select the voltage range 2.\r
+ - Tune the clock frequency if needed.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the voltage scaling range.\r
+ * @note During voltage scaling configuration, the system clock is stopped \r
+ * until the regulator is stabilized (VOSF = 0). This must be taken \r
+ * into account during application developement, in case a critical \r
+ * reaction time to interrupt is needed, and depending on peripheral \r
+ * used (timer, communication,...).\r
+ * \r
+ * @param PWR_VoltageScaling: specifies the voltage scaling range.\r
+ * This parameter can be:\r
+ * @arg PWR_VoltageScaling_Range1: Voltage Scaling Range 1 (VCORE = 1.8V)\r
+ * @arg PWR_VoltageScaling_Range2: Voltage Scaling Range 2 (VCORE = 1.5V)\r
+ * @arg PWR_VoltageScaling_Range3: Voltage Scaling Range 3 (VCORE = 1.2V) \r
+ * @retval None\r
+ */\r
+void PWR_VoltageScalingConfig(uint32_t PWR_VoltageScaling)\r
+{\r
+ uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(PWR_VoltageScaling));\r
+ \r
+ tmp = PWR->CR;\r
+\r
+ tmp &= CR_VOS_MASK;\r
+ tmp |= PWR_VoltageScaling;\r
+ \r
+ PWR->CR = tmp & 0xFFFFFFF3;\r
+\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Group6 Low Power modes configuration functions\r
+ * @brief Low Power modes configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Low Power modes configuration functions\r
+ =============================================================================== \r
+\r
+ The devices feature five low-power modes:\r
+ - Low power run mode: regulator in low power mode, limited clock frequency, \r
+ limited number of peripherals running.\r
+ - Sleep mode: Cortex-M3 core stopped, peripherals kept running.\r
+ - Low power sleep mode: Cortex-M3 core stopped, limited clock frequency, \r
+ limited number of peripherals running, regulator in low power mode.\r
+ - Stop mode: all clocks are stopped, regulator running, regulator in low power mode\r
+ - Standby mode: VCORE domain powered off\r
+ \r
+ Low power run mode (LP run)\r
+ ===========================\r
+ - Entry:\r
+ - Decrease the system frequency.\r
+ - The regulator is forced in low power mode using the PWR_EnterLowPowerRunMode()\r
+ function.\r
+ - Exit:\r
+ - The regulator is forced in Main regulator mode sing the PWR_EnterLowPowerRunMode()\r
+ function.\r
+ - Increase the system frequency if needed.\r
+\r
+ Sleep mode\r
+ ===========\r
+ - Entry:\r
+ - The Sleep mode is entered by using the PWR_EnterSleepMode(PWR_Regulator_ON,) \r
+ function with regulator ON.\r
+ - Exit:\r
+ - Any peripheral interrupt acknowledged by the nested vectored interrupt \r
+ controller (NVIC) can wake up the device from Sleep mode.\r
+\r
+ Low power sleep mode (LP sleep)\r
+ ===============================\r
+ - Entry:\r
+ - The Flash memory must be switched off by using the FLASH_SLEEPPowerDownCmd()\r
+ function.\r
+ - Decrease the system frequency.\r
+ - The regulator is forced in low power mode and the WFI or WFE instructions\r
+ are executed using the PWR_EnterSleepMode(PWR_Regulator_LowPower,) function \r
+ with regulator in LowPower.\r
+ - Exit:\r
+ - Any peripheral interrupt acknowledged by the nested vectored interrupt \r
+ controller (NVIC) can wake up the device from Sleep LP mode.\r
+\r
+ Stop mode\r
+ ==========\r
+ In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the MSI,\r
+ the HSI and the HSE RC oscillators are disabled. Internal SRAM and register \r
+ contents are preserved.\r
+ The voltage regulator can be configured either in normal or low-power mode.\r
+ To minimize the consumption In Stop mode, VREFINT, the BOR, PVD, and temperature\r
+ sensor can be switched off before entering the Stop mode. They can be switched \r
+ on again by software after exiting the Stop mode using the PWR_UltraLowPowerCmd()\r
+ function. \r
+ \r
+ - Entry:\r
+ - The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,) \r
+ function with regulator in LowPower or with Regulator ON.\r
+ - Exit:\r
+ - Any EXTI Line (Internal or External) configured in Interrupt/Event mode.\r
+ \r
+ Standby mode\r
+ ============\r
+ The Standby mode allows to achieve the lowest power consumption. It is based \r
+ on the Cortex-M3 deepsleep mode, with the voltage regulator disabled. \r
+ The VCORE domain is consequently powered off. The PLL, the MSI, the HSI \r
+ oscillator and the HSE oscillator are also switched off. SRAM and register \r
+ contents are lost except for the RTC registers, RTC backup registers and \r
+ Standby circuitry.\r
+ \r
+ The voltage regulator is OFF.\r
+ \r
+ To minimize the consumption In Standby mode, VREFINT, the BOR, PVD, and temperature\r
+ sensor can be switched off before entering the Standby mode. They can be switched \r
+ on again by software after exiting the Standby mode using the PWR_UltraLowPowerCmd()\r
+ function. \r
+ \r
+ - Entry:\r
+ - The Standby mode is entered using the PWR_EnterSTANDBYMode() function.\r
+ - Exit:\r
+ - WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,\r
+ tamper event, time-stamp event, external reset in NRST pin, IWDG reset. \r
+\r
+ Auto-wakeup (AWU) from low-power mode\r
+ =====================================\r
+ The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC \r
+ Wakeup event, a tamper event, a time-stamp event, or a comparator event, \r
+ without depending on an external interrupt (Auto-wakeup mode).\r
+\r
+ - RTC auto-wakeup (AWU) from the Stop mode\r
+ ----------------------------------------\r
+ \r
+ - To wake up from the Stop mode with an RTC alarm event, it is necessary to:\r
+ - Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt \r
+ or Event modes) using the EXTI_Init() function.\r
+ - Enable the RTC Alarm Interrupt using the RTC_ITConfig() function\r
+ - Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() \r
+ and RTC_AlarmCmd() functions.\r
+ - To wake up from the Stop mode with an RTC Tamper or time stamp event, it \r
+ is necessary to:\r
+ - Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt \r
+ or Event modes) using the EXTI_Init() function.\r
+ - Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() \r
+ function\r
+ - Configure the RTC to detect the tamper or time stamp event using the\r
+ RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()\r
+ functions.\r
+ - To wake up from the Stop mode with an RTC WakeUp event, it is necessary to:\r
+ - Configure the EXTI Line 20 to be sensitive to rising edges (Interrupt \r
+ or Event modes) using the EXTI_Init() function.\r
+ - Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function\r
+ - Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), \r
+ RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.\r
+\r
+ - RTC auto-wakeup (AWU) from the Standby mode\r
+ -------------------------------------------\r
+ - To wake up from the Standby mode with an RTC alarm event, it is necessary to:\r
+ - Enable the RTC Alarm Interrupt using the RTC_ITConfig() function\r
+ - Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() \r
+ and RTC_AlarmCmd() functions.\r
+ - To wake up from the Standby mode with an RTC Tamper or time stamp event, it \r
+ is necessary to:\r
+ - Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() \r
+ function\r
+ - Configure the RTC to detect the tamper or time stamp event using the\r
+ RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()\r
+ functions.\r
+ - To wake up from the Standby mode with an RTC WakeUp event, it is necessary to:\r
+ - Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function\r
+ - Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), \r
+ RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.\r
+\r
+ - Comparator auto-wakeup (AWU) from the Stop mode\r
+ -----------------------------------------------\r
+ - To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup\r
+ event, it is necessary to:\r
+ - Configure the EXTI Line 21 for comparator 1 or EXTI Line 22 for comparator 2 \r
+ to be sensitive to to the selected edges (falling, rising or falling \r
+ and rising) (Interrupt or Event modes) using the EXTI_Init() function.\r
+ - Configure the comparator to generate the event.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enters/Exits the Low Power Run mode.\r
+ * @note Low power run mode can only be entered when VCORE is in range 2.\r
+ * In addition, the dynamic voltage scaling must not be used when Low \r
+ * power run mode is selected. Only Stop and Sleep modes with regulator \r
+ * configured in Low power mode is allowed when Low power run mode is \r
+ * selected. \r
+ * @note In Low power run mode, all I/O pins keep the same state as in Run mode. \r
+ * @param NewState: new state of the Low Power Run mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void PWR_EnterLowPowerRunMode(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ PWR->CR |= PWR_CR_LPSDSR;\r
+ PWR->CR |= PWR_CR_LPRUN; \r
+ }\r
+ else\r
+ {\r
+ PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_LPRUN); \r
+ PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_LPSDSR); \r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Enters Sleep mode.\r
+ * @note In Sleep mode, all I/O pins keep the same state as in Run mode. \r
+ * @param PWR_Regulator: specifies the regulator state in Sleep mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_Regulator_ON: Sleep mode with regulator ON\r
+ * @arg PWR_Regulator_LowPower: Sleep mode with regulator in low power mode\r
+ * @note Low power sleep mode can only be entered when VCORE is in range 2.\r
+ * @note When the voltage regulator operates in low power mode, an additional \r
+ * startup delay is incurred when waking up from Low power sleep mode.\r
+ * \r
+ * @param PWR_SLEEPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction\r
+ * @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction\r
+ * @retval None\r
+ */\r
+void PWR_EnterSleepMode(uint32_t PWR_Regulator, uint8_t PWR_SLEEPEntry)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_REGULATOR(PWR_Regulator));\r
+\r
+ assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry));\r
+ \r
+ /* Select the regulator state in Sleep mode ---------------------------------*/\r
+ tmpreg = PWR->CR;\r
+ \r
+ /* Clear PDDS and LPDSR bits */\r
+ tmpreg &= CR_DS_MASK;\r
+ \r
+ /* Set LPDSR bit according to PWR_Regulator value */\r
+ tmpreg |= PWR_Regulator;\r
+ \r
+ /* Store the new value */\r
+ PWR->CR = tmpreg;\r
+\r
+ /* Clear SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);\r
+ \r
+ /* Select SLEEP mode entry -------------------------------------------------*/\r
+ if(PWR_SLEEPEntry == PWR_SLEEPEntry_WFI)\r
+ { \r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+ }\r
+ else\r
+ {\r
+ /* Request Wait For Event */\r
+ __WFE();\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enters STOP mode.\r
+ * @note In Stop mode, all I/O pins keep the same state as in Run mode.\r
+ * @note When exiting Stop mode by issuing an interrupt or a wakeup event, \r
+ * the MSI RC oscillator is selected as system clock.\r
+ * @note When the voltage regulator operates in low power mode, an additional \r
+ * startup delay is incurred when waking up from Stop mode. \r
+ * By keeping the internal regulator ON during Stop mode, the consumption \r
+ * is higher although the startup time is reduced. \r
+ * @param PWR_Regulator: specifies the regulator state in STOP mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_Regulator_ON: STOP mode with regulator ON\r
+ * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode\r
+ * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction\r
+ * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction\r
+ * @retval None\r
+ */\r
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_REGULATOR(PWR_Regulator));\r
+ assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));\r
+ \r
+ /* Select the regulator state in STOP mode ---------------------------------*/\r
+ tmpreg = PWR->CR;\r
+ /* Clear PDDS and LPDSR bits */\r
+ tmpreg &= CR_DS_MASK;\r
+ \r
+ /* Set LPDSR bit according to PWR_Regulator value */\r
+ tmpreg |= PWR_Regulator;\r
+ \r
+ /* Store the new value */\r
+ PWR->CR = tmpreg;\r
+ \r
+ /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR |= SCB_SCR_SLEEPDEEP;\r
+ \r
+ /* Select STOP mode entry --------------------------------------------------*/\r
+ if(PWR_STOPEntry == PWR_STOPEntry_WFI)\r
+ { \r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+ }\r
+ else\r
+ {\r
+ /* Request Wait For Event */\r
+ __WFE();\r
+ }\r
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); \r
+}\r
+\r
+/**\r
+ * @brief Enters STANDBY mode.\r
+ * @note In Standby mode, all I/O pins are high impedance except for:\r
+ * - Reset pad (still available) \r
+ * - RTC_AF1 pin (PC13) if configured for Wakeup pin 2 (WKUP2), tamper, \r
+ * time-stamp, RTC Alarm out, or RTC clock calibration out.\r
+ * - WKUP pin 1 (PA0) and WKUP pin 3 (PE6), if enabled. \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void PWR_EnterSTANDBYMode(void)\r
+{\r
+ /* Clear Wakeup flag */\r
+ PWR->CR |= PWR_CR_CWUF;\r
+ \r
+ /* Select STANDBY mode */\r
+ PWR->CR |= PWR_CR_PDDS;\r
+ \r
+ /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR |= SCB_SCR_SLEEPDEEP;\r
+ \r
+/* This option is used to ensure that store operations are completed */\r
+#if defined ( __CC_ARM )\r
+ __force_stores();\r
+#endif\r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Group7 Flags management functions\r
+ * @brief Flags management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Flags management functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Checks whether the specified PWR flag is set or not.\r
+ * @param PWR_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event \r
+ * was received from the WKUP pin or from the RTC alarm (Alarm A or Alarm B), \r
+ * RTC Tamper event, RTC TimeStamp event or RTC Wakeup.\r
+ * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was\r
+ * resumed from StandBy mode. \r
+ * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled \r
+ * by the PWR_PVDCmd() function.\r
+ * @arg PWR_FLAG_VREFINTRDY: Internal Voltage Reference Ready flag. This \r
+ * flag indicates the state of the internal voltage reference, VREFINT.\r
+ * @arg PWR_FLAG_VOS: Voltage Scaling select flag. A delay is required for \r
+ * the internal regulator to be ready after the voltage range is changed.\r
+ * The VOSF flag indicates that the regulator has reached the voltage level \r
+ * defined with bits VOS[1:0] of PWR_CR register.\r
+ * @arg PWR_FLAG_REGLP: Regulator LP flag. This flag is set by hardware \r
+ * when the MCU is in Low power run mode.\r
+ * When the MCU exits from Low power run mode, this flag stays SET until \r
+ * the regulator is ready in main mode. A polling on this flag is \r
+ * recommended to wait for the regulator main mode. \r
+ * This flag is RESET by hardware when the regulator is ready. \r
+ * @retval The new state of PWR_FLAG (SET or RESET).\r
+ */\r
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_GET_FLAG(PWR_FLAG));\r
+ \r
+ if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the flag status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the PWR's pending flags.\r
+ * @param PWR_FLAG: specifies the flag to clear.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_FLAG_WU: Wake Up flag\r
+ * @arg PWR_FLAG_SB: StandBy flag\r
+ * @retval None\r
+ */\r
+void PWR_ClearFlag(uint32_t PWR_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));\r
+ \r
+ PWR->CR |= PWR_FLAG << 2;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_rcc.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Reset and clock control (RCC) peripheral: \r
+ * - Internal/external clocks, PLL, CSS and MCO configuration\r
+ * - System, AHB and APB busses clocks configuration\r
+ * - Peripheral clocks configuration\r
+ * - Interrupts and flags management\r
+ *\r
+ * @verbatim\r
+ * \r
+ * ===================================================================\r
+ * RCC specific features\r
+ * ===================================================================\r
+ * \r
+ * After reset the device is running from MSI (2 MHz) with Flash 0 WS, \r
+ * all peripherals are off except internal SRAM, Flash and JTAG.\r
+ * - There is no prescaler on High speed (AHB) and Low speed (APB) busses;\r
+ * all peripherals mapped on these busses are running at MSI speed.\r
+ * - The clock for all peripherals is switched off, except the SRAM and FLASH.\r
+ * - All GPIOs are in input floating state, except the JTAG pins which\r
+ * are assigned to be used for debug purpose.\r
+ * \r
+ * Once the device started from reset, the user application has to: \r
+ * - Configure the clock source to be used to drive the System clock\r
+ * (if the application needs higher frequency/performance)\r
+ * - Configure the System clock frequency and Flash settings \r
+ * - Configure the AHB and APB busses prescalers\r
+ * - Enable the clock for the peripheral(s) to be used\r
+ * - Configure the clock source(s) for peripherals whose clocks are not\r
+ * derived from the System clock (ADC, RTC/LCD and IWDG) \r
+ * \r
+ * @endverbatim\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCC \r
+ * @brief RCC driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+\r
+/* ------------ RCC registers bit address in the alias region ----------- */\r
+#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)\r
+\r
+/* --- CR Register ---*/\r
+\r
+/* Alias word address of HSION bit */\r
+#define CR_OFFSET (RCC_OFFSET + 0x00)\r
+#define HSION_BitNumber 0x00\r
+#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))\r
+\r
+/* Alias word address of MSION bit */\r
+#define MSION_BitNumber 0x08\r
+#define CR_MSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MSION_BitNumber * 4))\r
+\r
+/* Alias word address of PLLON bit */\r
+#define PLLON_BitNumber 0x18\r
+#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))\r
+\r
+/* Alias word address of CSSON bit */\r
+#define CSSON_BitNumber 0x1C\r
+#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))\r
+\r
+/* --- CSR Register ---*/\r
+\r
+/* Alias word address of LSION bit */\r
+#define CSR_OFFSET (RCC_OFFSET + 0x34)\r
+#define LSION_BitNumber 0x00\r
+#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))\r
+\r
+/* Alias word address of RTCEN bit */\r
+#define RTCEN_BitNumber 0x16\r
+#define CSR_RTCEN_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCEN_BitNumber * 4))\r
+\r
+/* Alias word address of RTCRST bit */\r
+#define RTCRST_BitNumber 0x17\r
+#define CSR_RTCRST_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCRST_BitNumber * 4))\r
+\r
+\r
+/* ---------------------- RCC registers mask -------------------------------- */\r
+/* RCC Flag Mask */\r
+#define FLAG_MASK ((uint8_t)0x1F)\r
+\r
+/* CR register byte 3 (Bits[23:16]) base address */\r
+#define CR_BYTE3_ADDRESS ((uint32_t)0x40023802)\r
+\r
+/* ICSCR register byte 4 (Bits[31:24]) base address */\r
+#define ICSCR_BYTE4_ADDRESS ((uint32_t)0x40023807)\r
+\r
+/* CFGR register byte 3 (Bits[23:16]) base address */\r
+#define CFGR_BYTE3_ADDRESS ((uint32_t)0x4002380A)\r
+\r
+/* CFGR register byte 4 (Bits[31:24]) base address */\r
+#define CFGR_BYTE4_ADDRESS ((uint32_t)0x4002380B)\r
+\r
+/* CIR register byte 2 (Bits[15:8]) base address */\r
+#define CIR_BYTE2_ADDRESS ((uint32_t)0x4002380D)\r
+\r
+/* CIR register byte 3 (Bits[23:16]) base address */\r
+#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002380E)\r
+\r
+/* CSR register byte 2 (Bits[15:8]) base address */\r
+#define CSR_BYTE2_ADDRESS ((uint32_t)0x40023835)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+\r
+static __I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};\r
+static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup RCC_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions\r
+ * @brief Internal and external clocks, PLL, CSS and MCO configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Internal/external clocks, PLL, CSS and MCO configuration functions\r
+ =============================================================================== \r
+\r
+ This section provide functions allowing to configure the internal/external clocks,\r
+ PLL, CSS and MCO.\r
+ \r
+ 1. HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through\r
+ the PLL as System clock source.\r
+\r
+ 2. MSI (multi-speed internal), multispeed low power RC (65.536 KHz to 4.194 MHz)\r
+ MHz used as System clock source.\r
+\r
+ 3. LSI (low-speed internal), 37 KHz low consumption RC used as IWDG and/or RTC\r
+ clock source.\r
+\r
+ 4. HSE (high-speed external), 1 to 24 MHz crystal oscillator used directly or\r
+ through the PLL as System clock source. Can be used also as RTC clock source.\r
+\r
+ 5. LSE (low-speed external), 32 KHz oscillator used as RTC clock source. \r
+\r
+ 6. PLL (clocked by HSI or HSE), for System clock and USB (48 MHz).\r
+\r
+ 7. CSS (Clock security system), once enable and if a HSE clock failure occurs \r
+ (HSE used directly or through PLL as System clock source), the System clock\r
+ is automatically switched to MSI and an interrupt is generated if enabled. \r
+ The interrupt is linked to the Cortex-M3 NMI (Non-Maskable Interrupt) \r
+ exception vector. \r
+\r
+ 8. MCO (microcontroller clock output), used to output SYSCLK, HSI, MSI, HSE, PLL,\r
+ LSI or LSE clock (through a configurable prescaler) on PA8 pin.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Resets the RCC clock configuration to the default reset state.\r
+ * @note - The default reset state of the clock configuration is given below:\r
+ * - MSI ON and used as system clock source (MSI range is not modified\r
+ * by this function, it keep the value configured by user application)\r
+ * - HSI, HSE and PLL OFF\r
+ * - AHB, APB1 and APB2 prescaler set to 1.\r
+ * - CSS and MCO OFF\r
+ * - All interrupts disabled\r
+ * - However, this function doesn't modify the configuration of the\r
+ * - Peripheral clocks\r
+ * - LSI, LSE and RTC clocks \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void RCC_DeInit(void)\r
+{\r
+ \r
+ /* Set MSION bit */\r
+ RCC->CR |= (uint32_t)0x00000100;\r
+\r
+ /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */\r
+ RCC->CFGR &= (uint32_t)0x88FFC00C;\r
+ \r
+ /* Reset HSION, HSEON, CSSON and PLLON bits */\r
+ RCC->CR &= (uint32_t)0xEEFEFFFE;\r
+\r
+ /* Reset HSEBYP bit */\r
+ RCC->CR &= (uint32_t)0xFFFBFFFF;\r
+\r
+ /* Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */\r
+ RCC->CFGR &= (uint32_t)0xFF02FFFF;\r
+\r
+ /* Disable all interrupts */\r
+ RCC->CIR = 0x00000000;\r
+}\r
+\r
+/**\r
+ * @brief Configures the External High Speed oscillator (HSE).\r
+ * @note - After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application\r
+ * software should wait on HSERDY flag to be set indicating that HSE clock\r
+ * is stable and can be used to clock the PLL and/or system clock.\r
+ * - HSE state can not be changed if it is used directly or through the\r
+ * PLL as system clock. In this case, you have to select another source\r
+ * of the system clock then change the HSE state (ex. disable it).\r
+ * - The HSE is stopped by hardware when entering STOP and STANDBY modes. \r
+ * @note This function reset the CSSON bit, so if the Clock security system(CSS)\r
+ * was previously enabled you have to enable it again after calling this\r
+ * function.\r
+ * @param RCC_HSE: specifies the new state of the HSE.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after\r
+ * 6 HSE oscillator clock cycles.\r
+ * @arg RCC_HSE_ON: turn ON the HSE oscillator\r
+ * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock\r
+ * @retval None\r
+ */\r
+void RCC_HSEConfig(uint8_t RCC_HSE)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_HSE(RCC_HSE));\r
+\r
+ /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/\r
+ *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF;\r
+\r
+ /* Set the new HSE configuration -------------------------------------------*/\r
+ *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE;\r
+\r
+}\r
+\r
+/**\r
+ * @brief Waits for HSE start-up.\r
+ * @note This functions waits on HSERDY flag to be set and return SUCCESS if \r
+ * this flag is set, otherwise returns ERROR if the timeout is reached \r
+ * and this flag is not set. The timeout value is defined by the constant\r
+ * HSE_STARTUP_TIMEOUT in stm32l1xx.h file. You can tailor it depending\r
+ * on the HSE crystal used in your application. \r
+ * @param None\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: HSE oscillator is stable and ready to use\r
+ * - ERROR: HSE oscillator not yet ready\r
+ */\r
+ErrorStatus RCC_WaitForHSEStartUp(void)\r
+{\r
+ __IO uint32_t StartUpCounter = 0;\r
+ ErrorStatus status = ERROR;\r
+ FlagStatus HSEStatus = RESET;\r
+ \r
+ /* Wait till HSE is ready and if timeout is reached exit */\r
+ do\r
+ {\r
+ HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);\r
+ StartUpCounter++; \r
+ } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));\r
+ \r
+ if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)\r
+ {\r
+ status = SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ status = ERROR;\r
+ } \r
+ return (status);\r
+}\r
+\r
+/**\r
+ * @brief Adjusts the Internal Multi Speed oscillator (MSI) calibration value.\r
+ * @note The calibration is used to compensate for the variations in voltage\r
+ * and temperature that influence the frequency of the internal MSI RC.\r
+ * Refer to the Application Note AN3300 for more details on how to \r
+ * calibrate the MSI.\r
+ * @param MSICalibrationValue: specifies the MSI calibration trimming value.\r
+ * This parameter must be a number between 0 and 0xFF.\r
+ * @retval None\r
+ */\r
+void RCC_AdjustMSICalibrationValue(uint8_t MSICalibrationValue)\r
+{\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_MSI_CALIBRATION_VALUE(MSICalibrationValue));\r
+\r
+ *(__IO uint8_t *) ICSCR_BYTE4_ADDRESS = MSICalibrationValue; \r
+}\r
+\r
+/**\r
+ * @brief Configures the Internal Multi Speed oscillator (MSI) clock range.\r
+ * @note - After restart from Reset or wakeup from STANDBY, the MSI clock is \r
+ * around 2.097 MHz. The MSI clock does not change after wake-up from\r
+ * STOP mode.\r
+ * - The MSI clock range can be modified on the fly. \r
+ * @param RCC_MSIRange: specifies the MSI Clock range.\r
+ * This parameter must be one of the following values:\r
+ * @arg RCC_MSIRange_0: MSI clock is around 65.536 KHz\r
+ * @arg RCC_MSIRange_1: MSI clock is around 131.072 KHz\r
+ * @arg RCC_MSIRange_2: MSI clock is around 262.144 KHz\r
+ * @arg RCC_MSIRange_3: MSI clock is around 524.288 KHz\r
+ * @arg RCC_MSIRange_4: MSI clock is around 1.048 MHz\r
+ * @arg RCC_MSIRange_5: MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)\r
+ * @arg RCC_MSIRange_6: MSI clock is around \r
+ * \r
+ * @retval None\r
+ */\r
+void RCC_MSIRangeConfig(uint32_t RCC_MSIRange)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_MSIRange));\r
+ \r
+ tmpreg = RCC->ICSCR;\r
+ \r
+ /* Clear MSIRANGE[2:0] bits */\r
+ tmpreg &= ~RCC_ICSCR_MSIRANGE;\r
+ \r
+ /* Set the MSIRANGE[2:0] bits according to RCC_MSIRange value */\r
+ tmpreg |= (uint32_t)RCC_MSIRange;\r
+\r
+ /* Store the new value */\r
+ RCC->ICSCR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Internal Multi Speed oscillator (MSI).\r
+ * @note - The MSI is stopped by hardware when entering STOP and STANDBY modes.\r
+ * It is used (enabled by hardware) as system clock source after\r
+ * startup from Reset, wakeup from STOP and STANDBY mode, or in case\r
+ * of failure of the HSE used directly or indirectly as system clock\r
+ * (if the Clock Security System CSS is enabled). \r
+ * - MSI can not be stopped if it is used as system clock source.\r
+ * In this case, you have to select another source of the system\r
+ * clock then stop the MSI. \r
+ * - After enabling the MSI, the application software should wait on\r
+ * MSIRDY flag to be set indicating that MSI clock is stable and can\r
+ * be used as system clock source. \r
+ * @param NewState: new state of the MSI.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator\r
+ * clock cycles. \r
+ * @retval None\r
+ */\r
+void RCC_MSICmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CR_MSION_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.\r
+ * @note The calibration is used to compensate for the variations in voltage\r
+ * and temperature that influence the frequency of the internal HSI RC.\r
+ * Refer to the Application Note AN3300 for more details on how to \r
+ * calibrate the HSI.\r
+ * @param HSICalibrationValue: specifies the HSI calibration trimming value.\r
+ * This parameter must be a number between 0 and 0x1F.\r
+ * @retval None\r
+ */\r
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_HSI_CALIBRATION_VALUE(HSICalibrationValue));\r
+ \r
+ tmpreg = RCC->ICSCR;\r
+ \r
+ /* Clear HSITRIM[4:0] bits */\r
+ tmpreg &= ~RCC_ICSCR_HSITRIM;\r
+ \r
+ /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */\r
+ tmpreg |= (uint32_t)HSICalibrationValue << 8;\r
+\r
+ /* Store the new value */\r
+ RCC->ICSCR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Internal High Speed oscillator (HSI).\r
+ * @note - After enabling the HSI, the application software should wait on \r
+ * HSIRDY flag to be set indicating that HSI clock is stable and can\r
+ * be used to clock the PLL and/or system clock.\r
+ * - HSI can not be stopped if it is used directly or through the PLL\r
+ * as system clock. In this case, you have to select another source \r
+ * of the system clock then stop the HSI.\r
+ * - The HSI is stopped by hardware when entering STOP and STANDBY modes. \r
+ * @param NewState: new state of the HSI.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator\r
+ * clock cycles. \r
+ * @retval None\r
+ */\r
+void RCC_HSICmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Configures the External Low Speed oscillator (LSE).\r
+ * @note - As the LSE is in the RTC domain and write access is denied to this\r
+ * domain after reset, you have to enable write access using \r
+ * PWR_RTCAccessCmd(ENABLE) function before to configure the LSE\r
+ * (to be done once after reset). \r
+ * - After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application\r
+ * software should wait on LSERDY flag to be set indicating that LSE clock\r
+ * is stable and can be used to clock the RTC.\r
+ * @param RCC_LSE: specifies the new state of the LSE.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after\r
+ * 6 LSE oscillator clock cycles.\r
+ * @arg RCC_LSE_ON: turn ON the LSE oscillator\r
+ * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock\r
+ * @retval None\r
+ */\r
+void RCC_LSEConfig(uint8_t RCC_LSE)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_LSE(RCC_LSE));\r
+ \r
+ /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/\r
+ *(__IO uint8_t *) CSR_BYTE2_ADDRESS = RCC_LSE_OFF;\r
+\r
+ /* Set the new LSE configuration -------------------------------------------*/\r
+ *(__IO uint8_t *) CSR_BYTE2_ADDRESS = RCC_LSE; \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Internal Low Speed oscillator (LSI). \r
+ * @note - After enabling the LSI, the application software should wait on \r
+ * LSIRDY flag to be set indicating that LSI clock is stable and can\r
+ * be used to clock the IWDG and/or the RTC.\r
+ * - LSI can not be disabled if the IWDG is running. \r
+ * @param NewState: new state of the LSI.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator\r
+ * clock cycles. \r
+ * @retval None\r
+ */\r
+void RCC_LSICmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Configures the PLL clock source and multiplication factor.\r
+ * @note This function must be used only when the PLL is disabled.\r
+ * \r
+ * @param RCC_PLLSource: specifies the PLL entry clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock source\r
+ * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock source\r
+ * @note The minimum input clock frequency for PLL is 2 MHz (when using HSE as\r
+ * PLL source).\r
+ * \r
+ * @param RCC_PLLMul: specifies the PLL multiplication factor, which drive the PLLVCO clock\r
+ * This parameter can be:\r
+ * @arg RCC_PLLMul_3: PLL clock source multiplied by 3\r
+ * @arg RCC_PLLMul_4: PLL clock source multiplied by 4\r
+ * @arg RCC_PLLMul_6: PLL clock source multiplied by 6\r
+ * @arg RCC_PLLMul_8: PLL clock source multiplied by 8\r
+ * @arg RCC_PLLMul_12: PLL clock source multiplied by 12\r
+ * @arg RCC_PLLMul_16: PLL clock source multiplied by 16 \r
+ * @arg RCC_PLLMul_24: PLL clock source multiplied by 24\r
+ * @arg RCC_PLLMul_32: PLL clock source multiplied by 32\r
+ * @arg RCC_PLLMul_48: PLL clock source multiplied by 48\r
+ * @note The application software must set correctly the PLL multiplication\r
+ * factor to avoid exceeding\r
+ * - 96 MHz as PLLVCO when the product is in range 1\r
+ * - 48 MHz as PLLVCO when the product is in range 2\r
+ * - 24 MHz when the product is in range 3\r
+ * @note When using the USB the PLLVCO should be 96MHz\r
+ * \r
+ * @param RCC_PLLDiv: specifies the PLL division factor.\r
+ * This parameter can be:\r
+ * @arg RCC_PLLDiv_2: PLL Clock output divided by 2 \r
+ * @arg RCC_PLLDiv_3: PLL Clock output divided by 3 \r
+ * @arg RCC_PLLDiv_4: PLL Clock output divided by 4 \r
+ * @note The application software must set correctly the output division to avoid\r
+ * exceeding 32 MHz as SYSCLK.\r
+ * \r
+ * @retval None\r
+ */\r
+void RCC_PLLConfig(uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));\r
+ assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));\r
+ assert_param(IS_RCC_PLL_DIV(RCC_PLLDiv));\r
+ \r
+ *(__IO uint8_t *) CFGR_BYTE3_ADDRESS = (uint8_t)(RCC_PLLSource | ((uint8_t)(RCC_PLLMul | (uint8_t)(RCC_PLLDiv))));\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the PLL.\r
+ * @note - After enabling the PLL, the application software should wait on \r
+ * PLLRDY flag to be set indicating that PLL clock is stable and can\r
+ * be used as system clock source.\r
+ * - The PLL can not be disabled if it is used as system clock source\r
+ * - The PLL is disabled by hardware when entering STOP and STANDBY modes. \r
+ * @param NewState: new state of the PLL.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_PLLCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Clock Security System.\r
+ * @note If a failure is detected on the HSE oscillator clock, this oscillator\r
+ * is automatically disabled and an interrupt is generated to inform the\r
+ * software about the failure (Clock Security System Interrupt, CSSI),\r
+ * allowing the MCU to perform rescue operations. The CSSI is linked to \r
+ * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector. \r
+ * @param NewState: new state of the Clock Security System.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Selects the clock source to output on MCO pin (PA8).\r
+ * @note PA8 should be configured in alternate function mode. \r
+ * @param RCC_MCOSource: specifies the clock source to output.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_MCOSource_NoClock: No clock selected\r
+ * @arg RCC_MCOSource_SYSCLK: System clock selected\r
+ * @arg RCC_MCOSource_HSI: HSI oscillator clock selected\r
+ * @arg RCC_MCOSource_MSI: MSI oscillator clock selected \r
+ * @arg RCC_MCOSource_HSE: HSE oscillator clock selected\r
+ * @arg RCC_MCOSource_PLLCLK: PLL clock selected\r
+ * @arg RCC_MCOSource_LSI: LSI clock selected\r
+ * @arg RCC_MCOSource_LSE: LSE clock selected \r
+ * @param RCC_MCODiv: specifies the MCO prescaler.\r
+ * This parameter can be one of the following values: \r
+ * @arg RCC_MCODiv_1: no division applied to MCO clock \r
+ * @arg RCC_MCODiv_2: division by 2 applied to MCO clock\r
+ * @arg RCC_MCODiv_4: division by 4 applied to MCO clock\r
+ * @arg RCC_MCODiv_8: division by 8 applied to MCO clock\r
+ * @arg RCC_MCODiv_16: division by 16 applied to MCO clock \r
+ * @retval None\r
+ */\r
+void RCC_MCOConfig(uint8_t RCC_MCOSource, uint8_t RCC_MCODiv)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));\r
+ assert_param(IS_RCC_MCO_DIV(RCC_MCODiv));\r
+ \r
+ /* Select MCO clock source and prescaler */\r
+ *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCOSource | RCC_MCODiv; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions\r
+ * @brief System, AHB and APB busses clocks configuration functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ System, AHB and APB busses clocks configuration functions\r
+ =============================================================================== \r
+\r
+ This section provide functions allowing to configure the System, AHB, APB1 and \r
+ APB2 busses clocks.\r
+ \r
+ 1. Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI,\r
+ HSE and PLL.\r
+ The AHB clock (HCLK) is derived from System clock through configurable prescaler\r
+ and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA and GPIO).\r
+ APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through \r
+ configurable prescalers and used to clock the peripherals mapped on these busses.\r
+ You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks. \r
+\r
+Note: All the peripheral clocks are derived from the System clock (SYSCLK) except:\r
+==== - The USB 48 MHz clock which is derived from the PLL VCO clock.\r
+ - The ADC clock which is always the HSI clock. A divider by 1, 2 or 4 allows\r
+ to adapt the clock frequency to the device operating conditions. \r
+ - The RTC/LCD clock which is derived from the LSE, LSI or 1 MHz HSE_RTC (HSE\r
+ divided by a programmable prescaler).\r
+ The System clock (SYSCLK) frequency must be higher or equal to the RTC/LCD\r
+ clock frequency.\r
+ - IWDG clock which is always the LSI clock.\r
+ \r
+ 2. The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 32 MHz.\r
+ Depending on the device voltage range, the maximum frequency should be \r
+ adapted accordingly:\r
+ +----------------------------------------------------------------+ \r
+ | Wait states | HCLK clock frequency (MHz) |\r
+ | |------------------------------------------------| \r
+ | (Latency) | voltage range | voltage range | \r
+ | | 1.65 V - 3.6 V | 2.0 V - 3.6 V |\r
+ | |----------------|---------------|---------------| \r
+ | | VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V |\r
+ |-------------- |----------------|---------------|---------------| \r
+ |0WS(1CPU cycle)|0 < HCLK <= 2 |0 < HCLK <= 8 |0 < HCLK <= 16 |\r
+ |---------------|----------------|---------------|---------------| \r
+ |1WS(2CPU cycle)|2 < HCLK <= 4 |8 < HCLK <= 16 |16 < HCLK <= 32| \r
+ +----------------------------------------------------------------+ \r
+\r
+ 3. After reset, the System clock source is the MSI (2 MHz) with 0 WS, Flash\r
+ 32-bit access is enabled and prefetch is disabled.\r
+ \r
+ It is recommended to use the following software sequences to tune the number\r
+ of wait states needed to access the Flash memory with the CPU frequency (HCLK).\r
+ - Increasing the CPU frequency (in the same voltage range)\r
+ - Program the Flash 64-bit access, using "FLASH_ReadAccess64Cmd(ENABLE)" function\r
+ - Check that 64-bit access is taken into account by reading FLASH_ACR\r
+ - Program Flash WS to 1, using "FLASH_SetLatency(FLASH_Latency_1)" function\r
+ - Check that the new number of WS is taken into account by reading FLASH_ACR\r
+ - Modify the CPU clock source, using "RCC_SYSCLKConfig()" function\r
+ - If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function\r
+ - Check that the new CPU clock source is taken into account by reading \r
+ the clock source status, using "RCC_GetSYSCLKSource()" function \r
+ - Decreasing the CPU frequency (in the same voltage range)\r
+ - Modify the CPU clock source, using "RCC_SYSCLKConfig()" function\r
+ - If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function\r
+ - Check that the new CPU clock source is taken into account by reading \r
+ the clock source status, using "RCC_GetSYSCLKSource()" function\r
+ - Program the new number of WS, using "FLASH_SetLatency()" function\r
+ - Check that the new number of WS is taken into account by reading FLASH_ACR\r
+ - Enable the Flash 32-bit access, using "FLASH_ReadAccess64Cmd(DISABLE)" function\r
+ - Check that 32-bit access is taken into account by reading FLASH_ACR\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the system clock (SYSCLK).\r
+ * @note - The MSI is used (enabled by hardware) as system clock source after\r
+ * startup from Reset, wake-up from STOP and STANDBY mode, or in case\r
+ * of failure of the HSE used directly or indirectly as system clock\r
+ * (if the Clock Security System CSS is enabled).\r
+ * - A switch from one clock source to another occurs only if the target\r
+ * clock source is ready (clock stable after startup delay or PLL locked). \r
+ * If a clock source which is not yet ready is selected, the switch will\r
+ * occur when the clock source will be ready. \r
+ * You can use RCC_GetSYSCLKSource() function to know which clock is\r
+ * currently used as system clock source. \r
+ * @param RCC_SYSCLKSource: specifies the clock source used as system clock source \r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SYSCLKSource_MSI: MSI selected as system clock source\r
+ * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source\r
+ * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source\r
+ * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source\r
+ * @retval None\r
+ */\r
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));\r
+ \r
+ tmpreg = RCC->CFGR;\r
+ \r
+ /* Clear SW[1:0] bits */\r
+ tmpreg &= ~RCC_CFGR_SW;\r
+ \r
+ /* Set SW[1:0] bits according to RCC_SYSCLKSource value */\r
+ tmpreg |= RCC_SYSCLKSource;\r
+ \r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Returns the clock source used as system clock.\r
+ * @param None\r
+ * @retval The clock source used as system clock. The returned value can be one \r
+ * of the following values:\r
+ * - 0x00: MSI used as system clock\r
+ * - 0x04: HSI used as system clock \r
+ * - 0x08: HSE used as system clock\r
+ * - 0x0C: PLL used as system clock\r
+ */\r
+uint8_t RCC_GetSYSCLKSource(void)\r
+{\r
+ return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));\r
+}\r
+\r
+/**\r
+ * @brief Configures the AHB clock (HCLK).\r
+ * @note Depending on the device voltage range, the software has to set correctly\r
+ * these bits to ensure that the system frequency does not exceed the\r
+ * maximum allowed frequency (for more details refer to section above\r
+ * "CPU, AHB and APB busses clocks configuration functions")\r
+ * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from \r
+ * the system clock (SYSCLK).\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK\r
+ * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2\r
+ * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4\r
+ * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8\r
+ * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16\r
+ * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64\r
+ * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128\r
+ * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256\r
+ * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512\r
+ * @retval None\r
+ */\r
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_HCLK(RCC_SYSCLK));\r
+ \r
+ tmpreg = RCC->CFGR;\r
+ \r
+ /* Clear HPRE[3:0] bits */\r
+ tmpreg &= ~RCC_CFGR_HPRE;\r
+ \r
+ /* Set HPRE[3:0] bits according to RCC_SYSCLK value */\r
+ tmpreg |= RCC_SYSCLK;\r
+ \r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Configures the Low Speed APB clock (PCLK1).\r
+ * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from \r
+ * the AHB clock (HCLK).\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_HCLK_Div1: APB1 clock = HCLK\r
+ * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2\r
+ * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4\r
+ * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8\r
+ * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16\r
+ * @retval None\r
+ */\r
+void RCC_PCLK1Config(uint32_t RCC_HCLK)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PCLK(RCC_HCLK));\r
+ \r
+ tmpreg = RCC->CFGR;\r
+ \r
+ /* Clear PPRE1[2:0] bits */\r
+ tmpreg &= ~RCC_CFGR_PPRE1;\r
+ \r
+ /* Set PPRE1[2:0] bits according to RCC_HCLK value */\r
+ tmpreg |= RCC_HCLK;\r
+ \r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Configures the High Speed APB clock (PCLK2).\r
+ * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from \r
+ * the AHB clock (HCLK).\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_HCLK_Div1: APB2 clock = HCLK\r
+ * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2\r
+ * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4\r
+ * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8\r
+ * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16\r
+ * @retval None\r
+ */\r
+void RCC_PCLK2Config(uint32_t RCC_HCLK)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PCLK(RCC_HCLK));\r
+ \r
+ tmpreg = RCC->CFGR;\r
+ \r
+ /* Clear PPRE2[2:0] bits */\r
+ tmpreg &= ~RCC_CFGR_PPRE2;\r
+ \r
+ /* Set PPRE2[2:0] bits according to RCC_HCLK value */\r
+ tmpreg |= RCC_HCLK << 3;\r
+ \r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Returns the frequencies of the System, AHB and APB busses clocks.\r
+ * @note - The frequency returned by this function is not the real frequency\r
+ * in the chip. It is calculated based on the predefined constant and\r
+ * the source selected by RCC_SYSCLKConfig():\r
+ * \r
+ * - If SYSCLK source is MSI, function returns constant the MSI value\r
+ * as defined by the MSI range, refer to RCC_MSIRangeConfig()\r
+ * \r
+ * - If SYSCLK source is HSI, function returns constant HSI_VALUE(*)\r
+ * \r
+ * - If SYSCLK source is HSE, function returns constant HSE_VALUE(**)\r
+ * \r
+ * - If SYSCLK source is PLL, function returns constant HSE_VALUE(**) \r
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.\r
+ * \r
+ * (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value\r
+ * 16 MHz) but the real value may vary depending on the variations\r
+ * in voltage and temperature, refer to RCC_AdjustHSICalibrationValue(). \r
+ * \r
+ * (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value\r
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real\r
+ * frequency of the crystal used. Otherwise, this function may\r
+ * return wrong result.\r
+ * \r
+ * - The result of this function could be not correct when using fractional\r
+ * value for HSE crystal. \r
+ * \r
+ * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold \r
+ * the clocks frequencies. \r
+ * @retval None\r
+ */\r
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)\r
+{\r
+ uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, presc = 0, msirange = 0;\r
+\r
+ /* Get SYSCLK source -------------------------------------------------------*/\r
+ tmp = RCC->CFGR & RCC_CFGR_SWS;\r
+ \r
+ switch (tmp)\r
+ {\r
+ case 0x00: /* MSI used as system clock */\r
+ msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> 13;\r
+ RCC_Clocks->SYSCLK_Frequency = (32768 * (1 << (msirange + 1)));\r
+ break;\r
+ case 0x04: /* HSI used as system clock */\r
+ RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;\r
+ break;\r
+ case 0x08: /* HSE used as system clock */\r
+ RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;\r
+ break;\r
+ case 0x0C: /* PLL used as system clock */\r
+ /* Get PLL clock source and multiplication factor ----------------------*/\r
+ pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;\r
+ plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;\r
+ pllmul = PLLMulTable[(pllmul >> 18)];\r
+ plldiv = (plldiv >> 22) + 1;\r
+ \r
+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;\r
+\r
+ if (pllsource == 0x00)\r
+ {\r
+ /* HSI oscillator clock selected as PLL clock source */\r
+ RCC_Clocks->SYSCLK_Frequency = (((HSI_VALUE) * pllmul) / plldiv);\r
+ }\r
+ else\r
+ {\r
+ /* HSE selected as PLL clock source */\r
+ RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE) * pllmul) / plldiv);\r
+ }\r
+ break;\r
+ default: /* MSI used as system clock */\r
+ msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> 13;\r
+ RCC_Clocks->SYSCLK_Frequency = (32768 * (1 << (msirange + 1)));\r
+ break;\r
+ }\r
+ /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/\r
+ /* Get HCLK prescaler */\r
+ tmp = RCC->CFGR & RCC_CFGR_HPRE;\r
+ tmp = tmp >> 4;\r
+ presc = APBAHBPrescTable[tmp]; \r
+ /* HCLK clock frequency */\r
+ RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;\r
+\r
+ /* Get PCLK1 prescaler */\r
+ tmp = RCC->CFGR & RCC_CFGR_PPRE1;\r
+ tmp = tmp >> 8;\r
+ presc = APBAHBPrescTable[tmp];\r
+ /* PCLK1 clock frequency */\r
+ RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;\r
+\r
+ /* Get PCLK2 prescaler */\r
+ tmp = RCC->CFGR & RCC_CFGR_PPRE2;\r
+ tmp = tmp >> 11;\r
+ presc = APBAHBPrescTable[tmp];\r
+ /* PCLK2 clock frequency */\r
+ RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Group3 Peripheral clocks configuration functions\r
+ * @brief Peripheral clocks configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Peripheral clocks configuration functions\r
+ =============================================================================== \r
+\r
+ This section provide functions allowing to configure the Peripheral clocks. \r
+ \r
+ 1. The RTC/LCD clock which is derived from the LSE, LSI or 1 MHz HSE_RTC (HSE\r
+ divided by a programmable prescaler).\r
+ \r
+ 2. After restart from Reset or wakeup from STANDBY, all peripherals are off\r
+ except internal SRAM, Flash and JTAG. Before to start using a peripheral you\r
+ have to enable its interface clock. You can do this using RCC_AHBPeriphClockCmd()\r
+ , RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions.\r
+\r
+ 3. To reset the peripherals configuration (to the default state after device reset)\r
+ you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and \r
+ RCC_APB1PeriphResetCmd() functions.\r
+ \r
+ 4. To further reduce power consumption in SLEEP mode the peripheral clocks can\r
+ be disabled prior to executing the WFI or WFE instructions. You can do this\r
+ using RCC_AHBPeriphClockLPModeCmd(), RCC_APB2PeriphClockLPModeCmd() and\r
+ RCC_APB1PeriphClockLPModeCmd() functions. \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the RTC and LCD clock (RTCCLK / LCDCLK).\r
+ * @note - As the RTC clock configuration bits are in the RTC domain and write\r
+ * access is denied to this domain after reset, you have to enable write\r
+ * access using PWR_RTCAccessCmd(ENABLE) function before to configure\r
+ * the RTC clock source (to be done once after reset). \r
+ * - Once the RTC clock is configured it can't be changed unless the RTC\r
+ * is reset using RCC_RTCResetCmd function, or by a Power On Reset (POR)\r
+ * - The RTC clock (RTCCLK) is used also to clock the LCD (LCDCLK).\r
+ * \r
+ * @param RCC_RTCCLKSource: specifies the RTC clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock\r
+ * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock\r
+ * @arg RCC_RTCCLKSource_HSE_Div2: HSE divided by 2 selected as RTC clock\r
+ * @arg RCC_RTCCLKSource_HSE_Div4: HSE divided by 4 selected as RTC clock\r
+ * @arg RCC_RTCCLKSource_HSE_Div8: HSE divided by 8 selected as RTC clock\r
+ * @arg RCC_RTCCLKSource_HSE_Div16: HSE divided by 16 selected as RTC clock\r
+ * \r
+ * @note - If the LSE or LSI is used as RTC clock source, the RTC continues to\r
+ * work in STOP and STANDBY modes, and can be used as wakeup source.\r
+ * However, when the HSE clock is used as RTC clock source, the RTC\r
+ * cannot be used in STOP and STANDBY modes.\r
+ * \r
+ * - The maximum input clock frequency for RTC is 1MHz (when using HSE as\r
+ * RTC clock source).\r
+ * \r
+ * @retval None\r
+ */\r
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));\r
+ \r
+ if ((RCC_RTCCLKSource & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE)\r
+ { \r
+ /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */\r
+ tmpreg = RCC->CR;\r
+\r
+ /* Clear RTCPRE[1:0] bits */\r
+ tmpreg &= ~RCC_CR_RTCPRE;\r
+\r
+ /* Configure HSE division factor for RTC clock */\r
+ tmpreg |= (RCC_RTCCLKSource & RCC_CR_RTCPRE);\r
+\r
+ /* Store the new value */\r
+ RCC->CR = tmpreg;\r
+ }\r
+ \r
+ RCC->CSR &= ~RCC_CSR_RTCSEL;\r
+ \r
+ /* Select the RTC clock source */\r
+ RCC->CSR |= (RCC_RTCCLKSource & RCC_CSR_RTCSEL);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the RTC clock.\r
+ * @note This function must be used only after the RTC clock source was selected\r
+ * using the RCC_RTCCLKConfig function.\r
+ * @param NewState: new state of the RTC clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_RTCCLKCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CSR_RTCEN_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Forces or releases the RTC peripheral and associated resources reset.\r
+ * @note This function resets the RTC peripheral, RTC clock source selection\r
+ * (in RCC_CSR) and the backup registers.\r
+ * @param NewState: new state of the RTC reset.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_RTCResetCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CSR_RTCRST_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the AHB peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before \r
+ * using it. \r
+ * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_AHBPeriph_GPIOA\r
+ * @arg RCC_AHBPeriph_GPIOB\r
+ * @arg RCC_AHBPeriph_GPIOC \r
+ * @arg RCC_AHBPeriph_GPIOD\r
+ * @arg RCC_AHBPeriph_GPIOE\r
+ * @arg RCC_AHBPeriph_GPIOH\r
+ * @arg RCC_AHBPeriph_CRC\r
+ * @arg RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode) \r
+ * @arg RCC_AHBPeriph_DMA1\r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->AHBENR |= RCC_AHBPeriph;\r
+ }\r
+ else\r
+ {\r
+ RCC->AHBENR &= ~RCC_AHBPeriph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the High Speed APB (APB2) peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before \r
+ * using it.\r
+ * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_APB2Periph_SYSCFG\r
+ * @arg RCC_APB2Periph_TIM9\r
+ * @arg RCC_APB2Periph_TIM10\r
+ * @arg RCC_APB2Periph_TIM11\r
+ * @arg RCC_APB2Periph_ADC1\r
+ * @arg RCC_APB2Periph_SPI1\r
+ * @arg RCC_APB2Periph_USART1 \r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB2ENR |= RCC_APB2Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB2ENR &= ~RCC_APB2Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before \r
+ * using it.\r
+ * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_APB1Periph_TIM2\r
+ * @arg RCC_APB1Periph_TIM3\r
+ * @arg RCC_APB1Periph_TIM4\r
+ * @arg RCC_APB1Periph_TIM6\r
+ * @arg RCC_APB1Periph_TIM7\r
+ * @arg RCC_APB1Periph_LCD\r
+ * @arg RCC_APB1Periph_WWDG\r
+ * @arg RCC_APB1Periph_SPI2\r
+ * @arg RCC_APB1Periph_USART2\r
+ * @arg RCC_APB1Periph_USART3\r
+ * @arg RCC_APB1Periph_I2C1\r
+ * @arg RCC_APB1Periph_I2C2\r
+ * @arg RCC_APB1Periph_USB\r
+ * @arg RCC_APB1Periph_PWR\r
+ * @arg RCC_APB1Periph_DAC\r
+ * @arg RCC_APB1Periph_COMP \r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB1ENR |= RCC_APB1Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB1ENR &= ~RCC_APB1Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Forces or releases AHB peripheral reset.\r
+ * @param RCC_AHBPeriph: specifies the AHB peripheral to reset.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_AHBPeriph_GPIOA\r
+ * @arg RCC_AHBPeriph_GPIOB\r
+ * @arg RCC_AHBPeriph_GPIOC \r
+ * @arg RCC_AHBPeriph_GPIOD\r
+ * @arg RCC_AHBPeriph_GPIOE\r
+ * @arg RCC_AHBPeriph_GPIOH\r
+ * @arg RCC_AHBPeriph_CRC\r
+ * @arg RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode) \r
+ * @arg RCC_AHBPeriph_DMA1 \r
+ * @param NewState: new state of the specified peripheral reset.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->AHBRSTR |= RCC_AHBPeriph;\r
+ }\r
+ else\r
+ {\r
+ RCC->AHBRSTR &= ~RCC_AHBPeriph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Forces or releases High Speed APB (APB2) peripheral reset.\r
+ * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_APB2Periph_SYSCFG\r
+ * @arg RCC_APB2Periph_TIM9\r
+ * @arg RCC_APB2Periph_TIM10\r
+ * @arg RCC_APB2Periph_TIM11\r
+ * @arg RCC_APB2Periph_ADC1\r
+ * @arg RCC_APB2Periph_SPI1\r
+ * @arg RCC_APB2Periph_USART1 \r
+ * @param NewState: new state of the specified peripheral reset.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB2RSTR |= RCC_APB2Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB2RSTR &= ~RCC_APB2Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Forces or releases Low Speed APB (APB1) peripheral reset.\r
+ * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_APB1Periph_TIM2\r
+ * @arg RCC_APB1Periph_TIM3\r
+ * @arg RCC_APB1Periph_TIM4\r
+ * @arg RCC_APB1Periph_TIM6\r
+ * @arg RCC_APB1Periph_TIM7\r
+ * @arg RCC_APB1Periph_LCD\r
+ * @arg RCC_APB1Periph_WWDG\r
+ * @arg RCC_APB1Periph_SPI2\r
+ * @arg RCC_APB1Periph_USART2\r
+ * @arg RCC_APB1Periph_USART3\r
+ * @arg RCC_APB1Periph_I2C1\r
+ * @arg RCC_APB1Periph_I2C2\r
+ * @arg RCC_APB1Periph_USB\r
+ * @arg RCC_APB1Periph_PWR\r
+ * @arg RCC_APB1Periph_DAC\r
+ * @arg RCC_APB1Periph_COMP \r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB1RSTR |= RCC_APB1Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB1RSTR &= ~RCC_APB1Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the AHB peripheral clock during SLEEP mode.\r
+ * @note - Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * - After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * - By default, all peripheral clocks are enabled during SLEEP mode. \r
+ * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_AHBPeriph_GPIOA\r
+ * @arg RCC_AHBPeriph_GPIOB\r
+ * @arg RCC_AHBPeriph_GPIOC \r
+ * @arg RCC_AHBPeriph_GPIOD\r
+ * @arg RCC_AHBPeriph_GPIOE\r
+ * @arg RCC_AHBPeriph_GPIOH\r
+ * @arg RCC_AHBPeriph_CRC\r
+ * @arg RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode) \r
+ * @arg RCC_AHBPeriph_SRAM \r
+ * @arg RCC_AHBPeriph_DMA1\r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_AHBPeriphClockLPModeCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_AHB_LPMODE_PERIPH(RCC_AHBPeriph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->AHBLPENR |= RCC_AHBPeriph;\r
+ }\r
+ else\r
+ {\r
+ RCC->AHBLPENR &= ~RCC_AHBPeriph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the APB2 peripheral clock during SLEEP mode.\r
+ * @note - Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * - After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * - By default, all peripheral clocks are enabled during SLEEP mode. \r
+ * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_APB2Periph_SYSCFG\r
+ * @arg RCC_APB2Periph_TIM9\r
+ * @arg RCC_APB2Periph_TIM10\r
+ * @arg RCC_APB2Periph_TIM11\r
+ * @arg RCC_APB2Periph_ADC1\r
+ * @arg RCC_APB2Periph_SPI1\r
+ * @arg RCC_APB2Periph_USART1 \r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB2LPENR |= RCC_APB2Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB2LPENR &= ~RCC_APB2Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the APB1 peripheral clock during SLEEP mode.\r
+ * @note - Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * - After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * - By default, all peripheral clocks are enabled during SLEEP mode. \r
+ * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_APB1Periph_TIM2\r
+ * @arg RCC_APB1Periph_TIM3\r
+ * @arg RCC_APB1Periph_TIM4\r
+ * @arg RCC_APB1Periph_TIM6\r
+ * @arg RCC_APB1Periph_TIM7\r
+ * @arg RCC_APB1Periph_LCD\r
+ * @arg RCC_APB1Periph_WWDG\r
+ * @arg RCC_APB1Periph_SPI2\r
+ * @arg RCC_APB1Periph_USART2\r
+ * @arg RCC_APB1Periph_USART3\r
+ * @arg RCC_APB1Periph_I2C1\r
+ * @arg RCC_APB1Periph_I2C2\r
+ * @arg RCC_APB1Periph_USB\r
+ * @arg RCC_APB1Periph_PWR\r
+ * @arg RCC_APB1Periph_DAC\r
+ * @arg RCC_APB1Periph_COMP \r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB1LPENR |= RCC_APB1Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB1LPENR &= ~RCC_APB1Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Group4 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Interrupts and flags management functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified RCC interrupts.\r
+ * @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled\r
+ * and if the HSE clock fails, the CSS interrupt occurs and an NMI is\r
+ * automatically generated. The NMI will be executed indefinitely, and \r
+ * since NMI has higher priority than any other IRQ (and main program)\r
+ * the application will be stacked in the NMI ISR unless the CSS interrupt\r
+ * pending bit is cleared.\r
+ * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt\r
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
+ * @arg RCC_IT_MSIRDY: MSI ready interrupt\r
+ * @param NewState: new state of the specified RCC interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_IT(RCC_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */\r
+ *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */\r
+ *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified RCC flag is set or not.\r
+ * @param RCC_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready\r
+ * @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready \r
+ * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready\r
+ * @arg RCC_FLAG_PLLRDY: PLL clock ready\r
+ * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready\r
+ * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready\r
+ * @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset \r
+ * @arg RCC_FLAG_PINRST: Pin reset\r
+ * @arg RCC_FLAG_PORRST: POR/PDR reset\r
+ * @arg RCC_FLAG_SFTRST: Software reset\r
+ * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset\r
+ * @arg RCC_FLAG_WWDGRST: Window Watchdog reset\r
+ * @arg RCC_FLAG_LPWRRST: Low Power reset\r
+ * @retval The new state of RCC_FLAG (SET or RESET).\r
+ */\r
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)\r
+{\r
+ uint32_t tmp = 0;\r
+ uint32_t statusreg = 0;\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_FLAG(RCC_FLAG));\r
+\r
+ /* Get the RCC register index */\r
+ tmp = RCC_FLAG >> 5;\r
+\r
+ if (tmp == 1) /* The flag to check is in CR register */\r
+ {\r
+ statusreg = RCC->CR;\r
+ }\r
+ else /* The flag to check is in CSR register (tmp == 2) */\r
+ {\r
+ statusreg = RCC->CSR;\r
+ }\r
+\r
+ /* Get the flag position */\r
+ tmp = RCC_FLAG & FLAG_MASK;\r
+\r
+ if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the flag status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the RCC reset flags.\r
+ * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, \r
+ * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void RCC_ClearFlag(void)\r
+{\r
+ /* Set RMVF bit to clear the reset flags */\r
+ RCC->CSR |= RCC_CSR_RMVF;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified RCC interrupt has occurred or not.\r
+ * @param RCC_IT: specifies the RCC interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt\r
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
+ * @arg RCC_IT_MSIRDY: MSI ready interrupt \r
+ * @arg RCC_IT_CSS: Clock Security System interrupt\r
+ * @retval The new state of RCC_IT (SET or RESET).\r
+ */\r
+ITStatus RCC_GetITStatus(uint8_t RCC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_GET_IT(RCC_IT));\r
+ \r
+ /* Check the status of the specified RCC interrupt */\r
+ if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the RCC_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the RCC's interrupt pending bits.\r
+ * @param RCC_IT: specifies the interrupt pending bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt\r
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
+ * @arg RCC_IT_MSIRDY: MSI ready interrupt \r
+ * @arg RCC_IT_CSS: Clock Security System interrupt\r
+ * @retval None\r
+ */\r
+void RCC_ClearITPendingBit(uint8_t RCC_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_CLEAR_IT(RCC_IT));\r
+ \r
+ /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt\r
+ pending bits */\r
+ *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_rtc.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Real-Time Clock (RTC) peripheral: \r
+ * - Initialization\r
+ * - Calendar (Time and Date) configuration\r
+ * - Alarms (Alarm A and Alarm B) configuration\r
+ * - WakeUp Timer configuration\r
+ * - Daylight Saving configuration\r
+ * - Output pin Configuration\r
+ * - Digital Calibration configuration\r
+ * - TimeStamp configuration\r
+ * - Tampers configuration\r
+ * - Backup Data Registers configuration\r
+ * - Output Type Config configuration\r
+ * - Interrupts and flags management \r
+ * \r
+ * @verbatim\r
+ * \r
+ * =================================================================== \r
+ * RTC Domain Reset\r
+ * =================================================================== \r
+ * After power-on reset, the RTC domain (RTC clock source configuration,\r
+ * RTC registers and RTC Backup data registers) is reset. You can also\r
+ * reset this domain by software using the RCC_RTCResetCmd() function. \r
+ * \r
+ * =================================================================== \r
+ * RTC Operating Condition\r
+ * =================================================================== \r
+ * As long as the supply voltage remains in the operating range, \r
+ * the RTC never stops, regardless of the device status (Run mode, \r
+ * low power modes or under reset).\r
+ * \r
+ * =================================================================== \r
+ * RTC Domain Access\r
+ * =================================================================== \r
+ * After reset, the RTC domain (RTC clock source configuration,\r
+ * RTC registers and RTC Backup data registers) are protected against \r
+ * possible stray write accesses. \r
+ * To enable access to the RTC Domain and RTC registers, proceed as follows:\r
+ * - Enable the Power Controller (PWR) APB1 interface clock using the\r
+ * RCC_APB1PeriphClockCmd() function.\r
+ * - Enable access to RTC domain using the PWR_RTCAccessCmd() function.\r
+ * - Select the RTC clock source using the RCC_RTCCLKConfig() function.\r
+ * - Enable RTC Clock using the RCC_RTCCLKCmd() function.\r
+ * \r
+ * =================================================================== \r
+ * RTC Driver: how to use it\r
+ * =================================================================== \r
+ * - Enable the RTC domain access (see description in the section above)\r
+ * - Configure the RTC Prescaler (Asynchronous and Synchronous) and\r
+ * RTC hour format using the RTC_Init() function.\r
+ * \r
+ * Time and Date configuration\r
+ * =========================== \r
+ * - To configure the RTC Calendar (Time and Date) use the RTC_SetTime()\r
+ * and RTC_SetDate() functions.\r
+ * - To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate()\r
+ * functions.\r
+ * - Use the RTC_DayLightSavingConfig() function to add or sub one\r
+ * hour to the RTC Calendar. \r
+ * \r
+ * Alarm configuration\r
+ * =================== \r
+ * - To configure the RTC Alarm use the RTC_SetAlarm() function.\r
+ * - Enable the selected RTC Alarm using the RTC_AlarmCmd() function \r
+ * - To read the RTC Alarm, use the RTC_GetAlarm() function.\r
+ * \r
+ * RTC Wakeup configuration\r
+ * ======================== \r
+ * - Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig()\r
+ * function.\r
+ * - Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter() \r
+ * function \r
+ * - Enable the RTC WakeUp using the RTC_WakeUpCmd() function \r
+ * - To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter() \r
+ * function.\r
+ * \r
+ * Outputs configuration\r
+ * ===================== \r
+ * The RTC has 2 different outputs:\r
+ * - AFO_ALARM: this output is used to manage the RTC Alarm A, Alarm B\r
+ * and WaKeUp signals. \r
+ * To output the selected RTC signal on RTC_AF1 pin, use the \r
+ * RTC_OutputConfig() function. \r
+ * - AFO_CALIB: this output is used to manage the RTC Clock divided \r
+ * by 64 (512Hz) signal.\r
+ * To output the RTC Clock on RTC_AF1 pin, use the RTC_CalibOutputCmd()\r
+ * function. \r
+ * \r
+ * Digital Calibration configuration\r
+ * ================================= \r
+ * - Configure the RTC Digital Calibration Value and the corresponding\r
+ * sign using the RTC_DigitalCalibConfig() function.\r
+ * - Enable the RTC Digital Calibration using the RTC_DigitalCalibCmd() \r
+ * function \r
+ * \r
+ * TimeStamp configuration\r
+ * ======================= \r
+ * - Configure the RTC_AF1 trigger and enables the RTC TimeStamp \r
+ * using the RTC_TimeStampCmd() function.\r
+ * - To read the RTC TimeStamp Time and Date register, use the \r
+ * RTC_GetTimeStamp() function. \r
+ *\r
+ * Tamper configuration\r
+ * ==================== \r
+ * - Configure the RTC Tamper trigger using the RTC_TamperConfig() \r
+ * function.\r
+ * - Enable the RTC Tamper using the RTC_TamperCmd() function.\r
+ *\r
+ * Backup Data Registers configuration\r
+ * =================================== \r
+ * - To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister()\r
+ * function. \r
+ * - To read the RTC Backup Data registers, use the RTC_ReadBackupRegister()\r
+ * function. \r
+ * \r
+ * =================================================================== \r
+ * RTC and low power modes\r
+ * =================================================================== \r
+ * The MCU can be woken up from a low power mode by an RTC alternate \r
+ * function.\r
+ * The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), \r
+ * RTC wakeup, RTC tamper event detection and RTC time stamp event detection.\r
+ * These RTC alternate functions can wake up the system from the Stop \r
+ * and Standby lowpower modes.\r
+ * The system can also wake up from low power modes without depending \r
+ * on an external interrupt (Auto-wakeup mode), by using the RTC alarm \r
+ * or the RTC wakeup events.\r
+ * The RTC provides a programmable time base for waking up from the \r
+ * Stop or Standby mode at regular intervals.\r
+ * Wakeup from STOP and Standby modes is possible only when the RTC \r
+ * clock source is LSE or LSI.\r
+ * \r
+ * =================================================================== \r
+ * Selection of RTC_AF1 alternate functions\r
+ * =================================================================== \r
+ * The RTC_AF1 pin (PC13) can be used for the following purposes:\r
+ * - Wakeup pin 2 (WKUP2) using the PWR_WakeUpPinCmd() function.\r
+ * - AFO_ALARM output \r
+ * - AFO_CALIB output\r
+ * - AFI_TAMPER\r
+ * - AFI_TIMESTAMP\r
+ * \r
+ * +------------------------------------------------------------------------------------------+ \r
+ * | Pin |AFO_ALARM |AFO_CALIB |AFI_TAMPER |AFI_TIMESTAMP | WKUP2 |ALARMOUTTYPE |\r
+ * | configuration | ENABLED | ENABLED | ENABLED | ENABLED |ENABLED | AFO_ALARM |\r
+ * | and function | | | | | |Configuration |\r
+ * |-----------------|----------|----------|-----------|--------------|--------|--------------| \r
+ * | Alarm out | | | | | Don't | |\r
+ * | output OD | 1 | 0 |Don't care | Don't care | care | 0 |\r
+ * |-----------------|----------|----------|-----------|--------------|--------|--------------| \r
+ * | Alarm out | | | | | Don't | |\r
+ * | output PP | 1 | 0 |Don't care | Don't care | care | 1 |\r
+ * |-----------------|----------|----------|-----------|--------------|--------|--------------| \r
+ * | Calibration out | | | | | Don't | |\r
+ * | output PP | 0 | 1 |Don't care | Don't care | care | Don't care |\r
+ * |-----------------|----------|----------|-----------|--------------|--------|--------------| \r
+ * | TAMPER input | | | | | Don't | | \r
+ * | floating | 0 | 0 | 1 | 0 | care | Don't care |\r
+ * |-----------------|----------|----------|-----------|--------------|--------|--------------| \r
+ * | TIMESTAMP and | | | | | Don't | |\r
+ * | TAMPER input | 0 | 0 | 1 | 1 | care | Don't care |\r
+ * | floating | | | | | | | \r
+ * |-----------------|----------|----------|-----------|--------------|--------|--------------| \r
+ * | TIMESTAMP input | | | | | Don't | | \r
+ * | floating | 0 | 0 | 0 | 1 | care | Don't care | \r
+ * |-----------------|----------|----------|-----------|--------------|--------|--------------| \r
+ * | Wakeup Pin 2 | 0 | 0 | 0 | 0 | 1 | Don't care | \r
+ * |-----------------|----------|----------|-----------|--------------|--------|--------------| \r
+ * | Standard GPIO | 0 | 0 | 0 | 0 | 0 | Don't care | \r
+ * +------------------------------------------------------------------------------------------+ \r
+ *\r
+ * @endverbatim\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_rtc.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RTC \r
+ * @brief RTC driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+\r
+/* Masks Definition */\r
+#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)\r
+#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F) \r
+#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF) \r
+#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F)\r
+#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \\r
+ RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \\r
+ RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \\r
+ RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F ))\r
+\r
+#define INITMODE_TIMEOUT ((uint32_t) 0x00002000)\r
+#define SYNCHRO_TIMEOUT ((uint32_t) 0x00001000)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+static uint8_t RTC_ByteToBcd2(uint8_t Value);\r
+static uint8_t RTC_Bcd2ToByte(uint8_t Value);\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup RTC_Private_Functions\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup RTC_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Initialization and Configuration functions\r
+ =============================================================================== \r
+\r
+ This section provide functions allowing to initialize and configure the RTC\r
+ Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers\r
+ Write protection, enter and exit the RTC initialization mode, RTC registers\r
+ synchronization check and reference clock detection enable.\r
+ \r
+ 1. The RTC Prescaler is programmed to generate the RTC 1Hz time base. It is\r
+ split into 2 programmable prescalers to minimize power consumption.\r
+ - A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler.\r
+ - When both prescalers are used, it is recommended to configure the asynchronous\r
+ prescaler to a high value to minimize consumption.\r
+\r
+ 2. All RTC registers are Write protected. Writing to the RTC registers\r
+ is enabled by writing a key into the Write Protection register, RTC_WPR.\r
+\r
+ 3. To Configure the RTC Calendar, user application should enter initialization\r
+ mode. In this mode, the calendar counter is stopped and its value can be \r
+ updated. When the initialization sequence is complete, the calendar restarts \r
+ counting after 4 RTCCLK cycles.\r
+\r
+ 4. To read the calendar through the shadow registers after Calendar initialization,\r
+ calendar update or after wakeup from low power modes the software must first \r
+ clear the RSF flag. The software must then wait until it is set again before \r
+ reading the calendar, which means that the calendar registers have been \r
+ correctly copied into the RTC_TR and RTC_DR shadow registers.\r
+ The RTC_WaitForSynchro() function implements the above software sequence \r
+ (RSF clear and RSF check).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the RTC registers to their default reset values.\r
+ * @note This function doesn't reset the RTC Clock source and RTC Backup Data\r
+ * registers. \r
+ * @param None\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC registers are deinitialized\r
+ * - ERROR: RTC registers are not deinitialized\r
+ */\r
+ErrorStatus RTC_DeInit(void)\r
+{\r
+ __IO uint32_t wutcounter = 0x00;\r
+ uint32_t wutwfstatus = 0x00;\r
+ ErrorStatus status = ERROR;\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Set Initialization mode */\r
+ if (RTC_EnterInitMode() == ERROR)\r
+ {\r
+ status = ERROR;\r
+ } \r
+ else\r
+ {\r
+ /* Reset TR, DR and CR registers */\r
+ RTC->TR = (uint32_t)0x00000000;\r
+ RTC->DR = (uint32_t)0x00002101;\r
+ /* Reset All CR bits except CR[2:0] */\r
+ RTC->CR &= (uint32_t)0x00000007;\r
+ \r
+ /* Wait till RTC WUTWF flag is set and if Time out is reached exit */\r
+ do\r
+ {\r
+ wutwfstatus = RTC->ISR & RTC_ISR_WUTWF;\r
+ wutcounter++; \r
+ } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));\r
+ \r
+ if ((RTC->ISR & RTC_ISR_WUTWF) == RESET)\r
+ {\r
+ status = ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Reset all RTC CR register bits */\r
+ RTC->CR &= (uint32_t)0x00000000;\r
+ RTC->WUTR = (uint32_t)0x0000FFFF;\r
+ RTC->PRER = (uint32_t)0x007F00FF;\r
+ RTC->CALIBR = (uint32_t)0x00000000;\r
+ RTC->ALRMAR = (uint32_t)0x00000000; \r
+ RTC->ALRMBR = (uint32_t)0x00000000;\r
+ \r
+ /* Reset ISR register and exit initialization mode */\r
+ RTC->ISR = (uint32_t)0x00000000;\r
+ \r
+ /* Reset Tamper and alternate functions configuration register */\r
+ RTC->TAFCR = 0x00000000;\r
+ \r
+ if(RTC_WaitForSynchro() == ERROR)\r
+ {\r
+ status = ERROR;\r
+ }\r
+ else\r
+ {\r
+ status = SUCCESS; \r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the RTC registers according to the specified parameters \r
+ * in RTC_InitStruct.\r
+ * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure that contains \r
+ * the configuration information for the RTC peripheral.\r
+ * @note The RTC Prescaler register is write protected and can be written in \r
+ * initialization mode only. \r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC registers are initialized\r
+ * - ERROR: RTC registers are not initialized \r
+ */\r
+ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct)\r
+{\r
+ ErrorStatus status = ERROR;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat));\r
+ assert_param(IS_RTC_ASYNCH_PREDIV(RTC_InitStruct->RTC_AsynchPrediv));\r
+ assert_param(IS_RTC_SYNCH_PREDIV(RTC_InitStruct->RTC_SynchPrediv));\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Set Initialization mode */\r
+ if (RTC_EnterInitMode() == ERROR)\r
+ {\r
+ status = ERROR;\r
+ } \r
+ else\r
+ {\r
+ /* Clear RTC CR FMT Bit */\r
+ RTC->CR &= ((uint32_t)~(RTC_CR_FMT));\r
+ /* Set RTC_CR register */\r
+ RTC->CR |= ((uint32_t)(RTC_InitStruct->RTC_HourFormat));\r
+ \r
+ /* Configure the RTC PRER */\r
+ RTC->PRER = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv);\r
+ RTC->PRER |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16);\r
+\r
+ /* Exit Initialization mode */\r
+ RTC_ExitInitMode();\r
+\r
+ status = SUCCESS; \r
+ }\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Fills each RTC_InitStruct member with its default value.\r
+ * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure which will be \r
+ * initialized.\r
+ * @retval None\r
+ */\r
+void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct)\r
+{\r
+ /* Initialize the RTC_HourFormat member */\r
+ RTC_InitStruct->RTC_HourFormat = RTC_HourFormat_24;\r
+ \r
+ /* Initialize the RTC_AsynchPrediv member */\r
+ RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F;\r
+\r
+ /* Initialize the RTC_SynchPrediv member */\r
+ RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF; \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the RTC registers write protection.\r
+ * @note All the RTC registers are write protected except for RTC_ISR[13:8], \r
+ * RTC_TAFCR and RTC_BKPxR.\r
+ * @note Writing a wrong key reactivates the write protection.\r
+ * @note The protection mechanism is not affected by system reset. \r
+ * @param NewState: new state of the write protection.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RTC_WriteProtectionCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enters the RTC Initialization mode.\r
+ * @note The RTC Initialization mode is write protected, use the \r
+ * RTC_WriteProtectionCmd(DISABLE) before calling this function. \r
+ * @param None\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC is in Init mode\r
+ * - ERROR: RTC is not in Init mode \r
+ */\r
+ErrorStatus RTC_EnterInitMode(void)\r
+{\r
+ __IO uint32_t initcounter = 0x00;\r
+ ErrorStatus status = ERROR;\r
+ uint32_t initstatus = 0x00;\r
+ \r
+ /* Check if the Initialization mode is set */\r
+ if ((RTC->ISR & RTC_ISR_INITF) == (uint32_t)RESET)\r
+ {\r
+ /* Set the Initialization mode */\r
+ RTC->ISR = (uint32_t)RTC_INIT_MASK;\r
+ \r
+ /* Wait till RTC is in INIT state and if Time out is reached exit */\r
+ do\r
+ {\r
+ initstatus = RTC->ISR & RTC_ISR_INITF;\r
+ initcounter++; \r
+ } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00));\r
+ \r
+ if ((RTC->ISR & RTC_ISR_INITF) != RESET)\r
+ {\r
+ status = SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ status = ERROR;\r
+ } \r
+ }\r
+ else\r
+ {\r
+ status = SUCCESS; \r
+ } \r
+ \r
+ return (status); \r
+}\r
+\r
+/**\r
+ * @brief Exits the RTC Initialization mode.\r
+ * @note When the initialization sequence is complete, the calendar restarts \r
+ * counting after 4 RTCCLK cycles. \r
+ * @note The RTC Initialization mode is write protected, use the \r
+ * RTC_WriteProtectionCmd(DISABLE) before calling this function. \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void RTC_ExitInitMode(void)\r
+{ \r
+ /* Exit Initialization mode */\r
+ RTC->ISR &= (uint32_t)~RTC_ISR_INIT; \r
+}\r
+\r
+/**\r
+ * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are \r
+ * synchronized with RTC APB clock.\r
+ * @note The RTC Resynchronization mode is write protected, use the \r
+ * RTC_WriteProtectionCmd(DISABLE) before calling this function. \r
+ * @note To read the calendar through the shadow registers after Calendar \r
+ * initialization, calendar update or after wakeup from low power modes \r
+ * the software must first clear the RSF flag. \r
+ * The software must then wait until it is set again before reading \r
+ * the calendar, which means that the calendar registers have been \r
+ * correctly copied into the RTC_TR and RTC_DR shadow registers. \r
+ * @param None\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC registers are synchronised\r
+ * - ERROR: RTC registers are not synchronised\r
+ */\r
+ErrorStatus RTC_WaitForSynchro(void)\r
+{\r
+ __IO uint32_t synchrocounter = 0;\r
+ ErrorStatus status = ERROR;\r
+ uint32_t synchrostatus = 0x00;\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+ \r
+ /* Clear RSF flag */\r
+ RTC->ISR &= (uint32_t)RTC_RSF_MASK;\r
+ \r
+ /* Wait the registers to be synchronised */\r
+ do\r
+ {\r
+ synchrostatus = RTC->ISR & RTC_ISR_RSF;\r
+ synchrocounter++; \r
+ } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00));\r
+ \r
+ if ((RTC->ISR & RTC_ISR_RSF) != RESET)\r
+ {\r
+ status = SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ status = ERROR;\r
+ } \r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+ \r
+ return (status); \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the RTC reference clock detection.\r
+ * @param NewState: new state of the RTC reference clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC reference clock detection is enabled\r
+ * - ERROR: RTC reference clock detection is disabled \r
+ */\r
+ErrorStatus RTC_RefClockCmd(FunctionalState NewState)\r
+{ \r
+ ErrorStatus status = ERROR;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+ \r
+ /* Set Initialization mode */\r
+ if (RTC_EnterInitMode() == ERROR)\r
+ {\r
+ status = ERROR;\r
+ } \r
+ else\r
+ { \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the RTC reference clock detection */\r
+ RTC->CR |= RTC_CR_REFCKON; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the RTC reference clock detection */\r
+ RTC->CR &= ~RTC_CR_REFCKON; \r
+ }\r
+ /* Exit Initialization mode */\r
+ RTC_ExitInitMode();\r
+ \r
+ status = SUCCESS;\r
+ }\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+ \r
+ return status; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group2 Time and Date configuration functions\r
+ * @brief Time and Date configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Time and Date configuration functions\r
+ =============================================================================== \r
+\r
+ This section provide functions allowing to program and read the RTC Calendar\r
+ (Time and Date).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Set the RTC current time.\r
+ * @param RTC_Format: specifies the format of the entered parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Format_BIN: Binary data format \r
+ * @arg RTC_Format_BCD: BCD data format\r
+ * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that contains \r
+ * the time configuration information for the RTC. \r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC Time register is configured\r
+ * - ERROR: RTC Time register is not configured\r
+ */\r
+ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ ErrorStatus status = ERROR;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(RTC_Format));\r
+ \r
+ if (RTC_Format == RTC_Format_BIN)\r
+ {\r
+ if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)\r
+ {\r
+ assert_param(IS_RTC_HOUR12(RTC_TimeStruct->RTC_Hours));\r
+ assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12));\r
+ } \r
+ else\r
+ {\r
+ RTC_TimeStruct->RTC_H12 = 0x00;\r
+ assert_param(IS_RTC_HOUR24(RTC_TimeStruct->RTC_Hours));\r
+ }\r
+ assert_param(IS_RTC_MINUTES(RTC_TimeStruct->RTC_Minutes));\r
+ assert_param(IS_RTC_SECONDS(RTC_TimeStruct->RTC_Seconds));\r
+ }\r
+ else\r
+ {\r
+ if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)\r
+ {\r
+ tmpreg = RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);\r
+ assert_param(IS_RTC_HOUR12(tmpreg));\r
+ assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); \r
+ } \r
+ else\r
+ {\r
+ RTC_TimeStruct->RTC_H12 = 0x00;\r
+ assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours)));\r
+ }\r
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes)));\r
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds)));\r
+ }\r
+ \r
+ /* Check the input parameters format */\r
+ if (RTC_Format != RTC_Format_BIN)\r
+ {\r
+ tmpreg = (((uint32_t)(RTC_TimeStruct->RTC_Hours) << 16) | \\r
+ ((uint32_t)(RTC_TimeStruct->RTC_Minutes) << 8) | \\r
+ ((uint32_t)RTC_TimeStruct->RTC_Seconds) | \\r
+ ((uint32_t)(RTC_TimeStruct->RTC_H12) << 16)); \r
+ } \r
+ else\r
+ {\r
+ tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Hours) << 16) | \\r
+ ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Minutes) << 8) | \\r
+ ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Seconds)) | \\r
+ (((uint32_t)RTC_TimeStruct->RTC_H12) << 16));\r
+ } \r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Set Initialization mode */\r
+ if (RTC_EnterInitMode() == ERROR)\r
+ {\r
+ status = ERROR;\r
+ } \r
+ else\r
+ {\r
+ /* Set the RTC_TR register */\r
+ RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);\r
+\r
+ /* Exit Initialization mode */\r
+ RTC_ExitInitMode(); \r
+\r
+ if(RTC_WaitForSynchro() == ERROR)\r
+ {\r
+ status = ERROR;\r
+ }\r
+ else\r
+ {\r
+ status = SUCCESS;\r
+ }\r
+ \r
+ }\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Fills each RTC_TimeStruct member with its default value\r
+ * (Time = 00h:00min:00sec).\r
+ * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure which will be \r
+ * initialized.\r
+ * @retval None\r
+ */\r
+void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct)\r
+{\r
+ /* Time = 00h:00min:00sec */\r
+ RTC_TimeStruct->RTC_H12 = RTC_H12_AM;\r
+ RTC_TimeStruct->RTC_Hours = 0;\r
+ RTC_TimeStruct->RTC_Minutes = 0;\r
+ RTC_TimeStruct->RTC_Seconds = 0; \r
+}\r
+\r
+/**\r
+ * @brief Get the RTC current Time.\r
+ * @param RTC_Format: specifies the format of the returned parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Format_BIN: Binary data format \r
+ * @arg RTC_Format_BCD: BCD data format\r
+ * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that will \r
+ * contain the returned current time configuration. \r
+ * @retval None\r
+ */\r
+void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(RTC_Format));\r
+\r
+ /* Get the RTC_TR register */\r
+ tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK); \r
+ \r
+ /* Fill the structure fields with the read parameters */\r
+ RTC_TimeStruct->RTC_Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16);\r
+ RTC_TimeStruct->RTC_Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8);\r
+ RTC_TimeStruct->RTC_Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));\r
+ RTC_TimeStruct->RTC_H12 = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); \r
+\r
+ /* Check the input parameters format */\r
+ if (RTC_Format == RTC_Format_BIN)\r
+ {\r
+ /* Convert the structure parameters to Binary format */\r
+ RTC_TimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);\r
+ RTC_TimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes);\r
+ RTC_TimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds); \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Set the RTC current date.\r
+ * @param RTC_Format: specifies the format of the entered parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Format_BIN: Binary data format \r
+ * @arg RTC_Format_BCD: BCD data format\r
+ * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains \r
+ * the date configuration information for the RTC.\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC Date register is configured\r
+ * - ERROR: RTC Date register is not configured\r
+ */\r
+ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ ErrorStatus status = ERROR;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(RTC_Format));\r
+\r
+ if ((RTC_Format == RTC_Format_BIN) && ((RTC_DateStruct->RTC_Month & 0x10) == 0x10))\r
+ {\r
+ RTC_DateStruct->RTC_Month = (RTC_DateStruct->RTC_Month & (uint32_t)~(0x10)) + 0x0A;\r
+ } \r
+ if (RTC_Format == RTC_Format_BIN)\r
+ {\r
+ assert_param(IS_RTC_YEAR(RTC_DateStruct->RTC_Year));\r
+ assert_param(IS_RTC_MONTH(RTC_DateStruct->RTC_Month));\r
+ assert_param(IS_RTC_DATE(RTC_DateStruct->RTC_Date));\r
+ }\r
+ else\r
+ {\r
+ assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year)));\r
+ tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);\r
+ assert_param(IS_RTC_MONTH(tmpreg));\r
+ tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);\r
+ assert_param(IS_RTC_DATE(tmpreg));\r
+ }\r
+ assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->RTC_WeekDay));\r
+\r
+ /* Check the input parameters format */\r
+ if (RTC_Format != RTC_Format_BIN)\r
+ {\r
+ tmpreg = ((((uint32_t)RTC_DateStruct->RTC_Year) << 16) | \\r
+ (((uint32_t)RTC_DateStruct->RTC_Month) << 8) | \\r
+ ((uint32_t)RTC_DateStruct->RTC_Date) | \\r
+ (((uint32_t)RTC_DateStruct->RTC_WeekDay) << 13)); \r
+ } \r
+ else\r
+ {\r
+ tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Year) << 16) | \\r
+ ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Month) << 8) | \\r
+ ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Date)) | \\r
+ ((uint32_t)RTC_DateStruct->RTC_WeekDay << 13));\r
+ }\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Set Initialization mode */\r
+ if (RTC_EnterInitMode() == ERROR)\r
+ {\r
+ status = ERROR;\r
+ } \r
+ else\r
+ {\r
+ /* Set the RTC_DR register */\r
+ RTC->DR = (uint32_t)(tmpreg & RTC_DR_RESERVED_MASK);\r
+\r
+ /* Exit Initialization mode */\r
+ RTC_ExitInitMode(); \r
+\r
+ if(RTC_WaitForSynchro() == ERROR)\r
+ {\r
+ status = ERROR;\r
+ }\r
+ else\r
+ {\r
+ status = SUCCESS;\r
+ }\r
+ }\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Fills each RTC_DateStruct member with its default value\r
+ * (Monday, January 01 xx00).\r
+ * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure which will be \r
+ * initialized.\r
+ * @retval None\r
+ */\r
+void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct)\r
+{\r
+ /* Monday, January 01 xx00 */\r
+ RTC_DateStruct->RTC_WeekDay = RTC_Weekday_Monday;\r
+ RTC_DateStruct->RTC_Date = 1;\r
+ RTC_DateStruct->RTC_Month = RTC_Month_January;\r
+ RTC_DateStruct->RTC_Year = 0;\r
+}\r
+\r
+/**\r
+ * @brief Get the RTC current date. \r
+ * @param RTC_Format: specifies the format of the returned parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Format_BIN: Binary data format \r
+ * @arg RTC_Format_BCD: BCD data format\r
+ * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that will \r
+ * contain the returned current date configuration. \r
+ * @retval None\r
+ */\r
+void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(RTC_Format));\r
+ \r
+ /* Get the RTC_TR register */\r
+ tmpreg = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK); \r
+\r
+ /* Fill the structure fields with the read parameters */\r
+ RTC_DateStruct->RTC_Year = (uint8_t)((tmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16);\r
+ RTC_DateStruct->RTC_Month = (uint8_t)((tmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8);\r
+ RTC_DateStruct->RTC_Date = (uint8_t)(tmpreg & (RTC_DR_DT | RTC_DR_DU));\r
+ RTC_DateStruct->RTC_WeekDay = (uint8_t)((tmpreg & (RTC_DR_WDU)) >> 13); \r
+\r
+ /* Check the input parameters format */\r
+ if (RTC_Format == RTC_Format_BIN)\r
+ {\r
+ /* Convert the structure parameters to Binary format */\r
+ RTC_DateStruct->RTC_Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year);\r
+ RTC_DateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);\r
+ RTC_DateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);\r
+ RTC_DateStruct->RTC_WeekDay = (uint8_t)(RTC_DateStruct->RTC_WeekDay); \r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group3 Alarms configuration functions\r
+ * @brief Alarms (Alarm A and Alarm B) configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Alarms (Alarm A and Alarm B) configuration functions\r
+ =============================================================================== \r
+\r
+ This section provide functions allowing to program and read the RTC Alarms.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Set the specified RTC Alarm.\r
+ * @note The Alarm register can only be written when the corresponding Alarm\r
+ * is disabled (Use the RTC_AlarmCmd(DISABLE)). \r
+ * @param RTC_Format: specifies the format of the returned parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Format_BIN: Binary data format \r
+ * @arg RTC_Format_BCD: BCD data format\r
+ * @param RTC_Alarm: specifies the alarm to be configured.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Alarm_A: to select Alarm A\r
+ * @arg RTC_Alarm_B: to select Alarm B \r
+ * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that \r
+ * contains the alarm configuration parameters. \r
+ * @retval None\r
+ */\r
+void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(RTC_Format));\r
+ assert_param(IS_RTC_ALARM(RTC_Alarm));\r
+ assert_param(IS_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask));\r
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel));\r
+\r
+ if (RTC_Format == RTC_Format_BIN)\r
+ {\r
+ if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)\r
+ {\r
+ assert_param(IS_RTC_HOUR12(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));\r
+ assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));\r
+ } \r
+ else\r
+ {\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;\r
+ assert_param(IS_RTC_HOUR24(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));\r
+ }\r
+ assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes));\r
+ assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds));\r
+ \r
+ if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)\r
+ {\r
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_AlarmStruct->RTC_AlarmDateWeekDay));\r
+ }\r
+ else\r
+ {\r
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_AlarmStruct->RTC_AlarmDateWeekDay));\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)\r
+ {\r
+ tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours);\r
+ assert_param(IS_RTC_HOUR12(tmpreg));\r
+ assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));\r
+ } \r
+ else\r
+ {\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;\r
+ assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)));\r
+ }\r
+ \r
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)));\r
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)));\r
+ \r
+ if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)\r
+ {\r
+ tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);\r
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); \r
+ }\r
+ else\r
+ {\r
+ tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);\r
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); \r
+ } \r
+ }\r
+\r
+ /* Check the input parameters format */\r
+ if (RTC_Format != RTC_Format_BIN)\r
+ {\r
+ tmpreg = (((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \\r
+ ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \\r
+ ((uint32_t)RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds) | \\r
+ ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \\r
+ ((uint32_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \\r
+ ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \\r
+ ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); \r
+ } \r
+ else\r
+ {\r
+ tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \\r
+ ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \\r
+ ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)) | \\r
+ ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \\r
+ ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \\r
+ ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \\r
+ ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); \r
+ } \r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Configure the Alarm register */\r
+ if (RTC_Alarm == RTC_Alarm_A)\r
+ {\r
+ RTC->ALRMAR = (uint32_t)tmpreg;\r
+ }\r
+ else\r
+ {\r
+ RTC->ALRMBR = (uint32_t)tmpreg;\r
+ }\r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+}\r
+\r
+/**\r
+ * @brief Fills each RTC_AlarmStruct member with its default value\r
+ * (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask =\r
+ * all fields are masked).\r
+ * @param RTC_AlarmStruct: pointer to a @ref RTC_AlarmTypeDef structure which\r
+ * will be initialized.\r
+ * @retval None\r
+ */\r
+void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct)\r
+{\r
+ /* Alarm Time Settings : Time = 00h:00mn:00sec */\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = RTC_H12_AM;\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = 0;\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = 0;\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = 0;\r
+\r
+ /* Alarm Date Settings : Date = 1st day of the month */\r
+ RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date;\r
+ RTC_AlarmStruct->RTC_AlarmDateWeekDay = 1;\r
+\r
+ /* Alarm Masks Settings : Mask = all fields are not masked */\r
+ RTC_AlarmStruct->RTC_AlarmMask = RTC_AlarmMask_None;\r
+}\r
+\r
+/**\r
+ * @brief Get the RTC Alarm value and masks.\r
+ * @param RTC_Format: specifies the format of the output parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Format_BIN: Binary data format \r
+ * @arg RTC_Format_BCD: BCD data format\r
+ * @param RTC_Alarm: specifies the alarm to be read.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Alarm_A: to select Alarm A\r
+ * @arg RTC_Alarm_B: to select Alarm B \r
+ * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will \r
+ * contains the output alarm configuration values. \r
+ * @retval None\r
+ */\r
+void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(RTC_Format));\r
+ assert_param(IS_RTC_ALARM(RTC_Alarm)); \r
+\r
+ /* Get the RTC_ALRMxR register */\r
+ if (RTC_Alarm == RTC_Alarm_A)\r
+ {\r
+ tmpreg = (uint32_t)(RTC->ALRMAR);\r
+ }\r
+ else\r
+ {\r
+ tmpreg = (uint32_t)(RTC->ALRMBR);\r
+ }\r
+\r
+ /* Fill the structure with the read parameters */\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | \\r
+ RTC_ALRMAR_HU)) >> 16);\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | \\r
+ RTC_ALRMAR_MNU)) >> 8);\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | \\r
+ RTC_ALRMAR_SU));\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16);\r
+ RTC_AlarmStruct->RTC_AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24);\r
+ RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);\r
+ RTC_AlarmStruct->RTC_AlarmMask = (uint32_t)(tmpreg & RTC_AlarmMask_All);\r
+\r
+ if (RTC_Format == RTC_Format_BIN)\r
+ {\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = RTC_Bcd2ToByte(RTC_AlarmStruct-> \\r
+ RTC_AlarmTime.RTC_Hours);\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct-> \\r
+ RTC_AlarmTime.RTC_Minutes);\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct-> \\r
+ RTC_AlarmTime.RTC_Seconds);\r
+ RTC_AlarmStruct->RTC_AlarmDateWeekDay = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);\r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified RTC Alarm.\r
+ * @param RTC_Alarm: specifies the alarm to be configured.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RTC_Alarm_A: to select Alarm A\r
+ * @arg RTC_Alarm_B: to select Alarm B \r
+ * @param NewState: new state of the specified alarm.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC Alarm is enabled/disabled\r
+ * - ERROR: RTC Alarm is not enabled/disabled \r
+ */\r
+ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState)\r
+{\r
+ __IO uint32_t alarmcounter = 0x00;\r
+ uint32_t alarmstatus = 0x00;\r
+ ErrorStatus status = ERROR;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_CMD_ALARM(RTC_Alarm));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Configure the Alarm state */\r
+ if (NewState != DISABLE)\r
+ {\r
+ RTC->CR |= (uint32_t)RTC_Alarm;\r
+\r
+ status = SUCCESS; \r
+ }\r
+ else\r
+ { \r
+ /* Disable the Alarm in RTC_CR register */\r
+ RTC->CR &= (uint32_t)~RTC_Alarm;\r
+ \r
+ /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */\r
+ do\r
+ {\r
+ alarmstatus = RTC->ISR & (RTC_Alarm >> 8);\r
+ alarmcounter++; \r
+ } while((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00));\r
+ \r
+ if ((RTC->ISR & (RTC_Alarm >> 8)) == RESET)\r
+ {\r
+ status = ERROR;\r
+ } \r
+ else\r
+ {\r
+ status = SUCCESS;\r
+ } \r
+ } \r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group4 WakeUp Timer configuration functions\r
+ * @brief WakeUp Timer configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ WakeUp Timer configuration functions\r
+ =============================================================================== \r
+\r
+ This section provide functions allowing to program and read the RTC WakeUp.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the RTC Wakeup clock source.\r
+ * @note The WakeUp Clock source can only be changed when the RTC WakeUp\r
+ * is disabled (Use the RTC_WakeUpCmd(DISABLE)). \r
+ * @param RTC_WakeUpClock: Wakeup Clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_WakeUpClock_RTCCLK_Div16\r
+ * @arg RTC_WakeUpClock_RTCCLK_Div8\r
+ * @arg RTC_WakeUpClock_RTCCLK_Div4\r
+ * @arg RTC_WakeUpClock_RTCCLK_Div2\r
+ * @arg RTC_WakeUpClock_CK_SPRE_16bits\r
+ * @arg RTC_WakeUpClock_CK_SPRE_17bits\r
+ * @retval None\r
+ */\r
+void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_WAKEUP_CLOCK(RTC_WakeUpClock));\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Clear the Wakeup Timer clock source bits in CR register */\r
+ RTC->CR &= (uint32_t)~RTC_CR_WUCKSEL;\r
+\r
+ /* Configure the clock source */\r
+ RTC->CR |= (uint32_t)RTC_WakeUpClock;\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+}\r
+\r
+/**\r
+ * @brief Configures the RTC Wakeup counter.\r
+ * @note The RTC WakeUp counter can only be written when the RTC WakeUp\r
+ * is disabled (Use the RTC_WakeUpCmd(DISABLE)). \r
+ * @param RTC_WakeUpCounter: specifies the WakeUp counter.\r
+ * This parameter can be a value from 0x0000 to 0xFFFF. \r
+ * @retval None\r
+ */\r
+void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_WAKEUP_COUNTER(RTC_WakeUpCounter));\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+ \r
+ /* Configure the Wakeup Timer counter */\r
+ RTC->WUTR = (uint32_t)RTC_WakeUpCounter;\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+}\r
+\r
+/**\r
+ * @brief Returns the RTC WakeUp timer counter value.\r
+ * @param None\r
+ * @retval The RTC WakeUp Counter value.\r
+ */\r
+uint32_t RTC_GetWakeUpCounter(void)\r
+{\r
+ /* Get the counter value */\r
+ return ((uint32_t)(RTC->WUTR & RTC_WUTR_WUT));\r
+}\r
+\r
+/**\r
+ * @brief Enables or Disables the RTC WakeUp timer.\r
+ * @param NewState: new state of the WakeUp timer.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+ErrorStatus RTC_WakeUpCmd(FunctionalState NewState)\r
+{\r
+ __IO uint32_t wutcounter = 0x00;\r
+ uint32_t wutwfstatus = 0x00;\r
+ ErrorStatus status = ERROR;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the Wakeup Timer */\r
+ RTC->CR |= (uint32_t)RTC_CR_WUTE;\r
+ status = SUCCESS; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the Wakeup Timer */\r
+ RTC->CR &= (uint32_t)~RTC_CR_WUTE;\r
+ /* Wait till RTC WUTWF flag is set and if Time out is reached exit */\r
+ do\r
+ {\r
+ wutwfstatus = RTC->ISR & RTC_ISR_WUTWF;\r
+ wutcounter++; \r
+ } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));\r
+ \r
+ if ((RTC->ISR & RTC_ISR_WUTWF) == RESET)\r
+ {\r
+ status = ERROR;\r
+ }\r
+ else\r
+ {\r
+ status = SUCCESS;\r
+ } \r
+ }\r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group5 Daylight Saving configuration functions\r
+ * @brief Daylight Saving configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Daylight Saving configuration functions\r
+ =============================================================================== \r
+\r
+ This section provide functions allowing to configure the RTC DayLight Saving.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Adds or substract one hour from the current time.\r
+ * @param RTC_DayLightSaveOperation: the value of hour adjustment. \r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_DayLightSaving_SUB1H: Substract one hour (winter time)\r
+ * @arg RTC_DayLightSaving_ADD1H: Add one hour (summer time)\r
+ * @param RTC_StoreOperation: Specifies the value to be written in the BCK bit \r
+ * in CR register to store the operation.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_StoreOperation_Reset\r
+ * @arg RTC_StoreOperation_Set\r
+ * @retval None\r
+ */\r
+void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving));\r
+ assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation));\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Clear the bits to be configured */\r
+ RTC->CR &= (uint32_t)~(RTC_CR_BCK);\r
+\r
+ /* Configure the RTC_CR register */\r
+ RTC->CR |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation);\r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+}\r
+\r
+/**\r
+ * @brief Returns the RTC Day Light Saving stored operation.\r
+ * @param None\r
+ * @retval RTC Day Light Saving stored operation.\r
+ * - RTC_StoreOperation_Reset\r
+ * - RTC_StoreOperation_Set \r
+ */\r
+uint32_t RTC_GetStoreOperation(void)\r
+{\r
+ return (RTC->CR & RTC_CR_BCK);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group6 Output pin Configuration function\r
+ * @brief Output pin Configuration function \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Output pin Configuration function\r
+ =============================================================================== \r
+\r
+ This section provide functions allowing to configure the RTC Output source.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the RTC output source (AFO_ALARM).\r
+ * @param RTC_Output: Specifies which signal will be routed to the RTC output. \r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Output_Disable: No output selected\r
+ * @arg RTC_Output_AlarmA: signal of AlarmA mapped to output\r
+ * @arg RTC_Output_AlarmB: signal of AlarmB mapped to output\r
+ * @arg RTC_Output_WakeUp: signal of WakeUp mapped to output\r
+ * @param RTC_OutputPolarity: Specifies the polarity of the output signal. \r
+ * This parameter can be one of the following:\r
+ * @arg RTC_OutputPolarity_High: The output pin is high when the \r
+ * ALRAF/ALRBF/WUTF is high (depending on OSEL)\r
+ * @arg RTC_OutputPolarity_Low: The output pin is low when the \r
+ * ALRAF/ALRBF/WUTF is high (depending on OSEL)\r
+ * @retval None\r
+ */\r
+void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_OUTPUT(RTC_Output));\r
+ assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity));\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Clear the bits to be configured */\r
+ RTC->CR &= (uint32_t)~(RTC_CR_OSEL | RTC_CR_POL);\r
+\r
+ /* Configure the output selection and polarity */\r
+ RTC->CR |= (uint32_t)(RTC_Output | RTC_OutputPolarity);\r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group7 Digital Calibration configuration functions\r
+ * @brief Digital Calibration configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Digital Calibration configuration functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the digital calibration parameters.\r
+ * @param RTC_CalibSign: specifies the sign of the calibration value.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_CalibSign_Positive: The value sign is positive \r
+ * @arg RTC_CalibSign_Negative: The value sign is negative\r
+ * @param Value: value of calibration expressed in ppm (coded on 5 bits) \r
+ * - This value should be between 0 and 63 when using negative sign\r
+ * with a 2-ppm step.\r
+ * - This value should be between 0 and 126 when using positive sign\r
+ * with a 4-ppm step.\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC digital calibration are initialized\r
+ * - ERROR: RTC digital calibration are not initialized \r
+ */\r
+ErrorStatus RTC_DigitalCalibConfig(uint32_t RTC_CalibSign, uint32_t Value)\r
+{\r
+ ErrorStatus status = ERROR;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_CALIB_SIGN(RTC_CalibSign));\r
+ assert_param(IS_RTC_CALIB_VALUE(Value)); \r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Set Initialization mode */\r
+ if (RTC_EnterInitMode() == ERROR)\r
+ {\r
+ status = ERROR;\r
+ } \r
+ else\r
+ {\r
+ /* Set the calibration value */\r
+ RTC->CALIBR = (uint32_t)(RTC_CalibSign | Value);\r
+ /* Exit Initialization mode */\r
+ RTC_ExitInitMode();\r
+ \r
+ status = SUCCESS;\r
+ } \r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the digital calibration process.\r
+ * @param NewState: new state of the digital calibration.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC digital calibration are enabled/disabled\r
+ * - ERROR: RTC digital calibration are not enabled/disabled \r
+ */\r
+ErrorStatus RTC_DigitalCalibCmd(FunctionalState NewState)\r
+{\r
+ ErrorStatus status = ERROR;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+ \r
+ /* Set Initialization mode */\r
+ if (RTC_EnterInitMode() == ERROR)\r
+ {\r
+ status = ERROR;\r
+ }\r
+ else\r
+ {\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the Digital Calibration */\r
+ RTC->CR |= (uint32_t)RTC_CR_DCE;\r
+ }\r
+ else\r
+ { \r
+ /* Disable the Digital Calibration */\r
+ RTC->CR &= (uint32_t)~RTC_CR_DCE;\r
+ }\r
+ /* Exit Initialization mode */\r
+ RTC_ExitInitMode();\r
+ \r
+ status = SUCCESS;\r
+ } \r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the RTC clock to be output through the relative \r
+ * pin.\r
+ * @param NewState: new state of the digital calibration Output.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RTC_CalibOutputCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the RTC clock output */\r
+ RTC->CR |= (uint32_t)RTC_CR_COE;\r
+ }\r
+ else\r
+ { \r
+ /* Disable the RTC clock output */\r
+ RTC->CR &= (uint32_t)~RTC_CR_COE;\r
+ }\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup RTC_Group8 TimeStamp configuration functions\r
+ * @brief TimeStamp configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ TimeStamp configuration functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or Disables the RTC TimeStamp functionality with the \r
+ * specified time stamp pin stimulating edge.\r
+ * @param RTC_TimeStampEdge: Specifies the pin edge on which the TimeStamp is \r
+ * activated.\r
+ * This parameter can be one of the following:\r
+ * @arg RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising \r
+ * edge of the related pin.\r
+ * @arg RTC_TimeStampEdge_Falling: the Time stamp event occurs on the \r
+ * falling edge of the related pin.\r
+ * @param NewState: new state of the TimeStamp.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_TIMESTAMP_EDGE(RTC_TimeStampEdge));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ /* Get the RTC_CR register and clear the bits to be configured */\r
+ tmpreg = (uint32_t)(RTC->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));\r
+\r
+ /* Get the new configuration */\r
+ if (NewState != DISABLE)\r
+ {\r
+ tmpreg |= (uint32_t)(RTC_TimeStampEdge | RTC_CR_TSE);\r
+ }\r
+ else\r
+ {\r
+ tmpreg |= (uint32_t)(RTC_TimeStampEdge);\r
+ }\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Configure the Time Stamp TSEDGE and Enable bits */\r
+ RTC->CR = (uint32_t)tmpreg;\r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+}\r
+\r
+/**\r
+ * @brief Get the RTC TimeStamp value and masks.\r
+ * @param RTC_Format: specifies the format of the output parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Format_BIN: Binary data format \r
+ * @arg RTC_Format_BCD: BCD data format\r
+ * @param RTC_StampTimeStruct: pointer to a RTC_TimeTypeDef structure that will \r
+ * contains the TimeStamp time values. \r
+ * @param RTC_StampDateStruct: pointer to a RTC_DateTypeDef structure that will \r
+ * contains the TimeStamp date values. \r
+ * @retval None\r
+ */\r
+void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, \r
+ RTC_DateTypeDef* RTC_StampDateStruct)\r
+{\r
+ uint32_t tmptime = 0, tmpdate = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(RTC_Format));\r
+\r
+ /* Get the TimeStamp time and date registers values */\r
+ tmptime = (uint32_t)(RTC->TSTR & RTC_TR_RESERVED_MASK);\r
+ tmpdate = (uint32_t)(RTC->TSDR & RTC_DR_RESERVED_MASK);\r
+\r
+ /* Fill the Time structure fields with the read parameters */\r
+ RTC_StampTimeStruct->RTC_Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16);\r
+ RTC_StampTimeStruct->RTC_Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8);\r
+ RTC_StampTimeStruct->RTC_Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));\r
+ RTC_StampTimeStruct->RTC_H12 = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16); \r
+\r
+ /* Fill the Date structure fields with the read parameters */\r
+ RTC_StampDateStruct->RTC_Year = 0;\r
+ RTC_StampDateStruct->RTC_Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8);\r
+ RTC_StampDateStruct->RTC_Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));\r
+ RTC_StampDateStruct->RTC_WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);\r
+\r
+ /* Check the input parameters format */\r
+ if (RTC_Format == RTC_Format_BIN)\r
+ {\r
+ /* Convert the Time structure parameters to Binary format */\r
+ RTC_StampTimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Hours);\r
+ RTC_StampTimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Minutes);\r
+ RTC_StampTimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Seconds);\r
+\r
+ /* Convert the Date structure parameters to Binary format */\r
+ RTC_StampDateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Month);\r
+ RTC_StampDateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Date);\r
+ RTC_StampDateStruct->RTC_WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_WeekDay);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group9 Tampers configuration functions\r
+ * @brief Tampers configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Tampers configuration functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the select Tamper pin edge.\r
+ * @param RTC_Tamper: Selected tamper pin.\r
+ * This parameter can be RTC_Tamper_1.\r
+ * @param RTC_TamperTrigger: Specifies the trigger on the tamper pin that \r
+ * stimulates tamper event. \r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event.\r
+ * @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event. \r
+ * @retval None\r
+ */\r
+void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_TAMPER(RTC_Tamper)); \r
+ assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger));\r
+ \r
+ if (RTC_TamperTrigger == RTC_TamperTrigger_RisingEdge)\r
+ { \r
+ /* Configure the RTC_TAFCR register */\r
+ RTC->TAFCR &= (uint32_t)((uint32_t)~(RTC_Tamper << 1)); \r
+ }\r
+ else\r
+ { \r
+ /* Configure the RTC_TAFCR register */\r
+ RTC->TAFCR |= (uint32_t)(RTC_Tamper << 1); \r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Enables or Disables the Tamper detection.\r
+ * @param RTC_Tamper: Selected tamper pin.\r
+ * This parameter can be RTC_Tamper_1.\r
+ * @param NewState: new state of the tamper pin.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @retval None\r
+ */\r
+void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_TAMPER(RTC_Tamper)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected Tamper pin */\r
+ RTC->TAFCR |= (uint32_t)RTC_Tamper;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected Tamper pin */\r
+ RTC->TAFCR &= (uint32_t)~RTC_Tamper; \r
+ } \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group10 Backup Data Registers configuration functions\r
+ * @brief Backup Data Registers configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Backup Data Registers configuration functions \r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Writes a data in a specified RTC Backup data register.\r
+ * @param RTC_BKP_DR: RTC Backup data Register number.\r
+ * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to \r
+ * specify the register.\r
+ * @param Data: Data to be written in the specified RTC Backup data register. \r
+ * @retval None\r
+ */\r
+void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_BKP(RTC_BKP_DR));\r
+\r
+ tmp = RTC_BASE + 0x50;\r
+ tmp += (RTC_BKP_DR * 4);\r
+\r
+ /* Write the specified register */\r
+ *(__IO uint32_t *)tmp = (uint32_t)Data;\r
+}\r
+\r
+/**\r
+ * @brief Reads data from the specified RTC Backup data Register.\r
+ * @param RTC_BKP_DR: RTC Backup data Register number.\r
+ * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to \r
+ * specify the register. \r
+ * @retval None\r
+ */\r
+uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_BKP(RTC_BKP_DR));\r
+\r
+ tmp = RTC_BASE + 0x50;\r
+ tmp += (RTC_BKP_DR * 4);\r
+ \r
+ /* Read the specified register */\r
+ return (*(__IO uint32_t *)tmp);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group11 Output Type Config configuration functions\r
+ * @brief Output Type Config configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Output Type Config configuration functions \r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the RTC Output Pin mode. \r
+ * @param RTC_OutputType: specifies the RTC Output (PC13) pin mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in \r
+ * Open Drain mode.\r
+ * @arg RTC_OutputType_PushPull: RTC Output (PC13) is configured in \r
+ * Push Pull mode. \r
+ * @retval None\r
+ */\r
+void RTC_OutputTypeConfig(uint32_t RTC_OutputType)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType));\r
+ \r
+ RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_ALARMOUTTYPE);\r
+ RTC->TAFCR |= (uint32_t)(RTC_OutputType); \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group12 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Interrupts and flags management functions\r
+ =============================================================================== \r
+ All RTC interrupts are connected to the EXTI controller.\r
+ \r
+ - To enable the RTC Alarm interrupt, the following sequence is required:\r
+ - Configure and enable the EXTI Line 17 in interrupt mode and select the rising \r
+ edge sensitivity using the EXTI_Init() function.\r
+ - Configure and enable the RTC_Alarm IRQ channel in the NVIC using the NVIC_Init()\r
+ function.\r
+ - Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B) using\r
+ the RTC_SetAlarm() and RTC_AlarmCmd() functions.\r
+\r
+ - To enable the RTC Wakeup interrupt, the following sequence is required:\r
+ - Configure and enable the EXTI Line 20 in interrupt mode and select the rising \r
+ edge sensitivity using the EXTI_Init() function.\r
+ - Configure and enable the RTC_WKUP IRQ channel in the NVIC using the NVIC_Init()\r
+ function.\r
+ - Configure the RTC to generate the RTC wakeup timer event using the \r
+ RTC_WakeUpClockConfig(), RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.\r
+\r
+ - To enable the RTC Tamper interrupt, the following sequence is required:\r
+ - Configure and enable the EXTI Line 19 in interrupt mode and select the rising \r
+ edge sensitivity using the EXTI_Init() function.\r
+ - Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init()\r
+ function.\r
+ - Configure the RTC to detect the RTC tamper event using the \r
+ RTC_TamperTriggerConfig() and RTC_TamperCmd() functions.\r
+\r
+ - To enable the RTC TimeStamp interrupt, the following sequence is required:\r
+ - Configure and enable the EXTI Line 19 in interrupt mode and select the rising \r
+ edge sensitivity using the EXTI_Init() function.\r
+ - Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init()\r
+ function.\r
+ - Configure the RTC to detect the RTC time-stamp event using the \r
+ RTC_TimeStampCmd() functions.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified RTC interrupts.\r
+ * @param RTC_IT: specifies the RTC interrupt sources to be enabled or disabled. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg RTC_IT_TS: Time Stamp interrupt mask\r
+ * @arg RTC_IT_WUT: WakeUp Timer interrupt mask\r
+ * @arg RTC_IT_ALRB: Alarm B interrupt mask\r
+ * @arg RTC_IT_ALRA: Alarm A interrupt mask\r
+ * @arg RTC_IT_TAMP: Tamper event interrupt mask\r
+ * @param NewState: new state of the specified RTC interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_CONFIG_IT(RTC_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Configure the Interrupts in the RTC_CR register */\r
+ RTC->CR |= (uint32_t)(RTC_IT & ~RTC_TAFCR_TAMPIE);\r
+ /* Configure the Tamper Interrupt in the RTC_TAFCR */\r
+ RTC->TAFCR |= (uint32_t)(RTC_IT & RTC_TAFCR_TAMPIE);\r
+ }\r
+ else\r
+ {\r
+ /* Configure the Interrupts in the RTC_CR register */\r
+ RTC->CR &= (uint32_t)~(RTC_IT & (uint32_t)~RTC_TAFCR_TAMPIE);\r
+ /* Configure the Tamper Interrupt in the RTC_TAFCR */\r
+ RTC->TAFCR &= (uint32_t)~(RTC_IT & RTC_TAFCR_TAMPIE);\r
+ }\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified RTC flag is set or not.\r
+ * @param RTC_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag\r
+ * @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag\r
+ * @arg RTC_FLAG_TSF: Time Stamp event flag\r
+ * @arg RTC_FLAG_WUTF: WakeUp Timer flag\r
+ * @arg RTC_FLAG_ALRBF: Alarm B flag\r
+ * @arg RTC_FLAG_ALRAF: Alarm A flag\r
+ * @arg RTC_FLAG_INITF: Initialization mode flag\r
+ * @arg RTC_FLAG_RSF: Registers Synchronized flag\r
+ * @arg RTC_FLAG_INITS: Registers Configured flag\r
+ * @arg RTC_FLAG_WUTWF: WakeUp Timer Write flag\r
+ * @arg RTC_FLAG_ALRBWF: Alarm B Write flag\r
+ * @arg RTC_FLAG_ALRAWF: Alarm A write flag\r
+ * @retval The new state of RTC_FLAG (SET or RESET).\r
+ */\r
+FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_GET_FLAG(RTC_FLAG));\r
+ \r
+ /* Get all the flags */\r
+ tmpreg = (uint32_t)(RTC->ISR & RTC_FLAGS_MASK);\r
+ \r
+ /* Return the status of the flag */\r
+ if ((tmpreg & RTC_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the RTC's pending flags.\r
+ * @param RTC_FLAG: specifies the RTC flag to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag\r
+ * @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag \r
+ * @arg RTC_FLAG_TSF: Time Stamp event flag\r
+ * @arg RTC_FLAG_WUTF: WakeUp Timer flag\r
+ * @arg RTC_FLAG_ALRBF: Alarm B flag\r
+ * @arg RTC_FLAG_ALRAF: Alarm A flag\r
+ * @arg RTC_FLAG_RSF: Registers Synchronized flag\r
+ * @retval None\r
+ */\r
+void RTC_ClearFlag(uint32_t RTC_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));\r
+\r
+ /* Clear the Flags in the RTC_ISR register */\r
+ RTC->ISR = (uint32_t)((uint32_t)(~((RTC_FLAG | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); \r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified RTC interrupt has occurred or not.\r
+ * @param RTC_IT: specifies the RTC interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_IT_TS: Time Stamp interrupt \r
+ * @arg RTC_IT_WUT: WakeUp Timer interrupt \r
+ * @arg RTC_IT_ALRB: Alarm B interrupt \r
+ * @arg RTC_IT_ALRA: Alarm A interrupt \r
+ * @arg RTC_IT_TAMP1: Tamper 1 event interrupt \r
+ * @retval The new state of RTC_IT (SET or RESET).\r
+ */\r
+ITStatus RTC_GetITStatus(uint32_t RTC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t tmpreg = 0, enablestatus = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_GET_IT(RTC_IT));\r
+ \r
+ /* Get the TAMPER Interrupt enable bit and pending bit */\r
+ tmpreg = (uint32_t)(RTC->TAFCR & (RTC_TAFCR_TAMPIE));\r
+ \r
+ /* Get the Interrupt enable Status */\r
+ enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & (RTC_IT >> 15)));\r
+ \r
+ /* Get the Interrupt pending bit */\r
+ tmpreg = (uint32_t)((RTC->ISR & (uint32_t)(RTC_IT >> 4)));\r
+ \r
+ /* Get the status of the Interrupt */\r
+ if ((enablestatus != (uint32_t)RESET) && ((tmpreg & 0x0000FFFF) != (uint32_t)RESET))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the RTC's interrupt pending bits.\r
+ * @param RTC_IT: specifies the RTC interrupt pending bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RTC_IT_TS: Time Stamp interrupt \r
+ * @arg RTC_IT_WUT: WakeUp Timer interrupt \r
+ * @arg RTC_IT_ALRB: Alarm B interrupt \r
+ * @arg RTC_IT_ALRA: Alarm A interrupt \r
+ * @arg RTC_IT_TAMP1: Tamper 1 event interrupt \r
+ * @retval None\r
+ */\r
+void RTC_ClearITPendingBit(uint32_t RTC_IT)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_CLEAR_IT(RTC_IT));\r
+\r
+ /* Get the RTC_ISR Interrupt pending bits mask */\r
+ tmpreg = (uint32_t)(RTC_IT >> 4);\r
+\r
+ /* Clear the interrupt pending bits in the RTC_ISR register */\r
+ RTC->ISR = (uint32_t)((uint32_t)(~((tmpreg | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief Converts a 2 digit decimal to BCD format.\r
+ * @param Value: Byte to be converted.\r
+ * @retval Converted byte\r
+ */\r
+static uint8_t RTC_ByteToBcd2(uint8_t Value)\r
+{\r
+ uint8_t bcdhigh = 0;\r
+ \r
+ while (Value >= 10)\r
+ {\r
+ bcdhigh++;\r
+ Value -= 10;\r
+ }\r
+ \r
+ return ((uint8_t)(bcdhigh << 4) | Value);\r
+}\r
+\r
+/**\r
+ * @brief Convert from 2 digit BCD to Binary.\r
+ * @param Value: BCD value to be converted.\r
+ * @retval Converted word\r
+ */\r
+static uint8_t RTC_Bcd2ToByte(uint8_t Value)\r
+{\r
+ uint8_t tmp = 0;\r
+ tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;\r
+ return (tmp + (Value & (uint8_t)0x0F));\r
+}\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_spi.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Serial peripheral interface (SPI): \r
+ * - Initialization and Configuration\r
+ * - Data transfers functions\r
+ * - Hardware CRC Calculation\r
+ * - DMA transfers management\r
+ * - Interrupts and flags management \r
+ * \r
+ * @verbatim\r
+ * \r
+ * The I2S feature is not implemented in STM32L1xx Ultra Low Power\r
+ * Medium-density devices and will be supported in future products.\r
+ * \r
+ * ===================================================================\r
+ * How to use this driver\r
+ * ===================================================================\r
+ * 1. Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE)\r
+ * function for SPI1 or using RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE)\r
+ * function for SPI2.\r
+ *\r
+ * 2. Enable SCK, MOSI, MISO and NSS GPIO clocks using RCC_AHBPeriphClockCmd()\r
+ * function. \r
+ *\r
+ * 3. Peripherals alternate function: \r
+ * - Connect the pin to the desired peripherals' Alternate \r
+ * Function (AF) using GPIO_PinAFConfig() function\r
+ * - Configure the desired pin in alternate function by:\r
+ * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF\r
+ * - Select the type, pull-up/pull-down and output speed via \r
+ * GPIO_PuPd, GPIO_OType and GPIO_Speed members\r
+ * - Call GPIO_Init() function\r
+ * \r
+ * 4. Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave \r
+ * Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()\r
+ * function.\r
+ *\r
+ * 5. Enable the NVIC and the corresponding interrupt using the function \r
+ * SPI_ITConfig() if you need to use interrupt mode. \r
+ *\r
+ * 6. When using the DMA mode \r
+ * - Configure the DMA using DMA_Init() function\r
+ * - Active the needed channel Request using SPI_I2S_DMACmd() function\r
+ * \r
+ * 7. Enable the SPI using the SPI_Cmd() function.\r
+ * \r
+ * 8. Enable the DMA using the DMA_Cmd() function when using DMA mode. \r
+ *\r
+ * 9. Optionally you can enable/configure the following parameters without\r
+ * re-initialization (i.e there is no need to call again SPI_Init() function):\r
+ * - When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx)\r
+ * is programmed as Data direction parameter using the SPI_Init() function\r
+ * it can be possible to switch between SPI_Direction_Tx or SPI_Direction_Rx\r
+ * using the SPI_BiDirectionalLineConfig() function.\r
+ * - When SPI_NSS_Soft is selected as Slave Select Management parameter \r
+ * using the SPI_Init() function it can be possible to manage the \r
+ * NSS internal signal using the SPI_NSSInternalSoftwareConfig() function.\r
+ * - Reconfigure the data size using the SPI_DataSizeConfig() function \r
+ * - Enable or disable the SS output using the SPI_SSOutputCmd() function \r
+ * \r
+ * 10. To use the CRC Hardware calculation feature refer to the Peripheral \r
+ * CRC hardware Calculation subsection.\r
+ *\r
+ * @endverbatim \r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_spi.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SPI \r
+ * @brief SPI driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* SPI registers Masks */\r
+#define CR1_CLEAR_MASK ((uint16_t)0x3040)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup SPI_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SPI_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Initialization and Configuration functions\r
+ =============================================================================== \r
+\r
+ This section provides a set of functions allowing to initialize the SPI Direction,\r
+ SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS Management, SPI Baud\r
+ Rate Prescaler, SPI First Bit and SPI CRC Polynomial.\r
+ \r
+ The SPI_Init() function follows the SPI configuration procedures for Master mode\r
+ and Slave mode (details for these procedures are available in reference manual\r
+ (RM0038)).\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the SPIx peripheral registers to their default\r
+ * reset values.\r
+ * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+ * @retval None\r
+ */\r
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+\r
+ if (SPIx == SPI1)\r
+ {\r
+ /* Enable SPI1 reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);\r
+ /* Release SPI1 from reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);\r
+ }\r
+ else\r
+ {\r
+ if (SPIx == SPI2)\r
+ {\r
+ /* Enable SPI2 reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);\r
+ /* Release SPI2 from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the SPIx peripheral according to the specified \r
+ * parameters in the SPI_InitStruct.\r
+ * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+ * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that\r
+ * contains the configuration information for the specified SPI peripheral.\r
+ * @retval None\r
+ */\r
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)\r
+{\r
+ uint16_t tmpreg = 0;\r
+ \r
+ /* check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ \r
+ /* Check the SPI parameters */\r
+ assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));\r
+ assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));\r
+ assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));\r
+ assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));\r
+ assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));\r
+ assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));\r
+ assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));\r
+ assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));\r
+ assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));\r
+\r
+/*---------------------------- SPIx CR1 Configuration ------------------------*/\r
+ /* Get the SPIx CR1 value */\r
+ tmpreg = SPIx->CR1;\r
+ /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */\r
+ tmpreg &= CR1_CLEAR_MASK;\r
+ /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler\r
+ master/salve mode, CPOL and CPHA */\r
+ /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */\r
+ /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */\r
+ /* Set LSBFirst bit according to SPI_FirstBit value */\r
+ /* Set BR bits according to SPI_BaudRatePrescaler value */\r
+ /* Set CPOL bit according to SPI_CPOL value */\r
+ /* Set CPHA bit according to SPI_CPHA value */\r
+ tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |\r
+ SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | \r
+ SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | \r
+ SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);\r
+ /* Write to SPIx CR1 */\r
+ SPIx->CR1 = tmpreg;\r
+ \r
+/*---------------------------- SPIx CRCPOLY Configuration --------------------*/\r
+ /* Write to SPIx CRCPOLY */\r
+ SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;\r
+}\r
+\r
+/**\r
+ * @brief Fills each SPI_InitStruct member with its default value.\r
+ * @param SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)\r
+{\r
+/*--------------- Reset SPI init structure parameters values -----------------*/\r
+ /* Initialize the SPI_Direction member */\r
+ SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;\r
+ /* initialize the SPI_Mode member */\r
+ SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;\r
+ /* initialize the SPI_DataSize member */\r
+ SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;\r
+ /* Initialize the SPI_CPOL member */\r
+ SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;\r
+ /* Initialize the SPI_CPHA member */\r
+ SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;\r
+ /* Initialize the SPI_NSS member */\r
+ SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;\r
+ /* Initialize the SPI_BaudRatePrescaler member */\r
+ SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;\r
+ /* Initialize the SPI_FirstBit member */\r
+ SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;\r
+ /* Initialize the SPI_CRCPolynomial member */\r
+ SPI_InitStruct->SPI_CRCPolynomial = 7;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified SPI peripheral.\r
+ * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+ * @param NewState: new state of the SPIx peripheral. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI peripheral */\r
+ SPIx->CR1 |= SPI_CR1_SPE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI peripheral */\r
+ SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the data size for the selected SPI.\r
+ * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+ * @param SPI_DataSize: specifies the SPI data size.\r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_DataSize_16b: Set data frame format to 16bit\r
+ * @arg SPI_DataSize_8b: Set data frame format to 8bit\r
+ * @retval None\r
+ */\r
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_DATASIZE(SPI_DataSize));\r
+ /* Clear DFF bit */\r
+ SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b;\r
+ /* Set new DFF bit value */\r
+ SPIx->CR1 |= SPI_DataSize;\r
+}\r
+\r
+/**\r
+ * @brief Selects the data transfer direction in bidirectional mode for the specified SPI.\r
+ * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+ * @param SPI_Direction: specifies the data transfer direction in bidirectional mode. \r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_Direction_Tx: Selects Tx transmission direction\r
+ * @arg SPI_Direction_Rx: Selects Rx receive direction\r
+ * @retval None\r
+ */\r
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_DIRECTION(SPI_Direction));\r
+ if (SPI_Direction == SPI_Direction_Tx)\r
+ {\r
+ /* Set the Tx only mode */\r
+ SPIx->CR1 |= SPI_Direction_Tx;\r
+ }\r
+ else\r
+ {\r
+ /* Set the Rx only mode */\r
+ SPIx->CR1 &= SPI_Direction_Rx;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures internally by software the NSS pin for the selected SPI.\r
+ * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+ * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state.\r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally\r
+ * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally\r
+ * @retval None\r
+ */\r
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));\r
+ if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)\r
+ {\r
+ /* Set NSS pin internally by software */\r
+ SPIx->CR1 |= SPI_NSSInternalSoft_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Reset NSS pin internally by software */\r
+ SPIx->CR1 &= SPI_NSSInternalSoft_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the SS output for the selected SPI.\r
+ * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+ * @param NewState: new state of the SPIx SS output. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI SS output */\r
+ SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI SS output */\r
+ SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Group2 Data transfers functions\r
+ * @brief Data transfers functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Data transfers functions\r
+ =============================================================================== \r
+\r
+ This section provides a set of functions allowing to manage the SPI data transfers\r
+ \r
+ In reception, data are received and then stored into an internal Rx buffer while \r
+ In transmission, data are first stored into an internal Tx buffer before being \r
+ transmitted.\r
+\r
+ The read access of the SPI_DR register can be done using the SPI_I2S_ReceiveData()\r
+ function and returns the Rx buffered value. Whereas a write access to the SPI_DR \r
+ can be done using SPI_I2S_SendData() function and stores the written data into \r
+ Tx buffer.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Returns the most recent received data by the SPIx peripheral. \r
+ * @param SPIx: where x can be 1 or 2 in SPI mode.\r
+ * @retval The value of the received data.\r
+ */\r
+uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ \r
+ /* Return the data in the DR register */\r
+ return SPIx->DR;\r
+}\r
+\r
+/**\r
+ * @brief Transmits a Data through the SPIx peripheral.\r
+ * @param SPIx: where x can be 1 or 2 in SPI mode. \r
+ * @param Data: Data to be transmitted.\r
+ * @retval None\r
+ */\r
+void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ \r
+ /* Write in the DR register the data to be sent */\r
+ SPIx->DR = Data;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Group3 Hardware CRC Calculation functions\r
+ * @brief Hardware CRC Calculation functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Hardware CRC Calculation functions\r
+ =============================================================================== \r
+\r
+ This section provides a set of functions allowing to manage the SPI CRC hardware \r
+ calculation\r
+\r
+ SPI communication using CRC is possible through the following procedure:\r
+ 1. Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler, \r
+ Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()\r
+ function.\r
+ 2. Enable the CRC calculation using the SPI_CalculateCRC() function.\r
+ 3. Enable the SPI using the SPI_Cmd() function\r
+ 4. Before writing the last data to the TX buffer, set the CRCNext bit using the \r
+ SPI_TransmitCRC() function to indicate that after transmission of the last \r
+ data, the CRC should be transmitted.\r
+ 5. After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT\r
+ bit is reset. The CRC is also received and compared against the SPI_RXCRCR \r
+ value. \r
+ If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt\r
+ can be generated when the SPI_I2S_IT_ERR interrupt is enabled.\r
+\r
+Note: \r
+-----\r
+ - It is advised to don't read the calculate CRC values during the communication.\r
+\r
+ - When the SPI is in slave mode, be careful to enable CRC calculation only \r
+ when the clock is stable, that is, when the clock is in the steady state. \r
+ If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive \r
+ to the SCK slave input clock as soon as CRCEN is set, and this, whatever \r
+ the value of the SPE bit.\r
+\r
+ - With high bitrate frequencies, be careful when transmitting the CRC.\r
+ As the number of used CPU cycles has to be as low as possible in the CRC \r
+ transfer phase, it is forbidden to call software functions in the CRC \r
+ transmission sequence to avoid errors in the last data and CRC reception. \r
+ In fact, CRCNEXT bit has to be written before the end of the transmission/reception \r
+ of the last data.\r
+\r
+ - For high bit rate frequencies, it is advised to use the DMA mode to avoid the\r
+ degradation of the SPI speed performance due to CPU accesses impacting the \r
+ SPI bandwidth.\r
+\r
+ - When the STM32L15xxx are configured as slaves and the NSS hardware mode is \r
+ used, the NSS pin needs to be kept low between the data phase and the CRC \r
+ phase.\r
+\r
+ - When the SPI is configured in slave mode with the CRC feature enabled, CRC\r
+ calculation takes place even if a high level is applied on the NSS pin. \r
+ This may happen for example in case of a multislave environment where the \r
+ communication master addresses slaves alternately.\r
+\r
+ - Between a slave deselection (high level on NSS) and a new slave selection \r
+ (low level on NSS), the CRC value should be cleared on both master and slave\r
+ sides in order to resynchronize the master and slave for their respective \r
+ CRC calculation.\r
+\r
+ To clear the CRC, follow the procedure below:\r
+ 1. Disable SPI using the SPI_Cmd() function\r
+ 2. Disable the CRC calculation using the SPI_CalculateCRC() function.\r
+ 3. Enable the CRC calculation using the SPI_CalculateCRC() function.\r
+ 4. Enable SPI using the SPI_Cmd() function.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the CRC value calculation of the transferred bytes.\r
+ * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+ * @param NewState: new state of the SPIx CRC value calculation.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI CRC calculation */\r
+ SPIx->CR1 |= SPI_CR1_CRCEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI CRC calculation */\r
+ SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Transmit the SPIx CRC value.\r
+ * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+ * @retval None\r
+ */\r
+void SPI_TransmitCRC(SPI_TypeDef* SPIx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ \r
+ /* Enable the selected SPI CRC transmission */\r
+ SPIx->CR1 |= SPI_CR1_CRCNEXT;\r
+}\r
+\r
+/**\r
+ * @brief Returns the transmit or the receive CRC register value for the specified SPI.\r
+ * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+ * @param SPI_CRC: specifies the CRC register to be read.\r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_CRC_Tx: Selects Tx CRC register\r
+ * @arg SPI_CRC_Rx: Selects Rx CRC register\r
+ * @retval The selected CRC register value..\r
+ */\r
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)\r
+{\r
+ uint16_t crcreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_CRC(SPI_CRC));\r
+ if (SPI_CRC != SPI_CRC_Rx)\r
+ {\r
+ /* Get the Tx CRC register */\r
+ crcreg = SPIx->TXCRCR;\r
+ }\r
+ else\r
+ {\r
+ /* Get the Rx CRC register */\r
+ crcreg = SPIx->RXCRCR;\r
+ }\r
+ /* Return the selected CRC register */\r
+ return crcreg;\r
+}\r
+\r
+/**\r
+ * @brief Returns the CRC Polynomial register value for the specified SPI.\r
+ * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+ * @retval The CRC Polynomial register value.\r
+ */\r
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ \r
+ /* Return the CRC polynomial register */\r
+ return SPIx->CRCPR;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Group4 DMA transfers management functions\r
+ * @brief DMA transfers management functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ DMA transfers management functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the SPIx DMA interface.\r
+ * @param SPIx: where x can be 1 or 2 in SPI mode \r
+ * @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request\r
+ * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request\r
+ * @param NewState: new state of the selected SPI DMA transfer request.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI DMA requests */\r
+ SPIx->CR2 |= SPI_I2S_DMAReq;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI DMA requests */\r
+ SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Group5 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Interrupts and flags management functions\r
+ =============================================================================== \r
+\r
+ This section provides a set of functions allowing to configure the SPI Interrupts \r
+ sources and check or clear the flags or pending bits status.\r
+ The user should identify which mode will be used in his application to manage \r
+ the communication: Polling mode, Interrupt mode or DMA mode. \r
+ \r
+ Polling Mode\r
+ =============\r
+ In Polling Mode, the SPI communication can be managed by 6 flags:\r
+ 1. SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register\r
+ 2. SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register\r
+ 3. SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI.\r
+ 4. SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur \r
+ 5. SPI_FLAG_MODF : to indicate if a Mode Fault error occur\r
+ 6. SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur\r
+\r
+Note: Do not use the BSY flag to handle each data transmission or reception.\r
+----- It is better to use the TXE and RXNE flags instead.\r
+\r
+ In this Mode it is advised to use the following functions:\r
+ - FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);\r
+ - void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);\r
+\r
+ Interrupt Mode\r
+ ===============\r
+ In Interrupt Mode, the SPI communication can be managed by 3 interrupt sources\r
+ and 5 pending bits: \r
+ Pending Bits:\r
+ ------------- \r
+ 1. SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register\r
+ 2. SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register\r
+ 3. SPI_IT_CRCERR : to indicate if a CRC Calculation error occur \r
+ 4. SPI_IT_MODF : to indicate if a Mode Fault error occur\r
+ 5. SPI_I2S_IT_OVR : to indicate if an Overrun error occur\r
+\r
+ Interrupt Source:\r
+ -----------------\r
+ 1. SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty \r
+ interrupt. \r
+ 2. SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not \r
+ empty interrupt.\r
+ 3. SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt.\r
+\r
+ In this Mode it is advised to use the following functions:\r
+ - void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);\r
+ - ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);\r
+ - void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);\r
+\r
+ DMA Mode\r
+ ========\r
+ In DMA Mode, the SPI communication can be managed by 2 DMA Channel requests:\r
+ 1. SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request\r
+ 2. SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request\r
+\r
+ In this Mode it is advised to use the following function:\r
+ - void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified SPI interrupts.\r
+ * @param SPIx: where x can be 1 or 2 in SPI mode \r
+ * @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled. \r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask\r
+ * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask\r
+ * @arg SPI_I2S_IT_ERR: Error interrupt mask\r
+ * @param NewState: new state of the specified SPI interrupt.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)\r
+{\r
+ uint16_t itpos = 0, itmask = 0 ;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));\r
+\r
+ /* Get the SPI IT index */\r
+ itpos = SPI_I2S_IT >> 4;\r
+\r
+ /* Set the IT mask */\r
+ itmask = (uint16_t)1 << (uint16_t)itpos;\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI interrupt */\r
+ SPIx->CR2 |= itmask;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI interrupt */\r
+ SPIx->CR2 &= (uint16_t)~itmask;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified SPI flag is set or not.\r
+ * @param SPIx: where x can be 1 or 2 in SPI mode \r
+ * @param SPI_I2S_FLAG: specifies the SPI flag to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.\r
+ * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.\r
+ * @arg SPI_I2S_FLAG_BSY: Busy flag.\r
+ * @arg SPI_I2S_FLAG_OVR: Overrun flag.\r
+ * @arg SPI_I2S_FLAG_MODF: Mode Fault flag.\r
+ * @arg SPI_I2S_FLAG_CRCERR: CRC Error flag.\r
+ * @retval The new state of SPI_I2S_FLAG (SET or RESET).\r
+ */\r
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));\r
+ \r
+ /* Check the status of the specified SPI flag */\r
+ if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)\r
+ {\r
+ /* SPI_I2S_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* SPI_I2S_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the SPI_I2S_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the SPIx CRC Error (CRCERR) flag.\r
+ * @param SPIx: where x can be 1 or 2 in SPI mode \r
+ * @param SPI_I2S_FLAG: specifies the SPI flag to clear. \r
+ * This function clears only CRCERR flag.\r
+ * @note\r
+ * - OVR (OverRun error) flag is cleared by software sequence: a read \r
+ * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read \r
+ * operation to SPI_SR register (SPI_I2S_GetFlagStatus()).\r
+ * - MODF (Mode Fault) flag is cleared by software sequence: a read/write \r
+ * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a \r
+ * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).\r
+ * @retval None\r
+ */\r
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));\r
+ \r
+ /* Clear the selected SPI CRC Error (CRCERR) flag */\r
+ SPIx->SR = (uint16_t)~SPI_I2S_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified SPI interrupt has occurred or not.\r
+ * @param SPIx: where x can be\r
+ * - 1 or 2 in SPI mode \r
+ * @param SPI_I2S_IT: specifies the SPI interrupt source to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.\r
+ * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.\r
+ * @arg SPI_I2S_IT_OVR: Overrun interrupt.\r
+ * @arg SPI_I2S_IT_MODF: Mode Fault interrupt.\r
+ * @arg SPI_I2S_IT_CRCERR: CRC Error interrupt.\r
+ * @retval The new state of SPI_I2S_IT (SET or RESET).\r
+ */\r
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint16_t itpos = 0, itmask = 0, enablestatus = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));\r
+\r
+ /* Get the SPI_I2S_IT index */\r
+ itpos = 0x01 << (SPI_I2S_IT & 0x0F);\r
+\r
+ /* Get the SPI_I2S_IT IT mask */\r
+ itmask = SPI_I2S_IT >> 4;\r
+\r
+ /* Set the IT mask */\r
+ itmask = 0x01 << itmask;\r
+\r
+ /* Get the SPI_I2S_IT enable bit status */\r
+ enablestatus = (SPIx->CR2 & itmask) ;\r
+\r
+ /* Check the status of the specified SPI interrupt */\r
+ if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)\r
+ {\r
+ /* SPI_I2S_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* SPI_I2S_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the SPI_I2S_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit.\r
+ * @param SPIx: where x can be\r
+ * - 1 or 2 in SPI mode \r
+ * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.\r
+ * This function clears only CRCERR interrupt pending bit. \r
+ * @note\r
+ * - OVR (OverRun Error) interrupt pending bit is cleared by software \r
+ * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) \r
+ * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).\r
+ * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:\r
+ * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) \r
+ * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable \r
+ * the SPI).\r
+ * @retval None\r
+ */\r
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)\r
+{\r
+ uint16_t itpos = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));\r
+\r
+ /* Get the SPI_I2S IT index */\r
+ itpos = 0x01 << (SPI_I2S_IT & 0x0F);\r
+\r
+ /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */\r
+ SPIx->SR = (uint16_t)~itpos;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_syscfg.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the SYSCFG and RI peripherals: \r
+ * - SYSCFG Initialization and Configuration\r
+ * - RI Initialization and Configuration\r
+ *\r
+ * @verbatim\r
+ * \r
+ * ===================================================================\r
+ * How to use this driver\r
+ * ===================================================================\r
+ * \r
+ * This driver provides functions for:\r
+ * \r
+ * 1. Remapping the memory accessible in the code area using\r
+ * SYSCFG_MemoryRemapConfig() \r
+ * 2. Manage the EXTI lines connection to the GPIOs using\r
+ * SYSCFG_EXTILineConfig().\r
+ * 3. Routing of I/Os toward the input captures of timers (TIM2, TIM3 and TIM4).\r
+ * 4. Input routing of COMP1 and COMP2\r
+ * 5. Routing of internal reference voltage VREFINT to PB0 and PB1.\r
+ *\r
+ * 6. The RI registers can be accessed only when the comparator \r
+ * APB interface clock is enabled.\r
+ * To enable comparator clock use:\r
+ * RCC_APB1PeriphClockCmd(RCC_APB1Periph_COMP, ENABLE);\r
+ *\r
+ * Following functions uses RI registers:\r
+ * - SYSCFG_RIDeInit()\r
+ * - SYSCFG_RITIMSelect()\r
+ * - SYSCFG_RITIMInputCaptureConfig()\r
+ * - SYSCFG_RIResistorConfig()\r
+ * - SYSCFG_RIIOSwitchConfig()\r
+ * - SYSCFG_RISwitchControlModeCmd()\r
+ * - SYSCFG_RIHysteresisConfig()\r
+ *\r
+ * 7- The SYSCFG registers can be accessed only when the SYSCFG \r
+ * interface APB clock is enabled.\r
+ * To enable SYSCFG APB clock use:\r
+ * RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);\r
+ *\r
+ * Following functions uses SYSCFG registers:\r
+ * - SYSCFG_MemoryRemapConfig()\r
+ * - SYSCFG_USBPuCmd()\r
+ * - SYSCFG_EXTILineConfig()\r
+ * \r
+ * @endverbatim\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_syscfg.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SYSCFG \r
+ * @brief SYSCFG driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#define TIM_SELECT_MASK ((uint32_t)0xFFFCFFFF) /*!< TIM select mask */\r
+#define IC_ROUTING_MASK ((uint32_t)0x0000000F) /*!< Input Capture routing mask */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup SYSCFG_Private_Functions\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup SYSCFG_Group1 SYSCFG Initialization and Configuration functions\r
+ * @brief SYSCFG Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ SYSCFG Initialization and Configuration functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the SYSCFG registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ * @ Note: MEMRMP bits are not reset by APB2 reset.\r
+ */\r
+void SYSCFG_DeInit(void)\r
+{\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Deinitializes the RI registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SYSCFG_RIDeInit(void)\r
+{\r
+ RI->ICR = ((uint32_t)0x00000000); /*!< Set RI->ICR to reset value */\r
+ RI->ASCR1 = ((uint32_t)0x00000000); /*!< Set RI->ASCR1 to reset value */ \r
+ RI->ASCR2 = ((uint32_t)0x00000000); /*!< Set RI->ASCR2 to reset value */ \r
+ RI->HYSCR1 = ((uint32_t)0x00000000); /*!< Set RI->HYSCR1 to reset value */\r
+ RI->HYSCR2 = ((uint32_t)0x00000000); /*!< Set RI->HYSCR2 to reset value */\r
+ RI->HYSCR3 = ((uint32_t)0x00000000); /*!< Set RI->HYSCR3 to reset value */\r
+}\r
+\r
+/**\r
+ * @brief Changes the mapping of the specified memory.\r
+ * @param SYSCFG_Memory: selects the memory remapping.\r
+ * This parameter can be one of the following values:\r
+ * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000 \r
+ * @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000\r
+ * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000 \r
+ * @retval None\r
+ */\r
+void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SYSCFG_MEMORY_REMAP_CONFING(SYSCFG_MemoryRemap));\r
+ SYSCFG->MEMRMP = SYSCFG_MemoryRemap;\r
+}\r
+\r
+/**\r
+ * @brief Control the internal pull-up on USB DP line.\r
+ * @param NewState: New state of the internal pull-up on USB DP line. \r
+ * This parameter can be ENABLE: Connect internal pull-up on USB DP line.\r
+ * or DISABLE: Disconnect internal pull-up on USB DP line.\r
+ * @retval None\r
+ */\r
+void SYSCFG_USBPuCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ { \r
+ /* Connect internal pull-up on USB DP line */\r
+ SYSCFG->PMC |= (uint32_t) SYSCFG_PMC_USB_PU;\r
+ }\r
+ else\r
+ {\r
+ /* Disconnect internal pull-up on USB DP line */\r
+ SYSCFG->PMC &= (uint32_t)(~SYSCFG_PMC_USB_PU);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the GPIO pin used as EXTI Line.\r
+ * @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source \r
+ * for EXTI lines where x can be (A, B, C, D, E or H).\r
+ * @param EXTI_PinSourcex: specifies the EXTI line to be configured.\r
+ * This parameter can be EXTI_PinSourcex where x can be (0..15)\r
+ * @retval None\r
+ */\r
+void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)\r
+{\r
+ uint32_t tmp = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));\r
+ assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));\r
+ \r
+ tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));\r
+ SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;\r
+ SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SYSCFG_Group2 RI Initialization and Configuration functions\r
+ * @brief RI Initialization and Configuration functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ RI Initialization and Configuration functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the routing interface to select which Timer to be routed.\r
+ * @note Routing capability can be applied only on one of the three timers\r
+ * (TIM2, TIM3 or TIM4) at a time.\r
+ * @param TIM_Select: Timer select.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_Select_None: No timer selected and default Timer mapping is enabled.\r
+ * @arg TIM_Select_TIM2: Timer 2 Input Captures to be routed.\r
+ * @arg TIM_Select_TIM3: Timer 3 Input Captures to be routed.\r
+ * @arg TIM_Select_TIM4: Timer 4 Input Captures to be routed.\r
+ * @retval None.\r
+ */\r
+void SYSCFG_RITIMSelect(uint32_t TIM_Select)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RI_TIM(TIM_Select));\r
+\r
+ /* Get the old register value */\r
+ tmpreg = RI->ICR;\r
+\r
+ /* Clear the TIMx select bits */\r
+ tmpreg &= TIM_SELECT_MASK;\r
+\r
+ /* Select the Timer */\r
+ tmpreg |= (TIM_Select);\r
+\r
+ /* Write to RI->ICR register */\r
+ RI->ICR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Configures the routing interface to map Input Capture 1, 2, 3 or 4\r
+ * to a selected I/O pin.\r
+ * @param RI_InputCapture selects which input capture to be routed.\r
+ * This parameter can be one (or combination) of the following parameters:\r
+ * @arg RI_InputCapture_IC1: Input capture 1 is selected.\r
+ * @arg RI_InputCapture_IC2: Input capture 2 is selected.\r
+ * @arg RI_InputCapture_IC3: Input capture 3 is selected.\r
+ * @arg RI_InputCapture_IC4: Input capture 4 is selected.\r
+ * @param RI_InputCaptureRouting: selects which pin to be routed to Input Capture.\r
+ * This parameter can be one of the following values:\r
+ * @arg RI_InputCaptureRouting_0 to RI_InputCaptureRouting_15\r
+ * e.g.\r
+ * SYSCFG_RITIMSelect(TIM_Select_TIM2)\r
+ * SYSCFG_RITIMInputCaptureConfig(RI_InputCapture_IC1, RI_InputCaptureRouting_1)\r
+ * allows routing of Input capture IC1 of TIM2 to PA4.\r
+ * For details about correspondence between RI_InputCaptureRouting_x \r
+ * and I/O pins refer to the parameters' description in the header file\r
+ * or refer to the product reference manual.\r
+ * @note Input capture selection bits are not reset by this function.\r
+ * To reset input capture selection bits, use SYSCFG_RIDeInit() function.\r
+ * @note The I/O should be configured in alternate function mode (AF14) using\r
+ * GPIO_PinAFConfig() function.\r
+ * @retval None.\r
+ */\r
+void SYSCFG_RITIMInputCaptureConfig(uint32_t RI_InputCapture, uint32_t RI_InputCaptureRouting)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RI_INPUTCAPTURE(RI_InputCapture));\r
+ assert_param(IS_RI_INPUTCAPTURE_ROUTING(RI_InputCaptureRouting));\r
+\r
+ /* Get the old register value */\r
+ tmpreg = RI->ICR;\r
+\r
+ /* Select input captures to be routed */\r
+ tmpreg |= (RI_InputCapture);\r
+\r
+ if((RI_InputCapture & RI_InputCapture_IC1) == RI_InputCapture_IC1)\r
+ {\r
+ /* Clear the input capture select bits */\r
+ tmpreg &= (uint32_t)(~IC_ROUTING_MASK);\r
+\r
+ /* Set RI_InputCaptureRouting bits */\r
+ tmpreg |= (uint32_t)( RI_InputCaptureRouting);\r
+ }\r
+\r
+ if((RI_InputCapture & RI_InputCapture_IC2) == RI_InputCapture_IC2)\r
+ {\r
+ /* Clear the input capture select bits */\r
+ tmpreg &= (uint32_t)(~(IC_ROUTING_MASK << 4));\r
+\r
+ /* Set RI_InputCaptureRouting bits */\r
+ tmpreg |= (uint32_t)( (RI_InputCaptureRouting << 4)); \r
+ }\r
+\r
+ if((RI_InputCapture & RI_InputCapture_IC3) == RI_InputCapture_IC3)\r
+ {\r
+ /* Clear the input capture select bits */\r
+ tmpreg &= (uint32_t)(~(IC_ROUTING_MASK << 8));\r
+\r
+ /* Set RI_InputCaptureRouting bits */\r
+ tmpreg |= (uint32_t)( (RI_InputCaptureRouting << 8)); \r
+ }\r
+\r
+ if((RI_InputCapture & RI_InputCapture_IC4) == RI_InputCapture_IC4)\r
+ {\r
+ /* Clear the input capture select bits */\r
+ tmpreg &= (uint32_t)(~(IC_ROUTING_MASK << 12));\r
+\r
+ /* Set RI_InputCaptureRouting bits */\r
+ tmpreg |= (uint32_t)( (RI_InputCaptureRouting << 12)); \r
+ }\r
+\r
+ /* Write to RI->ICR register */\r
+ RI->ICR = tmpreg;\r
+}\r
+/**\r
+ * @brief Configures the Pull-up and Pull-down Resistors \r
+ * @param RI_Resistor selects the resistor to connect. \r
+ * This parameter can be one of the following values:\r
+ * @arg RI_Resistor_10KPU: 10K pull-up resistor\r
+ * @arg RI_Resistor_400KPU: 400K pull-up resistor \r
+ * @arg RI_Resistor_10KPD: 10K pull-down resistor \r
+ * @arg RI_Resistor_400KPD: 400K pull-down resistor\r
+ * @param NewState: New state of the analog switch associated to the selected \r
+ * resistor.\r
+ * This parameter can be:\r
+ * ENABLE so the selected resistor is connected\r
+ * or DISABLE so the selected resistor is disconnected\r
+ * @note To avoid extra power consumption, only one resistor should be enabled\r
+ * at a time. \r
+ * @retval None\r
+ */\r
+void SYSCFG_RIResistorConfig(uint32_t RI_Resistor, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RI_RESISTOR(RI_Resistor));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the resistor */\r
+ COMP->CSR |= (uint32_t) RI_Resistor;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Resistor */\r
+ COMP->CSR &= (uint32_t) (~RI_Resistor);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Close or Open the routing interface Input Output switches.\r
+ * @param RI_IOSwitch: selects the I/O analog switch number.\r
+ * This parameter can be one of the following values:\r
+ * @arg RI_IOSwitch_CH0 --> RI_IOSwitch_CH15\r
+ * @arg RI_IOSwitch_CH18 --> RI_IOSwitch_CH25\r
+ * @arg RI_IOSwitch_GR10_1 --> RI_IOSwitch_GR10_4\r
+ * @arg RI_IOSwitch_GR6_1 --> RI_IOSwitch_GR6_2\r
+ * @arg RI_IOSwitch_GR5_1 --> RI_IOSwitch_GR5_3\r
+ * @arg RI_IOSwitch_GR4_1 --> RI_IOSwitch_GR4_3\r
+ * @arg RI_IOSwitch_VCOMP\r
+ * @param NewState: New state of the analog switch. \r
+ * This parameter can be \r
+ * ENABLE so the Input Output switch is closed\r
+ * or DISABLE so the Input Output switch is open\r
+ * @retval None\r
+ */\r
+void SYSCFG_RIIOSwitchConfig(uint32_t RI_IOSwitch, FunctionalState NewState)\r
+{\r
+ uint32_t ioswitchmask = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RI_IOSWITCH(RI_IOSwitch));\r
+ \r
+ /* Read Analog switch register index */\r
+ ioswitchmask = RI_IOSwitch >> 31;\r
+ \r
+ /* Get Bits[30:0] of the IO switch */\r
+ RI_IOSwitch &= 0x7FFFFFFF;\r
+ \r
+ \r
+ if (NewState != DISABLE)\r
+ { \r
+ if (ioswitchmask != 0)\r
+ {\r
+ /* Close the analog switches */\r
+ RI->ASCR1 |= RI_IOSwitch;\r
+ }\r
+ else\r
+ {\r
+ /* Open the analog switches */\r
+ RI->ASCR2 |= RI_IOSwitch;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if (ioswitchmask != 0)\r
+ {\r
+ /* Close the analog switches */\r
+ RI->ASCR1 &= (~ (uint32_t)RI_IOSwitch);\r
+ }\r
+ else\r
+ {\r
+ /* Open the analog switches */\r
+ RI->ASCR2 &= (~ (uint32_t)RI_IOSwitch);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enable or disable the switch control mode.\r
+ * @param NewState: New state of the switch control mode. This parameter can\r
+ * be ENABLE: ADC analog switches closed if the corresponding \r
+ * I/O switch is also closed.\r
+ * When using COMP1 switch control mode must be enabled.\r
+ * or DISABLE: ADC analog switches open or controlled by the ADC interface.\r
+ * When using the ADC for acquisition switch control mode \r
+ * must be disabled.\r
+ * @note COMP1 comparator and ADC cannot be used at the same time since \r
+ * they share the ADC switch matrix.\r
+ * @retval None\r
+ */\r
+void SYSCFG_RISwitchControlModeCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
+ \r
+ if (NewState != DISABLE)\r
+ { \r
+ /* Enable the Switch control mode */ \r
+ RI->ASCR1 |= (uint32_t) RI_ASCR1_SCM;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Switch control mode */ \r
+ RI->ASCR1 &= (uint32_t)(~RI_ASCR1_SCM);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enable or disable Hysteresis of the input schmitt triger of Ports A..E\r
+ * When the I/Os are programmed in input mode by standard I/O port \r
+ * registers, the Schmitt trigger and the hysteresis are enabled by default. \r
+ * When hysteresis is disabled, it is possible to read the \r
+ * corresponding port with a trigger level of VDDIO/2. \r
+ * @param RI_Port: selects the GPIO Port.\r
+ * This parameter can be one of the following values:\r
+ * @arg RI_PortA : Port A is selected\r
+ * @arg RI_PortB : Port B is selected\r
+ * @arg RI_PortC : Port C is selected\r
+ * @arg RI_PortD : Port D is selected\r
+ * @arg RI_PortE : Port E is selected\r
+ * @param RI_Pin : Selects the pin(s) on which to enable or disable hysteresis.\r
+ * This parameter can any value from RI_Pin_x where x can be (0..15) or RI_Pin_All.\r
+ * @param NewState new state of the Hysteresis.\r
+ * This parameter can be:\r
+ * ENABLE so the Hysteresis is on\r
+ * or DISABLE so the Hysteresis is off\r
+ * @retval None\r
+ */\r
+void SYSCFG_RIHysteresisConfig(uint8_t RI_Port, uint16_t RI_Pin,\r
+ FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RI_PORT(RI_Port));\r
+ assert_param(IS_RI_PIN(RI_Pin));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if(RI_Port == RI_PortA)\r
+ { \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Hysteresis on */\r
+ RI->HYSCR1 &= (uint32_t)~((uint32_t)RI_Pin);\r
+ }\r
+ else\r
+ {\r
+ /* Hysteresis off */\r
+ RI->HYSCR1 |= (uint32_t) RI_Pin;\r
+ }\r
+ }\r
+ \r
+ else if(RI_Port == RI_PortB)\r
+ {\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Hysteresis on */\r
+ RI->HYSCR1 &= (uint32_t) (~((uint32_t)RI_Pin) << 16);\r
+ }\r
+ else\r
+ {\r
+ /* Hysteresis off */\r
+ RI->HYSCR1 |= (uint32_t) ((uint32_t)(RI_Pin) << 16);\r
+ }\r
+ } \r
+ \r
+ else if(RI_Port == RI_PortC)\r
+ {\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Hysteresis on */\r
+ RI->HYSCR2 &= (uint32_t) (~((uint32_t)RI_Pin));\r
+ }\r
+ else\r
+ {\r
+ /* Hysteresis off */\r
+ RI->HYSCR2 |= (uint32_t) (RI_Pin );\r
+ }\r
+ } \r
+ else if(RI_Port == RI_PortD)\r
+ {\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Hysteresis on */\r
+ RI->HYSCR2 &= (uint32_t) (~((uint32_t)RI_Pin) << 16);\r
+ }\r
+ else\r
+ {\r
+ /* Hysteresis off */\r
+ RI->HYSCR2 |= (uint32_t) ((uint32_t)(RI_Pin) << 16);\r
+\r
+ }\r
+ } \r
+ else /* RI_Port == RI_PortE */\r
+ {\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Hysteresis on */\r
+ RI->HYSCR3 &= (uint32_t) (~((uint32_t)RI_Pin));\r
+ }\r
+ else\r
+ {\r
+ /* Hysteresis off */\r
+ RI->HYSCR3 |= (uint32_t) (RI_Pin );\r
+ }\r
+ } \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ \r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_tim.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the TIM peripheral:\r
+ * - TimeBase management\r
+ * - Output Compare management\r
+ * - Input Capture management\r
+ * - Interrupts, DMA and flags management\r
+ * - Clocks management\r
+ * - Synchronization management\r
+ * - Specific interface management\r
+ * - Specific remapping management \r
+ * \r
+ * @verbatim\r
+ * \r
+ * ===================================================================\r
+ * How to use this driver\r
+ * ===================================================================\r
+ * This driver provides functions to configure and program the TIM \r
+ * of all STM32L1xx devices\r
+ * These functions are split in 8 groups: \r
+ * \r
+ * 1. TIM TimeBase management: this group includes all needed functions \r
+ * to configure the TM Timebase unit:\r
+ * - Set/Get Prescaler\r
+ * - Set/Get Autoreload \r
+ * - Counter modes configuration\r
+ * - Set Clock division \r
+ * - Select the One Pulse mode\r
+ * - Update Request Configuration\r
+ * - Update Disable Configuration\r
+ * - Auto-Preload Configuration \r
+ * - Enable/Disable the counter \r
+ * \r
+ * 2. TIM Output Compare management: this group includes all needed \r
+ * functions to configure the Capture/Compare unit used in Output \r
+ * compare mode: \r
+ * - Configure each channel, independently, in Output Compare mode\r
+ * - Select the output compare modes\r
+ * - Select the Polarities of each channel\r
+ * - Set/Get the Capture/Compare register values\r
+ * - Select the Output Compare Fast mode \r
+ * - Select the Output Compare Forced mode \r
+ * - Output Compare-Preload Configuration \r
+ * - Clear Output Compare Reference\r
+ * - Select the OCREF Clear signal\r
+ * - Enable/Disable the Capture/Compare Channels \r
+ * \r
+ * 3. TIM Input Capture management: this group includes all needed \r
+ * functions to configure the Capture/Compare unit used in \r
+ * Input Capture mode:\r
+ * - Configure each channel in input capture mode\r
+ * - Configure Channel1/2 in PWM Input mode\r
+ * - Set the Input Capture Prescaler\r
+ * - Get the Capture/Compare values \r
+ * \r
+ * 4. TIM interrupts, DMA and flags management\r
+ * - Enable/Disable interrupt sources\r
+ * - Get flags status\r
+ * - Clear flags/ Pending bits\r
+ * - Enable/Disable DMA requests \r
+ * - Configure DMA burst mode\r
+ * - Select CaptureCompare DMA request \r
+ * \r
+ * 5. TIM clocks management: this group includes all needed functions \r
+ * to configure the clock controller unit:\r
+ * - Select internal/External clock\r
+ * - Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx\r
+ * \r
+ * 6. TIM synchronization management: this group includes all needed \r
+ * functions to configure the Synchronization unit:\r
+ * - Select Input Trigger \r
+ * - Select Output Trigger \r
+ * - Select Master Slave Mode \r
+ * - ETR Configuration when used as external trigger \r
+ * \r
+ * 7. TIM specific interface management, this group includes all \r
+ * needed functions to use the specific TIM interface:\r
+ * - Encoder Interface Configuration\r
+ * - Select Hall Sensor \r
+ * \r
+ * 8. TIM specific remapping management includes the Remapping \r
+ * configuration of specific timers \r
+ * \r
+ * @endverbatim\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_tim.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup TIM \r
+ * @brief TIM driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+\r
+/* ---------------------- TIM registers bit mask ------------------------ */\r
+#define SMCR_ETR_MASK ((uint16_t)0x00FF) \r
+#define CCMR_OFFSET ((uint16_t)0x0018)\r
+#define CCER_CCE_SET ((uint16_t)0x0001) \r
+ \r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+\r
+static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter);\r
+static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter);\r
+static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter);\r
+static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter);\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup TIM_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup TIM_Group1 TimeBase management functions\r
+ * @brief TimeBase management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ TimeBase management functions\r
+ =============================================================================== \r
+ \r
+ =================================================================== \r
+ TIM Driver: how to use it in Timing(Time base) Mode\r
+ =================================================================== \r
+ To use the Timer in Timing(Time base) mode, the following steps are mandatory:\r
+ \r
+ 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function\r
+ \r
+ 2. Fill the TIM_TimeBaseInitStruct with the desired parameters.\r
+ \r
+ 3. Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure the Time Base unit\r
+ with the corresponding configuration\r
+ \r
+ 4. Enable the NVIC if you need to generate the update interrupt. \r
+ \r
+ 5. Enable the corresponding interrupt using the function TIM_ITConfig(TIMx, TIM_IT_Update) \r
+ \r
+ 6. Call the TIM_Cmd(ENABLE) function to enable the TIM counter.\r
+ \r
+ Note1: All other functions can be used seperatly to modify, if needed,\r
+ a specific feature of the Timer. \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the TIMx peripheral registers to their default reset values.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @retval None\r
+ * \r
+ */\r
+void TIM_DeInit(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx)); \r
+ \r
+ if (TIMx == TIM2)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);\r
+ }\r
+ else if (TIMx == TIM3)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);\r
+ }\r
+ else if (TIMx == TIM4)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);\r
+ } \r
+\r
+ else if (TIMx == TIM6)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);\r
+ } \r
+ else if (TIMx == TIM7)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);\r
+ } \r
+\r
+ else if (TIMx == TIM9)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE);\r
+ } \r
+ else if (TIMx == TIM10)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE);\r
+ } \r
+ else\r
+ {\r
+ if (TIMx == TIM11)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE); \r
+ } \r
+ }\r
+ \r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIMx Time Base Unit peripheral according to \r
+ * the specified parameters in the TIM_TimeBaseInitStruct.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef\r
+ * structure that contains the configuration information for\r
+ * the specified TIM peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)\r
+{\r
+ uint16_t tmpcr1 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx)); \r
+ assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));\r
+ assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));\r
+\r
+ tmpcr1 = TIMx->CR1; \r
+\r
+ if(((TIMx) == TIM2) || ((TIMx) == TIM3) || ((TIMx) == TIM4))\r
+ { \r
+ /* Select the Counter Mode */\r
+ tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));\r
+ tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;\r
+ }\r
+ \r
+ if(((TIMx) != TIM6) && ((TIMx) != TIM7))\r
+ {\r
+ /* Set the clock division */\r
+ tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD));\r
+ tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;\r
+ }\r
+\r
+ TIMx->CR1 = tmpcr1;\r
+\r
+ /* Set the Autoreload value */\r
+ TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;\r
+ \r
+ /* Set the Prescaler value */\r
+ TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;\r
+ \r
+ /* Generate an update event to reload the Prescaler value immediatly */\r
+ TIMx->EGR = TIM_PSCReloadMode_Immediate; \r
+}\r
+\r
+/**\r
+ * @brief Fills each TIM_TimeBaseInitStruct member with its default value.\r
+ * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef\r
+ * structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)\r
+{\r
+ /* Set the default configuration */\r
+ TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF;\r
+ TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;\r
+ TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;\r
+ TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Prescaler.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @param Prescaler: specifies the Prescaler Register value\r
+ * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.\r
+ * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.\r
+ * @retval None\r
+ */\r
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));\r
+ \r
+ /* Set the Prescaler value */\r
+ TIMx->PSC = Prescaler;\r
+ /* Set or reset the UG Bit */\r
+ TIMx->EGR = TIM_PSCReloadMode;\r
+}\r
+\r
+/**\r
+ * @brief Specifies the TIMx Counter Mode to be used.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_CounterMode: specifies the Counter Mode to be used\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CounterMode_Up: TIM Up Counting Mode\r
+ * @arg TIM_CounterMode_Down: TIM Down Counting Mode\r
+ * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1\r
+ * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2\r
+ * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3\r
+ * @retval None\r
+ */\r
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)\r
+{\r
+ uint16_t tmpcr1 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));\r
+ \r
+ tmpcr1 = TIMx->CR1;\r
+ /* Reset the CMS and DIR Bits */\r
+ tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));\r
+ /* Set the Counter Mode */\r
+ tmpcr1 |= TIM_CounterMode;\r
+ /* Write to TIMx CR1 register */\r
+ TIMx->CR1 = tmpcr1;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Counter Register value\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @param Counter: specifies the Counter register new value.\r
+ * @retval None\r
+ */\r
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ \r
+ /* Set the Counter Register value */\r
+ TIMx->CNT = Counter;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Autoreload Register value\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @param Autoreload: specifies the Autoreload register new value.\r
+ * @retval None\r
+ */\r
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ \r
+ /* Set the Autoreload Register value */\r
+ TIMx->ARR = Autoreload;\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIMx Counter value.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @retval Counter Register value.\r
+ */\r
+uint32_t TIM_GetCounter(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ \r
+ /* Get the Counter Register value */\r
+ return TIMx->CNT;\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIMx Prescaler value.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @retval Prescaler Register value.\r
+ */\r
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ \r
+ /* Get the Prescaler Register value */\r
+ return TIMx->PSC;\r
+}\r
+\r
+/**\r
+ * @brief Enables or Disables the TIMx Update event.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @param NewState: new state of the TIMx UDIS bit\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the Update Disable Bit */\r
+ TIMx->CR1 |= TIM_CR1_UDIS;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the Update Disable Bit */\r
+ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Update Request Interrupt source.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @param TIM_UpdateSource: specifies the Update source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow\r
+ or the setting of UG bit, or an update generation\r
+ through the slave mode controller.\r
+ * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.\r
+ * @retval None\r
+ */\r
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));\r
+ \r
+ if (TIM_UpdateSource != TIM_UpdateSource_Global)\r
+ {\r
+ /* Set the URS Bit */\r
+ TIMx->CR1 |= TIM_CR1_URS;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the URS Bit */\r
+ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables TIMx peripheral Preload register on ARR.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @param NewState: new state of the TIMx peripheral Preload register\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the ARR Preload Bit */\r
+ TIMx->CR1 |= TIM_CR1_ARPE;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the ARR Preload Bit */\r
+ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIMx\92s One Pulse Mode.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @param TIM_OPMode: specifies the OPM Mode to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OPMode_Single\r
+ * @arg TIM_OPMode_Repetitive\r
+ * @retval None\r
+ */\r
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OPM_MODE(TIM_OPMode));\r
+ \r
+ /* Reset the OPM Bit */\r
+ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM);\r
+ /* Configure the OPM Mode */\r
+ TIMx->CR1 |= TIM_OPMode;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Clock Division value.\r
+ * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_CKD: specifies the clock division value.\r
+ * This parameter can be one of the following value:\r
+ * @arg TIM_CKD_DIV1: TDTS = Tck_tim\r
+ * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim\r
+ * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim\r
+ * @retval None\r
+ */\r
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ assert_param(IS_TIM_CKD_DIV(TIM_CKD));\r
+ \r
+ /* Reset the CKD Bits */\r
+ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD);\r
+ /* Set the CKD value */\r
+ TIMx->CR1 |= TIM_CKD;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified TIM peripheral.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIMx peripheral.\r
+ * @param NewState: new state of the TIMx peripheral.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the TIM Counter */\r
+ TIMx->CR1 |= TIM_CR1_CEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the TIM Counter */\r
+ TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN));\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Group2 Output Compare management functions\r
+ * @brief Output Compare management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Output Compare management functions\r
+ =============================================================================== \r
+ \r
+ =================================================================== \r
+ TIM Driver: how to use it in Output Compare Mode\r
+ =================================================================== \r
+ To use the Timer in Output Compare mode, the following steps are mandatory:\r
+ \r
+ 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function\r
+ \r
+ 2. Configure the TIM pins by configuring the corresponding GPIO pins\r
+ \r
+ 2. Configure the Time base unit as described in the first part of this driver, if needed,\r
+ else the Timer will run with the default configuration:\r
+ - Autoreload value = 0xFFFF\r
+ - Prescaler value = 0x0000\r
+ - Counter mode = Up counting\r
+ - Clock Division = TIM_CKD_DIV1\r
+ \r
+ 3. Fill the TIM_OCInitStruct with the desired parameters including:\r
+ - The TIM Output Compare mode: TIM_OCMode\r
+ - TIM Output State: TIM_OutputState\r
+ - TIM Pulse value: TIM_Pulse\r
+ - TIM Output Compare Polarity : TIM_OCPolarity\r
+ \r
+ 4. Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired channel with the \r
+ corresponding configuration\r
+ \r
+ 5. Call the TIM_Cmd(ENABLE) function to enable the TIM counter.\r
+ \r
+ Note1: All other functions can be used separately to modify, if needed,\r
+ a specific feature of the Timer. \r
+ \r
+ Note2: In case of PWM mode, this function is mandatory:\r
+ TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE); \r
+ \r
+ Note3: If the corresponding interrupt or DMA request are needed, the user should:\r
+ 1. Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests). \r
+ 2. Enable the corresponding interrupt (or DMA request) using the function \r
+ TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the TIMx Channel1 according to the specified\r
+ * parameters in the TIM_OCInitStruct.\r
+ * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
+ * that contains the configuration information for the specified TIM \r
+ * peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
+{\r
+ uint16_t tmpccmrx = 0, tmpccer = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r
+ /* Disable the Channel 1: Reset the CC1E Bit */\r
+ TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);\r
+ \r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ \r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmrx = TIMx->CCMR1;\r
+ \r
+ /* Reset the Output Compare Mode Bits */\r
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M));\r
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S));\r
+ \r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;\r
+ \r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P));\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;\r
+ \r
+ /* Set the Output State */\r
+ tmpccer |= TIM_OCInitStruct->TIM_OutputState;\r
+ \r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;\r
+ \r
+ /* Write to TIMx CCMR1 */\r
+ TIMx->CCMR1 = tmpccmrx;\r
+ \r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIMx Channel2 according to the specified\r
+ * parameters in the TIM_OCInitStruct.\r
+ * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
+ * that contains the configuration information for the specified TIM \r
+ * peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
+{\r
+ uint16_t tmpccmrx = 0, tmpccer = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); \r
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r
+ /* Disable the Channel 2: Reset the CC2E Bit */\r
+ TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E));\r
+ \r
+ /* Get the TIMx CCER register value */ \r
+ tmpccer = TIMx->CCER;\r
+ \r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmrx = TIMx->CCMR1;\r
+ \r
+ /* Reset the Output Compare Mode Bits */\r
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M));\r
+ \r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);\r
+ \r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P));\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);\r
+ \r
+ /* Set the Output State */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);\r
+ \r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;\r
+ \r
+ /* Write to TIMx CCMR1 */\r
+ TIMx->CCMR1 = tmpccmrx;\r
+ \r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIMx Channel3 according to the specified\r
+ * parameters in the TIM_OCInitStruct.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
+ * that contains the configuration information for the specified TIM \r
+ * peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
+{\r
+ uint16_t tmpccmrx = 0, tmpccer = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r
+\r
+ /* Disable the Channel 2: Reset the CC2E Bit */\r
+ TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E));\r
+ \r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ \r
+ /* Get the TIMx CCMR2 register value */\r
+ tmpccmrx = TIMx->CCMR2;\r
+ \r
+ /* Reset the Output Compare Mode Bits */\r
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M));\r
+ \r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;\r
+ \r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P));\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);\r
+ \r
+ /* Set the Output State */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);\r
+ \r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;\r
+ \r
+ /* Write to TIMx CCMR2 */\r
+ TIMx->CCMR2 = tmpccmrx;\r
+ \r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIMx Channel4 according to the specified\r
+ * parameters in the TIM_OCInitStruct.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
+ * that contains the configuration information for the specified TIM \r
+ * peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
+{\r
+ uint16_t tmpccmrx = 0, tmpccer = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); \r
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r
+\r
+ /* Disable the Channel 2: Reset the CC4E Bit */\r
+ TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E));\r
+ \r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ \r
+ /* Get the TIMx CCMR2 register value */\r
+ tmpccmrx = TIMx->CCMR2;\r
+ \r
+ /* Reset the Output Compare Mode Bits */\r
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M));\r
+ \r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);\r
+ \r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P));\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);\r
+ \r
+ /* Set the Output State */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);\r
+ \r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;\r
+ \r
+ /* Write to TIMx CCMR2 */ \r
+ TIMx->CCMR2 = tmpccmrx;\r
+ \r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Fills each TIM_OCInitStruct member with its default value.\r
+ * @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will\r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)\r
+{\r
+ /* Set the default configuration */\r
+ TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;\r
+ TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;\r
+ TIM_OCInitStruct->TIM_Pulse = 0x0000;\r
+ TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIM Output Compare Mode.\r
+ * @note This function disables the selected channel before changing the Output\r
+ * Compare Mode.\r
+ * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.\r
+ * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_Channel: specifies the TIM Channel\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_Channel_1: TIM Channel 1\r
+ * @arg TIM_Channel_2: TIM Channel 2\r
+ * @arg TIM_Channel_3: TIM Channel 3\r
+ * @arg TIM_Channel_4: TIM Channel 4\r
+ * @param TIM_OCMode: specifies the TIM Output Compare Mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCMode_Timing\r
+ * @arg TIM_OCMode_Active\r
+ * @arg TIM_OCMode_Toggle\r
+ * @arg TIM_OCMode_PWM1\r
+ * @arg TIM_OCMode_PWM2\r
+ * @arg TIM_ForcedAction_Active\r
+ * @arg TIM_ForcedAction_InActive\r
+ * @retval None\r
+ */\r
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)\r
+{\r
+ uint32_t tmp = 0;\r
+ uint16_t tmp1 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); \r
+ assert_param(IS_TIM_OCM(TIM_OCMode));\r
+ \r
+ tmp = (uint32_t) TIMx;\r
+ tmp += CCMR_OFFSET;\r
+\r
+ tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel;\r
+\r
+ /* Disable the Channel: Reset the CCxE Bit */\r
+ TIMx->CCER &= (uint16_t) ~tmp1;\r
+\r
+ if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))\r
+ {\r
+ tmp += (TIM_Channel>>1);\r
+\r
+ /* Reset the OCxM bits in the CCMRx register */\r
+ *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M);\r
+ \r
+ /* Configure the OCxM bits in the CCMRx register */\r
+ *(__IO uint32_t *) tmp |= TIM_OCMode;\r
+ }\r
+ else\r
+ {\r
+ tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;\r
+\r
+ /* Reset the OCxM bits in the CCMRx register */\r
+ *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M);\r
+ \r
+ /* Configure the OCxM bits in the CCMRx register */\r
+ *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Capture Compare1 Register value\r
+ * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param Compare1: specifies the Capture Compare1 register new value.\r
+ * @retval None\r
+\r
+ */\r
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ \r
+ /* Set the Capture Compare1 Register value */\r
+ TIMx->CCR1 = Compare1;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Capture Compare2 Register value\r
+ * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+ * @param Compare2: specifies the Capture Compare2 register new value.\r
+ * @retval None\r
+\r
+ */\r
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ \r
+ /* Set the Capture Compare2 Register value */\r
+ TIMx->CCR2 = Compare2;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Capture Compare3 Register value\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param Compare3: specifies the Capture Compare3 register new value.\r
+ * @retval None\r
+\r
+ */\r
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ \r
+ /* Set the Capture Compare3 Register value */\r
+ TIMx->CCR3 = Compare3;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Capture Compare4 Register value\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param Compare4: specifies the Capture Compare4 register new value.\r
+ * @retval None\r
+\r
+ */\r
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ \r
+ /* Set the Capture Compare4 Register value */\r
+ TIMx->CCR4 = Compare4;\r
+}\r
+\r
+/**\r
+ * @brief Forces the TIMx output 1 waveform to active or inactive level.\r
+ * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ForcedAction_Active: Force active level on OC1REF\r
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.\r
+ * @retval None\r
+ */\r
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC1M Bits */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M);\r
+ /* Configure The Forced output Mode */\r
+ tmpccmr1 |= TIM_ForcedAction;\r
+ /* Write to TIMx CCMR1 register */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+ \r
+/**\r
+ * @brief Forces the TIMx output 2 waveform to active or inactive level.\r
+ * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM \r
+ * peripheral.\r
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ForcedAction_Active: Force active level on OC2REF\r
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.\r
+ * @retval None\r
+ */\r
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
+ \r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC2M Bits */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M);\r
+ /* Configure The Forced output Mode */\r
+ tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);\r
+ /* Write to TIMx CCMR1 register */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Forces the TIMx output 3 waveform to active or inactive level.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ForcedAction_Active: Force active level on OC3REF\r
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.\r
+ * @retval None\r
+ */\r
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
+ \r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC1M Bits */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M);\r
+ /* Configure The Forced output Mode */\r
+ tmpccmr2 |= TIM_ForcedAction;\r
+ /* Write to TIMx CCMR2 register */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Forces the TIMx output 4 waveform to active or inactive level.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ForcedAction_Active: Force active level on OC4REF\r
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.\r
+ * @retval None\r
+ */\r
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
+ \r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC2M Bits */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M);\r
+ /* Configure The Forced output Mode */\r
+ tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);\r
+ /* Write to TIMx CCMR2 register */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR1.\r
+ * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCPreload_Enable\r
+ * @arg TIM_OCPreload_Disable\r
+ * @retval None\r
+ */\r
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
+ \r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC1PE Bit */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE);\r
+ /* Enable or Disable the Output Compare Preload feature */\r
+ tmpccmr1 |= TIM_OCPreload;\r
+ /* Write to TIMx CCMR1 register */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR2.\r
+ * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCPreload_Enable\r
+ * @arg TIM_OCPreload_Disable\r
+ * @retval None\r
+ */\r
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
+ \r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC2PE Bit */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE);\r
+ /* Enable or Disable the Output Compare Preload feature */\r
+ tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);\r
+ /* Write to TIMx CCMR1 register */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR3.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCPreload_Enable\r
+ * @arg TIM_OCPreload_Disable\r
+ * @retval None\r
+ */\r
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
+ \r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC3PE Bit */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE);\r
+ /* Enable or Disable the Output Compare Preload feature */\r
+ tmpccmr2 |= TIM_OCPreload;\r
+ /* Write to TIMx CCMR2 register */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR4.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCPreload_Enable\r
+ * @arg TIM_OCPreload_Disable\r
+ * @retval None\r
+ */\r
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
+ \r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC4PE Bit */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE);\r
+ /* Enable or Disable the Output Compare Preload feature */\r
+ tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);\r
+ /* Write to TIMx CCMR2 register */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Output Compare 1 Fast feature.\r
+ * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable\r
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable\r
+ * @retval None\r
+ */\r
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
+ \r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC1FE Bit */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE);\r
+ /* Enable or Disable the Output Compare Fast Bit */\r
+ tmpccmr1 |= TIM_OCFast;\r
+ /* Write to TIMx CCMR1 */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Output Compare 2 Fast feature.\r
+ * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable\r
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable\r
+ * @retval None\r
+ */\r
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
+ \r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC2FE Bit */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE);\r
+ /* Enable or Disable the Output Compare Fast Bit */\r
+ tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);\r
+ /* Write to TIMx CCMR1 */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Output Compare 3 Fast feature.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable\r
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable\r
+ * @retval None\r
+ */\r
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
+ \r
+ /* Get the TIMx CCMR2 register value */\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC3FE Bit */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE);\r
+ /* Enable or Disable the Output Compare Fast Bit */\r
+ tmpccmr2 |= TIM_OCFast;\r
+ /* Write to TIMx CCMR2 */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Output Compare 4 Fast feature.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable\r
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable\r
+ * @retval None\r
+ */\r
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
+ \r
+ /* Get the TIMx CCMR2 register value */\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC4FE Bit */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE);\r
+ /* Enable or Disable the Output Compare Fast Bit */\r
+ tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);\r
+ /* Write to TIMx CCMR2 */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Clears or safeguards the OCREF1 signal on an external event\r
+ * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCClear_Enable: TIM Output clear enable\r
+ * @arg TIM_OCClear_Disable: TIM Output clear disable\r
+ * @retval None\r
+ */\r
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
+ \r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC1CE Bit */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE);\r
+ /* Enable or Disable the Output Compare Clear Bit */\r
+ tmpccmr1 |= TIM_OCClear;\r
+ /* Write to TIMx CCMR1 register */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Clears or safeguards the OCREF2 signal on an external event\r
+ * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
+\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCClear_Enable: TIM Output clear enable\r
+ * @arg TIM_OCClear_Disable: TIM Output clear disable\r
+ * @retval None\r
+ */\r
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
+ \r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC2CE Bit */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE);\r
+ /* Enable or Disable the Output Compare Clear Bit */\r
+ tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);\r
+ /* Write to TIMx CCMR1 register */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Clears or safeguards the OCREF3 signal on an external event\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCClear_Enable: TIM Output clear enable\r
+ * @arg TIM_OCClear_Disable: TIM Output clear disable\r
+ * @retval None\r
+ */\r
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
+ \r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC3CE Bit */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE);\r
+ /* Enable or Disable the Output Compare Clear Bit */\r
+ tmpccmr2 |= TIM_OCClear;\r
+ /* Write to TIMx CCMR2 register */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Clears or safeguards the OCREF4 signal on an external event\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCClear_Enable: TIM Output clear enable\r
+ * @arg TIM_OCClear_Disable: TIM Output clear disable\r
+ * @retval None\r
+ */\r
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
+ \r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC4CE Bit */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE);\r
+ /* Enable or Disable the Output Compare Clear Bit */\r
+ tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);\r
+ /* Write to TIMx CCMR2 register */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx channel 1 polarity.\r
+ * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_OCPolarity: specifies the OC1 Polarity\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_OCPolarity_High: Output Compare active high\r
+ * @arg TIM_OCPolarity_Low: Output Compare active low\r
+ * @retval None\r
+ */\r
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
+{\r
+ uint16_t tmpccer = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
+ \r
+ tmpccer = TIMx->CCER;\r
+ /* Set or Reset the CC1P Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P);\r
+ tmpccer |= TIM_OCPolarity;\r
+ /* Write to TIMx CCER register */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx channel 2 polarity.\r
+ * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+ * @param TIM_OCPolarity: specifies the OC2 Polarity\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_OCPolarity_High: Output Compare active high\r
+ * @arg TIM_OCPolarity_Low: Output Compare active low\r
+ * @retval None\r
+ */\r
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
+{\r
+ uint16_t tmpccer = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
+ \r
+ tmpccer = TIMx->CCER;\r
+ /* Set or Reset the CC2P Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P);\r
+ tmpccer |= (uint16_t)(TIM_OCPolarity << 4);\r
+ /* Write to TIMx CCER register */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx channel 3 polarity.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_OCPolarity: specifies the OC3 Polarity\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_OCPolarity_High: Output Compare active high\r
+ * @arg TIM_OCPolarity_Low: Output Compare active low\r
+ * @retval None\r
+ */\r
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
+{\r
+ uint16_t tmpccer = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
+ \r
+ tmpccer = TIMx->CCER;\r
+ /* Set or Reset the CC3P Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P);\r
+ tmpccer |= (uint16_t)(TIM_OCPolarity << 8);\r
+ /* Write to TIMx CCER register */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx channel 4 polarity.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_OCPolarity: specifies the OC4 Polarity\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_OCPolarity_High: Output Compare active high\r
+ * @arg TIM_OCPolarity_Low: Output Compare active low\r
+ * @retval None\r
+ */\r
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
+{\r
+ uint16_t tmpccer = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
+ \r
+ tmpccer = TIMx->CCER;\r
+ /* Set or Reset the CC4P Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P);\r
+ tmpccer |= (uint16_t)(TIM_OCPolarity << 12);\r
+ /* Write to TIMx CCER register */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Selects the OCReference Clear source.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_OCReferenceClear: specifies the OCReference Clear source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCReferenceClear_ETRF: The internal OCreference clear input is connected to ETRF.\r
+ * @arg TIM_OCReferenceClear_OCREFCLR: The internal OCreference clear input is connected to OCREF_CLR input. \r
+ * @retval None\r
+ */\r
+void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(TIM_OCREFERENCECECLEAR_SOURCE(TIM_OCReferenceClear));\r
+\r
+ /* Set the TIM_OCReferenceClear source */\r
+ TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_OCCS);\r
+ TIMx->SMCR |= TIM_OCReferenceClear;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIM Capture Compare Channel x.\r
+ * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_Channel: specifies the TIM Channel\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_Channel_1: TIM Channel 1\r
+ * @arg TIM_Channel_2: TIM Channel 2\r
+ * @arg TIM_Channel_3: TIM Channel 3\r
+ * @arg TIM_Channel_4: TIM Channel 4\r
+ * @param TIM_CCx: specifies the TIM Channel CCxE bit new state.\r
+ * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. \r
+ * @retval None\r
+ */\r
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)\r
+{\r
+ uint16_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); \r
+ assert_param(IS_TIM_CCX(TIM_CCx));\r
+\r
+ tmp = CCER_CCE_SET << TIM_Channel;\r
+\r
+ /* Reset the CCxE Bit */\r
+ TIMx->CCER &= (uint16_t)~ tmp;\r
+\r
+ /* Set or reset the CCxE Bit */ \r
+ TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Group3 Input Capture management functions\r
+ * @brief Input Capture management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Input Capture management functions\r
+ =============================================================================== \r
+ \r
+ =================================================================== \r
+ TIM Driver: how to use it in Input Capture Mode\r
+ =================================================================== \r
+ To use the Timer in Input Capture mode, the following steps are mandatory:\r
+ \r
+ 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function\r
+ \r
+ 2. Configure the TIM pins by configuring the corresponding GPIO pins\r
+ \r
+ 2. Configure the Time base unit as described in the first part of this driver, if needed,\r
+ else the Timer will run with the default configuration:\r
+ - Autoreload value = 0xFFFF\r
+ - Prescaler value = 0x0000\r
+ - Counter mode = Up counting\r
+ - Clock Division = TIM_CKD_DIV1\r
+ \r
+ 3. Fill the TIM_ICInitStruct with the desired parameters including:\r
+ - TIM Channel: TIM_Channel\r
+ - TIM Input Capture polarity: TIM_ICPolarity\r
+ - TIM Input Capture selection: TIM_ICSelection\r
+ - TIM Input Capture Prescaler: TIM_ICPrescaler\r
+ - TIM Input CApture filter value: TIM_ICFilter\r
+ \r
+ 4. Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel with the \r
+ corresponding configuration and to measure only frequency or duty cycle of the input signal,\r
+ or,\r
+ Call TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired channels with the \r
+ corresponding configuration and to measure the frequency and the duty cycle of the input signal\r
+ \r
+ 5. Enable the NVIC or the DMA to read the measured frequency. \r
+ \r
+ 6. Enable the corresponding interrupt (or DMA request) to read the Captured value,\r
+ using the function TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) \r
+ \r
+ 7. Call the TIM_Cmd(ENABLE) function to enable the TIM counter.\r
+ \r
+ 8. Use TIM_GetCapturex(TIMx); to read the captured value.\r
+ \r
+ Note1: All other functions can be used seperatly to modify, if needed,\r
+ a specific feature of the Timer. \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the TIM peripheral according to the specified\r
+ * parameters in the TIM_ICInitStruct.\r
+ * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure\r
+ * that contains the configuration information for the specified TIM \r
+ * peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));\r
+ assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));\r
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));\r
+ assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));\r
+ \r
+ if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)\r
+ {\r
+ /* TI1 Configuration */\r
+ TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
+ TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+ else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)\r
+ {\r
+ /* TI2 Configuration */\r
+ TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
+ TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+ else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)\r
+ {\r
+ /* TI3 Configuration */\r
+ TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
+ TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+ else\r
+ {\r
+ /* TI4 Configuration */\r
+ TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
+ TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Fills each TIM_ICInitStruct member with its default value.\r
+ * @param TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure which will\r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)\r
+{\r
+ /* Set the default configuration */\r
+ TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;\r
+ TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;\r
+ TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;\r
+ TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;\r
+ TIM_ICInitStruct->TIM_ICFilter = 0x00;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIM peripheral according to the specified\r
+ * parameters in the TIM_ICInitStruct to measure an external PWM signal.\r
+ * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+ * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure\r
+ * that contains the configuration information for the specified TIM \r
+ * peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)\r
+{\r
+ uint16_t icoppositepolarity = TIM_ICPolarity_Rising;\r
+ uint16_t icoppositeselection = TIM_ICSelection_DirectTI;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ /* Select the Opposite Input Polarity */\r
+ if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)\r
+ {\r
+ icoppositepolarity = TIM_ICPolarity_Falling;\r
+ }\r
+ else\r
+ {\r
+ icoppositepolarity = TIM_ICPolarity_Rising;\r
+ }\r
+ /* Select the Opposite Input */\r
+ if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)\r
+ {\r
+ icoppositeselection = TIM_ICSelection_IndirectTI;\r
+ }\r
+ else\r
+ {\r
+ icoppositeselection = TIM_ICSelection_DirectTI;\r
+ }\r
+ if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)\r
+ {\r
+ /* TI1 Configuration */\r
+ TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ /* TI2 Configuration */\r
+ TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+ else\r
+ { \r
+ /* TI2 Configuration */\r
+ TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ /* TI1 Configuration */\r
+ TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIMx Input Capture 1 value.\r
+ * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+ * @retval Capture Compare 1 Register value.\r
+\r
+ */\r
+uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ \r
+ /* Get the Capture 1 Register value */\r
+ return TIMx->CCR1;\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIMx Input Capture 2 value.\r
+ * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+ * @retval Capture Compare 2 Register value.\r
+\r
+ */\r
+uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ \r
+ /* Get the Capture 2 Register value */\r
+ return TIMx->CCR2;\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIMx Input Capture 3 value.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @retval Capture Compare 3 Register value.\r
+ */\r
+uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); \r
+ \r
+ /* Get the Capture 3 Register value */\r
+ return TIMx->CCR3;\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIMx Input Capture 4 value.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @retval Capture Compare 4 Register value.\r
+ */\r
+uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ \r
+ /* Get the Capture 4 Register value */\r
+ return TIMx->CCR4;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Input Capture 1 prescaler.\r
+ * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPSC_DIV1: no prescaler\r
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
+ * @retval None\r
+ */\r
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
+ \r
+ /* Reset the IC1PSC Bits */\r
+ TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC);\r
+ /* Set the IC1PSC value */\r
+ TIMx->CCMR1 |= TIM_ICPSC;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Input Capture 2 prescaler.\r
+ * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+ * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPSC_DIV1: no prescaler\r
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
+ * @retval None\r
+ */\r
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
+ \r
+ /* Reset the IC2PSC Bits */\r
+ TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC);\r
+ /* Set the IC2PSC value */\r
+ TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Input Capture 3 prescaler.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPSC_DIV1: no prescaler\r
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
+ * @retval None\r
+ */\r
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
+ \r
+ /* Reset the IC3PSC Bits */\r
+ TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC);\r
+ /* Set the IC3PSC value */\r
+ TIMx->CCMR2 |= TIM_ICPSC;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Input Capture 4 prescaler.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPSC_DIV1: no prescaler\r
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
+ * @retval None\r
+ */\r
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
+ \r
+ /* Reset the IC4PSC Bits */\r
+ TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC);\r
+ /* Set the IC4PSC value */\r
+ TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Group4 Interrupts DMA and flags management functions\r
+ * @brief Interrupts, DMA and flags management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Interrupts, DMA and flags management functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified TIM interrupts.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIMx peripheral.\r
+ * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg TIM_IT_Update: TIM update Interrupt source\r
+ * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source\r
+ * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source\r
+ * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source\r
+ * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source\r
+ * @arg TIM_IT_Trigger: TIM Trigger Interrupt source\r
+ * @note \r
+ * - TIM6 and TIM7 can only generate an update interrupt. \r
+ * - TIM_IT_CC2, TIM_IT_CC3, TIM_IT_CC4 and TIM_IT_Trigger can not be used with TIM10 and TIM11\r
+ * - TIM_IT_CC3, TIM_IT_CC4 can not be used with TIM9. \r
+ * @param NewState: new state of the TIM interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IT(TIM_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the Interrupt sources */\r
+ TIMx->DIER |= TIM_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Interrupt sources */\r
+ TIMx->DIER &= (uint16_t)~TIM_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx event to be generate by software.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @param TIM_EventSource: specifies the event source.\r
+ * This parameter can be one or more of the following values: \r
+ * @arg TIM_EventSource_Update: Timer update Event source\r
+ * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source\r
+ * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source\r
+ * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source\r
+ * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source \r
+ * @arg TIM_EventSource_Trigger: Timer Trigger Event source\r
+ * @note \r
+ * - TIM6 and TIM7 can only generate an update event. \r
+ * - TIM9 can only generate an update event, Capture Compare 1 event, \r
+ * Capture Compare 2 event and TIM_EventSource_Trigger. \r
+ * - TIM10 and TIM11 can only generate an update event and Capture Compare 1 event. \r
+ * @retval None\r
+ */\r
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); \r
+ /* Set the event sources */\r
+ TIMx->EGR = TIM_EventSource;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified TIM flag is set or not.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @param TIM_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_FLAG_Update: TIM update Flag\r
+ * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag\r
+ * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag\r
+ * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag\r
+ * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag\r
+ * @arg TIM_FLAG_Trigger: TIM Trigger Flag\r
+ * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag\r
+ * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag\r
+ * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag\r
+ * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag\r
+ * @note\r
+ * - TIM6 and TIM7 can have only one update flag.\r
+ * - TIM9 can have only update flag, TIM_FLAG_CC1, TIM_FLAG_CC2 and TIM_FLAG_Trigger,\r
+ * TIM_FLAG_CC1OF or TIM_FLAG_CC2OF flags \r
+ * - TIM10 and TIM11 can have only update flag, TIM_FLAG_CC1 or TIM_FLAG_CC1OF flags \r
+ * @retval The new state of TIM_FLAG (SET or RESET).\r
+ */\r
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)\r
+{ \r
+ ITStatus bitstatus = RESET; \r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_GET_FLAG(TIM_FLAG));\r
+ \r
+ if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the TIMx's pending flags.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @param TIM_FLAG: specifies the flag bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg TIM_FLAG_Update: TIM update Flag\r
+ * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag\r
+ * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag\r
+ * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag\r
+ * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag\r
+ * @arg TIM_FLAG_Trigger: TIM Trigger Flag\r
+ * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag\r
+ * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag\r
+ * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag\r
+ * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag\r
+ * @note\r
+ * - TIM6 and TIM7 can have only one update flag. \r
+ * - TIM9 can have only update flag, TIM_FLAG_CC1, TIM_FLAG_CC2 and TIM_FLAG_Trigger flags\r
+ * TIM_FLAG_CC1OF or TIM_FLAG_CC2OF flags \r
+ * - TIM10 and TIM11 can have only update flag, TIM_FLAG_CC1\r
+ * or TIM_FLAG_CC1OF flags \r
+ * @retval None\r
+ */\r
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));\r
+ \r
+ /* Clear the flags */\r
+ TIMx->SR = (uint16_t)~TIM_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the TIM interrupt has occurred or not.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @param TIM_IT: specifies the TIM interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_IT_Update: TIM update Interrupt source\r
+ * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source\r
+ * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source\r
+ * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source\r
+ * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source\r
+ * @arg TIM_IT_Trigger: TIM Trigger Interrupt source\r
+ * @note\r
+ * - TIM6 and TIM7 can generate only an update interrupt.\r
+ * - TIM9 can have only update interrupt, TIM_FLAG_CC1 or TIM_FLAG_CC2,\r
+ * interrupt and TIM_IT_Trigger interrupt.\r
+ * - TIM10 and TIM11 can have only update interrupt or TIM_FLAG_CC1\r
+ * interrupt \r
+ * @retval The new state of the TIM_IT(SET or RESET).\r
+ */\r
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)\r
+{\r
+ ITStatus bitstatus = RESET; \r
+ uint16_t itstatus = 0x0, itenable = 0x0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_GET_IT(TIM_IT));\r
+ \r
+ itstatus = TIMx->SR & TIM_IT;\r
+ \r
+ itenable = TIMx->DIER & TIM_IT;\r
+ if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the TIMx's interrupt pending bits.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @param TIM_IT: specifies the pending bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg TIM_IT_Update: TIM update Interrupt source\r
+ * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source\r
+ * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source\r
+ * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source\r
+ * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source\r
+ * @arg TIM_IT_Trigger: TIM Trigger Interrupt source\r
+ * @note\r
+ * - TIM6 and TIM7 can generate only an update interrupt.\r
+ * - TIM9 can have only update interrupt, TIM_IT_CC1 or TIM_IT_CC2,\r
+ * and TIM_IT_Trigger interrupt. \r
+ * - TIM10 and TIM11 can have only update interrupt or TIM_IT_CC1\r
+ * interrupt \r
+ * @retval None\r
+ */\r
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IT(TIM_IT));\r
+ \r
+ /* Clear the IT pending Bit */\r
+ TIMx->SR = (uint16_t)~TIM_IT;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx\92s DMA interface.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_DMABase: DMA Base address.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR,\r
+ * TIM_DMABase_DIER, TIM_DMABase_SR, TIM_DMABase_EGR,\r
+ * TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,\r
+ * TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,\r
+ * TIM_DMABase_CCR1, TIM_DMABase_CCR2, TIM_DMABase_CCR3, \r
+ * TIM_DMABase_CCR4, TIM_DMABase_DCR.\r
+ * @param TIM_DMABurstLength: DMA Burst length.\r
+ * This parameter can be one value between:\r
+ * TIM_DMABurstLength_1Byte and TIM_DMABurstLength_18Bytes.\r
+ * @retval None\r
+ */\r
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); \r
+ assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));\r
+ /* Set the DMA Base and the DMA Burst Length */\r
+ TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIMx\92s DMA Requests.\r
+ * @param TIMx: where x can be 2, 3, 4, 6 or 7 to select the TIM peripheral. \r
+ * @param TIM_DMASource: specifies the DMA Request sources.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg TIM_DMA_Update: TIM update Interrupt source\r
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source\r
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source\r
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source\r
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source\r
+ * @arg TIM_DMA_Trigger: TIM Trigger DMA source\r
+ * @param NewState: new state of the DMA Request sources.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));\r
+ assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the DMA sources */\r
+ TIMx->DIER |= TIM_DMASource; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the DMA sources */\r
+ TIMx->DIER &= (uint16_t)~TIM_DMASource;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIMx peripheral Capture Compare DMA source.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param NewState: new state of the Capture Compare DMA source\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the CCDS Bit */\r
+ TIMx->CR2 |= TIM_CR2_CCDS;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the CCDS Bit */\r
+ TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Group5 Clocks management functions\r
+ * @brief Clocks management functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Clocks management functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the TIMx internal Clock\r
+ * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ /* Disable slave mode to clock the prescaler directly with the internal clock */\r
+ TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Internal Trigger as External Clock\r
+ * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+ * @param TIM_ITRSource: Trigger source.\r
+ * This parameter can be one of the following values:\r
+ * @param TIM_TS_ITR0: Internal Trigger 0\r
+ * @param TIM_TS_ITR1: Internal Trigger 1\r
+ * @param TIM_TS_ITR2: Internal Trigger 2\r
+ * @param TIM_TS_ITR3: Internal Trigger 3\r
+ * @retval None\r
+ */\r
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));\r
+ /* Select the Internal Trigger */\r
+ TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);\r
+ /* Select the External clock mode1 */\r
+ TIMx->SMCR |= TIM_SlaveMode_External1;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Trigger as External Clock\r
+ * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+ * @param TIM_TIxExternalCLKSource: Trigger source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector\r
+ * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1\r
+ * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2\r
+ * @param TIM_ICPolarity: specifies the TIx Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising\r
+ * @arg TIM_ICPolarity_Falling\r
+ * @param ICFilter : specifies the filter value.\r
+ * This parameter must be a value between 0x0 and 0xF.\r
+ * @retval None\r
+ */\r
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,\r
+ uint16_t TIM_ICPolarity, uint16_t ICFilter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));\r
+ assert_param(IS_TIM_IC_FILTER(ICFilter));\r
+ \r
+ /* Configure the Timer Input Clock Source */\r
+ if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)\r
+ {\r
+ TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);\r
+ }\r
+ else\r
+ {\r
+ TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);\r
+ }\r
+ /* Select the Trigger source */\r
+ TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);\r
+ /* Select the External clock mode1 */\r
+ TIMx->SMCR |= TIM_SlaveMode_External1;\r
+}\r
+\r
+/**\r
+ * @brief Configures the External clock Mode1\r
+ * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+ * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.\r
+ * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.\r
+ * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.\r
+ * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.\r
+ * @param TIM_ExtTRGPolarity: The external Trigger Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.\r
+ * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.\r
+ * @param ExtTRGFilter: External Trigger Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F\r
+ * @retval None\r
+ */\r
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
+ uint16_t ExtTRGFilter)\r
+{\r
+ uint16_t tmpsmcr = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));\r
+ assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));\r
+ assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));\r
+ \r
+ /* Configure the ETR Clock source */\r
+ TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);\r
+ \r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = TIMx->SMCR;\r
+ /* Reset the SMS Bits */\r
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));\r
+ /* Select the External clock mode1 */\r
+ tmpsmcr |= TIM_SlaveMode_External1;\r
+ /* Select the Trigger selection : ETRF */\r
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));\r
+ tmpsmcr |= TIM_TS_ETRF;\r
+ /* Write to TIMx SMCR */\r
+ TIMx->SMCR = tmpsmcr;\r
+}\r
+\r
+/**\r
+ * @brief Configures the External clock Mode2\r
+ * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.\r
+ * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.\r
+ * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.\r
+ * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.\r
+ * @param TIM_ExtTRGPolarity: The external Trigger Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.\r
+ * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.\r
+ * @param ExtTRGFilter: External Trigger Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F\r
+ * @retval None\r
+ */\r
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, \r
+ uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));\r
+ assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));\r
+ assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));\r
+ \r
+ /* Configure the ETR Clock source */\r
+ TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);\r
+ /* Enable the External clock mode2 */\r
+ TIMx->SMCR |= TIM_SMCR_ECE;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Group6 Synchronization management functions\r
+ * @brief Synchronization management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Synchronization management functions\r
+ =============================================================================== \r
+ \r
+ =================================================================== \r
+ TIM Driver: how to use it in synchronization Mode\r
+ =================================================================== \r
+ Case of two/several Timers\r
+ **************************\r
+ 1. Configure the Master Timers using the following functions:\r
+ - void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); \r
+ - void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); \r
+ 2. Configure the Slave Timers using the following functions: \r
+ - void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); \r
+ - void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); \r
+ \r
+ Case of Timers and external trigger(ETR pin)\r
+ ******************************************** \r
+ 1. Configure the Etrenal trigger using this function:\r
+ - void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
+ uint16_t ExtTRGFilter);\r
+ 2. Configure the Slave Timers using the following functions: \r
+ - void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); \r
+ - void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Selects the Input Trigger source\r
+ * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+ * @param TIM_InputTriggerSource: The Input Trigger source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_TS_ITR0: Internal Trigger 0\r
+ * @arg TIM_TS_ITR1: Internal Trigger 1\r
+ * @arg TIM_TS_ITR2: Internal Trigger 2\r
+ * @arg TIM_TS_ITR3: Internal Trigger 3\r
+ * @arg TIM_TS_TI1F_ED: TI1 Edge Detector\r
+ * @arg TIM_TS_TI1FP1: Filtered Timer Input 1\r
+ * @arg TIM_TS_TI2FP2: Filtered Timer Input 2\r
+ * @arg TIM_TS_ETRF: External Trigger input\r
+ * @retval None\r
+ */\r
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)\r
+{\r
+ uint16_t tmpsmcr = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); \r
+ assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));\r
+\r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = TIMx->SMCR;\r
+ /* Reset the TS Bits */\r
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));\r
+ /* Set the Input Trigger source */\r
+ tmpsmcr |= TIM_InputTriggerSource;\r
+ /* Write to TIMx SMCR */\r
+ TIMx->SMCR = tmpsmcr;\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIMx Trigger Output Mode.\r
+ * @param TIMx: where x can be 2, 3, 4, 6, 7 or 9 to select the TIM peripheral.\r
+ * @param TIM_TRGOSource: specifies the Trigger Output source.\r
+ * This paramter can be one of the following values:\r
+ *\r
+ * - For all TIMx\r
+ * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO).\r
+ * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).\r
+ * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).\r
+ *\r
+ * - For all TIMx except TIM6 and TIM7\r
+ * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag\r
+ * is to be set, as soon as a capture or compare match occurs (TRGO).\r
+ * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).\r
+\r
+ * - For all TIMx except TIM6, TIM7, TIM10 and TIM11\r
+ * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).\r
+\r
+ * - For TIM2, TIM3 and TIM4\r
+ * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).\r
+ * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).\r
+ *\r
+ * @retval None\r
+ */\r
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST5_PERIPH(TIMx));\r
+ assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));\r
+\r
+ /* Reset the MMS Bits */\r
+ TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS);\r
+ /* Select the TRGO source */\r
+ TIMx->CR2 |= TIM_TRGOSource;\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIMx Slave Mode.\r
+ * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+ * @param TIM_SlaveMode: specifies the Timer Slave Mode.\r
+ * This paramter can be one of the following values:\r
+ * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes\r
+ * the counter and triggers an update of the registers.\r
+ * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high.\r
+ * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI.\r
+ * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.\r
+ * @retval None\r
+ */\r
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); \r
+ assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));\r
+ \r
+ /* Reset the SMS Bits */\r
+ TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS);\r
+ /* Select the Slave Mode */\r
+ TIMx->SMCR |= TIM_SlaveMode;\r
+}\r
+\r
+/**\r
+ * @brief Sets or Resets the TIMx Master/Slave Mode.\r
+ * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+ * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.\r
+ * This paramter can be one of the following values:\r
+ * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer\r
+ * and its slaves (through TRGO).\r
+ * @arg TIM_MasterSlaveMode_Disable: No action\r
+ * @retval None\r
+ */\r
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));\r
+ \r
+ /* Reset the MSM Bit */\r
+ TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM);\r
+ \r
+ /* Set or Reset the MSM Bit */\r
+ TIMx->SMCR |= TIM_MasterSlaveMode;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx External Trigger (ETR).\r
+ * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.\r
+ * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.\r
+ * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.\r
+ * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.\r
+ * @param TIM_ExtTRGPolarity: The external Trigger Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.\r
+ * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.\r
+ * @param ExtTRGFilter: External Trigger Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F\r
+ * @retval None\r
+ */\r
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
+ uint16_t ExtTRGFilter)\r
+{\r
+ uint16_t tmpsmcr = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));\r
+ assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));\r
+ assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));\r
+ \r
+ tmpsmcr = TIMx->SMCR;\r
+ /* Reset the ETR Bits */\r
+ tmpsmcr &= SMCR_ETR_MASK;\r
+ /* Set the Prescaler, the Filter value and the Polarity */\r
+ tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));\r
+ /* Write to TIMx SMCR */\r
+ TIMx->SMCR = tmpsmcr;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Group7 Specific interface management functions\r
+ * @brief Specific interface management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Specific interface management functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the TIMx Encoder Interface.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_EncoderMode: specifies the TIMx Encoder Mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.\r
+ * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.\r
+ * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending\r
+ * on the level of the other input.\r
+ * @param TIM_IC1Polarity: specifies the IC1 Polarity\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Falling: IC Falling edge.\r
+ * @arg TIM_ICPolarity_Rising: IC Rising edge.\r
+ * @param TIM_IC2Polarity: specifies the IC2 Polarity\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Falling: IC Falling edge.\r
+ * @arg TIM_ICPolarity_Rising: IC Rising edge.\r
+ * @retval None\r
+ */\r
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,\r
+ uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)\r
+{\r
+ uint16_t tmpsmcr = 0;\r
+ uint16_t tmpccmr1 = 0;\r
+ uint16_t tmpccer = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));\r
+ assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));\r
+ assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));\r
+ \r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = TIMx->SMCR;\r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ /* Set the encoder Mode */\r
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));\r
+ tmpsmcr |= TIM_EncoderMode;\r
+ /* Select the Capture Compare 1 and the Capture Compare 2 as input */\r
+ tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)));\r
+ tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;\r
+ /* Set the TI1 and the TI2 Polarities */\r
+ tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P)));\r
+ tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));\r
+ /* Write to TIMx SMCR */\r
+ TIMx->SMCR = tmpsmcr;\r
+ /* Write to TIMx CCMR1 */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIMx\92s Hall sensor interface.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param NewState: new state of the TIMx Hall sensor interface.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the TI1S Bit */\r
+ TIMx->CR2 |= TIM_CR2_TI1S;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the TI1S Bit */\r
+ TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Group8 Specific remapping management function\r
+ * @brief Specific remapping management function\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Specific remapping management function\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the TIM9, TIM10 and TIM11 Remapping input Capabilities.\r
+ * @param TIMx: where x can be 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_Remap: specifies the TIM input remapping source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM9_GPIO: TIM9 Channel 1 is connected to dedicated Timer pin(default)\r
+ * @arg TIM9_LSE: TIM9 Channel 1 is connected to LSE clock.\r
+ * @arg TIM10_GPIO: TIM10 Channel 1 is connected to dedicated Timer pin(default) \r
+ * @arg TIM10_LSI: TIM10 Channel 1 is connected to LSI clock.\r
+ * @arg TIM10_LSE: TIM10 Channel 1 is connected to LSE clock.\r
+ * @arg TIM10_RTC: TIM10 Channel 1 is connected to RTC Output event. \r
+ * @arg TIM11_GPIO: TIM11 Channel 1 is connected to dedicated Timer pin(default) \r
+ * @arg TIM11_MSI: TIM11 Channel 1 is connected to MSI clock.\r
+ * @arg TIM11_HSE_RTC: TIM11 Channel 1 is connected to HSE_RTC clock. \r
+ * @retval None\r
+ */\r
+void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ assert_param(IS_TIM_REMAP(TIM_Remap));\r
+\r
+ /* Set the Timer remapping configuration */\r
+ TIMx->OR = TIM_Remap;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief Configure the TI1 as Input.\r
+ * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_ICPolarity : The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising\r
+ * @arg TIM_ICPolarity_Falling\r
+ * @param TIM_ICSelection: specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.\r
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.\r
+ * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter)\r
+{\r
+ uint16_t tmpccmr1 = 0, tmpccer = 0;\r
+ \r
+ /* Disable the Channel 1: Reset the CC1E Bit */\r
+ TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E);\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ tmpccer = TIMx->CCER;\r
+ /* Select the Input and set the filter */\r
+ tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F)));\r
+ tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));\r
+ /* Select the Polarity and set the CC1E Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP));\r
+ tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);\r
+ /* Write to TIMx CCMR1 and CCER registers */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI2 as Input.\r
+ * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+ * @param TIM_ICPolarity : The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising\r
+ * @arg TIM_ICPolarity_Falling\r
+ * @param TIM_ICSelection: specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.\r
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.\r
+ * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter)\r
+{\r
+ uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;\r
+ \r
+ /* Disable the Channel 2: Reset the CC2E Bit */\r
+ TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E);\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ tmpccer = TIMx->CCER;\r
+ tmp = (uint16_t)(TIM_ICPolarity << 4);\r
+ /* Select the Input and set the filter */\r
+ tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F)));\r
+ tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);\r
+ tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);\r
+ /* Select the Polarity and set the CC2E Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP));\r
+ tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);\r
+ /* Write to TIMx CCMR1 and CCER registers */\r
+ TIMx->CCMR1 = tmpccmr1 ;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI3 as Input.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_ICPolarity : The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising\r
+ * @arg TIM_ICPolarity_Falling\r
+ * @param TIM_ICSelection: specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.\r
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.\r
+ * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter)\r
+{\r
+ uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;\r
+ \r
+ /* Disable the Channel 3: Reset the CC3E Bit */\r
+ TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E);\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ tmpccer = TIMx->CCER;\r
+ tmp = (uint16_t)(TIM_ICPolarity << 8);\r
+ /* Select the Input and set the filter */\r
+ tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F)));\r
+ tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));\r
+ /* Select the Polarity and set the CC3E Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP));\r
+ tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);\r
+ /* Write to TIMx CCMR2 and CCER registers */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI4 as Input.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_ICPolarity : The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising\r
+ * @arg TIM_ICPolarity_Falling\r
+ * @param TIM_ICSelection: specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.\r
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.\r
+ * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter)\r
+{\r
+ uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;\r
+ \r
+ /* Disable the Channel 4: Reset the CC4E Bit */\r
+ TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E);\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ tmpccer = TIMx->CCER;\r
+ tmp = (uint16_t)(TIM_ICPolarity << 12);\r
+ /* Select the Input and set the filter */\r
+ tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F)));\r
+ tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);\r
+ tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);\r
+\r
+ /* Select the Polarity and set the CC4E Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P | TIM_CCER_CC4NP));\r
+ tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);\r
+ /* Write to TIMx CCMR2 and CCER registers */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+ TIMx->CCER = tmpccer ;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_usart.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Universal synchronous asynchronous receiver\r
+ * transmitter (USART): \r
+ * - Initialization and Configuration\r
+ * - Data transfers\r
+ * - Multi-Processor Communication\r
+ * - LIN mode\r
+ * - Half-duplex mode\r
+ * - Smartcard mode\r
+ * - IrDA mode\r
+ * - DMA transfers management\r
+ * - Interrupts and flags management \r
+ * \r
+ * @verbatim\r
+ * \r
+ * ===================================================================\r
+ * How to use this driver\r
+ * ===================================================================\r
+ * 1. Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE)\r
+ * function for USART1 or using RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE)\r
+ * function for USART2 and USART3.\r
+ *\r
+ * 2. According to the USART mode, enable the GPIO clocks using \r
+ * RCC_AHBPeriphClockCmd() function. (The I/O can be TX, RX, CTS, \r
+ * or and SCLK). \r
+ *\r
+ * 3. Peripheral\92s alternate function: \r
+ * - Connect the pin to the desired peripherals' Alternate \r
+ * Function (AF) using GPIO_PinAFConfig() function\r
+ * - Configure the desired pin in alternate function by:\r
+ * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF\r
+ * - Select the type, pull-up/pull-down and output speed via \r
+ * GPIO_PuPd, GPIO_OType and GPIO_Speed members\r
+ * - Call GPIO_Init() function\r
+ * \r
+ * 4. Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware \r
+ * flow control and Mode(Receiver/Transmitter) using the SPI_Init()\r
+ * function.\r
+ *\r
+ * 5. For synchronous mode, enable the clock and program the polarity,\r
+ * phase and last bit using the USART_ClockInit() function.\r
+ *\r
+ * 5. Enable the NVIC and the corresponding interrupt using the function \r
+ * USART_ITConfig() if you need to use interrupt mode. \r
+ *\r
+ * 6. When using the DMA mode \r
+ * - Configure the DMA using DMA_Init() function\r
+ * - Active the needed channel Request using USART_DMACmd() function\r
+ * \r
+ * 7. Enable the USART using the USART_Cmd() function.\r
+ * \r
+ * 8. Enable the DMA using the DMA_Cmd() function, when using DMA mode. \r
+ *\r
+ * Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections\r
+ * for more details\r
+ * \r
+ * @endverbatim\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_usart.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup USART \r
+ * @brief USART driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+\r
+/*!< USART CR1 register clear Mask ((~(uint16_t)0xE9F3)) */\r
+#define CR1_CLEAR_MASK ((uint16_t)(USART_CR1_M | USART_CR1_PCE | \\r
+ USART_CR1_PS | USART_CR1_TE | \\r
+ USART_CR1_RE))\r
+\r
+/*!< USART CR2 register clock bits clear Mask ((~(uint16_t)0xF0FF)) */\r
+#define CR2_CLOCK_CLEAR_MASK ((uint16_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \\r
+ USART_CR2_CPHA | USART_CR2_LBCL))\r
+\r
+/*!< USART CR3 register clear Mask ((~(uint16_t)0xFCFF)) */\r
+#define CR3_CLEAR_MASK ((uint16_t)(USART_CR3_RTSE | USART_CR3_CTSE))\r
+\r
+/*!< USART Interrupts mask */\r
+#define IT_MASK ((uint16_t)0x001F)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup USART_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup USART_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Initialization and Configuration functions\r
+ =============================================================================== \r
+\r
+ This subsection provides a set of functions allowing to initialize the USART \r
+ in asynchronous and in synchronous modes.\r
+ - For the asynchronous mode only these parameters can be configured: \r
+ - Baud Rate\r
+ - Word Length \r
+ - Stop Bit\r
+ - Parity: If the parity is enabled, then the MSB bit of the data written\r
+ in the data register is transmitted but is changed by the parity bit.\r
+ Depending on the frame length defined by the M bit (8-bits or 9-bits),\r
+ the possible USART frame formats are as listed in the following table:\r
+ +-------------------------------------------------------------+ \r
+ | M bit | PCE bit | USART frame |\r
+ |---------------------|---------------------------------------| \r
+ | 0 | 0 | | SB | 8 bit data | STB | |\r
+ |---------|-----------|---------------------------------------| \r
+ | 0 | 1 | | SB | 7 bit data | PB | STB | |\r
+ |---------|-----------|---------------------------------------| \r
+ | 1 | 0 | | SB | 9 bit data | STB | |\r
+ |---------|-----------|---------------------------------------| \r
+ | 1 | 1 | | SB | 8 bit data | PB | STB | |\r
+ +-------------------------------------------------------------+ \r
+ - Hardware flow control\r
+ - Receiver/transmitter modes\r
+\r
+ The USART_Init() function follows the USART asynchronous configuration procedure\r
+ (details for the procedure are available in reference manual (RM0038)).\r
+\r
+ - For the synchronous mode in addition to the asynchronous mode parameters these \r
+ parameters should be also configured:\r
+ - USART Clock Enabled\r
+ - USART polarity\r
+ - USART phase\r
+ - USART LastBit\r
+ \r
+ These parameters can be configured using the USART_ClockInit() function.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Deinitializes the USARTx peripheral registers to their default reset values.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values: USART1, USART2 or USART3.\r
+ * @retval None\r
+ */\r
+void USART_DeInit(USART_TypeDef* USARTx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+\r
+ if (USARTx == USART1)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);\r
+ }\r
+ else if (USARTx == USART2)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);\r
+ }\r
+ else \r
+ {\r
+ if (USARTx == USART3)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); \r
+ }\r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Initializes the USARTx peripheral according to the specified\r
+ * parameters in the USART_InitStruct .\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param USART_InitStruct: pointer to a USART_InitTypeDef structure\r
+ * that contains the configuration information for the specified USART peripheral.\r
+ * @retval None\r
+ */\r
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)\r
+{\r
+ uint32_t tmpreg = 0x00, apbclock = 0x00;\r
+ uint32_t integerdivider = 0x00;\r
+ uint32_t fractionaldivider = 0x00;\r
+ RCC_ClocksTypeDef RCC_ClocksStatus;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); \r
+ assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));\r
+ assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));\r
+ assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));\r
+ assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));\r
+ assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));\r
+ \r
+/*---------------------------- USART CR2 Configuration -----------------------*/\r
+ tmpreg = USARTx->CR2;\r
+ /* Clear STOP[13:12] bits */\r
+ tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP);\r
+\r
+ /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/\r
+ /* Set STOP[13:12] bits according to USART_StopBits value */\r
+ tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;\r
+ \r
+ /* Write to USART CR2 */\r
+ USARTx->CR2 = (uint16_t)tmpreg;\r
+\r
+/*---------------------------- USART CR1 Configuration -----------------------*/\r
+ tmpreg = USARTx->CR1;\r
+ /* Clear M, PCE, PS, TE and RE bits */\r
+ tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK);\r
+\r
+ /* Configure the USART Word Length, Parity and mode ----------------------- */\r
+ /* Set the M bits according to USART_WordLength value */\r
+ /* Set PCE and PS bits according to USART_Parity value */\r
+ /* Set TE and RE bits according to USART_Mode value */\r
+ tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |\r
+ USART_InitStruct->USART_Mode;\r
+\r
+ /* Write to USART CR1 */\r
+ USARTx->CR1 = (uint16_t)tmpreg;\r
+\r
+/*---------------------------- USART CR3 Configuration -----------------------*/ \r
+ tmpreg = USARTx->CR3;\r
+ /* Clear CTSE and RTSE bits */\r
+ tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK);\r
+\r
+ /* Configure the USART HFC -------------------------------------------------*/\r
+ /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */\r
+ tmpreg |= USART_InitStruct->USART_HardwareFlowControl;\r
+\r
+ /* Write to USART CR3 */\r
+ USARTx->CR3 = (uint16_t)tmpreg;\r
+\r
+/*---------------------------- USART BRR Configuration -----------------------*/\r
+ /* Configure the USART Baud Rate -------------------------------------------*/\r
+ RCC_GetClocksFreq(&RCC_ClocksStatus);\r
+ if (USARTx == USART1) \r
+ {\r
+ apbclock = RCC_ClocksStatus.PCLK2_Frequency;\r
+ }\r
+ else\r
+ {\r
+ apbclock = RCC_ClocksStatus.PCLK1_Frequency;\r
+ }\r
+\r
+ /* Determine the integer part */\r
+ if ((USARTx->CR1 & USART_CR1_OVER8) != 0)\r
+ {\r
+ /* Integer part computing in case Oversampling mode is 8 Samples */\r
+ integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); \r
+ }\r
+ else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */\r
+ {\r
+ /* Integer part computing in case Oversampling mode is 16 Samples */\r
+ integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); \r
+ }\r
+ tmpreg = (integerdivider / 100) << 4;\r
+\r
+ /* Determine the fractional part */\r
+ fractionaldivider = integerdivider - (100 * (tmpreg >> 4));\r
+\r
+ /* Implement the fractional part in the register */\r
+ if ((USARTx->CR1 & USART_CR1_OVER8) != 0)\r
+ {\r
+ tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);\r
+ }\r
+ else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */\r
+ {\r
+ tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);\r
+ }\r
+ \r
+ /* Write to USART BRR */\r
+ USARTx->BRR = (uint16_t)tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Fills each USART_InitStruct member with its default value.\r
+ * @param USART_InitStruct: pointer to a USART_InitTypeDef structure\r
+ * which will be initialized.\r
+ * @retval None\r
+ */\r
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct)\r
+{\r
+ /* USART_InitStruct members default value */\r
+ USART_InitStruct->USART_BaudRate = 9600;\r
+ USART_InitStruct->USART_WordLength = USART_WordLength_8b;\r
+ USART_InitStruct->USART_StopBits = USART_StopBits_1;\r
+ USART_InitStruct->USART_Parity = USART_Parity_No ;\r
+ USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;\r
+ USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; \r
+}\r
+\r
+/**\r
+ * @brief Initializes the USARTx peripheral Clock according to the \r
+ * specified parameters in the USART_ClockInitStruct .\r
+ * @param USARTx: where x can be 1, 2, 3 to select the USART peripheral.\r
+ * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef\r
+ * structure that contains the configuration information for the specified \r
+ * USART peripheral. \r
+ * @retval None\r
+ */\r
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)\r
+{\r
+ uint32_t tmpreg = 0x00;\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));\r
+ assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));\r
+ assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));\r
+ assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));\r
+ \r
+/*---------------------------- USART CR2 Configuration -----------------------*/\r
+ tmpreg = USARTx->CR2;\r
+ /* Clear CLKEN, CPOL, CPHA and LBCL bits */\r
+ tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK);\r
+ /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/\r
+ /* Set CLKEN bit according to USART_Clock value */\r
+ /* Set CPOL bit according to USART_CPOL value */\r
+ /* Set CPHA bit according to USART_CPHA value */\r
+ /* Set LBCL bit according to USART_LastBit value */\r
+ tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | \r
+ USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;\r
+ /* Write to USART CR2 */\r
+ USARTx->CR2 = (uint16_t)tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Fills each USART_ClockInitStruct member with its default value.\r
+ * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef\r
+ * structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)\r
+{\r
+ /* USART_ClockInitStruct members default value */\r
+ USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;\r
+ USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;\r
+ USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;\r
+ USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified USART peripheral.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param NewState: new state of the USARTx peripheral.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected USART by setting the UE bit in the CR1 register */\r
+ USARTx->CR1 |= USART_CR1_UE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected USART by clearing the UE bit in the CR1 register */\r
+ USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_UE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sets the system clock prescaler.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param USART_Prescaler: specifies the prescaler clock. \r
+ * @retval None\r
+ */\r
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ \r
+ /* Clear the USART prescaler */\r
+ USARTx->GTPR &= USART_GTPR_GT;\r
+ /* Set the USART prescaler */\r
+ USARTx->GTPR |= USART_Prescaler;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the USART's 8x oversampling mode.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3.\r
+ * @param NewState: new state of the USART 8x oversampling mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ *\r
+ * @note\r
+ * This function has to be called before calling USART_Init()\r
+ * function in order to have correct baudrate Divider value.\r
+ * @retval : None\r
+ */\r
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */\r
+ USARTx->CR1 |= USART_CR1_OVER8;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */\r
+ USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_OVER8);\r
+ }\r
+} \r
+\r
+/**\r
+ * @brief Enables or disables the USART's one bit sampling method.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3.\r
+ * @param NewState: new state of the USART one bit sampling method.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval : None\r
+ */\r
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */\r
+ USARTx->CR3 |= USART_CR3_ONEBIT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the one bit method by clearing the ONEBITE bit in the CR3 register */\r
+ USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Group2 Data transfers functions\r
+ * @brief Data transfers functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Data transfers functions\r
+ =============================================================================== \r
+\r
+ This subsection provides a set of functions allowing to manage the USART data \r
+ transfers.\r
+ \r
+ During an USART reception, data shifts in least significant bit first through \r
+ the RX pin. In this mode, the USART_DR register consists of a buffer (RDR) \r
+ between the internal bus and the received shift register.\r
+\r
+ When a transmission is taking place, a write instruction to the USART_DR register \r
+ stores the data in the TDR register and which is copied in the shift register \r
+ at the end of the current transmission.\r
+\r
+ The read access of the USART_DR register can be done using the USART_ReceiveData()\r
+ function and returns the RDR buffered value. Whereas a write access to the USART_DR \r
+ can be done using USART_SendData() function and stores the written data into \r
+ TDR buffer.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Transmits single data through the USARTx peripheral.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param Data: the data to transmit.\r
+ * @retval None\r
+ */\r
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_DATA(Data)); \r
+ \r
+ /* Transmit Data */\r
+ USARTx->DR = (Data & (uint16_t)0x01FF);\r
+}\r
+\r
+/**\r
+ * @brief Returns the most recent received data by the USARTx peripheral.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @retval The received data.\r
+ */\r
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ \r
+ /* Receive Data */\r
+ return (uint16_t)(USARTx->DR & (uint16_t)0x01FF);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Group3 MultiProcessor Communication functions\r
+ * @brief Multi-Processor Communication functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Multi-Processor Communication functions\r
+ =============================================================================== \r
+\r
+ This subsection provides a set of functions allowing to manage the USART \r
+ multiprocessor communication.\r
+ \r
+ For instance one of the USARTs can be the master, its TX output is connected to \r
+ the RX input of the other USART. The others are slaves, their respective TX outputs \r
+ are logically ANDed together and connected to the RX input of the master.\r
+\r
+ USART multiprocessor communication is possible through the following procedure:\r
+ 1. Program the Baud rate, Word length = 9 bits, Stop bits, Parity, Mode transmitter \r
+ or Mode receiver and hardware flow control values using the USART_Init()\r
+ function.\r
+ 2. Configures the USART address using the USART_SetAddress() function.\r
+ 3. Configures the wake up methode (USART_WakeUp_IdleLine or USART_WakeUp_AddressMark)\r
+ using USART_WakeUpConfig() function only for the slaves.\r
+ 4. Enable the USART using the USART_Cmd() function.\r
+ 5. Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() function.\r
+\r
+ The USART Slave exit from mute mode when receive the wake up condition.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sets the address of the USART node.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param USART_Address: Indicates the address of the USART node.\r
+ * @retval None\r
+ */\r
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_ADDRESS(USART_Address)); \r
+ \r
+ /* Clear the USART address */\r
+ USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_ADD);\r
+ /* Set the USART address node */\r
+ USARTx->CR2 |= USART_Address;\r
+}\r
+\r
+/**\r
+ * @brief Determines if the USART is in mute mode or not.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param NewState: new state of the USART mute mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the USART mute mode by setting the RWU bit in the CR1 register */\r
+ USARTx->CR1 |= USART_CR1_RWU;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */\r
+ USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_RWU);\r
+ }\r
+}\r
+/**\r
+ * @brief Selects the USART WakeUp method.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param USART_WakeUp: specifies the USART wakeup method.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection\r
+ * @arg USART_WakeUp_AddressMark: WakeUp by an address mark\r
+ * @retval None\r
+ */\r
+void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_WAKEUP(USART_WakeUp));\r
+ \r
+ USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_WAKE);\r
+ USARTx->CR1 |= USART_WakeUp;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Group4 LIN mode functions\r
+ * @brief LIN mode functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ LIN mode functions\r
+ =============================================================================== \r
+\r
+ This subsection provides a set of functions allowing to manage the USART LIN \r
+ Mode communication.\r
+ \r
+ In LIN mode, 8-bit data format with 1 stop bit is required in accordance with \r
+ the LIN standard.\r
+\r
+ Only this LIN Feature is supported by the USART IP:\r
+ - LIN Master Synchronous Break send capability and LIN slave break detection\r
+ capability : 13-bit break generation and 10/11 bit break detection\r
+\r
+\r
+ USART LIN Master transmitter communication is possible through the following procedure:\r
+ 1. Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, \r
+ Mode transmitter or Mode receiver and hardware flow control values using \r
+ the USART_Init() function.\r
+ 2. Enable the USART using the USART_Cmd() function.\r
+ 3. Enable the LIN mode using the USART_LINCmd() function.\r
+ 4. Send the break character using USART_SendBreak() function.\r
+\r
+ USART LIN Master receiver communication is possible through the following procedure:\r
+ 1. Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, \r
+ Mode transmitter or Mode receiver and hardware flow control values using \r
+ the USART_Init() function.\r
+ 2. Enable the USART using the USART_Cmd() function.\r
+ 3. Configures the break detection length using the USART_LINBreakDetectLengthConfig()\r
+ function.\r
+ 4. Enable the LIN mode using the USART_LINCmd() function.\r
+\r
+Note:\r
+----\r
+ 1. In LIN mode, the following bits must be kept cleared:\r
+ - CLKEN in the USART_CR2 register,\r
+ - STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sets the USART LIN Break detection length.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param USART_LINBreakDetectLength: specifies the LIN break detection length.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_LINBreakDetectLength_10b: 10-bit break detection\r
+ * @arg USART_LINBreakDetectLength_11b: 11-bit break detection\r
+ * @retval None\r
+ */\r
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));\r
+ \r
+ USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LBDL);\r
+ USARTx->CR2 |= USART_LINBreakDetectLength; \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the USART\92s LIN mode.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param NewState: new state of the USART LIN mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the LIN mode by setting the LINEN bit in the CR2 register */\r
+ USARTx->CR2 |= USART_CR2_LINEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */\r
+ USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LINEN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Transmits break characters.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @retval None\r
+ */\r
+void USART_SendBreak(USART_TypeDef* USARTx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ \r
+ /* Send break characters */\r
+ USARTx->CR1 |= USART_CR1_SBK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Group5 Halfduplex mode function\r
+ * @brief Half-duplex mode function \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Half-duplex mode function\r
+ =============================================================================== \r
+\r
+ This subsection provides a set of functions allowing to manage the USART \r
+ Half-duplex communication.\r
+ \r
+ The USART can be configured to follow a single-wire half-duplex protocol where \r
+ the TX and RX lines are internally connected.\r
+\r
+ USART Half duplex communication is possible through the following procedure:\r
+ 1. Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter \r
+ or Mode receiver and hardware flow control values using the USART_Init()\r
+ function.\r
+ 2. Configures the USART address using the USART_SetAddress() function.\r
+ 3. Enable the USART using the USART_Cmd() function.\r
+ 4. Enable the half duplex mode using USART_HalfDuplexCmd() function.\r
+\r
+Note:\r
+----\r
+ 1. The RX pin is no longer used\r
+ 2. In Half-duplex mode the following bits must be kept cleared:\r
+ - LINEN and CLKEN bits in the USART_CR2 register.\r
+ - SCEN and IREN bits in the USART_CR3 register.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the USART\92s Half Duplex communication.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param NewState: new state of the USART Communication.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */\r
+ USARTx->CR3 |= USART_CR3_HDSEL;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */\r
+ USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_HDSEL);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup USART_Group6 Smartcard mode functions\r
+ * @brief Smartcard mode functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Smartcard mode functions\r
+ =============================================================================== \r
+\r
+ This subsection provides a set of functions allowing to manage the USART \r
+ Smartcard communication.\r
+ \r
+ The Smartcard interface is designed to support asynchronous protocol Smartcards as\r
+ defined in the ISO 7816-3 standard.\r
+\r
+ The USART can provide a clock to the smartcard through the SCLK output.\r
+ In smartcard mode, SCLK is not associated to the communication but is simply derived \r
+ from the internal peripheral input clock through a 5-bit prescaler.\r
+\r
+ Smartcard communication is possible through the following procedure:\r
+ 1. Configures the Smartcard Prsecaler using the USART_SetPrescaler() function.\r
+ 2. Configures the Smartcard Guard Time using the USART_SetGuardTime() function.\r
+ 3. Program the USART clock using the USART_ClockInit() function as following:\r
+ - USART Clock enabled\r
+ - USART CPOL Low\r
+ - USART CPHA on first edge\r
+ - USART Last Bit Clock Enabled\r
+ 4. Program the Smartcard interface using the USART_Init() function as following:\r
+ - Word Length = 9 Bits\r
+ - 1.5 Stop Bit\r
+ - Even parity\r
+ - BaudRate = 12096 baud\r
+ - Hardware flow control disabled (RTS and CTS signals)\r
+ - Tx and Rx enabled\r
+ 5. Optionally you can enable the parity error interrupt using the USART_ITConfig()\r
+ function\r
+ 6. Enable the USART using the USART_Cmd() function.\r
+ 7. Enable the Smartcard NACK using the USART_SmartCardNACKCmd() function.\r
+ 8. Enable the Smartcard interface using the USART_SmartCardCmd() function.\r
+\r
+ Please refer to the ISO 7816-3 specification for more details.\r
+\r
+Note: \r
+-----\r
+ 1. It is also possible to choose 0.5 stop bit for receiving but it is recommended \r
+ to use 1.5 stop bits for both transmitting and receiving to avoid switching \r
+ between the two configurations.\r
+ 2. In smartcard mode, the following bits must be kept cleared:\r
+ - LINEN bit in the USART_CR2 register.\r
+ - HDSEL and IREN bits in the USART_CR3 register.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sets the specified USART guard time.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param USART_GuardTime: specifies the guard time. \r
+ * @retval None\r
+ */\r
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ \r
+ /* Clear the USART Guard time */\r
+ USARTx->GTPR &= USART_GTPR_PSC;\r
+ /* Set the USART guard time */\r
+ USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the USART\92s Smart Card mode.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param NewState: new state of the Smart Card mode.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @retval None\r
+ */\r
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the SC mode by setting the SCEN bit in the CR3 register */\r
+ USARTx->CR3 |= USART_CR3_SCEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the SC mode by clearing the SCEN bit in the CR3 register */\r
+ USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_SCEN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables NACK transmission.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param NewState: new state of the NACK transmission.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @retval None\r
+ */\r
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the NACK transmission by setting the NACK bit in the CR3 register */\r
+ USARTx->CR3 |= USART_CR3_NACK;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */\r
+ USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_NACK);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Group7 IrDA mode functions\r
+ * @brief IrDA mode functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ IrDA mode functions\r
+ =============================================================================== \r
+\r
+ This subsection provides a set of functions allowing to manage the USART \r
+ IrDA communication.\r
+ \r
+ IrDA is a half duplex communication protocol. If the Transmitter is busy, any data\r
+ on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver \r
+ is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.\r
+ While receiving data, transmission should be avoided as the data to be transmitted\r
+ could be corrupted.\r
+\r
+ IrDA communication is possible through the following procedure:\r
+ 1. Program the Baud rate, Word length = 8 bits, Stop bits, Parity, Transmitter/Receiver \r
+ modes and hardware flow control values using the USART_Init() function.\r
+ 2. Enable the USART using the USART_Cmd() function.\r
+ 3. Configures the IrDA pulse width by configuring the prescaler using \r
+ the USART_SetPrescaler() function.\r
+ 4. Configures the IrDA USART_IrDAMode_LowPower or USART_IrDAMode_Normal mode\r
+ using the USART_IrDAConfig() function.\r
+ 5. Enable the IrDA using the USART_IrDACmd() function.\r
+\r
+Note: \r
+-----\r
+ 1. A pulse of width less than two and greater than one PSC period(s) may or may\r
+ not be rejected.\r
+ 2. The receiver set up time should be managed by software. The IrDA physical layer\r
+ specification specifies a minimum of 10 ms delay between transmission and \r
+ reception (IrDA is a half duplex protocol).\r
+ 3. In IrDA mode, the following bits must be kept cleared:\r
+ - LINEN, STOP and CLKEN bits in the USART_CR2 register.\r
+ - SCEN and HDSEL bits in the USART_CR3 register.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the USART\92s IrDA interface.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param USART_IrDAMode: specifies the IrDA mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_IrDAMode_LowPower\r
+ * @arg USART_IrDAMode_Normal\r
+ * @retval None\r
+ */\r
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));\r
+ \r
+ USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IRLP);\r
+ USARTx->CR3 |= USART_IrDAMode;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the USART\92s IrDA interface.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param NewState: new state of the IrDA mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the IrDA mode by setting the IREN bit in the CR3 register */\r
+ USARTx->CR3 |= USART_CR3_IREN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */\r
+ USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IREN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Group8 DMA transfers management functions\r
+ * @brief DMA transfers management functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ DMA transfers management functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Enables or disables the USART\92s DMA interface.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param USART_DMAReq: specifies the DMA request.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg USART_DMAReq_Tx: USART DMA transmit request\r
+ * @arg USART_DMAReq_Rx: USART DMA receive request\r
+ * @param NewState: new state of the DMA Request sources.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @retval None\r
+ */\r
+void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_DMAREQ(USART_DMAReq)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the DMA transfer for selected requests by setting the DMAT and/or\r
+ DMAR bits in the USART CR3 register */\r
+ USARTx->CR3 |= USART_DMAReq;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the DMA transfer for selected requests by clearing the DMAT and/or\r
+ DMAR bits in the USART CR3 register */\r
+ USARTx->CR3 &= (uint16_t)~USART_DMAReq;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup USART_Group9 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Interrupts and flags management functions\r
+ =============================================================================== \r
+\r
+ This subsection provides a set of functions allowing to configure the USART \r
+ Interrupts sources, DMA channels requests and check or clear the flags or \r
+ pending bits status.\r
+ The user should identify which mode will be used in his application to manage \r
+ the communication: Polling mode, Interrupt mode or DMA mode. \r
+ \r
+ Polling Mode\r
+ =============\r
+ In Polling Mode, the SPI communication can be managed by 10 flags:\r
+ 1. USART_FLAG_TXE : to indicate the status of the transmit buffer register\r
+ 2. USART_FLAG_RXNE : to indicate the status of the receive buffer register\r
+ 3. USART_FLAG_TC : to indicate the status of the transmit operation\r
+ 4. USART_FLAG_IDLE : to indicate the status of the Idle Line \r
+ 5. USART_FLAG_CTS : to indicate the status of the nCTS input\r
+ 6. USART_FLAG_LBD : to indicate the status of the LIN break detection\r
+ 7. USART_FLAG_NE : to indicate if a noise error occur\r
+ 8. USART_FLAG_FE : to indicate if a frame error occur\r
+ 9. USART_FLAG_PE : to indicate if a parity error occur\r
+ 10. USART_FLAG_ORE : to indicate if an Overrun error occur\r
+\r
+ In this Mode it is advised to use the following functions:\r
+ - FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);\r
+ - void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);\r
+\r
+ Interrupt Mode\r
+ ===============\r
+ In Interrupt Mode, the USART communication can be managed by 8 interrupt sources\r
+ and 10 pending bits: \r
+\r
+ Pending Bits:\r
+ ------------- \r
+ 1. USART_IT_TXE : to indicate the status of the transmit buffer register\r
+ 2. USART_IT_RXNE : to indicate the status of the receive buffer register\r
+ 3. USART_IT_TC : to indicate the status of the transmit operation\r
+ 4. USART_IT_IDLE : to indicate the status of the Idle Line \r
+ 5. USART_IT_CTS : to indicate the status of the nCTS input\r
+ 6. USART_IT_LBD : to indicate the status of the LIN break detection\r
+ 7. USART_IT_NE : to indicate if a noise error occur\r
+ 8. USART_IT_FE : to indicate if a frame error occur\r
+ 9. USART_IT_PE : to indicate if a parity error occur\r
+ 10. USART_IT_ORE : to indicate if an Overrun error occur\r
+\r
+ Interrupt Source:\r
+ -----------------\r
+ 1. USART_IT_TXE : specifies the interrupt source for the Tx buffer empty \r
+ interrupt. \r
+ 2. USART_IT_RXNE : specifies the interrupt source for the Rx buffer not \r
+ empty interrupt.\r
+ 3. USART_IT_TC : specifies the interrupt source for the Transmit complete \r
+ interrupt. \r
+ 4. USART_IT_IDLE : specifies the interrupt source for the Idle Line interrupt. \r
+ 5. USART_IT_CTS : specifies the interrupt source for the CTS interrupt. \r
+ 6. USART_IT_LBD : specifies the interrupt source for the LIN break detection\r
+ interrupt. \r
+ 7. USART_IT_PE : specifies the interrupt source for theparity error interrupt. \r
+ 8. USART_IT_ERR : specifies the interrupt source for the errors interrupt.\r
+\r
+ Note: Some parameters are coded in order to use them as interrupt source or \r
+ ---- as pending bits.\r
+\r
+ In this Mode it is advised to use the following functions:\r
+ - void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);\r
+ - ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);\r
+ - void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);\r
+\r
+ DMA Mode\r
+ ========\r
+ In DMA Mode, the USART communication can be managed by 2 DMA Channel requests:\r
+ 1. USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request\r
+ 2. USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request\r
+\r
+ In this Mode it is advised to use the following function:\r
+ - void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified USART interrupts.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_IT_CTS: CTS change interrupt\r
+ * @arg USART_IT_LBD: LIN Break detection interrupt\r
+ * @arg USART_IT_TXE: Tansmit Data Register empty interrupt\r
+ * @arg USART_IT_TC: Transmission complete interrupt\r
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt\r
+ * @arg USART_IT_IDLE: Idle line detection interrupt\r
+ * @arg USART_IT_PE: Parity Error interrupt\r
+ * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)\r
+ * @param NewState: new state of the specified USARTx interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState)\r
+{\r
+ uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;\r
+ uint32_t usartxbase = 0x00;\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_CONFIG_IT(USART_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ usartxbase = (uint32_t)USARTx;\r
+\r
+ /* Get the USART register index */\r
+ usartreg = (((uint8_t)USART_IT) >> 0x05);\r
+\r
+ /* Get the interrupt position */\r
+ itpos = USART_IT & IT_MASK;\r
+ itmask = (((uint32_t)0x01) << itpos);\r
+ \r
+ if (usartreg == 0x01) /* The IT is in CR1 register */\r
+ {\r
+ usartxbase += 0x0C;\r
+ }\r
+ else if (usartreg == 0x02) /* The IT is in CR2 register */\r
+ {\r
+ usartxbase += 0x10;\r
+ }\r
+ else /* The IT is in CR3 register */\r
+ {\r
+ usartxbase += 0x14; \r
+ }\r
+ if (NewState != DISABLE)\r
+ {\r
+ *(__IO uint32_t*)usartxbase |= itmask;\r
+ }\r
+ else\r
+ {\r
+ *(__IO uint32_t*)usartxbase &= ~itmask;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified USART flag is set or not.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param USART_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_FLAG_CTS: CTS Change flag\r
+ * @arg USART_FLAG_LBD: LIN Break detection flag\r
+ * @arg USART_FLAG_TXE: Transmit data register empty flag\r
+ * @arg USART_FLAG_TC: Transmission Complete flag\r
+ * @arg USART_FLAG_RXNE: Receive data register not empty flag\r
+ * @arg USART_FLAG_IDLE: Idle Line detection flag\r
+ * @arg USART_FLAG_ORE: OverRun Error flag\r
+ * @arg USART_FLAG_NE: Noise Error flag\r
+ * @arg USART_FLAG_FE: Framing Error flag\r
+ * @arg USART_FLAG_PE: Parity Error flag\r
+ * @retval The new state of USART_FLAG (SET or RESET).\r
+ */\r
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_FLAG(USART_FLAG));\r
+ \r
+ if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the USARTx's pending flags.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param USART_FLAG: specifies the flag to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg USART_FLAG_CTS: CTS Change flag.\r
+ * @arg USART_FLAG_LBD: LIN Break detection flag.\r
+ * @arg USART_FLAG_TC: Transmission Complete flag.\r
+ * @arg USART_FLAG_RXNE: Receive data register not empty flag.\r
+ * \r
+ * @note\r
+ * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun \r
+ * error) and IDLE (Idle line detected) flags are cleared by software \r
+ * sequence: a read operation to USART_SR register (USART_GetFlagStatus()) \r
+ * followed by a read operation to USART_DR register (USART_ReceiveData()).\r
+ * - RXNE flag can be also cleared by a read to the USART_DR register \r
+ * (USART_ReceiveData()).\r
+ * - TC flag can be also cleared by software sequence: a read operation to \r
+ * USART_SR register (USART_GetFlagStatus()) followed by a write operation\r
+ * to USART_DR register (USART_SendData()).\r
+ * - TXE flag is cleared only by a write to the USART_DR register \r
+ * (USART_SendData()).\r
+ * @retval None\r
+ */\r
+void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));\r
+ \r
+ USARTx->SR = (uint16_t)~USART_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified USART interrupt has occurred or not.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param USART_IT: specifies the USART interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_IT_CTS: CTS change interrupt\r
+ * @arg USART_IT_LBD: LIN Break detection interrupt\r
+ * @arg USART_IT_TXE: Tansmit Data Register empty interrupt\r
+ * @arg USART_IT_TC: Transmission complete interrupt\r
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt\r
+ * @arg USART_IT_IDLE: Idle line detection interrupt\r
+ * @arg USART_IT_ORE: OverRun Error interrupt\r
+ * @arg USART_IT_NE: Noise Error interrupt\r
+ * @arg USART_IT_FE: Framing Error interrupt\r
+ * @arg USART_IT_PE: Parity Error interrupt\r
+ * @retval The new state of USART_IT (SET or RESET).\r
+ */\r
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT)\r
+{\r
+ uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;\r
+ ITStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_GET_IT(USART_IT)); \r
+ \r
+ /* Get the USART register index */\r
+ usartreg = (((uint8_t)USART_IT) >> 0x05);\r
+ /* Get the interrupt position */\r
+ itmask = USART_IT & IT_MASK;\r
+ itmask = (uint32_t)0x01 << itmask;\r
+ \r
+ if (usartreg == 0x01) /* The IT is in CR1 register */\r
+ {\r
+ itmask &= USARTx->CR1;\r
+ }\r
+ else if (usartreg == 0x02) /* The IT is in CR2 register */\r
+ {\r
+ itmask &= USARTx->CR2;\r
+ }\r
+ else /* The IT is in CR3 register */\r
+ {\r
+ itmask &= USARTx->CR3;\r
+ }\r
+ \r
+ bitpos = USART_IT >> 0x08;\r
+ bitpos = (uint32_t)0x01 << bitpos;\r
+ bitpos &= USARTx->SR;\r
+ if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ \r
+ return bitstatus; \r
+}\r
+\r
+/**\r
+ * @brief Clears the USARTx\92s interrupt pending bits.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param USART_IT: specifies the interrupt pending bit to clear.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_IT_CTS: CTS change interrupt\r
+ * @arg USART_IT_LBD: LIN Break detection interrupt\r
+ * @arg USART_IT_TC: Transmission complete interrupt. \r
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt.\r
+ * \r
+ * @note\r
+ * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun \r
+ * error) and IDLE (Idle line detected) pending bits are cleared by \r
+ * software sequence: a read operation to USART_SR register \r
+ * (USART_GetITStatus()) followed by a read operation to USART_DR register \r
+ * (USART_ReceiveData()).\r
+ * - RXNE pending bit can be also cleared by a read to the USART_DR register \r
+ * (USART_ReceiveData()).\r
+ * - TC pending bit can be also cleared by software sequence: a read \r
+ * operation to USART_SR register (USART_GetITStatus()) followed by a write \r
+ * operation to USART_DR register (USART_SendData()).\r
+ * - TXE pending bit is cleared only by a write to the USART_DR register \r
+ * (USART_SendData()).\r
+ * @retval None\r
+ */\r
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT)\r
+{\r
+ uint16_t bitpos = 0x00, itmask = 0x00;\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_CLEAR_IT(USART_IT)); \r
+ \r
+ bitpos = USART_IT >> 0x08;\r
+ itmask = ((uint16_t)0x01 << (uint16_t)bitpos);\r
+ USARTx->SR = (uint16_t)~itmask;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_wwdg.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Window watchdog (WWDG) peripheral: \r
+ * - Prescaler, Refresh window and Counter configuration\r
+ * - WWDG activation\r
+ * - Interrupts and flags management\r
+ * \r
+ * @verbatim\r
+ * \r
+ * ===================================================================\r
+ * WWDG features\r
+ * ===================================================================\r
+ * \r
+ * Once enabled the WWDG generates a system reset on expiry of a programmed\r
+ * time period, unless the program refreshes the counter (downcounter) \r
+ * before to reach 0x3F value (i.e. a reset is generated when the counter\r
+ * value rolls over from 0x40 to 0x3F). \r
+ * An MCU reset is also generated if the counter value is refreshed\r
+ * before the counter has reached the refresh window value. This \r
+ * implies that the counter must be refreshed in a limited window.\r
+ * \r
+ * Once enabled the WWDG cannot be disabled except by a system reset. \r
+ * \r
+ * WWDGRST flag in RCC_CSR register can be used to inform when a WWDG\r
+ * reset occurs.\r
+ * \r
+ * The WWDG counter input clock is derived from the APB clock divided \r
+ * by a programmable prescaler.\r
+ * \r
+ * WWDG counter clock = PCLK1 / Prescaler\r
+ * WWDG timeout = (WWDG counter clock) * (counter value)\r
+ * \r
+ * Min-max timeout value @32MHz (PCLK1): ~128us / ~65.6ms\r
+ * \r
+ * ===================================================================\r
+ * How to use this driver\r
+ * =================================================================== \r
+ * 1. Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) function\r
+ * \r
+ * 2. Configure the WWDG prescaler using WWDG_SetPrescaler() function\r
+ * \r
+ * 3. Configure the WWDG refresh window using WWDG_SetWindowValue() function\r
+ * \r
+ * 4. Set the WWDG counter value and start it using WWDG_Enable() function.\r
+ * When the WWDG is enabled the counter value should be configured to \r
+ * a value greater than 0x40 to prevent generating an immediate reset. \r
+ * \r
+ * 5. Optionally you can enable the Early wakeup interrupt which is \r
+ * generated when the counter reach 0x40.\r
+ * Once enabled this interrupt cannot be disabled except by a system reset.\r
+ * \r
+ * 6. Then the application program must refresh the WWDG counter at regular\r
+ * intervals during normal operation to prevent an MCU reset, using\r
+ * WWDG_SetCounter() function. This operation must occur only when\r
+ * the counter value is lower than the refresh window value, \r
+ * programmed using WWDG_SetWindowValue(). \r
+ *\r
+ * @endverbatim \r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_wwdg.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup WWDG \r
+ * @brief WWDG driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+\r
+/* ----------- WWDG registers bit address in the alias region ----------- */\r
+#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)\r
+\r
+/* Alias word address of EWI bit */\r
+#define CFR_OFFSET (WWDG_OFFSET + 0x04)\r
+#define EWI_BitNumber 0x09\r
+#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))\r
+\r
+/* --------------------- WWDG registers bit mask ------------------------ */\r
+\r
+/* CFR register bit mask */\r
+#define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F)\r
+#define CFR_W_MASK ((uint32_t)0xFFFFFF80)\r
+#define BIT_MASK ((uint8_t)0x7F)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup WWDG_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions\r
+ * @brief Prescaler, Refresh window and Counter configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Prescaler, Refresh window and Counter configuration functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the WWDG peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void WWDG_DeInit(void)\r
+{\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Sets the WWDG Prescaler.\r
+ * @param WWDG_Prescaler: specifies the WWDG Prescaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1\r
+ * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2\r
+ * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4\r
+ * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8\r
+ * @retval None\r
+ */\r
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));\r
+ /* Clear WDGTB[1:0] bits */\r
+ tmpreg = WWDG->CFR & CFR_WDGTB_MASK;\r
+ /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */\r
+ tmpreg |= WWDG_Prescaler;\r
+ /* Store the new value */\r
+ WWDG->CFR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Sets the WWDG window value.\r
+ * @param WindowValue: specifies the window value to be compared to the downcounter.\r
+ * This parameter value must be lower than 0x80.\r
+ * @retval None\r
+ */\r
+void WWDG_SetWindowValue(uint8_t WindowValue)\r
+{\r
+ __IO uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));\r
+ /* Clear W[6:0] bits */\r
+\r
+ tmpreg = WWDG->CFR & CFR_W_MASK;\r
+\r
+ /* Set W[6:0] bits according to WindowValue value */\r
+ tmpreg |= WindowValue & (uint32_t) BIT_MASK;\r
+\r
+ /* Store the new value */\r
+ WWDG->CFR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables the WWDG Early Wakeup interrupt(EWI).\r
+ * @note Once enabled this interrupt cannot be disabled except by a system reset. \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void WWDG_EnableIT(void)\r
+{\r
+ *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;\r
+}\r
+\r
+/**\r
+ * @brief Sets the WWDG counter value.\r
+ * @param Counter: specifies the watchdog counter value.\r
+ * This parameter must be a number between 0x40 and 0x7F (to prevent generating\r
+ * an immediate reset) \r
+ * @retval None\r
+ */\r
+void WWDG_SetCounter(uint8_t Counter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_WWDG_COUNTER(Counter));\r
+ /* Write to T[6:0] bits to configure the counter value, no need to do\r
+ a read-modify-write; writing a 0 to WDGA bit does nothing */\r
+ WWDG->CR = Counter & BIT_MASK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup WWDG_Group2 WWDG activation functions\r
+ * @brief WWDG activation functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ WWDG activation functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables WWDG and load the counter value. \r
+ * @param Counter: specifies the watchdog counter value.\r
+ * This parameter must be a number between 0x40 and 0x7F (to prevent generating\r
+ * an immediate reset)\r
+ * @retval None\r
+ */\r
+void WWDG_Enable(uint8_t Counter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_WWDG_COUNTER(Counter));\r
+ WWDG->CR = WWDG_CR_WDGA | Counter;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup WWDG_Group3 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Interrupts and flags management functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Checks whether the Early Wakeup interrupt flag is set or not.\r
+ * @param None\r
+ * @retval The new state of the Early Wakeup interrupt flag (SET or RESET)\r
+ */\r
+FlagStatus WWDG_GetFlagStatus(void)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ \r
+ if ((WWDG->SR) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears Early Wakeup interrupt flag.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void WWDG_ClearFlag(void)\r
+{\r
+ WWDG->SR = (uint32_t)RESET;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
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