registered to meet timing
authormatt <matt@221aa14e-8319-0410-a670-987f0aec2ac5>
Fri, 30 Mar 2007 21:52:52 +0000 (21:52 +0000)
committermatt <matt@221aa14e-8319-0410-a670-987f0aec2ac5>
Fri, 30 Mar 2007 21:52:52 +0000 (21:52 +0000)
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4826 221aa14e-8319-0410-a670-987f0aec2ac5

usrp/fpga/sdr_lib/cic_decim.v

index 6c20416f193511779caf69ba478ebaecf74e56fe..8c44f006db83c9bdc1cbd11ac05a8fd56a07d5ef 100755 (executable)
@@ -35,7 +35,8 @@ module cic_decim
    input [bw-1:0] signal_in;
    output [bw-1:0] signal_out;
    reg [bw-1:0] signal_out;
-
+   wire [bw-1:0] signal_out_unreg;
+   
    wire [bw+maxbitgain-1:0] signal_in_ext;
    reg [bw+maxbitgain-1:0]  integrator [0:N-1];
    reg [bw+maxbitgain-1:0] differentiator [0:N-1];
@@ -83,7 +84,10 @@ module cic_decim
    wire [bw+maxbitgain-1:0] signal_out_unnorm = pipeline[N-1];
 
    cic_dec_shifter #(bw)
-       cic_dec_shifter(rate,signal_out_unnorm,signal_out);
+       cic_dec_shifter(rate,signal_out_unnorm,signal_out_unreg);
+
+   always @(posedge clock)
+     signal_out <= #1 signal_out_unreg;
    
 endmodule // cic_decim