+++ /dev/null
-/a.out
-/*.vcd
-/*.sav
-/*.lxt
+++ /dev/null
-// This tests just runs a few packets at 10/100 Mbps and 1 Gbps instead of only the usual 1 Gbps\r
-\r
-// Read from register 24 to confirm that Rx CRC check is enabled\r
-03 00 18 00 01 ff ff\r
-\r
-// Set speed to 1000 Mbps for a starter\r
-01 00 22 00 04\r
-\r
-// Setup Tx and Rx MAC addresses and type field to "IP"\r
-// Set Tx Data at offset 0, length 14 to 123456789ABC CBA987654321 0800\r
-10 00 00 00 0E 12 34 56 78 9A BC CB A9 87 65 43 21 08 00\r
-\r
-// Transmit a 1000-byte frame 1 time - and expect it to be received again!\r
-20 03 E8 00 01\r
-\r
-// Wait (indefinitely) for missing Rx packets\r
-22 00 00 \r
-\r
-// Set speed to 100 Mbps - this is 10x slower!\r
-01 00 22 00 02\r
-\r
-// Transmit a 1000-byte frame 1 time - and expect it to be received again!\r
-20 03 E8 00 01\r
-\r
-// Wait (indefinitely) for missing Rx packets\r
-22 00 00 \r
-\r
-// Set speed to 10 Mbps - this is yet another 10x slower!\r
-01 00 22 00 01\r
-\r
-// Transmit a 1000-byte frame 1 time - and expect it to be received again!\r
-20 03 E8 00 01\r
-\r
-// Wait (indefinitely) for missing Rx packets\r
-22 00 00 \r
-\r
-// Halt\r
-FF\r
+++ /dev/null
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// Phy_sim.v ////\r
-//// ////\r
-//// This file is part of the Ethernet IP core project ////\r
-//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////\r
-//// ////\r
-//// Author(s): ////\r
-//// - Jon Gao (gaojon@yahoo.com) ////\r
-//// ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// Copyright (C) 2001 Authors ////\r
-//// ////\r
-//// This source file may be used and distributed without ////\r
-//// restriction provided that this copyright statement is not ////\r
-//// removed from the file and that any derivative work contains ////\r
-//// the original copyright notice and the associated disclaimer. ////\r
-//// ////\r
-//// This source file is free software; you can redistribute it ////\r
-//// and/or modify it under the terms of the GNU Lesser General ////\r
-//// Public License as published by the Free Software Foundation; ////\r
-//// either version 2.1 of the License, or (at your option) any ////\r
-//// later version. ////\r
-//// ////\r
-//// This source is distributed in the hope that it will be ////\r
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\r
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\r
-//// PURPOSE. See the GNU Lesser General Public License for more ////\r
-//// details. ////\r
-//// ////\r
-//// You should have received a copy of the GNU Lesser General ////\r
-//// Public License along with this source; if not, download it ////\r
-//// from http://www.opencores.org/lgpl.shtml ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-// \r
-// CVS Revision History \r
-// \r
-// $Log: Phy_sim.v,v $\r
-// Revision 1.3 2006/11/17 17:53:07 maverickist\r
-// no message\r
-//\r
-// Revision 1.2 2006/01/19 14:07:50 maverickist\r
-// verification is complete.\r
-//\r
-// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator\r
-// no message\r
-// \r
-\r
-`timescale 1ns/100ps \r
-\r
-module Phy_sim(\r
- input Gtx_clk, // Used only in GMII mode\r
- output Rx_clk,\r
- output Tx_clk, // Used only in MII mode\r
- input Tx_er,\r
- input Tx_en,\r
- input [7:0] Txd,\r
- output Rx_er,\r
- output Rx_dv,\r
- output [7:0] Rxd,\r
- output Crs,\r
- output Col,\r
- input [2:0] Speed,\r
- input Done\r
-);\r
-\r
-//////////////////////////////////////////////////////////////////////\r
-// this file used to simulate Phy.\r
-// generate clk and loop the Tx data to Rx data\r
-// full duplex mode can be verified on loop mode.\r
-//////////////////////////////////////////////////////////////////////\r
-//////////////////////////////////////////////////////////////////////\r
-// internal signals\r
-//////////////////////////////////////////////////////////////////////\r
-reg Clk_25m; // Used for 100 Mbps mode\r
-reg Clk_2_5m; // Used for 10 Mbps mode\r
-\r
-//wire Rx_clk;\r
-//wire Tx_clk; // Used only in MII mode\r
-\r
- initial \r
- begin\r
- #10;\r
- while ( !Done )\r
- begin\r
- #20 Clk_25m = 0;\r
- #20 Clk_25m = 1;\r
- end\r
- end\r
-\r
- initial \r
- begin\r
- #10;\r
- while ( !Done )\r
- begin\r
- #200 Clk_2_5m = 0;\r
- #200 Clk_2_5m = 1;\r
- end\r
- end\r
-\r
- assign Rx_clk = Speed[2] ? Gtx_clk : Speed[1] ? Clk_25m : Speed[0] ? Clk_2_5m : 0; \r
- assign Tx_clk = Speed[2] ? Gtx_clk : Speed[1] ? Clk_25m : Speed[0] ? Clk_2_5m : 0;\r
-\r
- assign Rx_dv = Tx_en;\r
- assign Rxd = Txd;\r
- assign Rx_er = Tx_er;\r
- assign Crs = Tx_en;\r
- assign Col = 0;\r
-\r
-endmodule\r
+++ /dev/null
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// User_input_sim.v ////\r
-//// ////\r
-//// This file is part of the Ethernet IP core project ////\r
-//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////\r
-//// ////\r
-//// Author(s): ////\r
-//// - Jon Gao (gaojon@yahoo.com) ////\r
-//// ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// Copyright (C) 2001 Authors ////\r
-//// ////\r
-//// This source file may be used and distributed without ////\r
-//// restriction provided that this copyright statement is not ////\r
-//// removed from the file and that any derivative work contains ////\r
-//// the original copyright notice and the associated disclaimer. ////\r
-//// ////\r
-//// This source file is free software; you can redistribute it ////\r
-//// and/or modify it under the terms of the GNU Lesser General ////\r
-//// Public License as published by the Free Software Foundation; ////\r
-//// either version 2.1 of the License, or (at your option) any ////\r
-//// later version. ////\r
-//// ////\r
-//// This source is distributed in the hope that it will be ////\r
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\r
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\r
-//// PURPOSE. See the GNU Lesser General Public License for more ////\r
-//// details. ////\r
-//// ////\r
-//// You should have received a copy of the GNU Lesser General ////\r
-//// Public License along with this source; if not, download it ////\r
-//// from http://www.opencores.org/lgpl.shtml ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-// \r
-// CVS Revision History \r
-// \r
-// $Log: User_int_sim.v,v $\r
-// Revision 1.3 2006/11/17 17:53:07 maverickist\r
-// no message\r
-//\r
-// Revision 1.2 2006/01/19 14:07:50 maverickist\r
-// verification is complete.\r
-//\r
-// Revision 1.2 2005/12/13 12:15:35 Administrator\r
-// no message\r
-//\r
-// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator\r
-// no message\r
-// \r
-module User_int_sim (\r
- Reset,\r
- Clk_user,\r
- CPU_init_end,\r
-\r
- Rx_mac_ra,\r
- Rx_mac_rd,\r
- Rx_mac_data,\r
- Rx_mac_BE,\r
- Rx_mac_pa,\r
- Rx_mac_sop,\r
- Rx_mac_eop,\r
-\r
- Tx_mac_wa,\r
- Tx_mac_wr,\r
- Tx_mac_data,\r
- Tx_mac_BE,\r
- Tx_mac_sop,\r
- Tx_mac_eop\r
-);\r
-\r
- input Reset;\r
- input Clk_user;\r
- input CPU_init_end;\r
-\r
- input Rx_mac_ra;\r
- output Rx_mac_rd;\r
- input [31:0] Rx_mac_data;\r
- input [1:0] Rx_mac_BE;\r
- input Rx_mac_pa;\r
- input Rx_mac_sop;\r
- input Rx_mac_eop;\r
-\r
- input Tx_mac_wa;\r
- output reg Tx_mac_wr;\r
- output reg [31:0] Tx_mac_data;\r
- output reg [1:0] Tx_mac_BE; // Big endian\r
- output reg Tx_mac_sop;\r
- output reg Tx_mac_eop;\r
-\r
-//////////////////////////////////////////////////////////////////////\r
-// Internal signals\r
-//////////////////////////////////////////////////////////////////////\r
-\r
- reg [4:0] operation;\r
- reg [31:0] data;\r
- reg Rx_mac_rd;\r
- reg Start_tran;\r
-\r
-//////////////////////////////////////////////////////////////////////\r
-//generate Tx user data\r
-//////////////////////////////////////////////////////////////////////\r
-\r
- initial\r
- begin\r
- operation = 0;\r
- data = 0;\r
- end\r
-\r
- task SendPacket;\r
- input [15:0] Length;\r
- input [7:0] StartByte;\r
-\r
- reg [15:0] Counter;\r
- reg [7:0] TxData;\r
-\r
- begin\r
- Counter=Length;\r
- TxData = StartByte;\r
- Tx_mac_sop = 1; // First time\r
- while ( Counter>0 )\r
- begin\r
- while ( !Tx_mac_wa )\r
- begin\r
- Tx_mac_wr = 0;\r
- @( posedge Clk_user );\r
- end\r
-\r
- Tx_mac_data[31:24] = TxData;\r
- Tx_mac_data[23:16] = TxData+1;\r
- Tx_mac_data[15:8] = TxData+2;\r
- Tx_mac_data[ 7:0] = TxData+3;\r
- TxData = TxData+4;\r
- if ( Counter<=4 )\r
- begin\r
- // Indicate how many bytes are valid\r
- if ( Counter==4 )\r
- Tx_mac_BE = 2'b00;\r
- else\r
- Tx_mac_BE = Counter;\r
- Tx_mac_eop = 1;\r
- end\r
- Tx_mac_wr = 1;\r
-\r
- if ( Counter >= 4 )\r
- Counter = Counter - 4;\r
- else\r
- Counter = 0;\r
- @( posedge Clk_user );\r
- Tx_mac_sop = 0;\r
- end\r
-\r
- Tx_mac_eop = 0;\r
- Tx_mac_wr = 0;\r
- Tx_mac_data = 32'h0;\r
- Tx_mac_BE = 2'b00;\r
- end\r
- endtask\r
-\r
- always @( posedge Clk_user or posedge Reset )\r
- if (Reset)\r
- Start_tran <= 0;\r
- else if (Tx_mac_eop && !Tx_mac_wa) \r
- Start_tran <= 0; \r
- else if (Tx_mac_wa)\r
- Start_tran <= 1;\r
-\r
- always @(posedge Clk_user)\r
- if (Tx_mac_wa && CPU_init_end)\r
- /* $ip_32W_gen("../data/config.ini",operation,data); */\r
- ;\r
- else\r
- begin\r
- operation <= 0;\r
- data <= 0;\r
- end\r
-\r
- initial\r
- begin\r
- Tx_mac_sop = 0;\r
- Tx_mac_eop = 0;\r
- Tx_mac_wr = 0;\r
- Tx_mac_data = 32'h0;\r
- Tx_mac_BE = 2'b00;\r
-\r
- #100;\r
- while ( Reset )\r
- @( posedge Clk_user );\r
-\r
- @( posedge Clk_user );\r
-\r
- while ( !CPU_init_end )\r
- @( posedge Clk_user );\r
-\r
- SendPacket( 64, 8'h11 );\r
- repeat( 20 )\r
- @( posedge Clk_user );\r
- SendPacket( 1500, 8'h12 );\r
- \r
- end\r
-\r
-// assign Tx_mac_data = data;\r
-// assign Tx_mac_wr = operation[4];\r
-// assign Tx_mac_sop = operation[3];\r
-// assign Tx_mac_eop = operation[2];\r
-// assign Tx_mac_BE = operation[1:0];\r
-\r
-//////////////////////////////////////////////////////////////////////\r
-//verify Rx user data\r
-//////////////////////////////////////////////////////////////////////\r
-\r
- always @ (posedge Clk_user or posedge Reset)\r
- if (Reset)\r
- Rx_mac_rd <= 0;\r
- else if (Rx_mac_ra)\r
- Rx_mac_rd <= 1;\r
- else\r
- Rx_mac_rd <= 0;\r
-\r
- always @ (posedge Clk_user )\r
- if (Rx_mac_pa) \r
- /* $ip_32W_check( Rx_mac_data,\r
- {Rx_mac_sop,Rx_mac_eop,Rx_mac_eop?Rx_mac_BE:2'b0});\r
- */\r
- ;\r
-\r
-endmodule\r
+++ /dev/null
-// This tests sends 5 packets, injecting a bit error in two of them\r
-// to verify the Rx CRC check works. The corresponding RMON statistics\r
-// counter is finally checked to verify that the error was registered\r
-\r
-// Read from register 24 to confirm that Rx CRC check is enabled\r
-03 00 18 00 01 ff ff\r
-\r
-// Set speed to 1000 Mbps\r
-01 00 22 00 04\r
-\r
-// Setup Tx and Rx MAC addresses and type field to "IP"\r
-// Set Tx Data at offset 0, length 14 to 123456789ABC CBA987654321 0800\r
-10 00 00 00 0E 12 34 56 78 9A BC CB A9 87 65 43 21 08 00\r
-\r
-//--- Packets #0 & 1 --------------------------------------------------------\r
-\r
-// Transmit a 200-byte frame 1 time - and expect it to be received again!\r
-20 00 C8 00 01\r
-\r
-// Wait (indefinitely) for missing Rx packets\r
-22 00 00 \r
-\r
-// Transmit a 200-byte frame 1 time - but expect to receive it with error!\r
-25 00 C8 00 01\r
-\r
-// Inject a single bit error in the packet (data bit 0) - this will cause a CRC error\r
-23 00 01\r
-\r
-// Wait (indefinitely) for missing Rx packets\r
-22 00 00 \r
-\r
-//--- Packets #2 & 3 --------------------------------------------------------\r
-\r
-// Transmit a 200-byte frame 1 time - and expect it to be received again!\r
-20 00 C8 00 01\r
-\r
-// Wait (indefinitely) for missing Rx packets\r
-22 00 00 \r
-\r
-// Transmit a 200-byte frame 1 time - but expect to receive it with error!\r
-25 00 C8 00 01\r
-\r
-// Inject a single bit error in the packet (data bit 7) - this will cause a CRC error\r
-23 00 80\r
-\r
-// Wait (indefinitely) for missing Rx packets\r
-22 00 00 \r
-\r
-//--- Packets #4 & 5 --------------------------------------------------------\r
-\r
-// Transmit a 200-byte frame 1 time - and expect it to be received again!\r
-20 00 C8 00 01\r
-\r
-// Wait (indefinitely) for missing Rx packets\r
-22 00 00 \r
-\r
-// Transmit a 200-byte frame 1 time - but don't expect it to be received again!\r
-21 00 C8 00 01\r
-\r
-// Inject a single bit error in the packet (RxEn) - this will cause a packet discard!\r
-// (because it happens early in the packet)\r
-23 01 00\r
-\r
-// Wait (indefinitely) for missing Rx packets\r
-22 00 00 \r
-\r
-//--- Packets #6 & 7 --------------------------------------------------------\r
-\r
-// Transmit a 200-byte frame 1 time - and expect it to be received again!\r
-20 00 C8 00 01\r
-\r
-// Wait (indefinitely) for missing Rx packets\r
-22 00 00 \r
-\r
-// Transmit a 200-byte frame 1 time - but don't expect it to be received again!\r
-21 00 C8 00 01\r
-\r
-// Inject a single bit error in the packet (RxEr)\r
-23 02 00\r
-\r
-// Wait (indefinitely) for missing Rx packets\r
-22 00 00 \r
-\r
-//--- Packet #8 -------------------------------------------------------------\r
-\r
-// Transmit a 200-byte frame 1 time - and expect it to be received again!\r
-20 00 C8 00 01\r
-\r
-// Wait (indefinitely) for missing Rx packets\r
-22 00 00 \r
-\r
-//---------------------------------------------------------------------------\r
-\r
-// Set CPU_rd_addr to address RxCRCErrCounter\r
-01 00 1C 00 05\r
-\r
-// Assert CPU_rd_apply\r
-01 00 1D 00 01\r
-\r
-// Kill a little time while waiting for CPU_rd_grant to assert...\r
-02 00 1E\r
-02 00 1E\r
-02 00 1E\r
-02 00 1E\r
-\r
-// Confirm that CPU_rd_grant is asserted\r
-03 00 1E 00 01 ff ff\r
-\r
-// Read & check low part of RxCRCErrCounter (0x0002)\r
-03 00 1F 00 02 ff ff\r
-\r
-// Read & check high part of RxCRCErrCounter (0x0000)\r
-03 00 20 00 00 ff ff\r
-\r
-// Negate CPU_rd_apply\r
-01 00 1D 00 00\r
-\r
-//---------------------------------------------------------------------------\r
-\r
-// Set CPU_rd_addr to address RxTooShortTooLongCounter\r
-01 00 1C 00 07\r
-\r
-// Assert CPU_rd_apply\r
-01 00 1D 00 01\r
-\r
-// Kill a little time while waiting for CPU_rd_grant to assert...\r
-02 00 1E\r
-02 00 1E\r
-02 00 1E\r
-02 00 1E\r
-\r
-// Confirm that CPU_rd_grant is asserted\r
-03 00 1E 00 01 ff ff\r
-\r
-// Read & check low part of RxTooShortTooLongCounter (0x0002)\r
-03 00 1F 00 02 ff ff\r
-\r
-// Read & check high part of RxTooShortTooLongCounter (0x0000)\r
-03 00 20 00 00 ff ff\r
-\r
-// Negate CPU_rd_apply\r
-01 00 1D 00 00\r
-\r
-\r
-// Halt\r
-FF\r
+++ /dev/null
-../../rtl/verilog/MAC_rx/Broadcast_filter.v\r
-../../rtl/verilog/MAC_rx/CRC_chk.v\r
-../../rtl/verilog/MAC_rx/MAC_rx_add_chk.v\r
-../../rtl/verilog/MAC_rx/MAC_rx_ctrl.v\r
-../../rtl/verilog/MAC_rx/MAC_rx_FF.v\r
-\r
-../../rtl/verilog/MAC_tx/CRC_gen.v\r
-../../rtl/verilog/MAC_tx/flow_ctrl.v\r
-../../rtl/verilog/MAC_tx/MAC_tx_addr_add.v\r
-../../rtl/verilog/MAC_tx/MAC_tx_ctrl.v\r
-../../rtl/verilog/MAC_tx/MAC_tx_FF.v\r
-../../rtl/verilog/MAC_tx/Ramdon_gen.v\r
-\r
-../../rtl/verilog/miim/eth_clockgen.v\r
-../../rtl/verilog/miim/eth_outputcontrol.v\r
-../../rtl/verilog/miim/eth_shiftreg.v\r
-\r
-../../rtl/verilog/RMON/RMON_addr_gen.v\r
-../../rtl/verilog/RMON/RMON_ctrl.v\r
-../../rtl/verilog/RMON/RMON_dpram.v\r
-\r
-../../rtl/verilog/TECH/duram.v\r
-../../rtl/verilog/TECH/eth_clk_div2.v\r
-../../rtl/verilog/TECH/eth_clk_switch.v\r
-\r
-../../rtl/verilog/TECH/xilinx/BUFGMUX.v\r
-../../rtl/verilog/TECH/xilinx/RAMB16_S36_S36.v\r
-\r
-../../rtl/verilog/Clk_ctrl.v\r
-../../rtl/verilog/eth_miim.v\r
-../../rtl/verilog/MAC_rx.v\r
-../../rtl/verilog/MAC_top.v\r
-../../rtl/verilog/MAC_tx.v\r
-../../rtl/verilog/Phy_int.v\r
-../../rtl/verilog/Reg_int.v\r
-../../rtl/verilog/RMON.v\r
-\r
-../../bench/verilog/Phy_sim.v\r
-../../bench/verilog/User_int_sim.v\r
-../../bench/verilog/host_sim.v\r
-../../bench/verilog/xlnx_glbl.v\r
-../../bench/verilog/tb_top.v\r
+++ /dev/null
-module host_sim(\r
- input Reset,\r
- input Clk_reg,\r
- output reg CSB,\r
- output reg WRB,\r
- output reg CPU_init_end,\r
- output reg [15:0] CD_in,\r
- input [15:0] CD_out,\r
- output reg [7:0] CA\r
-);\r
-\r
-////////////////////////////////////////\r
-\r
-task CPU_init;\r
- begin\r
- CA = 0;\r
- CD_in = 0;\r
- WRB = 1;\r
- CSB = 1; \r
- end\r
-endtask\r
-\r
-////////////////////////////////////////\r
-\r
-task CPU_wr;\r
- input [6:0] Addr;\r
- input [15:0] Data;\r
- begin\r
- CA = {Addr,1'b0};\r
- CD_in = Data;\r
- WRB = 0;\r
- CSB = 0; \r
- #20;\r
- CA = 0;\r
- CD_in = 0;\r
- WRB = 1;\r
- CSB = 1;\r
- #20;\r
- end\r
-endtask\r
-\r
-/////////////////////////////////////////\r
-\r
-task CPU_rd;\r
- input [6:0] Addr;\r
- begin\r
- CA = {Addr,1'b0};\r
- WRB = 1;\r
- CSB = 0; \r
- #20;\r
- CA = 0;\r
- WRB = 1;\r
- CSB = 1;\r
- #20; \r
- end\r
-endtask\r
-\r
-/////////////////////////////////////////\r
-\r
-integer i;\r
-\r
-reg [31:0] CPU_data [255:0];\r
-reg [7:0] write_times;\r
-reg [7:0] write_add;\r
-reg [15:0] write_data;\r
-\r
-initial\r
- begin\r
- CPU_init;\r
- CPU_init_end=0;\r
- //$readmemh("../data/CPU.vec",CPU_data);\r
- //{write_times,write_add,write_data}=CPU_data[0];\r
- {write_times,write_add,write_data}='b0;\r
- #90;\r
- for (i=0;i<write_times;i=i+1)\r
- begin\r
- {write_times,write_add,write_data}=CPU_data[i];\r
- CPU_wr(write_add[6:0],write_data);\r
- end\r
- CPU_init_end=1;\r
- end\r
-endmodule\r
+++ /dev/null
-iverilog -I ..\..\rtl\verilog -c files.lst\r
+++ /dev/null
-vvp a.out %*\r
+++ /dev/null
-// This test performs transmission & reception of several Jumbo-frame of ~2Kbytes\r
-// In one of the frames an error is injected to allow analysis of how the\r
-// MAC Rx interface reacts to errors in long packets\r
-\r
-// Read from register 24 to confirm that Rx CRC check is enabled\r
-03 00 18 00 01 ff ff\r
-\r
-// Set speed to 1000 Mbps\r
-01 00 22 00 04\r
-\r
-// Setup Tx and Rx MAC addresses and type field to "IP"\r
-// Set Tx Data at offset 0, length 14 to 123456789ABC CBA987654321 0800\r
-10 00 00 00 0E 12 34 56 78 9A BC CB A9 87 65 43 21 08 00\r
-\r
-// Transmit a 2049-byte frame 2 times - and expect them to be received again!\r
-20 08 02 00 02\r
-\r
-// Wait (indefinitely) for missing Rx packets\r
-22 00 00 \r
-\r
-// Transmit a 2049-byte frame 1 time - but expect to receive it with error!\r
-25 08 02 00 01\r
-\r
-// Delay 256 NOPs to time the error injection to be late in the packet\r
-0F 01 00\r
-\r
-// Inject a single bit error in the packet (data bit 0)\r
-23 01 00\r
-\r
-// Wait (indefinitely) for missing Rx packets\r
-22 00 00 \r
-\r
-// Transmit a 2049-byte frame 2 times - and expect them to be received again!\r
-20 08 01 00 02\r
-\r
-// Wait (indefinitely) for missing Rx packets\r
-22 00 00 \r
-\r
-// Halt\r
-FF\r
+++ /dev/null
-// This test performs transmission & reception of several Jumbo-frames of ~2Kbytes each\r
-// At the same time it demonstrates the wire-speed capabilities of the core\r
-\r
-// Read from register 24 to confirm that Rx CRC check is enabled\r
-03 00 18 00 01 ff ff\r
-\r
-// Set speed to 1000 Mbps\r
-01 00 22 00 04\r
-\r
-// Setup Tx and Rx MAC addresses and type field to "IP"\r
-// Set Tx Data at offset 0, length 14 to 123456789ABC CBA987654321 0800\r
-10 00 00 00 0E 12 34 56 78 9A BC CB A9 87 65 43 21 08 00\r
-\r
-// Transmit a 2047-byte frame 3 times - and expect them to be received again!\r
-20 07 ff 00 03\r
-// Transmit a 2048-byte frame 3 times - and expect them to be received again!\r
-20 08 00 00 03\r
-// Transmit a 2049-byte frame 3 times - and expect them to be received again!\r
-20 08 01 00 03\r
-// Transmit a 2050-byte frame 3 times - and expect them to be received again!\r
-20 08 02 00 03\r
-\r
-// Wait (indefinitely) for missing Rx packets\r
-22 00 00 \r
-\r
-// Halt\r
-FF\r
+++ /dev/null
-// Read from register 24 to confirm that Rx CRC check is enabled\r
-03 00 18 00 01 ff ff\r
-\r
-// Set speed to 1000 Mbps\r
-01 00 22 00 04\r
-\r
-// Set MDIO clock (MDC) divider to 4 to speed up test\r
-01 00 23 00 04\r
-03 00 23 00 04 ff ff\r
-\r
-// Check default (reset) values in new (added) MDIO registers\r
-//03 00 23 00 64 ff ff\r
-03 00 24 00 00 ff ff\r
-03 00 25 00 00 ff ff\r
-03 00 26 00 00 ff ff\r
-03 00 27 00 00 ff ff\r
-03 00 28 00 00 ff ff\r
-\r
-// Set RGAD=0x00 (all zeroes), FIAD=0x1f (all ones), check it\r
-// - these values allows easy recognition in the waveform\r
-01 00 25 00 1f\r
-03 00 25 00 1f ff ff\r
-\r
-// Now start the read operation by writing a 1 to the MIICOMMAND[1] - RSTAT\r
-01 00 24 00 02\r
-03 00 24 00 02 ff ff\r
-\r
-// Delay for 768 NOP\r
-0F 03 00\r
-\r
-// Check that the read operation has completed\r
-03 00 28 00 00 ff ff\r
-\r
-// Set RGAD=0x1f (all ones), FIAD=0x00 (all zeroes), check it\r
-// - these values allows easy recognition in the waveform\r
-01 00 25 1f 00\r
-03 00 25 1f 00 ff ff\r
-// Set MIITX_DATA = 0xAAAA, check it\r
-01 00 26 AA AA\r
-03 00 26 AA AA ff ff\r
-// Check MIISTATUS - must still be zero\r
-03 00 28 00 00 ff ff\r
-\r
-// Now start the write operation by writing a 1 to the MIICOMMAND[2] - WCTRLDATA\r
-01 00 24 00 04\r
-03 00 24 00 04 ff ff\r
-\r
-// Delay for 768 NOP\r
-0F 03 00\r
-\r
-// Check that the write operation has completed\r
-03 00 28 00 00 ff ff\r
+++ /dev/null
-
-// Skeleton PHY interface simulator
-
-module miim_model(input mdc_i,
- inout mdio,
- input phy_resetn_i,
- input phy_clk_i,
- output phy_intn_o,
- output [2:0] speed_o);
-
- assign phy_intn_o = 1; // No interrupts
- assign speed_o = 3'b100; // 1G mode
-
-endmodule // miim_model
+++ /dev/null
-// Read from register 24 to confirm that Rx CRC check is enabled\r
-03 00 18 00 01 ff ff\r
-\r
-// Set speed to 1000 Mbps\r
-01 00 22 00 04\r
-\r
-// Write MAC address 12 35 56 78 9A BC to Rx Address buffer\r
-01 00 10 00 00\r
-01 00 0f 00 12\r
-01 00 11 00 01\r
-01 00 11 00 00\r
-01 00 10 00 01\r
-01 00 0f 00 34\r
-01 00 11 00 01\r
-01 00 11 00 00\r
-01 00 10 00 02\r
-01 00 0f 00 56\r
-01 00 11 00 01\r
-01 00 11 00 00\r
-01 00 10 00 03\r
-01 00 0f 00 78\r
-01 00 11 00 01\r
-01 00 11 00 00\r
-01 00 10 00 04\r
-01 00 0f 00 9A\r
-01 00 11 00 01\r
-01 00 11 00 00\r
-01 00 10 00 05\r
-01 00 0f 00 BC\r
-01 00 11 00 01\r
-01 00 11 00 00\r
-\r
-// Write 1 to register 14, MAC_rx_add_chk_en\r
-// This turns on the Rx Destination MAC address filter\r
-01 00 0e 00 01\r
-\r
-// Setup Tx and Rx MAC addresses and type field to "IP"\r
-// Set Tx Data at offset 0, length 14 to 123456789ABC CBA987654321 0800\r
-// (i.e. Destination MAC address is 123456789ABC matching the above)\r
-10 00 00 00 0E 12 34 56 78 9A BC CB A9 87 65 43 21 08 00\r
-\r
-// Transmit a 60-byte frame 1 time - and expect it to be received again!\r
-20 00 3C 00 01\r
-// Transmit a 61-byte frame 1 time - and expect it to be received again!\r
-20 00 3D 00 01\r
-// Transmit a 62-byte frame 1 time - and expect it to be received again!\r
-20 00 3E 00 01\r
-// Transmit a 63-byte frame 1 time - and expect it to be received again!\r
-20 00 3F 00 01\r
-// Transmit a 64-byte frame 1 time - and expect it to be received again!\r
-20 00 40 00 01\r
-\r
-// Transmit a 500-byte frame 1 time - and expect it to be received again!\r
-20 01 4C 00 01\r
-\r
-// Transmit a 1500-byte frame 1 time - and expect it to be received again!\r
-20 05 DC 00 01\r
-\r
-// Transmit a 1514-byte frame 1 time - and expect it to be received again!\r
-20 05 EA 00 01\r
-\r
-// Transmit a 60-byte frame 3 times - and expect them to be received again!\r
-20 00 3C 00 03\r
-// Transmit a 61-byte frame 3 times - and expect them to be received again!\r
-20 00 3D 00 03\r
-// Transmit a 62-byte frame 3 times - and expect them to be received again!\r
-20 00 3E 00 03\r
-// Transmit a 63-byte frame 3 times - and expect them to be received again!\r
-20 00 3F 00 03\r
-// Transmit a 64-byte frame 3 times - and expect them to be received again!\r
-20 00 40 00 03\r
-\r
-// Transmit a 1510-byte frame 1 time - and expect it to be received again!\r
-20 05 E6 00 01\r
-\r
-// Wait (indefinitely) for missing Rx packets\r
-22 00 00 \r
-\r
-// Change Tx MAC to something different - we won't receive frames with this ID\r
-10 00 00 00 06 11 22 33 44 55 66\r
-\r
-// Transmit a 60 byte frame 3 times - but don't expect them to be received!\r
-21 00 3C 00 03\r
-\r
-//// Change Tx MAC back to 12 34 56 78 9A BC\r
-10 00 00 00 06 12 34 56 78 9A BC\r
-\r
-// Transmit a 60 byte frame 3 times - and expect them to be received again!\r
-20 00 3C 00 03\r
-\r
-// Wait (indefinitely) for missing Rx packets\r
-22 00 00 \r
+++ /dev/null
-// This test demonstrates the ability to transmit a PAUSE frame, and the effect of\r
-// a PAUSE frame on the receiver\r
-\r
-// Read from register 24 to confirm that Rx CRC check is enabled\r
-03 00 18 00 01 ff ff\r
-\r
-// Set speed to 1000 Mbps\r
-01 00 22 00 04\r
-\r
-// Setup Tx and Rx MAC addresses and type field to "IP"\r
-// Set Tx Data at offset 0, length 14 to 123456789ABC CBA987654321 0800\r
-10 00 00 00 0E 12 34 56 78 9A BC CB A9 87 65 43 21 08 00\r
-\r
-// Set PAUSE quanta to 256 - corresponding to a pause of 256x512 = 128Kb = 16KB\r
-01 00 03 01 00\r
-\r
-// Enable the transmitter to send a PAUSE frame\r
-01 00 02 00 01\r
-\r
-// Enable the transmitter to react to received PAUSE frames\r
-01 00 0b 00 01\r
-\r
-// Expect to receive a PAUSE frame with quanta 256\r
-24 01 00\r
-\r
-// Transmit a 512-byte frame 1 time - and expect it to be received again!\r
-20 02 00 00 01\r
-\r
-// Request the transmission of a PAUSE frame - it will loopback to ourselves and delay\r
-// further transmission for a period of 16 KB, causing a significant (visible) delay\r
-// between first and second 512-byte frame!\r
-01 00 0c 00 01\r
-\r
-// - now this second time, we will experience a delay\r
-// Transmit a 512-byte frame 1 time - and expect it to be received again!\r
-20 02 00 00 01\r
-// - and a final 3rd time\r
-// Transmit a 512-byte frame 1 time - and expect it to be received again!\r
-20 02 00 00 01\r
-\r
-// Wait (indefinitely) for missing Rx packets\r
-22 00 00 \r
-\r
-// Halt\r
-FF\r
+++ /dev/null
-`timescale 1 ns / 1 ps\r
-\r
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// tb_top.v ////\r
-//// ////\r
-//// This file is part of the Ethernet IP core project ////\r
-//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////\r
-//// ////\r
-//// Author(s): ////\r
-//// - Jon Gao (gaojon@yahoo.com) ////\r
-//// ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// Copyright (C) 2001 Authors ////\r
-//// ////\r
-//// This source file may be used and distributed without ////\r
-//// restriction provided that this copyright statement is not ////\r
-//// removed from the file and that any derivative work contains ////\r
-//// the original copyright notice and the associated disclaimer. ////\r
-//// ////\r
-//// This source file is free software; you can redistribute it ////\r
-//// and/or modify it under the terms of the GNU Lesser General ////\r
-//// Public License as published by the Free Software Foundation; ////\r
-//// either version 2.1 of the License, or (at your option) any ////\r
-//// later version. ////\r
-//// ////\r
-//// This source is distributed in the hope that it will be ////\r
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\r
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\r
-//// PURPOSE. See the GNU Lesser General Public License for more ////\r
-//// details. ////\r
-//// ////\r
-//// You should have received a copy of the GNU Lesser General ////\r
-//// Public License along with this source; if not, download it ////\r
-//// from http://www.opencores.org/lgpl.shtml ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-// \r
-// CVS Revision History \r
-// \r
-// $Log: tb_top.v,v $\r
-// Revision 1.3 2006/01/19 14:07:51 maverickist\r
-// verification is complete.\r
-//\r
-// Revision 1.2 2005/12/16 06:44:13 Administrator\r
-// replaced tab with space.\r
-// passed 9.6k length frame test.\r
-//\r
-// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator\r
-// no message\r
-// \r
-\r
-module tb_top;\r
-\r
- //-------------------- Instantiate Xilinx glbl module ----------------------\r
- // - this is needed to get ModelSim to work because e.g. I/O buffer models\r
- // refer directly to glbl.GTS and similar signals\r
-\r
- wire GSR;\r
- wire GTS;\r
- xlnx_glbl glbl( .GSR( GSR ), .GTS( GTS ) );\r
-\r
- reg VLOG_ExitSignal = 0;\r
- reg Done = 0;\r
- reg Error = 0;\r
-\r
- //-------------------------------------------------------------------------\r
-\r
- // System signals\r
- wire Reset;\r
- reg Clk_125M;\r
- reg Clk_user;\r
-\r
- reg RST_I;\r
- reg CLK_I;\r
- reg STB_I;\r
- reg CYC_I;\r
- reg [6:0] ADR_I;\r
- reg WE_I;\r
- reg [15:0] DAT_I;\r
- wire [15:0] DAT_O;\r
- wire ACK_O;\r
-\r
- // User interface (Rx)\r
- wire Rx_mac_ra;\r
- reg Rx_mac_rd = 0;\r
- wire [31:0] Rx_mac_data;\r
- wire [1:0] Rx_mac_BE;\r
- wire Rx_mac_pa;\r
- wire Rx_mac_sop;\r
- wire Rx_mac_err;\r
- wire Rx_mac_eop;\r
-\r
- // User interface (Tx)\r
- wire Tx_mac_wa;\r
- reg Tx_mac_wr = 0;\r
- reg [31:0] Tx_mac_data = 32'bx;\r
- reg [1:0] Tx_mac_BE = 2'bx;\r
- reg Tx_mac_sop = 1'bx;\r
- reg Tx_mac_eop = 1'bx;\r
-\r
- // PHY interface (GMII/MII)\r
- wire Gtx_clk;\r
- wire Rx_clk;\r
- wire Tx_clk;\r
- wire Tx_er;\r
- wire Tx_en;\r
- wire [7:0] Txd;\r
- wire Rx_er;\r
- wire Rx_dv;\r
- wire [7:0] Rxd;\r
- wire Crs;\r
- wire Col;\r
-\r
- // PHY int host interface\r
-\r
- wire Line_loop_en;\r
- wire [2:0] Speed;\r
-\r
- // MDIO interface\r
- wire Mdio; // MII Management Data In\r
- wire Mdc; // MII Management Data Clock\r
-\r
- //-------------------------------------------------------------------------\r
-\r
- // Generate generic reset signal from Wishbone specific one\r
- assign Reset = RST_I;\r
-\r
- MAC_top U_MAC_top(\r
- // System signals\r
- .Clk_125M ( Clk_125M ),\r
- .Clk_user ( Clk_user ),\r
- .Speed ( Speed ),\r
-\r
- // Wishbone compliant core host interface\r
- .RST_I ( RST_I ),\r
- .CLK_I ( CLK_I ),\r
- .STB_I ( STB_I ),\r
- .CYC_I ( CYC_I ),\r
- .ADR_I ( ADR_I ),\r
- .WE_I ( WE_I ),\r
- .DAT_I ( DAT_I ),\r
- .DAT_O ( DAT_O ),\r
- .ACK_O ( ACK_O ),\r
-\r
- // User (packet) interface\r
- .Rx_mac_ra ( Rx_mac_ra ), \r
- .Rx_mac_rd ( Rx_mac_rd ),\r
- .Rx_mac_data( Rx_mac_data ),\r
- .Rx_mac_BE ( Rx_mac_BE ),\r
- .Rx_mac_pa ( Rx_mac_pa ),\r
- .Rx_mac_sop ( Rx_mac_sop ),\r
- .Rx_mac_err ( Rx_mac_err ),\r
- .Rx_mac_eop ( Rx_mac_eop ),\r
-\r
- .Tx_mac_wa ( Tx_mac_wa ),\r
- .Tx_mac_wr ( Tx_mac_wr ),\r
- .Tx_mac_data( Tx_mac_data ),\r
- .Tx_mac_BE ( Tx_mac_BE ),\r
- .Tx_mac_sop ( Tx_mac_sop ),\r
- .Tx_mac_eop ( Tx_mac_eop ),\r
-\r
- // PHY interface (GMII/MII)\r
- .Gtx_clk ( Gtx_clk ),\r
- .Rx_clk ( Rx_clk ),\r
- .Tx_clk ( Tx_clk ),\r
- .Tx_er ( Tx_er ),\r
- .Tx_en ( Tx_en ),\r
- .Txd ( Txd ),\r
- .Rx_er ( Rx_er ),\r
- .Rx_dv ( Rx_dv ),\r
- .Rxd ( Rxd ),\r
- .Crs ( Crs ),\r
- .Col ( Col ),\r
-\r
- // MDIO interface (to PHY)\r
- .Mdio ( Mdio ),\r
- .Mdc ( Mdc )\r
- );\r
-\r
- reg [15:0] InjectError;\r
- reg InjectErrorDone;\r
- reg [15:0] TxError;\r
- wire Tx_er_Modified;\r
- wire Tx_en_Modified;\r
- wire [7:0] Txd_Modified;\r
-\r
- Phy_sim U_Phy_sim(\r
- .Gtx_clk( Gtx_clk ),\r
- .Rx_clk ( Rx_clk ),\r
- .Tx_clk ( Tx_clk ),\r
- .Tx_er ( Tx_er_Modified ),\r
- .Tx_en ( Tx_en_Modified ),\r
- .Txd ( Txd_Modified ),\r
- .Rx_er ( Rx_er ),\r
- .Rx_dv ( Rx_dv ),\r
- .Rxd ( Rxd ),\r
- .Crs ( Crs ),\r
- .Col ( Col ),\r
- .Speed ( Speed ),\r
- .Done ( Done )\r
- );\r
-\r
- integer TxTrackPreAmble;\r
-\r
- always @( posedge Reset or posedge Tx_clk )\r
- if ( Reset )\r
- TxTrackPreAmble <= 0;\r
- else\r
- if ( ~Tx_en )\r
- TxTrackPreAmble <= 0;\r
- else\r
- TxTrackPreAmble <= TxTrackPreAmble + 1;\r
-\r
- // Asserted after the Destination MAC address in the packet\r
- wire TxInPayload = Tx_en & (TxTrackPreAmble > (7+6));\r
- assign Tx_er_Modified = Tx_er ^ ( TxError[9] & TxInPayload );\r
- assign Tx_en_Modified = Tx_en ^ ( TxError[8] & TxInPayload );\r
- assign Txd_Modified = Txd ^ ( TxError[7:0] & {8{TxInPayload}} );\r
-\r
- always @( posedge Reset or posedge Tx_clk )\r
- if ( Reset )\r
- begin\r
- InjectError <= 0;\r
- InjectErrorDone <= 0;\r
- TxError <= 'b0;\r
- end\r
- else\r
- if ( InjectError )\r
- begin\r
- TxError <= InjectError;\r
- InjectError <= 0;\r
- InjectErrorDone <= TxInPayload;\r
- end\r
- else if ( TxInPayload || InjectErrorDone )\r
- begin\r
- TxError <= 8'h00;\r
- InjectErrorDone <= 0;\r
- end\r
-\r
- //-------------------------------------------------------------------------\r
- // Track pause on Tx interface\r
-\r
- reg TxEnSeenOnce; \r
- integer TxTrackPause;\r
-\r
- always @( posedge Reset or posedge Tx_clk )\r
- if ( Reset )\r
- begin\r
- TxEnSeenOnce <= 0;\r
- TxTrackPause <= 0;\r
- end\r
- else\r
- if ( Tx_en )\r
- begin\r
- if ( TxEnSeenOnce && (TxTrackPause >= 64) ) // 512 bits\r
- $display( "IDLE period on Tx interface ended after %0d Tx clocks (%0d bits, tick ~ %0d)",\r
- TxTrackPause,\r
- (Speed == 4) ? TxTrackPause*8 : TxTrackPause*4,\r
- (Speed == 4) ? TxTrackPause*8/512 : TxTrackPause*4/512 );\r
- TxEnSeenOnce <= 1;\r
- TxTrackPause <= 0;\r
- end\r
- else\r
- TxTrackPause <= TxTrackPause + 1;\r
-\r
- //-------------------------------------------------------------------------\r
- // Host access routines (register read & write)\r
- //-------------------------------------------------------------------------\r
-\r
- task HostInit;\r
- begin\r
- RST_I <= 1;\r
-\r
- STB_I <= 0;\r
- CYC_I <= 0;\r
- ADR_I <= 'b0;\r
- WE_I <= 0;\r
- DAT_I <= 'b0;\r
-\r
- #100 RST_I <= 0;\r
-\r
- // Wait a couple of clock edges before continuing to allow\r
- // internal logic to get out of reset\r
- repeat( 2 )\r
- @( posedge CLK_I );\r
- end\r
- endtask\r
- \r
- task HostWriteReg;\r
- input [6:0] Addr;\r
- input [15:0] Data;\r
- begin\r
- @( posedge CLK_I );\r
- ADR_I <= Addr;\r
- DAT_I <= Data;\r
- WE_I <= 1;\r
- STB_I <= 1;\r
- CYC_I <= 1;\r
-\r
- @( posedge CLK_I );\r
-\r
- while ( ~ACK_O )\r
- @( posedge CLK_I );\r
-\r
- STB_I <= 0;\r
- CYC_I <= 0;\r
- end\r
- endtask\r
- \r
- task HostReadReg;\r
- input [6:0] Addr;\r
- output [15:0] Data;\r
- begin\r
- @( posedge CLK_I );\r
- ADR_I <= Addr;\r
- WE_I <= 0;\r
- STB_I <= 1;\r
- CYC_I <= 1;\r
-\r
- @( posedge CLK_I );\r
-\r
- while ( ~ACK_O )\r
- @( posedge CLK_I );\r
-\r
- Data = DAT_O;\r
- STB_I <= 0;\r
- CYC_I <= 0;\r
- end\r
- endtask\r
-\r
- //-------------------------------------------------------------------------\r
- // User interface access routines (packet Tx and Rx)\r
- //-------------------------------------------------------------------------\r
-\r
- `define FIFOSIZE 10000\r
-\r
- integer FIFO_WrPtr = 0;\r
- integer FIFO_RdPtr = 0;\r
- integer FIFO_ElementCount = 0;\r
- reg [35:0] FIFO_Data[0:`FIFOSIZE];\r
-\r
- function FIFO_Empty;\r
- input Dummy;\r
- begin\r
- if ( FIFO_ElementCount > 0 )\r
- FIFO_Empty = 0;\r
- else\r
- FIFO_Empty = 1;\r
- end\r
- endfunction\r
-\r
- function FIFO_Full;\r
- input Dummy;\r
- begin\r
- if ( FIFO_ElementCount < `FIFOSIZE )\r
- FIFO_Full = 0;\r
- else\r
- FIFO_Full = 1;\r
- end\r
- endfunction\r
-\r
- task FIFO_Wr;\r
- input [35:0] Data;\r
-\r
- begin\r
- if ( !FIFO_Full(0) )\r
- begin\r
- FIFO_Data[ FIFO_WrPtr ] = Data;\r
- FIFO_WrPtr = (FIFO_WrPtr + 1) % `FIFOSIZE;\r
- FIFO_ElementCount = FIFO_ElementCount + 1;\r
- end\r
- else\r
- begin\r
- $display( "ERROR: FIFO_Wr() - FIFO overflow!" );\r
- Error = 1;\r
- $finish;\r
- end\r
- end\r
- endtask\r
-\r
- task FIFO_Rd;\r
- output [35:0] Data;\r
-\r
- begin\r
- if ( !FIFO_Empty(0) )\r
- begin\r
- Data = FIFO_Data[ FIFO_RdPtr ];\r
- FIFO_RdPtr = (FIFO_RdPtr + 1) % `FIFOSIZE;\r
- FIFO_ElementCount = FIFO_ElementCount - 1;\r
- end\r
- else\r
- begin\r
- $display( "ERROR: FIFO_Rd() - Reading from empty FIFO!" );\r
- Error = 1;\r
- $finish;\r
- end\r
- end\r
- endtask\r
-\r
- //-------------------------------------------------------------------------\r
-\r
- `define TXDATALEN 8000\r
- reg [7:0] TxData[0:`TXDATALEN-1];\r
- reg [7:0] TxAltData[0:`TXDATALEN-1];\r
-\r
- // By default change payload after Ethernet Header\r
- reg [15:0] TxHeaderLength = 14;\r
-\r
- real TxStartTime;\r
- integer TxPacketCount = 0;\r
- integer TxByteCount;\r
-\r
- task SendPacket;\r
- input [15:0] Length;\r
- // 0: Don't write to FIFO, 1: Write to FIFO, 2: Write Alternate to FIFO, 3: Write IGNORE to FIFO\r
- input [1:0] Wr2FIFO;\r
-\r
- reg [15:0] Counter;\r
- integer TxIndex;\r
- integer i;\r
-\r
- reg [31:0] Tx_fifo_data;\r
-\r
- begin\r
- @( posedge Clk_user ); #1;\r
-\r
- TxPacketCount = TxPacketCount + 1;\r
- TxByteCount = TxByteCount + Length;\r
-\r
- Counter=Length;\r
- TxIndex = 0;\r
- Tx_mac_sop = 1; // First time\r
-\r
- if ( TxStartTime == 0 )\r
- TxStartTime = $realtime;\r
-\r
- while ( Counter>0 )\r
- begin\r
- while ( !Tx_mac_wa )\r
- begin\r
- Tx_mac_wr = 0;\r
- @( posedge Clk_user ); #1;\r
- end\r
-\r
- Tx_mac_data[31:24] = TxData[ TxIndex ];\r
- Tx_mac_data[23:16] = TxData[ TxIndex+1 ];\r
- Tx_mac_data[15:8] = TxData[ TxIndex+2 ];\r
- Tx_mac_data[ 7:0] = TxData[ TxIndex+3 ];\r
-\r
- // Default take data from regular tx buffer\r
- Tx_fifo_data = Tx_mac_data;\r
- if ( Wr2FIFO==2 )\r
- begin\r
- // Put content of Alternate Tx buffer on Rx expectancy queue\r
- if ( (TxIndex+0)<TxHeaderLength )\r
- Tx_fifo_data[31:24] = TxAltData[ TxIndex ];\r
- if ( (TxIndex+1)<TxHeaderLength )\r
- Tx_fifo_data[23:16] = TxAltData[ TxIndex+1 ];\r
- if ( (TxIndex+2)<TxHeaderLength )\r
- Tx_fifo_data[15:8] = TxAltData[ TxIndex+2 ];\r
- if ( (TxIndex+3)<TxHeaderLength )\r
- Tx_fifo_data[ 7:0] = TxAltData[ TxIndex+3 ];\r
- end\r
-\r
- for ( i=0; i<4; i=i+1 )\r
- begin\r
- if ( TxIndex >= TxHeaderLength )\r
- TxData[ TxIndex ] = TxData[ TxIndex ] + 1;\r
- TxIndex = TxIndex+1;\r
- end\r
-\r
- if ( Counter<=4 )\r
- begin\r
- // Indicate how many bytes are valid\r
- if ( Counter==4 )\r
- Tx_mac_BE = 2'b00;\r
- else\r
- Tx_mac_BE = Counter;\r
- Tx_mac_eop = 1;\r
- end\r
- else\r
- begin\r
- Tx_mac_BE = 2'b00;\r
- Tx_mac_eop = 0;\r
- end\r
-\r
- casez ( Wr2FIFO )\r
- 1,\r
- 2: FIFO_Wr( { Tx_mac_sop, Tx_mac_eop, Tx_mac_BE, Tx_fifo_data } );\r
- 3: // Ignore\r
- begin\r
- FIFO_Wr( { 2'b11, 2'b00, 32'h00000000 } );\r
- Wr2FIFO = 0;\r
- end\r
- endcase\r
-\r
- Tx_mac_wr = 1;\r
-\r
- if ( Counter >= 4 )\r
- Counter = Counter - 4;\r
- else\r
- Counter = 0;\r
- @( posedge Clk_user ); #1;\r
- Tx_mac_sop = 0;\r
- end\r
-\r
- Tx_mac_sop = 1'bx;\r
- Tx_mac_eop = 1'bx;\r
- Tx_mac_wr = 0;\r
- Tx_mac_data = 32'bx;\r
- Tx_mac_BE = 2'bx;\r
- end\r
- endtask\r
-\r
- //-------------------------------------------------------------------------\r
-\r
- reg Negate_Rx_mac_rd;\r
-\r
- always @( posedge Clk_user or posedge Reset )\r
- if ( Reset )\r
- Rx_mac_rd <= 0;\r
- else if ( Rx_mac_ra & ~Negate_Rx_mac_rd )\r
- Rx_mac_rd <= 1;\r
- else\r
- Rx_mac_rd <= 0;\r
-\r
- real RxStartTime;\r
- integer RxPacketCount;\r
- integer RxByteCount;\r
-\r
- reg InPacket;\r
- integer RxPacketLength;\r
- reg IgnoreUntilNextERR;\r
-\r
- always @( posedge Clk_user or posedge Reset )\r
- if ( Reset )\r
- begin\r
- InPacket = 0;\r
- RxPacketCount = 0;\r
- Negate_Rx_mac_rd <= 0;\r
- IgnoreUntilNextERR = 0;\r
- end\r
- else\r
- begin\r
- Negate_Rx_mac_rd <= 0;\r
-\r
- if ( Rx_mac_pa )\r
- begin : RxWord\r
- reg [35:0] RxData;\r
- reg [35:0] Expected;\r
- reg [35:0] Mask;\r
-\r
- RxData = { Rx_mac_sop, Rx_mac_eop, Rx_mac_BE, Rx_mac_data };\r
- casez ( Rx_mac_BE )\r
- 2'b01: Mask = 36'hfff000000;\r
- 2'b10: Mask = 36'hfffff0000;\r
- 2'b11: Mask = 36'hfffffff00;\r
- default: Mask = 36'hfffffffff;\r
- endcase\r
-\r
- // Retrieve expected packet data\r
-\r
- if ( !IgnoreUntilNextERR )\r
- begin\r
- FIFO_Rd( Expected );\r
- if ( Expected[35] & Expected[34] )\r
- begin\r
- // Both SOP & EOP are asserted in expectancy data\r
- // - this means that we should ignore all data received until next EOP\r
- $display( "The payload of this packet will be IGNORED - and an ERROR must be signalled!" );\r
- IgnoreUntilNextERR = 1;\r
- end\r
- end\r
- if ( IgnoreUntilNextERR )\r
- Mask = 36'h000000000;\r
-\r
- //$display( "DEBUG: RxData=0x%0x, Expected=0x%0x", RxData, Expected );\r
-\r
- if ( (RxData & Mask) !== (Expected & Mask) )\r
- begin\r
- $display( "ERROR: Receiving unexpected packet data: Got 0x%0x, expected 0x%0x (Mask=0x%0x)",\r
- RxData, Expected, Mask );\r
- Error = 1;\r
- end\r
-\r
- if ( InPacket )\r
- begin\r
- if ( Rx_mac_eop )\r
- begin\r
- // Ensure Rx_mac_rd is negated for one clock\r
- Negate_Rx_mac_rd <= 1;\r
- if ( Rx_mac_BE==2'b00 )\r
- RxPacketLength = RxPacketLength + 4;\r
- else\r
- RxPacketLength = RxPacketLength + Rx_mac_BE;\r
- $display( "Rx packet #%0d of length %0d ends",\r
- RxPacketCount,\r
- RxPacketLength );\r
- RxPacketCount = RxPacketCount + 1;\r
- RxByteCount = RxByteCount + RxPacketLength;\r
- InPacket = 0;\r
- end\r
- else\r
- RxPacketLength = RxPacketLength + 4;\r
- end\r
- else\r
- begin\r
- if ( Rx_mac_sop )\r
- begin\r
- RxPacketLength = 4;\r
- $display( "Rx packet #%0d begins: 0x%08x", RxPacketCount, Rx_mac_data );\r
- InPacket = 1;\r
- if ( RxStartTime == 0 )\r
- RxStartTime = $realtime;\r
- end\r
- else\r
- begin\r
- $display( "ERROR: Unexpectedly reading from Rx FIFO while not receiving a packet!" );\r
- Error = 1;\r
- end\r
- end\r
-\r
- if ( Rx_mac_err )\r
- begin\r
- if ( !Rx_mac_eop )\r
- begin\r
- $display( "ERROR: Rx_mac_err was asserted without Rx_mac_eop also being asserted!" );\r
- Error = 1;\r
- end\r
- if ( IgnoreUntilNextERR )\r
- $display( "Info: Rx_mac_err was asserted as expected!" );\r
- else\r
- begin\r
- $display( "ERROR: Rx_mac_err was unexpectedly asserted!" );\r
- Error = 1;\r
- end\r
- IgnoreUntilNextERR = 0;\r
- end\r
- end\r
- end\r
-\r
- //-------------------------------------------------------------------------\r
- // Script handling\r
- //-------------------------------------------------------------------------\r
-\r
- integer PC;\r
-\r
- task ScriptWriteReg;\r
- input [15:0] Addr;\r
- input [15:0] Data;\r
-\r
- begin\r
- $display( "WriteReg( 0x%04x, 0x%04x )", Addr, Data );\r
- HostWriteReg( Addr, Data );\r
- end\r
- endtask\r
-\r
- task ScriptReadReg;\r
- input [15:0] Addr;\r
-\r
- reg [15:0] Data;\r
-\r
- begin\r
- $write( "ReadReg( 0x%04x ): ", Addr );\r
- HostReadReg( Addr, Data );\r
- $display( "0x%04x", Data );\r
- end\r
- endtask\r
-\r
- task ScriptReadRegAndMatch;\r
- input [15:0] Addr;\r
- input [15:0] Data;\r
- input [15:0] Mask;\r
-\r
- reg [15:0] Read;\r
-\r
- begin\r
- $write( "ReadRegAndMatch( 0x%04x, 0x%04x, 0x%04x ): ", Addr, Data, Mask );\r
-\r
- HostReadReg( Addr, Read );\r
- $display( "0x%04x, masked=0x%04x", Read, Read & Mask );\r
-\r
- if ( Data !== (Read & Mask) )\r
- begin\r
- $display( "Error: Unexpected data read" );\r
- Error = 1;\r
- end\r
- end\r
- endtask\r
-\r
- integer RxExpectPacketCount = 0;\r
-\r
- task ScriptSendPacket;\r
- input [15:0] Length;\r
- // 0: Don't receive, 1: Receive & match, 2: Receive & match alternate, 3: Receive & ignore\r
- input [1:0] ExpectToRx;\r
-\r
- begin\r
- $display( "ScriptSendPacket( 0x%04x, %0d )", Length, ExpectToRx );\r
- SendPacket( Length, ExpectToRx );\r
- if ( ExpectToRx != 0 )\r
- RxExpectPacketCount = RxExpectPacketCount + 1;\r
- end\r
- endtask\r
-\r
- `define SCRIPTLEN 10000\r
- integer i;\r
- reg [7:0] Script[0:`SCRIPTLEN-1];\r
-\r
- function [15:0] Get16bit;\r
- input Dummy;\r
-\r
- reg [15:0] Data;\r
-\r
- begin\r
- Data[15:8] = Script[PC];\r
- Data[7:0] = Script[PC+1];\r
- PC = PC+2;\r
-\r
- Get16bit = Data;\r
- end\r
- endfunction\r
-\r
- task ExecuteScript;\r
-\r
- reg [7:0] OpCode;\r
- reg [15:0] Addr;\r
- reg [15:0] Data;\r
- reg [15:0] Length;\r
- reg [15:0] Count;\r
- reg [15:0] Mask;\r
-\r
- reg ScriptDone;\r
-\r
- begin\r
- ScriptDone = 0;\r
- Error = 0;\r
- PC = 0;\r
- \r
- while ( !ScriptDone )\r
- begin\r
- OpCode = Script[PC];\r
- //$write( "PC=%0d, OpCode=%02x: ", PC, OpCode );\r
- PC = PC+1;\r
- \r
- casez ( OpCode )\r
- 8'h00: // NOP\r
- begin\r
-// $display( "NOP" );\r
- #10;\r
- end\r
- 8'h01: // Write\r
- begin\r
- Addr = Get16bit(i);\r
- Data = Get16bit(i);\r
- ScriptWriteReg( Addr, Data );\r
- end\r
- 8'h02: // Read\r
- begin\r
- Addr = Get16bit(i);\r
- ScriptReadReg( Addr );\r
- end\r
- 8'h03: // Read & match\r
- begin\r
- Addr = Get16bit(i);\r
- Data = Get16bit(i);\r
- Mask = Get16bit(i);\r
- ScriptReadRegAndMatch( Addr, Data, Mask );\r
- end\r
-\r
- 8'h0f: // Delay\r
- begin\r
- Count = Get16bit(i);\r
- $display( "Delay %0d", Count );\r
- while ( Count > 0 )\r
- begin\r
- #10;\r
- Count = Count - 1;\r
- end\r
- end\r
-\r
- 8'h10: // Setup Tx Data\r
- begin\r
- Addr = Get16bit(i);\r
- Length = Get16bit(i);\r
- $write( "TxData( 0x%04x ), length=%0d: ", Addr, Length );\r
- while ( Length != 0 )\r
- begin\r
- TxData[Addr] = Script[PC];\r
- $write( " 0x%02x", Script[PC] );\r
- PC = PC + 1;\r
- Addr = Addr + 1;\r
- Length = Length - 1;\r
- end\r
- $display( "" );\r
- end\r
-\r
- 8'h11: // Setup Alternative Tx Data\r
- begin\r
- Addr = Get16bit(i);\r
- Length = Get16bit(i);\r
- $write( "TxAltData( 0x%04x ), length=%0d: ", Addr, Length );\r
- while ( Length != 0 )\r
- begin\r
- TxAltData[Addr] = Script[PC];\r
- $write( " 0x%02x", Script[PC] );\r
- PC = PC + 1;\r
- Addr = Addr + 1;\r
- Length = Length - 1;\r
- end\r
- $display( "" );\r
- end\r
-\r
- 8'h20: // Transmit packet - and put it on Rx expectancy queue\r
- begin\r
- Length = Get16bit(i); // Length in bytes\r
- Count = Get16bit(i); // Number of times\r
- while ( Count != 0 )\r
- begin\r
- ScriptSendPacket( Length, 1 );\r
- Count = Count - 1;\r
- end\r
- end\r
-\r
- 8'h21: // Transmit packet - but DON'T put it on Rx expectancy queue\r
- begin\r
- Length = Get16bit(i); // Length in bytes\r
- Count = Get16bit(i); // Number of times\r
- while ( Count != 0 )\r
- begin\r
- ScriptSendPacket( Length, 0 );\r
- Count = Count - 1;\r
- end\r
- end\r
-\r
- 8'h22: // Wait\r
- begin : OpCode22\r
- reg NoTimeOut;\r
- Count = Get16bit(i); // Timeout in ns\r
- if ( Count==0 )\r
- NoTimeOut = 1;\r
- else\r
- NoTimeOut = 0;\r
-\r
- $display( "Waiting for # of Rx packets = # of Tx packets..." );\r
- $display( "Timeout = %0d ns - Current # Rx =%0d, Expected=%0d",\r
- Count, RxPacketCount, RxExpectPacketCount );\r
-\r
- while( (NoTimeOut || (Count != 0)) && ( RxExpectPacketCount != RxPacketCount ) && !Error )\r
- begin\r
- #1;\r
- if ( !NoTimeOut )\r
- Count = Count - 1;\r
- //$display( "NoTimeOut=%0d, Count=%0d", NoTimeOut, Count );\r
- end\r
-\r
- if ( !Error )\r
- if ( RxExpectPacketCount != RxPacketCount )\r
- begin\r
- $display( "ERROR: Timeout waiting for Rx packet(s)!" );\r
- ScriptDone = 1;\r
- Error = 1;\r
- end\r
- else\r
- $display( "...Done waiting (time remaining = %0d ns)!", Count );\r
- end\r
-\r
- 8'h23: // Inject bit error in Tx packet\r
- begin\r
- InjectError = Get16bit(i); // Get bit error pattern\r
- $display( "Injecting a single bit-error in Tx packet: TxEr=%0d, TxEn=%0d, TxD=0x%02h (0x%03h)",\r
- InjectError[9], InjectError[8], InjectError[7:0], InjectError );\r
- end\r
-\r
- 8'h24: // Store internally generated PAUSE frame in Rx expect queue\r
- begin\r
- Count = Get16bit(i); // Timeout in ns\r
- $display( "Generating PAUSE frame (tick=%0d) on Rx expect queue", Count );\r
- RxExpectPacketCount = RxExpectPacketCount + 1;\r
- FIFO_Wr( { 1'b1, 1'b0, 2'b00, 32'h0180c200 } );\r
- FIFO_Wr( { 1'b0, 1'b0, 2'b00, 16'h0001, 16'h0000 } );\r
- FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h00000000 } );\r
- FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h88080001 } );\r
- FIFO_Wr( { 1'b0, 1'b0, 2'b00, Count, 16'h0000 } );\r
- FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h00000000 } );\r
- FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h00000000 } );\r
- FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h00000000 } );\r
- FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h00000000 } );\r
- FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h00000000 } );\r
- FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h00000000 } );\r
- FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h00000000 } );\r
- FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h00000000 } );\r
- FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h00000000 } );\r
- FIFO_Wr( { 1'b0, 1'b1, 2'b00, 32'h00000000 } );\r
- end\r
-\r
- 8'h25: // Transmit packet - and indicate that it must be IGNORED upon reception\r
- begin\r
- Length = Get16bit(i); // Length in bytes\r
- Count = Get16bit(i); // Number of times\r
- while ( Count != 0 )\r
- begin\r
- ScriptSendPacket( Length, 3 );\r
- Count = Count - 1;\r
- end\r
- end\r
-\r
- 8'h26: // Transmit packet - and put it on expectancy queue with Alternate header!\r
- begin\r
- Length = Get16bit(i); // Length in bytes\r
- Count = Get16bit(i); // Number of times\r
- while ( Count != 0 )\r
- begin\r
- ScriptSendPacket( Length, 2 );\r
- Count = Count - 1;\r
- end\r
- end\r
-\r
- 8'hff: // Halt\r
- begin\r
- $display( "HALT" );\r
- ScriptDone = 1;\r
- Done = 1;\r
- end\r
-\r
- default: // Unknown opcode\r
- begin\r
- $display( "Unknown instruction encountered @ PC=%0d: OpCode=0x%02x", PC-1, OpCode );\r
- Error = 1;\r
- end\r
-\r
- endcase\r
-\r
- if ( Error )\r
- begin\r
- ScriptDone = 1;\r
- Done = 1;\r
- end\r
- end\r
-\r
- if ( Error )\r
- $display( "ERROR: Test failed!");\r
- else\r
- begin : ScriptSuccess\r
- real TxTimeElapsed;\r
- real RxTimeElapsed;\r
- real ReferenceTime;\r
-\r
- ReferenceTime = $realtime;\r
- #1;\r
- ReferenceTime = $realtime - ReferenceTime;\r
-\r
- TxTimeElapsed = $realtime - TxStartTime;\r
- RxTimeElapsed = $realtime - RxStartTime;\r
-\r
- $display( "TxStartTime=%0e, Now=%0e", TxStartTime, $realtime );\r
- $display( "RxStartTime=%0e, Now=%0e", RxStartTime, $realtime );\r
- \r
- $display( "Tx stats: %0d packet(s) send, total of %0d bytes in %0e ns ~ %1.2f Mbps",\r
- TxPacketCount, TxByteCount, TxTimeElapsed, TxByteCount*8*1e3/TxTimeElapsed );\r
- $display( "Rx stats: %0d packet(s) received, total of %0d bytes in %0e ns ~ %1.2f Mbps",\r
- RxPacketCount, RxByteCount, RxTimeElapsed, RxByteCount*8*1e3/RxTimeElapsed );\r
- $display( "Test succeeded!");\r
- end\r
-\r
- end\r
- endtask\r
-\r
- //-------------------------------------------------------------------------\r
- // Generate all clocks\r
- //-------------------------------------------------------------------------\r
-\r
- // GMII master clock (125 MHz)\r
- initial \r
- begin\r
- #10;\r
- while ( !Done )\r
- begin\r
- #4 Clk_125M = 0;\r
- #4 Clk_125M = 1;\r
- end\r
- end\r
-\r
- // User (packet) interface clock (100 MHz)\r
- initial \r
- begin\r
- #10;\r
- while ( !Done )\r
- begin\r
- #5 Clk_user = 0;\r
- #5 Clk_user = 1;\r
- end\r
- end\r
-\r
- // Wishbone host interface clock (50 MHz)\r
- initial\r
- begin\r
- #10;\r
- while ( !Done )\r
- begin\r
- #10 CLK_I = 0;\r
- #10 CLK_I = 1;\r
- end\r
- end\r
-\r
- //-------------------------------------------------------------------------\r
-\r
- initial\r
- begin\r
- if ( $test$plusargs( "vcd" ) )\r
- begin\r
- $display( "Turning VCD data dump on" );\r
- $dumpfile();\r
- $dumpvars( 0 ); // Dump all signals in entire design\r
- end\r
- end\r
-\r
- //-------------------------------------------------------------------------\r
-\r
- reg [1023:0] ScriptFile;\r
-\r
- initial\r
- begin\r
- HostInit;\r
-\r
- TxStartTime = 0;\r
- RxStartTime = 0;\r
- TxByteCount = 0;\r
- RxByteCount = 0;\r
-\r
- for ( i=0; i<`TXDATALEN; i=i+1 )\r
- TxData[i] = (i & 8'hff);\r
-\r
- // Fill script memory with HALTs\r
- for ( i=0; i<`SCRIPTLEN; i=i+1 )\r
- Script[i] = 8'hff;\r
-\r
- if ( !$value$plusargs( "script=%s", ScriptFile ) )\r
- begin\r
- $display( "Using default script file" );\r
- ScriptFile = "test.scr";\r
- end\r
-\r
- $readmemh( ScriptFile, Script );\r
-\r
-// for ( i=0; i<40; i=i+1 )\r
-// $display( "Script[%0d]=0x%02x", i, Script[i] );\r
-\r
- #10;\r
-\r
- ExecuteScript;\r
- end\r
-\r
-endmodule\r
+++ /dev/null
-// This tests just runs trough a couple of different packet lengths\r
-\r
-// Read from register 24 to confirm that Rx CRC check is enabled\r
-03 00 18 00 01 ff ff\r
-\r
-// Set speed to 1000 Mbps\r
-01 00 22 00 04\r
-\r
-// Setup Tx and Rx MAC addresses and type field to "IP"\r
-// Set Tx Data at offset 0, length 14 to 123456789ABC CBA987654321 0800\r
-10 00 00 00 0E 12 34 56 78 9A BC CB A9 87 65 43 21 08 00\r
-\r
-// Transmit a 320-byte frame 1 time - and expect it to be received again!\r
-20 01 40 00 01\r
-\r
-// Transmit a 80-byte frame 1 time - and expect it to be received again!\r
-20 00 50 00 01\r
-\r
-// Wait (indefinitely) for missing Rx packets\r
-22 00 00 \r
-\r
-// Halt\r
-FF\r
+++ /dev/null
-// Read from register 24 to confirm that Rx CRC check is enabled\r
-03 00 18 00 01 ff ff\r
-\r
-// Set speed to 1000 Mbps\r
-01 00 22 00 04\r
-\r
-// Write MAC address 12 35 56 78 9A BC to Rx Address buffer\r
-01 00 10 00 00\r
-01 00 0f 00 12\r
-01 00 11 00 01\r
-01 00 11 00 00\r
-01 00 10 00 01\r
-01 00 0f 00 34\r
-01 00 11 00 01\r
-01 00 11 00 00\r
-01 00 10 00 02\r
-01 00 0f 00 56\r
-01 00 11 00 01\r
-01 00 11 00 00\r
-01 00 10 00 03\r
-01 00 0f 00 78\r
-01 00 11 00 01\r
-01 00 11 00 00\r
-01 00 10 00 04\r
-01 00 0f 00 9A\r
-01 00 11 00 01\r
-01 00 11 00 00\r
-01 00 10 00 05\r
-01 00 0f 00 BC\r
-01 00 11 00 01\r
-01 00 11 00 00\r
-\r
-// Write 1 to register 14, MAC_rx_add_chk_en\r
-// This turns on the Rx Destination MAC address filter\r
-01 00 0e 00 01\r
-\r
-// Setup Tx and Rx MAC addresses and type field to "IP"\r
-// Set Tx Data at offset 0, length 14 to 123456789ABC CBA987654321 0800\r
-// (i.e. Destination MAC address is 123456789ABC matching the above)\r
-10 00 00 00 0E 12 34 56 78 9A BC CB A9 87 65 43 21 08 00\r
-\r
-// Setup Alternate Tx and Rx MAC addresses and type field to "IP"\r
-// Set Tx Data at offset 0, length 14 to 123456789ABC 112233445566 0800\r
-// (i.e. Destination MAC address is 123456789ABC matching the above)\r
-11 00 00 00 0E 12 34 56 78 9A BC 11 22 33 44 55 66 08 00\r
-\r
-// Transmit a 60-byte frame 3 times - and expect them to be received again!\r
-20 00 3C 00 03\r
-\r
-// Wait (indefinitely) for missing Rx packets\r
-22 00 00 \r
-\r
-// Write MAC address 11 22 33 44 55 66 to Tx MAC Source Address buffer\r
-01 00 09 00 00\r
-01 00 08 00 11\r
-01 00 0a 00 01\r
-01 00 0a 00 00\r
-01 00 09 00 01\r
-01 00 08 00 22\r
-01 00 0a 00 01\r
-01 00 0a 00 00\r
-01 00 09 00 02\r
-01 00 08 00 33\r
-01 00 0a 00 01\r
-01 00 0a 00 00\r
-01 00 09 00 03\r
-01 00 08 00 44\r
-01 00 0a 00 01\r
-01 00 0a 00 00\r
-01 00 09 00 04\r
-01 00 08 00 55\r
-01 00 0a 00 01\r
-01 00 0a 00 00\r
-01 00 09 00 05\r
-01 00 08 00 66\r
-01 00 0a 00 01\r
-01 00 0a 00 00\r
-\r
-// Transmit a 60 byte frame 3 times - and expect them to be received again!\r
-20 00 3C 00 03\r
-\r
-// Wait (indefinitely) for missing Rx packets\r
-22 00 00 \r
-\r
-// Write 1 to register 7, MAC_tx_add_en\r
-// This turns on the Tx Source MAC address replacement mechanism\r
-01 00 07 00 01\r
-\r
-// Transmit a 60 byte frame 3 times - and expect them to be received again with Alternate header!\r
-26 00 3C 00 03\r
-\r
-// Wait (indefinitely) for missing Rx packets\r
-22 00 00 \r
+++ /dev/null
-module xlnx_glbl\r
-(\r
- GSR,\r
- GTS\r
-);\r
-\r
- //--------------------------------------------------------------------------\r
- // Parameters\r
- //--------------------------------------------------------------------------\r
-\r
- //--------------------------------------------------------------------------\r
- // IO declarations\r
- //--------------------------------------------------------------------------\r
-\r
- output GSR;\r
- output GTS;\r
-\r
- //--------------------------------------------------------------------------\r
- // Local declarations\r
- //--------------------------------------------------------------------------\r
-\r
- //--------------------------------------------------------------------------\r
- // Internal declarations\r
- //--------------------------------------------------------------------------\r
-\r
- assign GSR = 0;\r
- assign GTS = 0;\r
- \r
-endmodule\r
+++ /dev/null
-// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S1_S2.v,v 1.10 2005/03/14 22:54:41 wloo Exp $
-///////////////////////////////////////////////////////////////////////////////
-// Copyright (c) 1995/2005 Xilinx, Inc.
-// All Right Reserved.
-///////////////////////////////////////////////////////////////////////////////
-// ____ ____
-// / /\/ /
-// /___/ \ / Vendor : Xilinx
-// \ \ \/ Version : 8.1i (I.13)
-// \ \ Description : Xilinx Functional Simulation Library Component
-// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
-// /___/ /\ Filename : RAMB16_S1_S2.v
-// \ \ / \ Timestamp : Thu Mar 10 16:43:35 PST 2005
-// \___\/\___\
-//
-// Revision:
-// 03/23/04 - Initial version.
-// End Revision
-
-`ifdef legacy_model
-
-`timescale 1 ps / 1 ps
-
-module RAMB16_S1_S2 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, SSRA, SSRB, WEA, WEB);
-
- parameter INIT_A = 1'h0;
- parameter INIT_B = 2'h0;
- parameter SRVAL_A = 1'h0;
- parameter SRVAL_B = 2'h0;
- parameter WRITE_MODE_A = "WRITE_FIRST";
- parameter WRITE_MODE_B = "WRITE_FIRST";
- parameter SIM_COLLISION_CHECK = "ALL";
- localparam SETUP_ALL = 1000;
- localparam SETUP_READ_FIRST = 3000;
-
- parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-
- output [0:0] DOA;
- reg [0:0] doa_out;
- wire doa_out0;
-
- input [13:0] ADDRA;
- input [0:0] DIA;
- input ENA, CLKA, WEA, SSRA;
-
- output [1:0] DOB;
- reg [1:0] dob_out;
- wire dob_out0, dob_out1;
-
- input [12:0] ADDRB;
- input [1:0] DIB;
- input ENB, CLKB, WEB, SSRB;
-
- reg [18431:0] mem;
- reg [8:0] count;
- reg [1:0] wr_mode_a, wr_mode_b;
-
- reg [5:0] dmi, dbi;
- reg [5:0] pmi, pbi;
-
- wire [13:0] addra_int;
- reg [13:0] addra_reg;
- wire [0:0] dia_int;
- wire ena_int, clka_int, wea_int, ssra_int;
- reg ena_reg, wea_reg, ssra_reg;
- wire [12:0] addrb_int;
- reg [12:0] addrb_reg;
- wire [1:0] dib_int;
- wire enb_int, clkb_int, web_int, ssrb_int;
- reg display_flag;
- reg enb_reg, web_reg, ssrb_reg;
-
- time time_clka, time_clkb;
- time time_clka_clkb;
- time time_clkb_clka;
-
- reg setup_all_a_b;
- reg setup_all_b_a;
- reg setup_zero;
- reg setup_rf_a_b;
- reg setup_rf_b_a;
- reg [1:0] data_collision, data_collision_a_b, data_collision_b_a;
- reg memory_collision, memory_collision_a_b, memory_collision_b_a;
- reg address_collision, address_collision_a_b, address_collision_b_a;
- reg change_clka;
- reg change_clkb;
-
- wire [14:0] data_addra_int;
- wire [14:0] data_addra_reg;
- wire [14:0] data_addrb_int;
- wire [14:0] data_addrb_reg;
- wire [15:0] parity_addra_int;
- wire [15:0] parity_addra_reg;
- wire [15:0] parity_addrb_int;
- wire [15:0] parity_addrb_reg;
-
- tri0 GSR = glbl.GSR;
-
- always @(GSR)
- if (GSR) begin
- assign doa_out = INIT_A[0:0];
- assign dob_out = INIT_B[1:0];
- end
- else begin
- deassign doa_out;
- deassign dob_out;
- end
-
- buf b_doa_out0 (doa_out0, doa_out[0]);
- buf b_dob_out0 (dob_out0, dob_out[0]);
- buf b_dob_out1 (dob_out1, dob_out[1]);
-
- buf b_doa0 (DOA[0], doa_out0);
- buf b_dob0 (DOB[0], dob_out0);
- buf b_dob1 (DOB[1], dob_out1);
-
- buf b_addra_0 (addra_int[0], ADDRA[0]);
- buf b_addra_1 (addra_int[1], ADDRA[1]);
- buf b_addra_2 (addra_int[2], ADDRA[2]);
- buf b_addra_3 (addra_int[3], ADDRA[3]);
- buf b_addra_4 (addra_int[4], ADDRA[4]);
- buf b_addra_5 (addra_int[5], ADDRA[5]);
- buf b_addra_6 (addra_int[6], ADDRA[6]);
- buf b_addra_7 (addra_int[7], ADDRA[7]);
- buf b_addra_8 (addra_int[8], ADDRA[8]);
- buf b_addra_9 (addra_int[9], ADDRA[9]);
- buf b_addra_10 (addra_int[10], ADDRA[10]);
- buf b_addra_11 (addra_int[11], ADDRA[11]);
- buf b_addra_12 (addra_int[12], ADDRA[12]);
- buf b_addra_13 (addra_int[13], ADDRA[13]);
- buf b_dia_0 (dia_int[0], DIA[0]);
- buf b_ena (ena_int, ENA);
- buf b_clka (clka_int, CLKA);
- buf b_ssra (ssra_int, SSRA);
- buf b_wea (wea_int, WEA);
- buf b_addrb_0 (addrb_int[0], ADDRB[0]);
- buf b_addrb_1 (addrb_int[1], ADDRB[1]);
- buf b_addrb_2 (addrb_int[2], ADDRB[2]);
- buf b_addrb_3 (addrb_int[3], ADDRB[3]);
- buf b_addrb_4 (addrb_int[4], ADDRB[4]);
- buf b_addrb_5 (addrb_int[5], ADDRB[5]);
- buf b_addrb_6 (addrb_int[6], ADDRB[6]);
- buf b_addrb_7 (addrb_int[7], ADDRB[7]);
- buf b_addrb_8 (addrb_int[8], ADDRB[8]);
- buf b_addrb_9 (addrb_int[9], ADDRB[9]);
- buf b_addrb_10 (addrb_int[10], ADDRB[10]);
- buf b_addrb_11 (addrb_int[11], ADDRB[11]);
- buf b_addrb_12 (addrb_int[12], ADDRB[12]);
- buf b_dib_0 (dib_int[0], DIB[0]);
- buf b_dib_1 (dib_int[1], DIB[1]);
- buf b_enb (enb_int, ENB);
- buf b_clkb (clkb_int, CLKB);
- buf b_ssrb (ssrb_int, SSRB);
- buf b_web (web_int, WEB);
-
- initial begin
- for (count = 0; count < 256; count = count + 1) begin
- mem[count] <= INIT_00[count];
- mem[256 * 1 + count] <= INIT_01[count];
- mem[256 * 2 + count] <= INIT_02[count];
- mem[256 * 3 + count] <= INIT_03[count];
- mem[256 * 4 + count] <= INIT_04[count];
- mem[256 * 5 + count] <= INIT_05[count];
- mem[256 * 6 + count] <= INIT_06[count];
- mem[256 * 7 + count] <= INIT_07[count];
- mem[256 * 8 + count] <= INIT_08[count];
- mem[256 * 9 + count] <= INIT_09[count];
- mem[256 * 10 + count] <= INIT_0A[count];
- mem[256 * 11 + count] <= INIT_0B[count];
- mem[256 * 12 + count] <= INIT_0C[count];
- mem[256 * 13 + count] <= INIT_0D[count];
- mem[256 * 14 + count] <= INIT_0E[count];
- mem[256 * 15 + count] <= INIT_0F[count];
- mem[256 * 16 + count] <= INIT_10[count];
- mem[256 * 17 + count] <= INIT_11[count];
- mem[256 * 18 + count] <= INIT_12[count];
- mem[256 * 19 + count] <= INIT_13[count];
- mem[256 * 20 + count] <= INIT_14[count];
- mem[256 * 21 + count] <= INIT_15[count];
- mem[256 * 22 + count] <= INIT_16[count];
- mem[256 * 23 + count] <= INIT_17[count];
- mem[256 * 24 + count] <= INIT_18[count];
- mem[256 * 25 + count] <= INIT_19[count];
- mem[256 * 26 + count] <= INIT_1A[count];
- mem[256 * 27 + count] <= INIT_1B[count];
- mem[256 * 28 + count] <= INIT_1C[count];
- mem[256 * 29 + count] <= INIT_1D[count];
- mem[256 * 30 + count] <= INIT_1E[count];
- mem[256 * 31 + count] <= INIT_1F[count];
- mem[256 * 32 + count] <= INIT_20[count];
- mem[256 * 33 + count] <= INIT_21[count];
- mem[256 * 34 + count] <= INIT_22[count];
- mem[256 * 35 + count] <= INIT_23[count];
- mem[256 * 36 + count] <= INIT_24[count];
- mem[256 * 37 + count] <= INIT_25[count];
- mem[256 * 38 + count] <= INIT_26[count];
- mem[256 * 39 + count] <= INIT_27[count];
- mem[256 * 40 + count] <= INIT_28[count];
- mem[256 * 41 + count] <= INIT_29[count];
- mem[256 * 42 + count] <= INIT_2A[count];
- mem[256 * 43 + count] <= INIT_2B[count];
- mem[256 * 44 + count] <= INIT_2C[count];
- mem[256 * 45 + count] <= INIT_2D[count];
- mem[256 * 46 + count] <= INIT_2E[count];
- mem[256 * 47 + count] <= INIT_2F[count];
- mem[256 * 48 + count] <= INIT_30[count];
- mem[256 * 49 + count] <= INIT_31[count];
- mem[256 * 50 + count] <= INIT_32[count];
- mem[256 * 51 + count] <= INIT_33[count];
- mem[256 * 52 + count] <= INIT_34[count];
- mem[256 * 53 + count] <= INIT_35[count];
- mem[256 * 54 + count] <= INIT_36[count];
- mem[256 * 55 + count] <= INIT_37[count];
- mem[256 * 56 + count] <= INIT_38[count];
- mem[256 * 57 + count] <= INIT_39[count];
- mem[256 * 58 + count] <= INIT_3A[count];
- mem[256 * 59 + count] <= INIT_3B[count];
- mem[256 * 60 + count] <= INIT_3C[count];
- mem[256 * 61 + count] <= INIT_3D[count];
- mem[256 * 62 + count] <= INIT_3E[count];
- mem[256 * 63 + count] <= INIT_3F[count];
- end
- address_collision <= 0;
- address_collision_a_b <= 0;
- address_collision_b_a <= 0;
- change_clka <= 0;
- change_clkb <= 0;
- data_collision <= 0;
- data_collision_a_b <= 0;
- data_collision_b_a <= 0;
- memory_collision <= 0;
- memory_collision_a_b <= 0;
- memory_collision_b_a <= 0;
- setup_all_a_b <= 0;
- setup_all_b_a <= 0;
- setup_zero <= 0;
- setup_rf_a_b <= 0;
- setup_rf_b_a <= 0;
- end
-
- assign data_addra_int = addra_int * 1;
- assign data_addra_reg = addra_reg * 1;
- assign data_addrb_int = addrb_int * 2;
- assign data_addrb_reg = addrb_reg * 2;
-
-
- initial begin
-
- display_flag = 1;
-
- case (SIM_COLLISION_CHECK)
-
- "NONE" : begin
- assign setup_all_a_b = 1'b0;
- assign setup_all_b_a = 1'b0;
- assign setup_zero = 1'b0;
- assign setup_rf_a_b = 1'b0;
- assign setup_rf_b_a = 1'b0;
- assign display_flag = 0;
- end
- "WARNING_ONLY" : begin
- assign data_collision = 2'b00;
- assign data_collision_a_b = 2'b00;
- assign data_collision_b_a = 2'b00;
- assign memory_collision = 1'b0;
- assign memory_collision_a_b = 1'b0;
- assign memory_collision_b_a = 1'b0;
- end
- "GENERATE_X_ONLY" : begin
- assign display_flag = 0;
- end
- "ALL" : ;
- default : begin
- $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S1_S2 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK);
- $finish;
- end
-
- endcase // case(SIM_COLLISION_CHECK)
-
- end // initial begin
-
-
- always @(posedge clka_int) begin
- time_clka = $time;
- #0 time_clkb_clka = time_clka - time_clkb;
- change_clka = ~change_clka;
- end
-
- always @(posedge clkb_int) begin
- time_clkb = $time;
- #0 time_clka_clkb = time_clkb - time_clka;
- change_clkb = ~change_clkb;
- end
-
- always @(change_clkb) begin
- if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL))
- setup_all_a_b = 1;
- if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST))
- setup_rf_a_b = 1;
- end
-
- always @(change_clka) begin
- if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL))
- setup_all_b_a = 1;
- if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST))
- setup_rf_b_a = 1;
- end
-
- always @(change_clkb or change_clka) begin
- if ((time_clkb_clka == 0) && (time_clka_clkb == 0))
- setup_zero = 1;
- end
-
- always @(posedge setup_zero) begin
- if ((ena_int == 1) && (wea_int == 1) &&
- (enb_int == 1) && (web_int == 1) &&
- (data_addra_int[14:1] == data_addrb_int[14:1]))
- memory_collision <= 1;
- end
-
- always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin
- if ((ena_reg == 1) && (wea_reg == 1) &&
- (enb_int == 1) && (web_int == 1) &&
- (data_addra_reg[14:1] == data_addrb_int[14:1]))
- memory_collision_a_b <= 1;
- end
-
- always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin
- if ((ena_int == 1) && (wea_int == 1) &&
- (enb_reg == 1) && (web_reg == 1) &&
- (data_addra_int[14:1] == data_addrb_reg[14:1]))
- memory_collision_b_a <= 1;
- end
-
- always @(posedge setup_all_a_b) begin
- if (data_addra_reg[14:1] == data_addrb_int[14:1]) begin
- if ((ena_reg == 1) && (enb_int == 1)) begin
- case ({wr_mode_a, wr_mode_b, wea_reg, web_int})
- 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
- 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
- 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end
-// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
-// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
-// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
- 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end
- 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end
- 6'b101011 : begin display_wa_wb; end
- 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
-// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
- 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
- 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
-// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
- 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
- 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
-// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
- 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
- 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
- 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
- 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
-// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
-// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
-// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
- 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
- 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
- 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
- endcase
- end
- end
- setup_all_a_b <= 0;
- end
-
-
- always @(posedge setup_all_b_a) begin
- if (data_addra_int[14:1] == data_addrb_reg[14:1]) begin
- if ((ena_int == 1) && (enb_reg == 1)) begin
- case ({wr_mode_a, wr_mode_b, wea_int, web_reg})
- 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
-// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
- 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end
- 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
-// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
- 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end
- 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
- 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
- 6'b101011 : begin display_wa_wb; end
- 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
- 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
- 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
- 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
- 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
- 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
- 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
- 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
- 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
- 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
- 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
- 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
-// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
-// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
-// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
- 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
- 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
- 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
- endcase
- end
- end
- setup_all_b_a <= 0;
- end
-
-
- always @(posedge setup_zero) begin
- if (data_addra_int[14:1] == data_addrb_int[14:1]) begin
- if ((ena_int == 1) && (enb_int == 1)) begin
- case ({wr_mode_a, wr_mode_b, wea_int, web_int})
- 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end
- 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end
- 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end
- 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end
- 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end
- 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end
- 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end
- 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end
- 6'b101011 : begin display_wa_wb; end
- 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end
-// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end
- 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end
- 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end
-// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end
- 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end
- 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end
-// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end
- 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end
- 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end
- 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end
- 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end
-// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end
-// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end
-// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end
- 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end
- 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end
- 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end
- endcase
- end
- end
- setup_zero <= 0;
- end
-
- task display_ra_wb;
- begin
- if (display_flag)
- $display("Memory Collision Error on RAMB16_S1_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int);
- end
- endtask
-
- task display_wa_rb;
- begin
- if (display_flag)
- $display("Memory Collision Error on RAMB16_S1_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int);
- end
- endtask
-
- task display_wa_wb;
- begin
- if (display_flag)
- $display("Memory Collision Error on RAMB16_S1_S2:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int);
- end
- endtask
-
-
- always @(posedge setup_rf_a_b) begin
- if (data_addra_reg[14:1] == data_addrb_int[14:1]) begin
- if ((ena_reg == 1) && (enb_int == 1)) begin
- case ({wr_mode_a, wr_mode_b, wea_reg, web_int})
-// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
-// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
-// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
- 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
- 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
- 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end
-// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
-// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
-// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
-// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
-// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
-// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
-// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
-// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
-// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
-// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
-// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
-// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
-// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
-// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
-// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
- 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
- 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
- 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
-// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
-// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
-// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
- endcase
- end
- end
- setup_rf_a_b <= 0;
- end
-
-
- always @(posedge setup_rf_b_a) begin
- if (data_addra_int[14:1] == data_addrb_reg[14:1]) begin
- if ((ena_int == 1) && (enb_reg == 1)) begin
- case ({wr_mode_a, wr_mode_b, wea_int, web_reg})
-// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
- 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
-// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
-// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
- 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
-// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
-// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
- 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
-// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
-// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
- 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
-// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
-// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
- 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
-// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
-// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
- 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
-// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
-// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
-// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
-// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
-// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
-// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
-// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
-// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
-// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
-// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
- endcase
- end
- end
- setup_rf_b_a <= 0;
- end
-
-
- always @(posedge clka_int) begin
- addra_reg <= addra_int;
- ena_reg <= ena_int;
- ssra_reg <= ssra_int;
- wea_reg <= wea_int;
- end
-
- always @(posedge clkb_int) begin
- addrb_reg <= addrb_int;
- enb_reg <= enb_int;
- ssrb_reg <= ssrb_int;
- web_reg <= web_int;
- end
-
- // Data
- always @(posedge memory_collision) begin
- for (dmi = 0; dmi < 1; dmi = dmi + 1) begin
- mem[data_addra_int + dmi] <= 1'bX;
- end
- memory_collision <= 0;
- end
-
- always @(posedge memory_collision_a_b) begin
- for (dmi = 0; dmi < 1; dmi = dmi + 1) begin
- mem[data_addra_reg + dmi] <= 1'bX;
- end
- memory_collision_a_b <= 0;
- end
-
- always @(posedge memory_collision_b_a) begin
- for (dmi = 0; dmi < 1; dmi = dmi + 1) begin
- mem[data_addra_int + dmi] <= 1'bX;
- end
- memory_collision_b_a <= 0;
- end
-
- always @(posedge data_collision[1]) begin
- if (ssra_int == 0) begin
- doa_out <= 1'bX;
- end
- data_collision[1] <= 0;
- end
-
- always @(posedge data_collision[0]) begin
- if (ssrb_int == 0) begin
- for (dbi = 0; dbi < 1; dbi = dbi + 1) begin
- dob_out[data_addra_int[0 : 0] + dbi] <= 1'bX;
- end
- end
- data_collision[0] <= 0;
- end
-
- always @(posedge data_collision_a_b[1]) begin
- if (ssra_reg == 0) begin
- doa_out <= 1'bX;
- end
- data_collision_a_b[1] <= 0;
- end
-
- always @(posedge data_collision_a_b[0]) begin
- if (ssrb_int == 0) begin
- for (dbi = 0; dbi < 1; dbi = dbi + 1) begin
- dob_out[data_addra_reg[0 : 0] + dbi] <= 1'bX;
- end
- end
- data_collision_a_b[0] <= 0;
- end
-
- always @(posedge data_collision_b_a[1]) begin
- if (ssra_int == 0) begin
- doa_out <= 1'bX;
- end
- data_collision_b_a[1] <= 0;
- end
-
- always @(posedge data_collision_b_a[0]) begin
- if (ssrb_reg == 0) begin
- for (dbi = 0; dbi < 1; dbi = dbi + 1) begin
- dob_out[data_addra_int[0 : 0] + dbi] <= 1'bX;
- end
- end
- data_collision_b_a[0] <= 0;
- end
-
-
- initial begin
- case (WRITE_MODE_A)
- "WRITE_FIRST" : wr_mode_a <= 2'b00;
- "READ_FIRST" : wr_mode_a <= 2'b01;
- "NO_CHANGE" : wr_mode_a <= 2'b10;
- default : begin
- $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S1_S2 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A);
- $finish;
- end
- endcase
- end
-
- initial begin
- case (WRITE_MODE_B)
- "WRITE_FIRST" : wr_mode_b <= 2'b00;
- "READ_FIRST" : wr_mode_b <= 2'b01;
- "NO_CHANGE" : wr_mode_b <= 2'b10;
- default : begin
- $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S1_S2 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B);
- $finish;
- end
- endcase
- end
-
- // Port A
- always @(posedge clka_int) begin
- if (ena_int == 1'b1) begin
- if (ssra_int == 1'b1) begin
- doa_out[0] <= SRVAL_A[0];
- end
- else begin
- if (wea_int == 1'b1) begin
- if (wr_mode_a == 2'b00) begin
- doa_out <= dia_int;
- end
- else if (wr_mode_a == 2'b01) begin
- doa_out[0] <= mem[data_addra_int + 0];
- end
- end
- else begin
- doa_out[0] <= mem[data_addra_int + 0];
- end
- end
- end
- end
-
- always @(posedge clka_int) begin
- if (ena_int == 1'b1 && wea_int == 1'b1) begin
- mem[data_addra_int + 0] <= dia_int[0];
- end
- end
-
- // Port B
- always @(posedge clkb_int) begin
- if (enb_int == 1'b1) begin
- if (ssrb_int == 1'b1) begin
- dob_out[0] <= SRVAL_B[0];
- dob_out[1] <= SRVAL_B[1];
- end
- else begin
- if (web_int == 1'b1) begin
- if (wr_mode_b == 2'b00) begin
- dob_out <= dib_int;
- end
- else if (wr_mode_b == 2'b01) begin
- dob_out[0] <= mem[data_addrb_int + 0];
- dob_out[1] <= mem[data_addrb_int + 1];
- end
- end
- else begin
- dob_out[0] <= mem[data_addrb_int + 0];
- dob_out[1] <= mem[data_addrb_int + 1];
- end
- end
- end
- end
-
- always @(posedge clkb_int) begin
- if (enb_int == 1'b1 && web_int == 1'b1) begin
- mem[data_addrb_int + 0] <= dib_int[0];
- mem[data_addrb_int + 1] <= dib_int[1];
- end
- end
-
- specify
- (CLKA *> DOA) = (100, 100);
- (CLKB *> DOB) = (100, 100);
- endspecify
-
-endmodule
-
-`else
-
-// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S1_S2.v,v 1.10 2005/03/14 22:54:41 wloo Exp $
-///////////////////////////////////////////////////////////////////////////////
-// Copyright (c) 1995/2005 Xilinx, Inc.
-// All Right Reserved.
-///////////////////////////////////////////////////////////////////////////////
-// ____ ____
-// / /\/ /
-// /___/ \ / Vendor : Xilinx
-// \ \ \/ Version : 8.1i (I.13)
-// \ \ Description : Xilinx Timing Simulation Library Component
-// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
-// /___/ /\ Filename : RAMB16_S1_S2.v
-// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005
-// \___\/\___\
-//
-// Revision:
-// 03/23/04 - Initial version.
-// 03/10/05 - Initialized outputs.
-// End Revision
-
-`timescale 1 ps/1 ps
-
-module RAMB16_S1_S2 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, SSRA, SSRB, WEA, WEB);
-
- parameter INIT_A = 1'h0;
- parameter INIT_B = 2'h0;
- parameter SRVAL_A = 1'h0;
- parameter SRVAL_B = 2'h0;
- parameter WRITE_MODE_A = "WRITE_FIRST";
- parameter WRITE_MODE_B = "WRITE_FIRST";
- parameter SIM_COLLISION_CHECK = "ALL";
- localparam SETUP_ALL = 1000;
- localparam SETUP_READ_FIRST = 3000;
-
- parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-
- output [0:0] DOA;
- output [1:0] DOB;
-
- input [13:0] ADDRA;
- input [0:0] DIA;
- input ENA, CLKA, WEA, SSRA;
- input [12:0] ADDRB;
- input [1:0] DIB;
- input ENB, CLKB, WEB, SSRB;
-
- reg [0:0] doa_out = INIT_A[0:0];
- reg [1:0] dob_out = INIT_B[1:0];
-
- reg [1:0] mem [8191:0];
-
- reg [8:0] count, countp;
- reg [1:0] wr_mode_a, wr_mode_b;
-
- reg [5:0] dmi, dbi;
- reg [5:0] pmi, pbi;
-
- wire [13:0] addra_int;
- reg [13:0] addra_reg;
- wire [0:0] dia_int;
- wire ena_int, clka_int, wea_int, ssra_int;
- reg ena_reg, wea_reg, ssra_reg;
- wire [12:0] addrb_int;
- reg [12:0] addrb_reg;
- wire [1:0] dib_int;
- wire enb_int, clkb_int, web_int, ssrb_int;
- reg display_flag, output_flag;
- reg enb_reg, web_reg, ssrb_reg;
-
- time time_clka, time_clkb;
- time time_clka_clkb;
- time time_clkb_clka;
-
- reg setup_all_a_b;
- reg setup_all_b_a;
- reg setup_zero;
- reg setup_rf_a_b;
- reg setup_rf_b_a;
- reg [1:0] data_collision, data_collision_a_b, data_collision_b_a;
- reg memory_collision, memory_collision_a_b, memory_collision_b_a;
- reg change_clka;
- reg change_clkb;
-
- wire [14:0] data_addra_int;
- wire [14:0] data_addra_reg;
- wire [14:0] data_addrb_int;
- wire [14:0] data_addrb_reg;
-
- wire dia_enable = ena_int && wea_int;
- wire dib_enable = enb_int && web_int;
-
- tri0 GSR = glbl.GSR;
- wire gsr_int;
-
- buf b_gsr (gsr_int, GSR);
-
- buf b_doa [0:0] (DOA, doa_out);
- buf b_addra [13:0] (addra_int, ADDRA);
- buf b_dia [0:0] (dia_int, DIA);
- buf b_ena (ena_int, ENA);
- buf b_clka (clka_int, CLKA);
- buf b_ssra (ssra_int, SSRA);
- buf b_wea (wea_int, WEA);
-
- buf b_dob [1:0] (DOB, dob_out);
- buf b_addrb [12:0] (addrb_int, ADDRB);
- buf b_dib [1:0] (dib_int, DIB);
- buf b_enb (enb_int, ENB);
- buf b_clkb (clkb_int, CLKB);
- buf b_ssrb (ssrb_int, SSRB);
- buf b_web (web_int, WEB);
-
-
- always @(gsr_int)
- if (gsr_int) begin
- assign {doa_out} = INIT_A;
- assign {dob_out} = INIT_B;
- end
- else begin
- deassign doa_out;
- deassign dob_out;
- end
-
-
- initial begin
-
- for (count = 0; count < 128; count = count + 1) begin
- mem[count] = INIT_00[(count * 2) +: 2];
- mem[128 * 1 + count] = INIT_01[(count * 2) +: 2];
- mem[128 * 2 + count] = INIT_02[(count * 2) +: 2];
- mem[128 * 3 + count] = INIT_03[(count * 2) +: 2];
- mem[128 * 4 + count] = INIT_04[(count * 2) +: 2];
- mem[128 * 5 + count] = INIT_05[(count * 2) +: 2];
- mem[128 * 6 + count] = INIT_06[(count * 2) +: 2];
- mem[128 * 7 + count] = INIT_07[(count * 2) +: 2];
- mem[128 * 8 + count] = INIT_08[(count * 2) +: 2];
- mem[128 * 9 + count] = INIT_09[(count * 2) +: 2];
- mem[128 * 10 + count] = INIT_0A[(count * 2) +: 2];
- mem[128 * 11 + count] = INIT_0B[(count * 2) +: 2];
- mem[128 * 12 + count] = INIT_0C[(count * 2) +: 2];
- mem[128 * 13 + count] = INIT_0D[(count * 2) +: 2];
- mem[128 * 14 + count] = INIT_0E[(count * 2) +: 2];
- mem[128 * 15 + count] = INIT_0F[(count * 2) +: 2];
- mem[128 * 16 + count] = INIT_10[(count * 2) +: 2];
- mem[128 * 17 + count] = INIT_11[(count * 2) +: 2];
- mem[128 * 18 + count] = INIT_12[(count * 2) +: 2];
- mem[128 * 19 + count] = INIT_13[(count * 2) +: 2];
- mem[128 * 20 + count] = INIT_14[(count * 2) +: 2];
- mem[128 * 21 + count] = INIT_15[(count * 2) +: 2];
- mem[128 * 22 + count] = INIT_16[(count * 2) +: 2];
- mem[128 * 23 + count] = INIT_17[(count * 2) +: 2];
- mem[128 * 24 + count] = INIT_18[(count * 2) +: 2];
- mem[128 * 25 + count] = INIT_19[(count * 2) +: 2];
- mem[128 * 26 + count] = INIT_1A[(count * 2) +: 2];
- mem[128 * 27 + count] = INIT_1B[(count * 2) +: 2];
- mem[128 * 28 + count] = INIT_1C[(count * 2) +: 2];
- mem[128 * 29 + count] = INIT_1D[(count * 2) +: 2];
- mem[128 * 30 + count] = INIT_1E[(count * 2) +: 2];
- mem[128 * 31 + count] = INIT_1F[(count * 2) +: 2];
- mem[128 * 32 + count] = INIT_20[(count * 2) +: 2];
- mem[128 * 33 + count] = INIT_21[(count * 2) +: 2];
- mem[128 * 34 + count] = INIT_22[(count * 2) +: 2];
- mem[128 * 35 + count] = INIT_23[(count * 2) +: 2];
- mem[128 * 36 + count] = INIT_24[(count * 2) +: 2];
- mem[128 * 37 + count] = INIT_25[(count * 2) +: 2];
- mem[128 * 38 + count] = INIT_26[(count * 2) +: 2];
- mem[128 * 39 + count] = INIT_27[(count * 2) +: 2];
- mem[128 * 40 + count] = INIT_28[(count * 2) +: 2];
- mem[128 * 41 + count] = INIT_29[(count * 2) +: 2];
- mem[128 * 42 + count] = INIT_2A[(count * 2) +: 2];
- mem[128 * 43 + count] = INIT_2B[(count * 2) +: 2];
- mem[128 * 44 + count] = INIT_2C[(count * 2) +: 2];
- mem[128 * 45 + count] = INIT_2D[(count * 2) +: 2];
- mem[128 * 46 + count] = INIT_2E[(count * 2) +: 2];
- mem[128 * 47 + count] = INIT_2F[(count * 2) +: 2];
- mem[128 * 48 + count] = INIT_30[(count * 2) +: 2];
- mem[128 * 49 + count] = INIT_31[(count * 2) +: 2];
- mem[128 * 50 + count] = INIT_32[(count * 2) +: 2];
- mem[128 * 51 + count] = INIT_33[(count * 2) +: 2];
- mem[128 * 52 + count] = INIT_34[(count * 2) +: 2];
- mem[128 * 53 + count] = INIT_35[(count * 2) +: 2];
- mem[128 * 54 + count] = INIT_36[(count * 2) +: 2];
- mem[128 * 55 + count] = INIT_37[(count * 2) +: 2];
- mem[128 * 56 + count] = INIT_38[(count * 2) +: 2];
- mem[128 * 57 + count] = INIT_39[(count * 2) +: 2];
- mem[128 * 58 + count] = INIT_3A[(count * 2) +: 2];
- mem[128 * 59 + count] = INIT_3B[(count * 2) +: 2];
- mem[128 * 60 + count] = INIT_3C[(count * 2) +: 2];
- mem[128 * 61 + count] = INIT_3D[(count * 2) +: 2];
- mem[128 * 62 + count] = INIT_3E[(count * 2) +: 2];
- mem[128 * 63 + count] = INIT_3F[(count * 2) +: 2];
- end
-
-
- change_clka <= 0;
- change_clkb <= 0;
- data_collision <= 0;
- data_collision_a_b <= 0;
- data_collision_b_a <= 0;
- memory_collision <= 0;
- memory_collision_a_b <= 0;
- memory_collision_b_a <= 0;
- setup_all_a_b <= 0;
- setup_all_b_a <= 0;
- setup_zero <= 0;
- setup_rf_a_b <= 0;
- setup_rf_b_a <= 0;
- end
-
- assign data_addra_int = addra_int * 1;
- assign data_addra_reg = addra_reg * 1;
- assign data_addrb_int = addrb_int * 2;
- assign data_addrb_reg = addrb_reg * 2;
-
-
- initial begin
-
- display_flag = 1;
- output_flag = 1;
-
- case (SIM_COLLISION_CHECK)
-
- "NONE" : begin
- output_flag = 0;
- display_flag = 0;
- end
- "WARNING_ONLY" : output_flag = 0;
- "GENERATE_ONLY" : display_flag = 0;
- "ALL" : ;
-
- default : begin
- $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S1_S2 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_ONLY.", SIM_COLLISION_CHECK);
- $finish;
- end
-
- endcase // case(SIM_COLLISION_CHECK)
-
- end // initial begin
-
-
- always @(posedge clka_int) begin
- if ((output_flag || display_flag)) begin
- time_clka = $time;
- #0 time_clkb_clka = time_clka - time_clkb;
- change_clka = ~change_clka;
- end
- end
-
- always @(posedge clkb_int) begin
- if ((output_flag || display_flag)) begin
- time_clkb = $time;
- #0 time_clka_clkb = time_clkb - time_clka;
- change_clkb = ~change_clkb;
- end
- end
-
- always @(change_clkb) begin
- if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL))
- setup_all_a_b = 1;
- if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST))
- setup_rf_a_b = 1;
- end
-
- always @(change_clka) begin
- if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL))
- setup_all_b_a = 1;
- if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST))
- setup_rf_b_a = 1;
- end
-
- always @(change_clkb or change_clka) begin
- if ((time_clkb_clka == 0) && (time_clka_clkb == 0))
- setup_zero = 1;
- end
-
- always @(posedge setup_zero) begin
- if ((ena_int == 1) && (wea_int == 1) &&
- (enb_int == 1) && (web_int == 1) &&
- (data_addra_int[14:1] == data_addrb_int[14:1]))
- memory_collision <= 1;
- end
-
- always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin
- if ((ena_reg == 1) && (wea_reg == 1) &&
- (enb_int == 1) && (web_int == 1) &&
- (data_addra_reg[14:1] == data_addrb_int[14:1]))
- memory_collision_a_b <= 1;
- end
-
- always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin
- if ((ena_int == 1) && (wea_int == 1) &&
- (enb_reg == 1) && (web_reg == 1) &&
- (data_addra_int[14:1] == data_addrb_reg[14:1]))
- memory_collision_b_a <= 1;
- end
-
- always @(posedge setup_all_a_b) begin
- if (data_addra_reg[14:1] == data_addrb_int[14:1]) begin
- if ((ena_reg == 1) && (enb_int == 1)) begin
- case ({wr_mode_a, wr_mode_b, wea_reg, web_int})
- 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
- 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
- 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end
-// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
-// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
-// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
- 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end
- 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end
- 6'b101011 : begin display_wa_wb; end
- 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
-// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
- 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
- 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
-// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
- 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
- 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
-// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
- 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
- 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
- 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
- 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
-// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
-// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
-// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
- 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
- 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
- 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
- endcase
- end
- end
- setup_all_a_b <= 0;
- end
-
-
- always @(posedge setup_all_b_a) begin
- if (data_addra_int[14:1] == data_addrb_reg[14:1]) begin
- if ((ena_int == 1) && (enb_reg == 1)) begin
- case ({wr_mode_a, wr_mode_b, wea_int, web_reg})
- 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
-// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
- 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end
- 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
-// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
- 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end
- 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
- 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
- 6'b101011 : begin display_wa_wb; end
- 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
- 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
- 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
- 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
- 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
- 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
- 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
- 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
- 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
- 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
- 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
- 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
-// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
-// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
-// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
- 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
- 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
- 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
- endcase
- end
- end
- setup_all_b_a <= 0;
- end
-
-
- always @(posedge setup_zero) begin
- if (data_addra_int[14:1] == data_addrb_int[14:1]) begin
- if ((ena_int == 1) && (enb_int == 1)) begin
- case ({wr_mode_a, wr_mode_b, wea_int, web_int})
- 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end
- 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end
- 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end
- 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end
- 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end
- 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end
- 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end
- 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end
- 6'b101011 : begin display_wa_wb; end
- 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end
-// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end
- 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end
- 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end
-// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end
- 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end
- 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end
-// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end
- 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end
- 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end
- 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end
- 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end
-// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end
-// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end
-// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end
- 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end
- 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end
- 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end
- endcase
- end
- end
- setup_zero <= 0;
- end
-
- task display_ra_wb;
- begin
- if (display_flag)
- $display("Memory Collision Error on RAMB16_S1_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int);
- end
- endtask
-
- task display_wa_rb;
- begin
- if (display_flag)
- $display("Memory Collision Error on RAMB16_S1_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int);
- end
- endtask
-
- task display_wa_wb;
- begin
- if (display_flag)
- $display("Memory Collision Error on RAMB16_S1_S2:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int);
- end
- endtask
-
-
- always @(posedge setup_rf_a_b) begin
- if (data_addra_reg[14:1] == data_addrb_int[14:1]) begin
- if ((ena_reg == 1) && (enb_int == 1)) begin
- case ({wr_mode_a, wr_mode_b, wea_reg, web_int})
-// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
-// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
-// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
- 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
- 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
- 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end
-// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
-// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
-// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
-// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
-// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
-// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
-// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
-// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
-// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
-// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
-// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
-// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
-// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
-// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
-// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
- 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
- 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
- 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
-// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
-// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
-// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
- endcase
- end
- end
- setup_rf_a_b <= 0;
- end
-
-
- always @(posedge setup_rf_b_a) begin
- if (data_addra_int[14:1] == data_addrb_reg[14:1]) begin
- if ((ena_int == 1) && (enb_reg == 1)) begin
- case ({wr_mode_a, wr_mode_b, wea_int, web_reg})
-// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
- 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
-// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
-// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
- 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
-// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
-// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
- 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
-// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
-// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
- 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
-// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
-// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
- 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
-// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
-// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
- 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
-// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
-// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
-// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
-// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
-// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
-// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
-// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
-// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
-// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
-// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
- endcase
- end
- end
- setup_rf_b_a <= 0;
- end
-
-
- always @(posedge clka_int) begin
- if ((output_flag || display_flag)) begin
- addra_reg <= addra_int;
- ena_reg <= ena_int;
- ssra_reg <= ssra_int;
- wea_reg <= wea_int;
- end
- end
-
- always @(posedge clkb_int) begin
- if ((output_flag || display_flag)) begin
- addrb_reg <= addrb_int;
- enb_reg <= enb_int;
- ssrb_reg <= ssrb_int;
- web_reg <= web_int;
- end
- end
-
-
- // Data
- always @(posedge memory_collision) begin
- if ((output_flag || display_flag)) begin
- mem[addra_int[13:1]][addra_int[0:0] * 1 +: 1] <= 1'bx;
- memory_collision <= 0;
- end
-
- end
-
- always @(posedge memory_collision_a_b) begin
- if ((output_flag || display_flag)) begin
- mem[addra_reg[13:1]][addra_reg[0:0] * 1 +: 1] <= 1'bx;
- memory_collision_a_b <= 0;
- end
- end
-
- always @(posedge memory_collision_b_a) begin
- if ((output_flag || display_flag)) begin
- mem[addra_int[13:1]][addra_int[0:0] * 1 +: 1] <= 1'bx;
- memory_collision_b_a <= 0;
- end
- end
-
- always @(posedge data_collision[1]) begin
- if (ssra_int == 0 && output_flag) begin
- doa_out <= #100 1'bX;
- end
- data_collision[1] <= 0;
- end
-
- always @(posedge data_collision[0]) begin
- if (ssrb_int == 0 && output_flag) begin
- dob_out[addra_int[0:0] * 1 +: 1] <= #100 1'bX;
- end
- data_collision[0] <= 0;
- end
-
- always @(posedge data_collision_a_b[1]) begin
- if (ssra_reg == 0 && output_flag) begin
- doa_out <= #100 1'bX;
- end
- data_collision_a_b[1] <= 0;
- end
-
- always @(posedge data_collision_a_b[0]) begin
- if (ssrb_int == 0 && output_flag) begin
- dob_out[addra_reg[0:0] * 1 +: 1] <= #100 1'bX;
- end
- data_collision_a_b[0] <= 0;
- end
-
- always @(posedge data_collision_b_a[1]) begin
- if (ssra_int == 0 && output_flag) begin
- doa_out <= #100 1'bX;
- end
- data_collision_b_a[1] <= 0;
- end
-
- always @(posedge data_collision_b_a[0]) begin
- if (ssrb_reg == 0 && output_flag) begin
- dob_out[addra_int[0:0] * 1 +: 1] <= #100 1'bX;
- end
- data_collision_b_a[0] <= 0;
- end
-
-
- initial begin
- case (WRITE_MODE_A)
- "WRITE_FIRST" : wr_mode_a <= 2'b00;
- "READ_FIRST" : wr_mode_a <= 2'b01;
- "NO_CHANGE" : wr_mode_a <= 2'b10;
- default : begin
- $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S1_S2 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A);
- $finish;
- end
- endcase
- end
-
- initial begin
- case (WRITE_MODE_B)
- "WRITE_FIRST" : wr_mode_b <= 2'b00;
- "READ_FIRST" : wr_mode_b <= 2'b01;
- "NO_CHANGE" : wr_mode_b <= 2'b10;
- default : begin
- $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S1_S2 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B);
- $finish;
- end
- endcase
- end
-
-
- // Port A
- always @(posedge clka_int) begin
-
- if (ena_int == 1'b1) begin
-
- if (ssra_int == 1'b1) begin
- {doa_out} <= #100 SRVAL_A;
- end
- else begin
- if (wea_int == 1'b1) begin
- if (wr_mode_a == 2'b00) begin
- doa_out <= #100 dia_int;
- end
- else if (wr_mode_a == 2'b01) begin
-
- doa_out <= #100 mem[addra_int[13:1]][addra_int[0:0] * 1 +: 1];
-
- end
- end
- else begin
-
- doa_out <= #100 mem[addra_int[13:1]][addra_int[0:0] * 1 +: 1];
-
- end
- end
-
- // memory
- if (wea_int == 1'b1) begin
- mem[addra_int[13:1]][addra_int[0:0] * 1 +: 1] <= dia_int;
- end
-
- end
- end
-
-
- // Port B
- always @(posedge clkb_int) begin
-
- if (enb_int == 1'b1) begin
-
- if (ssrb_int == 1'b1) begin
- {dob_out} <= #100 SRVAL_B;
- end
- else begin
- if (web_int == 1'b1) begin
- if (wr_mode_b == 2'b00) begin
- dob_out <= #100 dib_int;
- end
- else if (wr_mode_b == 2'b01) begin
- dob_out <= #100 mem[addrb_int];
- end
- end
- else begin
- dob_out <= #100 mem[addrb_int];
- end
- end
-
- // memory
- if (web_int == 1'b1) begin
- mem[addrb_int] <= dib_int;
- end
-
- end
- end
-
-
-endmodule
-
-`endif
+++ /dev/null
-NET "Reset_n" LOC = "C15"; // PushButton #4\r
-NET "Clk_100M" LOC = "B15";\r
-NET "Clk_125M" LOC = "A16"; // GMII only\r
-\r
-NET "RS232_TXD" LOC = "A9";\r
-NET "RS232_RXD" LOC = "F1";\r
-\r
-NET "USB_TXD" LOC = "D1";\r
-NET "USB_RXD" LOC = "A8";\r
-\r
-NET "PHY_RESET_n" LOC = "E25";\r
-\r
-NET "PHY_RXC" LOC = "B13";\r
-NET "PHY_RXD<0>" LOC = "D16";\r
-NET "PHY_RXD<1>" LOC = "C16";\r
-NET "PHY_RXD<2>" LOC = "D15";\r
-NET "PHY_RXD<3>" LOC = "D14";\r
-NET "PHY_RXD<4>" LOC = "E14";\r
-NET "PHY_RXD<5>" LOC = "F14";\r
-NET "PHY_RXD<6>" LOC = "F11";\r
-NET "PHY_RXD<7>" LOC = "F12";\r
-NET "PHY_RXDV" LOC = "F13";\r
-NET "PHY_RXER" LOC = "E13";\r
-\r
-NET "PHY_GTX_CLK" LOC = "C26"; // GMII only\r
-NET "PHY_TXC" LOC = "A10";\r
-NET "PHY_TXD<0>" LOC = "H26";\r
-NET "PHY_TXD<1>" LOC = "H24";\r
-NET "PHY_TXD<2>" LOC = "G26";\r
-NET "PHY_TXD<3>" LOC = "G24";\r
-NET "PHY_TXD<4>" LOC = "F26";\r
-NET "PHY_TXD<5>" LOC = "F24";\r
-NET "PHY_TXD<6>" LOC = "E26";\r
-NET "PHY_TXD<7>" LOC = "E24";\r
-NET "PHY_TXEN" LOC = "D26";\r
-NET "PHY_TXER" LOC = "D24";\r
-\r
-NET "PHY_COL" LOC = "B24";\r
-NET "PHY_CRS" LOC = "D25";\r
-\r
-NET "PHY_MDC" LOC = "G25";\r
-NET "PHY_MDIO" LOC = "H25";\r
-\r
-NET "LED<1>" LOC = "D13"; // LED #1-4\r
-NET "LED<2>" LOC = "D12";\r
-NET "LED<3>" LOC = "C11";\r
-NET "LED<4>" LOC = "D11";\r
-\r
-NET "Clk_100M" PERIOD = 10.000 ; # 100 MHz\r
-NET "Clk_125M" PERIOD = 8.000 ; # 125 MHz\r
-NET "PHY_RXC" PERIOD = 8.000 ; # 125 MHz\r
-NET "PHY_TXC" PERIOD = 8.000 ; # 125 MHz\r
+++ /dev/null
-module demo(\r
- Reset_n,\r
- Clk_100M,\r
- Clk_125M, // GMII only\r
-\r
- RS232_TXD,\r
- RS232_RXD,\r
-\r
- USB_TXD,\r
- USB_RXD,\r
-\r
- //--- 10/100/1000BASE-T Ethernet PHY (MII/GMII)\r
- PHY_RESET_n,\r
-\r
- PHY_RXC,\r
- PHY_RXD,\r
- PHY_RXDV,\r
- PHY_RXER,\r
-\r
- PHY_GTX_CLK, // GMII only\r
- PHY_TXC,\r
- PHY_TXD,\r
- PHY_TXEN,\r
- PHY_TXER,\r
-\r
- PHY_COL,\r
- PHY_CRS,\r
-\r
- PHY_MDC,\r
- PHY_MDIO,\r
-\r
- // Misc. I/Os\r
- LED,\r
- Button\r
-);\r
-\r
- input Reset_n;\r
- input Clk_100M;\r
- input Clk_125M; // GMII\r
-\r
- output RS232_TXD;\r
- input RS232_RXD;\r
-\r
- output USB_TXD;\r
- input USB_RXD;\r
-\r
- //--- 10/100/1000BASE-T Ethernet PHY (MII/GMII)\r
- output PHY_RESET_n;\r
-\r
- input PHY_RXC;\r
- input [7:0] PHY_RXD;\r
- input PHY_RXDV;\r
- input PHY_RXER;\r
-\r
- output PHY_GTX_CLK; // GMII only\r
- input PHY_TXC;\r
- output [7:0] PHY_TXD;\r
- output PHY_TXEN;\r
- output PHY_TXER;\r
-\r
- input PHY_COL;\r
- input PHY_CRS;\r
-\r
- output PHY_MDC;\r
- inout PHY_MDIO;\r
-\r
- // Misc. I/Os\r
- output [1:4] LED;\r
-\r
- input [1:4] Button;\r
-\r
- //-------------------------------------------------------------------------\r
- // Local declarations\r
- //-------------------------------------------------------------------------\r
-\r
- // Rename to "standard" core clock name\r
- wire Clk = Clk_100M;\r
-\r
- reg [27:0] Counter;\r
- always @( negedge Reset_n or posedge Clk )\r
- if ( ~Reset_n )\r
- Counter <= 0;\r
- else\r
- Counter <= Counter + 1;\r
-\r
- assign LED[1:4] = Counter[27:24];\r
-\r
- //-------------------------------------------------------------------------\r
- // Instantiation of sub-modules\r
- //-------------------------------------------------------------------------\r
-\r
- //--- UART ----------------------------------------------------------------\r
-\r
- wire UART_RXD;\r
- wire UART_TXD;\r
- wire UART_RxValid;\r
- wire [7:0] UART_RxData;\r
- wire UART_TxReady;\r
- wire UART_TxValid;\r
- wire [7:0] UART_TxData;\r
-\r
- demo_uart demo_uart(\r
- .Reset_n( Reset_n ),\r
- .Clk ( Clk ),\r
-\r
- // Interface to UART PHY\r
- .RXD_i( UART_RXD ),\r
- .TXD_o( UART_TXD ),\r
-\r
- // Clk is divided by (Prescaler+1) to generate 16x the bitrate\r
-`ifdef EHDL_SIMULATION\r
- .Prescaler_i( 16'd3 ), // Corresponds to VERY FAST - for simulation only!\r
-`else \r
- .Prescaler_i( 16'd650 ), // Corresponds to 9600 baud (assuming 100 MHz clock)\r
-`endif\r
- \r
- // Pulsed when RxData is valid\r
- .RxValid_o( UART_RxValid ),\r
- .RxData_o ( UART_RxData ),\r
-\r
- // Asserted when ready for a new Tx byte\r
- .TxReady_o( UART_TxReady ),\r
-\r
- // Pulsed when TxData is valid\r
- .TxValid_i( UART_TxValid ),\r
- .TxData_i ( UART_TxData )\r
- );\r
-\r
- // Transmit & receive in parallel on either RS232 or USB/RS232 interface\r
-// assign UART_RXD = RS232_RXD & USB_RXD; // RS232 signals are high when inactive\r
- assign UART_RXD = RS232_RXD;\r
-\r
- assign RS232_TXD = UART_TXD;\r
- assign USB_TXD = UART_TXD;\r
-\r
- //--- UART-to-Wishbone Master ---------------------------------------------\r
-\r
- wire WB_STB_ETH;\r
- wire WB_STB_PDM;\r
- wire WB_STB_PG;\r
- wire WB_CYC;\r
- wire [14:0] WB_ADR;\r
- wire WB_WE;\r
- wire [15:0] WB_DAT_Wr;\r
- wire [15:0] WB_DAT_Rd;\r
- wire WB_ACK;\r
-\r
- demo_wishbone_master demo_wishbone_master(\r
- .Reset_n( Reset_n ),\r
- .Clk ( Clk ),\r
-\r
- //--- UART interface\r
-\r
- // Pulsed when RxData_i is valid\r
- .RxValid_i( UART_RxValid ),\r
- .RxData_i ( UART_RxData ),\r
-\r
- // Asserted when ready for a new Tx byte\r
- .TxReady_i( UART_TxReady ),\r
-\r
- // Pulsed when TxData_o is valid\r
- .TxValid_o( UART_TxValid ),\r
- .TxData_o ( UART_TxData ),\r
-\r
- //--- Wishbone interface\r
- .STB_ETH_O( WB_STB_ETH ),\r
- .STB_PDM_O( WB_STB_PDM ),\r
- .STB_PG_O ( WB_STB_PG ),\r
- .CYC_O ( WB_CYC ),\r
- .ADR_O ( WB_ADR ),\r
- .WE_O ( WB_WE ), \r
- .DAT_O ( WB_DAT_Wr ),\r
- .DAT_I ( WB_DAT_Rd ),\r
- .ACK_I ( WB_ACK )\r
- );\r
-\r
- //--- Wishbone clients ----------------------------------------------------\r
-\r
- //--- Packet Descriptor Memory --------------------------------------------\r
-\r
- wire [15:0] WB_DAT_Rd_PDM;\r
- wire WB_ACK_PDM;\r
-\r
- wire PDM_Rd;\r
- wire [13:0] PDM_Addr;\r
- wire [31:0] PDM_RdData;\r
-\r
- demo_packet_descriptor_memory demo_packet_descriptor_memory(\r
- .Reset_n( Reset_n ),\r
- .Clk ( Clk ),\r
-\r
- //--- Wishbone interface\r
- .STB_I( WB_STB_PDM ),\r
- .CYC_I( WB_CYC ),\r
- .ADR_I( WB_ADR ),\r
- .WE_I ( WB_WE ), \r
- .DAT_I( WB_DAT_Wr ),\r
- .DAT_O( WB_DAT_Rd_PDM ),\r
- .ACK_O( WB_ACK_PDM ),\r
-\r
- //--- Packet Generator interface\r
- // RdData_o is always valid exactly one clock after Addr_i changes\r
- // and Rd_i is asserted\r
- .Rd_i ( PDM_Rd ),\r
- .Addr_i ( PDM_Addr ),\r
- .RdData_o( PDM_RdData )\r
- );\r
-\r
- //--- Packet Generator ----------------------------------------------------\r
-\r
- wire [15:0] WB_DAT_Rd_PG;\r
- wire WB_ACK_PG;\r
-\r
- wire Rx_mac_ra;\r
- wire Rx_mac_rd;\r
- wire [31:0] Rx_mac_data;\r
- wire [1:0] Rx_mac_BE;\r
- wire Rx_mac_pa;\r
- wire Rx_mac_sop;\r
- wire Rx_mac_err;\r
- wire Rx_mac_eop;\r
-\r
- wire Tx_mac_wa;\r
- wire Tx_mac_wr;\r
- wire [31:0] Tx_mac_data;\r
- wire [1:0] Tx_mac_BE;\r
- wire Tx_mac_sop;\r
- wire Tx_mac_eop;\r
-\r
- demo_packet_generator demo_packet_generator(\r
- .Reset_n( Reset_n ),\r
- .Clk ( Clk ),\r
-\r
- //--- Wishbone interface\r
- .STB_I( WB_STB_PG ),\r
- .CYC_I( WB_CYC ),\r
- .ADR_I( WB_ADR[1:0] ),\r
- .WE_I ( WB_WE ),\r
- .DAT_I( WB_DAT_Wr ),\r
- .DAT_O( WB_DAT_Rd_PG ),\r
- .ACK_O( WB_ACK_PG ),\r
-\r
- //--- Packet Descriptor Memory interface\r
- // RdData_i is always valid exactly one clock after Addr_o changes\r
- // and Rd_o is asserted\r
- .Rd_o ( PDM_Rd ),\r
- .Addr_o ( PDM_Addr ),\r
- .RdData_i( PDM_RdData ),\r
-\r
- //--- User (packet) interface\r
- .Rx_mac_ra ( Rx_mac_ra ),\r
- .Rx_mac_rd ( Rx_mac_rd ),\r
- .Rx_mac_data( Rx_mac_data ),\r
- .Rx_mac_BE ( Rx_mac_BE ),\r
- .Rx_mac_pa ( Rx_mac_pa ),\r
- .Rx_mac_sop ( Rx_mac_sop ),\r
- .Rx_mac_err ( Rx_mac_err ),\r
- .Rx_mac_eop ( Rx_mac_eop ),\r
-\r
- .Tx_mac_wa ( Tx_mac_wa ),\r
- .Tx_mac_wr ( Tx_mac_wr ),\r
- .Tx_mac_data( Tx_mac_data ),\r
- .Tx_mac_BE ( Tx_mac_BE ),\r
- .Tx_mac_sop ( Tx_mac_sop ),\r
- .Tx_mac_eop ( Tx_mac_eop )\r
- );\r
-\r
- //--- Simple Wishbone client ----------------------------------------------\r
-\r
- reg [15:0] Reg1;\r
- reg [15:0] Reg2;\r
-\r
- reg WB_ACK_Reg;\r
- reg [15:0] WB_DAT_Reg;\r
-\r
- always @( negedge Reset_n or posedge Clk )\r
- if ( ~Reset_n )\r
- begin\r
- WB_ACK_Reg <= 0;\r
- WB_DAT_Reg <= 'b0;\r
-\r
- Reg1 <= 16'h1234;\r
- Reg2 <= 16'hABCD;\r
- end\r
- else\r
- begin\r
- WB_ACK_Reg <= 0;\r
- if ( WB_CYC & ~( WB_STB_ETH | WB_STB_PG | WB_STB_PDM ) )\r
- begin\r
- WB_ACK_Reg <= 1;\r
- if ( WB_WE )\r
- begin\r
- if ( WB_ADR[0] )\r
- Reg2 <= WB_DAT_Wr;\r
- else\r
- Reg1 <= WB_DAT_Wr;\r
- end\r
- else\r
- begin\r
- if ( WB_ADR[0] )\r
- WB_DAT_Reg <= Reg2;\r
- else\r
- WB_DAT_Reg <= Reg1;\r
- end\r
- end\r
- end\r
-\r
- //--- DUT - Ethernet Core -------------------------------------------------\r
-\r
- wire [15:0] WB_DAT_Rd_ETH;\r
- wire WB_ACK_ETH;\r
-\r
- wire [2:0] Speed;\r
-\r
- MAC_top dut(\r
- // System signals\r
- .Clk_125M( Clk_125M ),\r
- .Clk_user( Clk ),\r
- .Speed ( Speed ),\r
-\r
- // Wishbone compliant core host interface\r
- .RST_I( ~Reset_n ),\r
- .CLK_I( Clk ),\r
- .STB_I( WB_STB_ETH ),\r
- .CYC_I( WB_CYC ),\r
- .ADR_I( WB_ADR[6:0] ),\r
- .WE_I ( WB_WE ),\r
- .DAT_I( WB_DAT_Wr ),\r
- .DAT_O( WB_DAT_Rd_ETH ),\r
- .ACK_O( WB_ACK_ETH ),\r
-\r
- // User (packet) interface\r
- .Rx_mac_ra ( Rx_mac_ra ),\r
- .Rx_mac_rd ( Rx_mac_rd ),\r
- .Rx_mac_data( Rx_mac_data ),\r
- .Rx_mac_BE ( Rx_mac_BE ),\r
- .Rx_mac_pa ( Rx_mac_pa ),\r
- .Rx_mac_sop ( Rx_mac_sop ),\r
- .Rx_mac_err ( Rx_mac_err ),\r
- .Rx_mac_eop ( Rx_mac_eop ),\r
-\r
- .Tx_mac_wa ( Tx_mac_wa ),\r
- .Tx_mac_wr ( Tx_mac_wr ),\r
- .Tx_mac_data( Tx_mac_data ),\r
- .Tx_mac_BE ( Tx_mac_BE ),\r
- .Tx_mac_sop ( Tx_mac_sop ),\r
- .Tx_mac_eop ( Tx_mac_eop ),\r
-\r
- // PHY interface (GMII/MII)\r
- .Gtx_clk( PHY_GTX_CLK ), // Used only in GMII mode\r
- .Rx_clk ( PHY_RXC ),\r
- .Tx_clk ( PHY_TXC ), // Used only in MII mode\r
- .Tx_er ( PHY_TXER ),\r
- .Tx_en ( PHY_TXEN ),\r
- .Txd ( PHY_TXD ),\r
- .Rx_er ( PHY_RXER ),\r
- .Rx_dv ( PHY_RXDV ),\r
- .Rxd ( PHY_RXD ),\r
- .Crs ( PHY_CRS ),\r
- .Col ( PHY_COL ),\r
-\r
- // MDIO interface (to PHY)\r
- .Mdio( PHY_MDIO ),\r
- .Mdc ( PHY_MDC )\r
- );\r
-\r
- //--- Combination of Wishbone read data and acknowledge -------------------\r
-\r
- assign WB_DAT_Rd = ({16{WB_ACK_Reg}} & WB_DAT_Reg ) |\r
- ({16{WB_ACK_PDM}} & WB_DAT_Rd_PDM) |\r
- ({16{WB_ACK_PG }} & WB_DAT_Rd_PG ) |\r
- ({16{WB_ACK_ETH}} & WB_DAT_Rd_ETH);\r
-\r
- assign WB_ACK = WB_ACK_Reg | WB_ACK_PDM | WB_ACK_PG | WB_ACK_ETH;\r
-\r
- assign PHY_RESET_n = Reset_n; \r
-\r
-endmodule\r
+++ /dev/null
-module demo_packet_descriptor_memory(\r
- Reset_n,\r
- Clk,\r
-\r
- //--- Wishbone interface\r
- STB_I,\r
- CYC_I,\r
- ADR_I,\r
- WE_I, \r
- DAT_I,\r
- DAT_O,\r
- ACK_O,\r
-\r
- //--- Packet Generator interface\r
- // RdData_o is always valid exactly one clock after Addr_i changes\r
- // and Rd_i is asserted\r
- Rd_i,\r
- Addr_i,\r
- RdData_o\r
-);\r
-\r
- input Reset_n;\r
- input Clk;\r
-\r
- //--- Wishbone interface\r
- input STB_I;\r
- input CYC_I;\r
- input [14:0] ADR_I;\r
- input WE_I;\r
- input [15:0] DAT_I;\r
- output [15:0] DAT_O;\r
- output ACK_O;\r
-\r
- //--- Packet Generator interface\r
- // RdData_o is always valid exactly one clock after Addr_i changes\r
- // and Rd_i is asserted\r
- input Rd_i;\r
- input [13:0] Addr_i;\r
- output [31:0] RdData_o;\r
-\r
- //-------------------------------------------------------------------------\r
- // Local declarations\r
- //-------------------------------------------------------------------------\r
-\r
- reg ACK_O;\r
-\r
- //-------------------------------------------------------------------------\r
-\r
- wire [15:0] WrDataA = DAT_I;\r
- wire [15:0] RdDataA;\r
- wire [31:0] RdDataB;\r
-\r
- assign DAT_O = RdDataA;\r
- assign RdData_o = RdDataB;\r
-\r
- wire WB_Access = STB_I & CYC_I;\r
- wire WB_AccessClock1;\r
- reg WB_AccessClock2;\r
-\r
- assign WB_AccessClock1 = WB_Access & ~WB_AccessClock2;\r
-\r
- always @( negedge Reset_n or posedge Clk )\r
- if ( ~Reset_n )\r
- begin\r
- WB_AccessClock2 <= 0;\r
- ACK_O <= 0;\r
- end\r
- else\r
- begin\r
- WB_AccessClock2 <= WB_Access;\r
- ACK_O <= WB_AccessClock1;\r
- end\r
-\r
- //-------------------------------------------------------------------------\r
- // Instantiation of sub-modules\r
- //-------------------------------------------------------------------------\r
-\r
- //--- Instantiation of Xilinx 16 Kbit Dual Port Memory --------------------\r
-\r
- RAMB16_S1_S2 RAMB16_S1_S2_bit0 (\r
- .DOA( RdDataA[0] ),\r
- .DOB( { RdDataB[0], RdDataB[16+0] } ),\r
-\r
- .ADDRA( ADR_I[13:0] ),\r
- .DIA ( WrDataA[0] ),\r
- .ENA ( WB_AccessClock1 ),\r
- .CLKA ( Clk ),\r
- .WEA ( WE_I ),\r
- .SSRA ( 1'b0 ),\r
-\r
- .ADDRB( Addr_i[12:0] ),\r
- .DIB ( 2'b00 ),\r
- .ENB ( Rd_i ),\r
- .CLKB ( Clk ),\r
- .WEB ( 1'b0 ),\r
- .SSRB ( 1'b0 )\r
- );\r
-\r
- RAMB16_S1_S2 RAMB16_S1_S2_bit1 (\r
- .DOA( RdDataA[1] ),\r
- .DOB( { RdDataB[1], RdDataB[16+1] } ),\r
-\r
- .ADDRA( ADR_I[13:0] ),\r
- .DIA ( WrDataA[1] ),\r
- .ENA ( WB_AccessClock1 ),\r
- .CLKA ( Clk ),\r
- .WEA ( WE_I ),\r
- .SSRA ( 1'b0 ),\r
-\r
- .ADDRB( Addr_i[12:0] ),\r
- .DIB ( 2'b00 ),\r
- .ENB ( Rd_i ),\r
- .CLKB ( Clk ),\r
- .WEB ( 1'b0 ),\r
- .SSRB ( 1'b0 )\r
- );\r
-\r
- RAMB16_S1_S2 RAMB16_S1_S2_bit2 (\r
- .DOA( RdDataA[2] ),\r
- .DOB( { RdDataB[2], RdDataB[16+2] } ),\r
-\r
- .ADDRA( ADR_I[13:0] ),\r
- .DIA ( WrDataA[2] ),\r
- .ENA ( WB_AccessClock1 ),\r
- .CLKA ( Clk ),\r
- .WEA ( WE_I ),\r
- .SSRA ( 1'b0 ),\r
-\r
- .ADDRB( Addr_i[12:0] ),\r
- .DIB ( 2'b00 ),\r
- .ENB ( Rd_i ),\r
- .CLKB ( Clk ),\r
- .WEB ( 1'b0 ),\r
- .SSRB ( 1'b0 )\r
- );\r
-\r
- RAMB16_S1_S2 RAMB16_S1_S2_bit3 (\r
- .DOA( RdDataA[3] ),\r
- .DOB( { RdDataB[3], RdDataB[16+3] } ),\r
-\r
- .ADDRA( ADR_I[13:0] ),\r
- .DIA ( WrDataA[3] ),\r
- .ENA ( WB_AccessClock1 ),\r
- .CLKA ( Clk ),\r
- .WEA ( WE_I ),\r
- .SSRA ( 1'b0 ),\r
-\r
- .ADDRB( Addr_i[12:0] ),\r
- .DIB ( 2'b00 ),\r
- .ENB ( Rd_i ),\r
- .CLKB ( Clk ),\r
- .WEB ( 1'b0 ),\r
- .SSRB ( 1'b0 )\r
- );\r
-\r
- RAMB16_S1_S2 RAMB16_S1_S2_bit4 (\r
- .DOA( RdDataA[4] ),\r
- .DOB( { RdDataB[4], RdDataB[16+4] } ),\r
-\r
- .ADDRA( ADR_I[13:0] ),\r
- .DIA ( WrDataA[4] ),\r
- .ENA ( WB_AccessClock1 ),\r
- .CLKA ( Clk ),\r
- .WEA ( WE_I ),\r
- .SSRA ( 1'b0 ),\r
-\r
- .ADDRB( Addr_i[12:0] ),\r
- .DIB ( 2'b00 ),\r
- .ENB ( Rd_i ),\r
- .CLKB ( Clk ),\r
- .WEB ( 1'b0 ),\r
- .SSRB ( 1'b0 )\r
- );\r
-\r
- RAMB16_S1_S2 RAMB16_S1_S2_bit5 (\r
- .DOA( RdDataA[5] ),\r
- .DOB( { RdDataB[5], RdDataB[16+5] } ),\r
-\r
- .ADDRA( ADR_I[13:0] ),\r
- .DIA ( WrDataA[5] ),\r
- .ENA ( WB_AccessClock1 ),\r
- .CLKA ( Clk ),\r
- .WEA ( WE_I ),\r
- .SSRA ( 1'b0 ),\r
-\r
- .ADDRB( Addr_i[12:0] ),\r
- .DIB ( 2'b00 ),\r
- .ENB ( Rd_i ),\r
- .CLKB ( Clk ),\r
- .WEB ( 1'b0 ),\r
- .SSRB ( 1'b0 )\r
- );\r
-\r
- RAMB16_S1_S2 RAMB16_S1_S2_bit6 (\r
- .DOA( RdDataA[6] ),\r
- .DOB( { RdDataB[6], RdDataB[16+6] } ),\r
-\r
- .ADDRA( ADR_I[13:0] ),\r
- .DIA ( WrDataA[6] ),\r
- .ENA ( WB_AccessClock1 ),\r
- .CLKA ( Clk ),\r
- .WEA ( WE_I ),\r
- .SSRA ( 1'b0 ),\r
-\r
- .ADDRB( Addr_i[12:0] ),\r
- .DIB ( 2'b00 ),\r
- .ENB ( Rd_i ),\r
- .CLKB ( Clk ),\r
- .WEB ( 1'b0 ),\r
- .SSRB ( 1'b0 )\r
- );\r
-\r
- RAMB16_S1_S2 RAMB16_S1_S2_bit7 (\r
- .DOA( RdDataA[7] ),\r
- .DOB( { RdDataB[7], RdDataB[16+7] } ),\r
-\r
- .ADDRA( ADR_I[13:0] ),\r
- .DIA ( WrDataA[7] ),\r
- .ENA ( WB_AccessClock1 ),\r
- .CLKA ( Clk ),\r
- .WEA ( WE_I ),\r
- .SSRA ( 1'b0 ),\r
-\r
- .ADDRB( Addr_i[12:0] ),\r
- .DIB ( 2'b00 ),\r
- .ENB ( Rd_i ),\r
- .CLKB ( Clk ),\r
- .WEB ( 1'b0 ),\r
- .SSRB ( 1'b0 )\r
- );\r
-\r
- RAMB16_S1_S2 RAMB16_S1_S2_bit8 (\r
- .DOA( RdDataA[8] ),\r
- .DOB( { RdDataB[8], RdDataB[16+8] } ),\r
-\r
- .ADDRA( ADR_I[13:0] ),\r
- .DIA ( WrDataA[8] ),\r
- .ENA ( WB_AccessClock1 ),\r
- .CLKA ( Clk ),\r
- .WEA ( WE_I ),\r
- .SSRA ( 1'b0 ),\r
-\r
- .ADDRB( Addr_i[12:0] ),\r
- .DIB ( 2'b00 ),\r
- .ENB ( Rd_i ),\r
- .CLKB ( Clk ),\r
- .WEB ( 1'b0 ),\r
- .SSRB ( 1'b0 )\r
- );\r
-\r
- RAMB16_S1_S2 RAMB16_S1_S2_bit9 (\r
- .DOA( RdDataA[9] ),\r
- .DOB( { RdDataB[9], RdDataB[16+9] } ),\r
-\r
- .ADDRA( ADR_I[13:0] ),\r
- .DIA ( WrDataA[9] ),\r
- .ENA ( WB_AccessClock1 ),\r
- .CLKA ( Clk ),\r
- .WEA ( WE_I ),\r
- .SSRA ( 1'b0 ),\r
-\r
- .ADDRB( Addr_i[12:0] ),\r
- .DIB ( 2'b00 ),\r
- .ENB ( Rd_i ),\r
- .CLKB ( Clk ),\r
- .WEB ( 1'b0 ),\r
- .SSRB ( 1'b0 )\r
- );\r
-\r
- RAMB16_S1_S2 RAMB16_S1_S2_bit10 (\r
- .DOA( RdDataA[10] ),\r
- .DOB( { RdDataB[10], RdDataB[16+10] } ),\r
-\r
- .ADDRA( ADR_I[13:0] ),\r
- .DIA ( WrDataA[10] ),\r
- .ENA ( WB_AccessClock1 ),\r
- .CLKA ( Clk ),\r
- .WEA ( WE_I ),\r
- .SSRA ( 1'b0 ),\r
-\r
- .ADDRB( Addr_i[12:0] ),\r
- .DIB ( 2'b00 ),\r
- .ENB ( Rd_i ),\r
- .CLKB ( Clk ),\r
- .WEB ( 1'b0 ),\r
- .SSRB ( 1'b0 )\r
- );\r
-\r
- RAMB16_S1_S2 RAMB16_S1_S2_bit11 (\r
- .DOA( RdDataA[11] ),\r
- .DOB( { RdDataB[11], RdDataB[16+11] } ),\r
-\r
- .ADDRA( ADR_I[13:0] ),\r
- .DIA ( WrDataA[11] ),\r
- .ENA ( WB_AccessClock1 ),\r
- .CLKA ( Clk ),\r
- .WEA ( WE_I ),\r
- .SSRA ( 1'b0 ),\r
-\r
- .ADDRB( Addr_i[12:0] ),\r
- .DIB ( 2'b00 ),\r
- .ENB ( Rd_i ),\r
- .CLKB ( Clk ),\r
- .WEB ( 1'b0 ),\r
- .SSRB ( 1'b0 )\r
- );\r
-\r
- RAMB16_S1_S2 RAMB16_S1_S2_bit12 (\r
- .DOA( RdDataA[12] ),\r
- .DOB( { RdDataB[12], RdDataB[16+12] } ),\r
-\r
- .ADDRA( ADR_I[13:0] ),\r
- .DIA ( WrDataA[12] ),\r
- .ENA ( WB_AccessClock1 ),\r
- .CLKA ( Clk ),\r
- .WEA ( WE_I ),\r
- .SSRA ( 1'b0 ),\r
-\r
- .ADDRB( Addr_i[12:0] ),\r
- .DIB ( 2'b00 ),\r
- .ENB ( Rd_i ),\r
- .CLKB ( Clk ),\r
- .WEB ( 1'b0 ),\r
- .SSRB ( 1'b0 )\r
- );\r
-\r
- RAMB16_S1_S2 RAMB16_S1_S2_bit13 (\r
- .DOA( RdDataA[13] ),\r
- .DOB( { RdDataB[13], RdDataB[16+13] } ),\r
-\r
- .ADDRA( ADR_I[13:0] ),\r
- .DIA ( WrDataA[13] ),\r
- .ENA ( WB_AccessClock1 ),\r
- .CLKA ( Clk ),\r
- .WEA ( WE_I ),\r
- .SSRA ( 1'b0 ),\r
-\r
- .ADDRB( Addr_i[12:0] ),\r
- .DIB ( 2'b00 ),\r
- .ENB ( Rd_i ),\r
- .CLKB ( Clk ),\r
- .WEB ( 1'b0 ),\r
- .SSRB ( 1'b0 )\r
- );\r
-\r
- RAMB16_S1_S2 RAMB16_S1_S2_bit14 (\r
- .DOA( RdDataA[14] ),\r
- .DOB( { RdDataB[14], RdDataB[16+14] } ),\r
-\r
- .ADDRA( ADR_I[13:0] ),\r
- .DIA ( WrDataA[14] ),\r
- .ENA ( WB_AccessClock1 ),\r
- .CLKA ( Clk ),\r
- .WEA ( WE_I ),\r
- .SSRA ( 1'b0 ),\r
-\r
- .ADDRB( Addr_i[12:0] ),\r
- .DIB ( 2'b00 ),\r
- .ENB ( Rd_i ),\r
- .CLKB ( Clk ),\r
- .WEB ( 1'b0 ),\r
- .SSRB ( 1'b0 )\r
- );\r
-\r
- RAMB16_S1_S2 RAMB16_S1_S2_bit15 (\r
- .DOA( RdDataA[15] ),\r
- .DOB( { RdDataB[15], RdDataB[16+15] } ),\r
-\r
- .ADDRA( ADR_I[13:0] ),\r
- .DIA ( WrDataA[15] ),\r
- .ENA ( WB_AccessClock1 ),\r
- .CLKA ( Clk ),\r
- .WEA ( WE_I ),\r
- .SSRA ( 1'b0 ),\r
-\r
- .ADDRB( Addr_i[12:0] ),\r
- .DIB ( 2'b00 ),\r
- .ENB ( Rd_i ),\r
- .CLKB ( Clk ),\r
- .WEB ( 1'b0 ),\r
- .SSRB ( 1'b0 )\r
- );\r
-\r
-endmodule\r
+++ /dev/null
-module demo_packet_generator(\r
- Reset_n,\r
- Clk,\r
-\r
- //--- Wishbone interface\r
- STB_I,\r
- CYC_I,\r
- ADR_I,\r
- WE_I,\r
- DAT_I,\r
- DAT_O,\r
- ACK_O,\r
-\r
- //--- Packet Descriptor Memory interface\r
- // RdData_i is always valid exactly one clock after Addr_o changes\r
- // and Rd_o is asserted\r
- Rd_o,\r
- Addr_o,\r
- RdData_i,\r
-\r
- //--- User (packet) interface\r
- Rx_mac_ra,\r
- Rx_mac_rd,\r
- Rx_mac_data,\r
- Rx_mac_BE,\r
- Rx_mac_pa,\r
- Rx_mac_sop,\r
- Rx_mac_err,\r
- Rx_mac_eop,\r
-\r
- Tx_mac_wa,\r
- Tx_mac_wr,\r
- Tx_mac_data,\r
- Tx_mac_BE,\r
- Tx_mac_sop,\r
- Tx_mac_eop\r
-);\r
-\r
- input Reset_n;\r
- input Clk;\r
-\r
- //--- Wishbone interface\r
- input STB_I;\r
- input CYC_I;\r
- input [1:0] ADR_I;\r
- input WE_I;\r
- input [15:0] DAT_I;\r
- output [15:0] DAT_O;\r
- output ACK_O;\r
-\r
- //--- Packet Generator interface\r
- // RdData_o is always valid exactly one clock after Addr_o changes\r
- // and Rd_o is asserted\r
- output Rd_o;\r
- output [13:0] Addr_o;\r
- input [31:0] RdData_i;\r
-\r
- //--- User (packet) interface\r
- input Rx_mac_ra;\r
- output Rx_mac_rd;\r
- input [31:0] Rx_mac_data;\r
- input [1:0] Rx_mac_BE;\r
- input Rx_mac_pa;\r
- input Rx_mac_sop;\r
- input Rx_mac_err;\r
- input Rx_mac_eop;\r
-\r
- input Tx_mac_wa;\r
- output Tx_mac_wr;\r
- output [31:0] Tx_mac_data;\r
- output [1:0] Tx_mac_BE;\r
- output Tx_mac_sop;\r
- output Tx_mac_eop;\r
-\r
- //-------------------------------------------------------------------------\r
- // Local declarations\r
- //-------------------------------------------------------------------------\r
-\r
- reg ACK_O;\r
- reg [15:0] DAT_O;\r
-\r
- reg Rd_o;\r
- reg Tx_mac_wr;\r
- reg [1:0] Tx_mac_BE;\r
- reg Tx_mac_sop;\r
- reg Tx_mac_eop;\r
-\r
- //--- Wishbone interface --------------------------------------------------\r
-\r
- reg [1:0] PG_CFG;\r
- wire PG_Enable = PG_CFG[0];\r
- \r
- always @( negedge Reset_n or posedge Clk )\r
- if ( ~Reset_n )\r
- begin\r
- ACK_O <= 0;\r
- DAT_O <= 'b0;\r
-\r
- PG_CFG <= 2'h0;\r
- end\r
- else\r
- begin\r
- ACK_O <= 0;\r
- if ( CYC_I & STB_I )\r
- begin\r
- ACK_O <= ~ACK_O; // Generate single cycle pulse!\r
- if ( WE_I )\r
- begin\r
- PG_CFG <= DAT_I;\r
- end\r
- else\r
- begin\r
- DAT_O[1:0] <= PG_CFG;\r
- end\r
- end\r
- end\r
-\r
- //--- Packet Generator FSM ------------------------------------------------\r
-\r
- parameter PG_FSM_STATE_IDLE = 3'h0;\r
- parameter PG_FSM_STATE_LD_DESC_1 = 3'h1;\r
- parameter PG_FSM_STATE_LD_DESC_2 = 3'h2;\r
- parameter PG_FSM_STATE_RD_HEADER = 3'h3;\r
- parameter PG_FSM_STATE_PAYLOAD_SEQ_NUMBER = 3'h4;\r
- parameter PG_FSM_STATE_PAYLOAD = 3'h5;\r
- parameter PG_FSM_STATE_DONE = 3'h6;\r
- reg [2:0] PG_FSM_State;\r
-\r
- reg [9:0] DescHigh; // Selects currente descriptor\r
- reg [3:0] DescLow; // Index into a single descriptor (16 entries)\r
-\r
- reg PDM_CFG1_LAST;\r
- reg [3:0] PDM_CFG1_REPEAT;\r
- reg [3:0] PDM_CFG1_HDRLEN;\r
- reg [15:0] PDM_CFG2_PAYLDLEN;\r
-\r
- reg [31:0] Tx_mac_data_reg;\r
- reg WriteHeader;\r
- reg [15:0] PayloadRemaining;\r
- reg [31:0] PacketSequenceNumber;\r
- reg [31:0] Payload;\r
- \r
- always @( negedge Reset_n or posedge Clk )\r
- if ( ~Reset_n )\r
- begin\r
- PG_FSM_State <= PG_FSM_STATE_IDLE;\r
-\r
- Rd_o <= 0;\r
-\r
- DescHigh <= 10'b0;\r
- DescLow <= 4'b0;\r
-\r
- Tx_mac_wr <= 0;\r
- Tx_mac_sop <= 0;\r
- Tx_mac_eop <= 0;\r
- Tx_mac_BE <= 2'b00;\r
-\r
- Tx_mac_data_reg <= 32'b0;\r
- WriteHeader <= 0;\r
- PayloadRemaining <= 16'd0;\r
-\r
- PacketSequenceNumber <= 32'd0;\r
- Payload <= 32'h0;\r
-\r
- { PDM_CFG1_HDRLEN, PDM_CFG1_REPEAT, PDM_CFG1_LAST, PDM_CFG2_PAYLDLEN } <= 'b0;\r
- end\r
- else\r
- begin\r
- casez ( PG_FSM_State )\r
- PG_FSM_STATE_IDLE:\r
- if ( PG_Enable )\r
- begin\r
- PG_FSM_State <= PG_FSM_STATE_LD_DESC_1;\r
- Rd_o <= 1;\r
- end\r
- else\r
- begin\r
- DescHigh <= 10'b0;\r
- DescLow <= 4'b0;\r
- end\r
-\r
- PG_FSM_STATE_LD_DESC_1:\r
- begin\r
- PG_FSM_State <= PG_FSM_STATE_LD_DESC_2;\r
-\r
- DescLow <= DescLow + 1;\r
- end\r
-\r
- PG_FSM_STATE_LD_DESC_2:\r
- begin\r
- PG_FSM_State <= PG_FSM_STATE_RD_HEADER;\r
-\r
- { PDM_CFG1_LAST, PDM_CFG1_REPEAT, PDM_CFG1_HDRLEN, PDM_CFG2_PAYLDLEN } <=\r
- { RdData_i[31], RdData_i[23:20], RdData_i[19:16], RdData_i[15:0] };\r
- end\r
-\r
- PG_FSM_STATE_RD_HEADER:\r
- begin\r
- Tx_mac_wr <= 0;\r
- if ( Tx_mac_wa )\r
- begin\r
- // Space in Tx FIFO - write next header word\r
- DescLow <= DescLow + 1;\r
- Tx_mac_wr <= 1;\r
- Tx_mac_sop <= ( DescLow == 1 ); // Assert SOP on first header word\r
- WriteHeader <= 1;\r
- if ( DescLow == PDM_CFG1_HDRLEN )\r
- begin\r
- // The requested number of header words has been read\r
- // - proceed to generate packet payload\r
- PG_FSM_State <= PG_FSM_STATE_PAYLOAD_SEQ_NUMBER;\r
- PayloadRemaining <= PDM_CFG2_PAYLDLEN;\r
- end\r
- end\r
- end\r
-\r
- PG_FSM_STATE_PAYLOAD_SEQ_NUMBER:\r
- begin\r
- WriteHeader <= 0;\r
- Tx_mac_data_reg <= PacketSequenceNumber;\r
- Tx_mac_wr <= 0;\r
- Tx_mac_sop <= 0;\r
- if ( Tx_mac_wa )\r
- begin\r
- Tx_mac_wr <= 1;\r
- PG_FSM_State <= PG_FSM_STATE_PAYLOAD;\r
- Payload <= 32'h01020304;\r
- PayloadRemaining <= PayloadRemaining - 4;\r
- end\r
- end\r
-\r
- PG_FSM_STATE_PAYLOAD:\r
- begin\r
- Tx_mac_data_reg <= Payload;\r
- Tx_mac_wr <= 0;\r
- if ( Tx_mac_wa )\r
- begin\r
- Tx_mac_wr <= 1;\r
- Tx_mac_data_reg <= Payload;\r
- Payload[31:24] <= Payload[31:24] + 8'h04;\r
- Payload[23:16] <= Payload[23:16] + 8'h04;\r
- Payload[15: 8] <= Payload[15: 8] + 8'h04;\r
- Payload[ 7: 0] <= Payload[ 7: 0] + 8'h04;\r
- PayloadRemaining <= PayloadRemaining - 4;\r
- if ( PayloadRemaining <= 4 )\r
- begin\r
- PG_FSM_State <= PG_FSM_STATE_DONE;\r
-\r
- Tx_mac_eop <= 1;\r
- // Indicate how many bytes are valid in this last transfer\r
- Tx_mac_BE <= PayloadRemaining[1:0];\r
- end\r
- end\r
- end\r
-\r
- PG_FSM_STATE_DONE:\r
- begin\r
- // TBD: Add support for REPEAT, NEXT & LAST!\r
- Tx_mac_wr <= 0;\r
- Tx_mac_eop <= 0;\r
- end\r
- endcase\r
- end\r
-\r
- //-------------------------------------------------------------------------\r
-\r
- assign Tx_mac_data = WriteHeader ?\r
- RdData_i : Tx_mac_data_reg;\r
-\r
- assign Addr_o = { DescHigh, DescLow };\r
-\r
- assign Rx_mac_rd = 0;\r
-\r
-endmodule\r
+++ /dev/null
-module demo_uart(\r
- Reset_n,\r
- Clk,\r
-\r
- // Interface to UART PHY (RS232 level converter)\r
- RXD_i,\r
- TXD_o,\r
-\r
- // Clk is divided by (Prescaler+1) to generate 16x the bitrate\r
- Prescaler_i,\r
-\r
- // Pulsed when RxData is valid\r
- RxValid_o,\r
- RxData_o,\r
-\r
- // Asserted when ready for a new Tx byte\r
- TxReady_o,\r
-\r
- // Pulsed when TxData is valid\r
- TxValid_i,\r
- TxData_i\r
-);\r
-\r
- input Reset_n;\r
- input Clk;\r
-\r
- // Interface to UART PHY (RS232 level converter)\r
- input RXD_i;\r
- output TXD_o;\r
-\r
- // Clk is divided by (Prescaler+1) to generate 16x the bitrate\r
- input [15:0] Prescaler_i;\r
-\r
- // Pulsed when RxData is valid\r
- output RxValid_o;\r
- output [7:0] RxData_o;\r
-\r
- // Asserted when ready for a new Tx byte\r
- output TxReady_o;\r
-\r
- // Pulsed when TxData is valid\r
- input TxValid_i;\r
- input [7:0] TxData_i;\r
-\r
- //-------------------------------------------------------------------------\r
- // Local declarations\r
- //-------------------------------------------------------------------------\r
-\r
- reg TXD_o;\r
- reg RxValid_o;\r
- reg [7:0] RxData_o;\r
- reg TxReady_o;\r
-\r
- //-------------------------------------------------------------------------\r
- // Instantiation of sub-modules\r
- //-------------------------------------------------------------------------\r
-\r
- //--- Prescaler generating 16x bitrate clock ------------------------------\r
-\r
- reg Clk_16x;\r
- reg [15:0] Prescaler;\r
-\r
- always @( negedge Reset_n or posedge Clk )\r
- if ( ~Reset_n )\r
- begin\r
- Prescaler <= 0;\r
- Clk_16x <= 0;\r
- end\r
- else\r
- begin\r
- if ( Prescaler == Prescaler_i )\r
- begin\r
- Prescaler <= 0;\r
- Clk_16x <= 1;\r
- end\r
- else\r
- begin\r
- Prescaler <= Prescaler + 1;\r
- Clk_16x <= 0;\r
- end\r
- end\r
-\r
- //--- Transmitter logic ---------------------------------------------------\r
-\r
- reg [3:0] TxCounter;\r
- reg TxSendBit;\r
-\r
- always @( negedge Reset_n or posedge Clk )\r
- if ( ~Reset_n )\r
- begin\r
- TxCounter <= 0;\r
- TxSendBit <= 0;\r
- end\r
- else\r
- begin\r
- TxSendBit <= 0;\r
- if ( Clk_16x )\r
- begin \r
- if ( TxCounter == 15 )\r
- begin\r
- TxCounter <= 0;\r
- TxSendBit <= 1;\r
- end\r
- else\r
- TxCounter <= TxCounter + 1;\r
- end\r
- end\r
-\r
- reg [7:0] TxData_reg;\r
- reg [3:0] TxBitCnt;\r
- always @( negedge Reset_n or posedge Clk )\r
- if ( ~Reset_n )\r
- begin\r
- TXD_o <= 1;\r
- TxReady_o <= 1;\r
- TxData_reg <= 0;\r
- TxBitCnt <= 0;\r
- end\r
- else\r
- begin\r
- if ( TxReady_o )\r
- begin\r
- if ( TxValid_i )\r
- begin\r
- TxReady_o <= 0;\r
- TxData_reg <= TxData_i;\r
- TxBitCnt <= 0;\r
- end\r
- end\r
- else\r
- begin\r
- if ( TxSendBit )\r
- begin\r
- // Only do anything on bit boundaries\r
- casez ( TxBitCnt )\r
- 0: // Tx START bit\r
- TXD_o <= 0;\r
- 10: // Tx second STOP bit\r
- // Now we're done\r
- TxReady_o <= 1;\r
- default: // Tx data bit + first stop bit\r
- begin\r
- TXD_o <= TxData_reg[0];\r
- TxData_reg <= { 1'b1, TxData_reg[7:1] };\r
- end\r
- endcase\r
- \r
- TxBitCnt <= TxBitCnt+1;\r
- end\r
- end\r
- end\r
-\r
- //--- Receiver logic ------------------------------------------------------\r
-\r
- reg RxHunt;\r
- reg [3:0] RxCounter;\r
- reg RxSampleBit;\r
- reg RxDone;\r
-\r
- always @( negedge Reset_n or posedge Clk )\r
- if ( ~Reset_n )\r
- begin\r
- RxCounter <= 0;\r
- RxSampleBit <= 0;\r
-\r
- RxHunt <= 1;\r
- end\r
- else\r
- begin\r
- RxSampleBit <= 0;\r
-\r
- if ( RxDone )\r
- RxHunt <= 1;\r
-\r
- if ( Clk_16x )\r
- begin\r
- if ( RxHunt )\r
- begin\r
- if ( RXD_i == 0 )\r
- begin\r
- // Receiving start bit!\r
- RxHunt <= 0;\r
- // Reset 16x bit counter\r
- RxCounter <= 0;\r
- end\r
- end\r
- else\r
- begin\r
- RxCounter <= RxCounter + 1;\r
- if ( RxCounter == 7 )\r
- // In middle of Rx bit in next cycle\r
- RxSampleBit <= 1;\r
- end\r
- end\r
- end\r
-\r
- reg [3:0] RxBitCount;\r
-\r
- always @( negedge Reset_n or posedge Clk )\r
- if ( ~Reset_n )\r
- begin\r
- RxValid_o <= 0;\r
- RxData_o <= 'b0;\r
- RxBitCount <= 0;\r
- RxDone <= 0;\r
- end\r
- else\r
- begin\r
- RxValid_o <= 0;\r
- RxDone <= 0;\r
-\r
- if ( RxSampleBit )\r
- begin\r
- RxBitCount <= RxBitCount + 1;\r
-\r
- casez ( RxBitCount )\r
- 0: // START bit - just ignore it\r
- ;\r
- 9: // STOP bit - indicate we're ready again\r
- begin\r
- RxDone <= 1;\r
- RxBitCount <= 0;\r
- end\r
- default: // Rx Data bits\r
- begin\r
- RxData_o <= { RXD_i, RxData_o[7:1] };\r
- if ( RxBitCount == 8 )\r
- // Last data bit just received\r
- RxValid_o <= 1;\r
- end\r
- endcase\r
- end\r
- end\r
-\r
-endmodule\r
+++ /dev/null
-module demo_wishbone_master(\r
- Reset_n,\r
- Clk,\r
-\r
- //--- UART interface\r
-\r
- // Pulsed when RxData_i is valid\r
- RxValid_i,\r
- RxData_i,\r
-\r
- // Asserted when ready for a new Tx byte\r
- TxReady_i,\r
-\r
- // Pulsed when TxData_o is valid\r
- TxValid_o,\r
- TxData_o,\r
-\r
- //--- Wishbone interface\r
- STB_ETH_O,\r
- STB_PDM_O,\r
- STB_PG_O,\r
- CYC_O,\r
- ADR_O,\r
- WE_O, \r
- DAT_O,\r
- DAT_I,\r
- ACK_I\r
-);\r
-\r
- input Reset_n;\r
- input Clk;\r
-\r
- //--- UART interface\r
-\r
- // Pulsed when RxData_i is valid\r
- input RxValid_i;\r
- input [7:0] RxData_i;\r
-\r
- // Asserted when ready for a new Tx byte\r
- input TxReady_i;\r
-\r
- // Pulsed when TxData_o is valid\r
- output TxValid_o;\r
- output [7:0] TxData_o;\r
-\r
- output STB_ETH_O;\r
- output STB_PDM_O;\r
- output STB_PG_O;\r
- output CYC_O;\r
- output [14:0] ADR_O;\r
- output WE_O;\r
- output [15:0] DAT_O;\r
- input [15:0] DAT_I;\r
- input ACK_I;\r
-\r
- //-------------------------------------------------------------------------\r
- // Local declarations\r
- //-------------------------------------------------------------------------\r
-\r
- reg TxValid_o;\r
- reg [7:0] TxData_o;\r
- reg STB_ETH_O;\r
- reg STB_PDM_O;\r
- reg STB_PG_O;\r
- reg CYC_O;\r
- reg [14:0] ADR_O;\r
- reg WE_O;\r
- reg [15:0] DAT_O;\r
-\r
- //-------------------------------------------------------------------------\r
- // Instantiation of sub-modules\r
- //-------------------------------------------------------------------------\r
-\r
- //--- Transmit FSM --------------------------------------------------------\r
-\r
- parameter TX_STATE_IDLE = 0;\r
- parameter TX_STATE_INIT = 1;\r
- parameter TX_STATE_OK = 2;\r
- parameter TX_STATE_ERROR = 3;\r
- parameter TX_STATE_VALUE = 4;\r
- parameter TX_STATE_LF = 5;\r
-\r
- reg [2:0] TxState;\r
- reg [3:0] TxIndex;\r
- reg TxLast;\r
-\r
- wire [15:0] TxValue16;\r
- wire [3:0] TxHexDigit;\r
- wire [7:0] TxHexChar;\r
- reg TxOK;\r
- reg TxERROR;\r
- reg TxValue;\r
-\r
- always @( negedge Reset_n or posedge Clk )\r
- if ( ~Reset_n )\r
- begin\r
- TxState <= TX_STATE_INIT;\r
- TxIndex <= 0;\r
- TxLast <= 0;\r
-\r
- TxValid_o <= 0;\r
- TxData_o <= 'b0;\r
- end\r
- else\r
- begin\r
- TxValid_o <= 0;\r
-\r
- // Don't do anything in cycle following TxValid_o being pulsed\r
- if ( ~TxValid_o )\r
- begin\r
- casez ( TxState )\r
- TX_STATE_INIT:\r
- casez ( TxIndex )\r
- 0: TxData_o <= "R";\r
- 1: TxData_o <= "E";\r
- 2: TxData_o <= "A";\r
- 3: TxData_o <= "D";\r
- 4: TxData_o <= "Y";\r
- default: TxLast <= 1;\r
- endcase\r
- \r
- TX_STATE_OK:\r
- casez ( TxIndex )\r
- 0: TxData_o <= "O";\r
- 1: TxData_o <= "K";\r
- default: TxLast <= 1;\r
- endcase\r
-\r
- TX_STATE_ERROR:\r
- casez ( TxIndex )\r
- 0: TxData_o <= "E";\r
- 1: TxData_o <= "R";\r
- 2: TxData_o <= "R";\r
- 3: TxData_o <= "O";\r
- 4: TxData_o <= "R";\r
- default: TxLast <= 1;\r
- endcase\r
-\r
- TX_STATE_VALUE:\r
- casez ( TxIndex )\r
- 0,1,2,3: TxData_o <= TxHexChar;\r
- default: TxLast <= 1;\r
- endcase\r
-\r
- TX_STATE_LF:\r
- ;\r
-\r
- default:\r
- begin\r
- if ( TxOK )\r
- TxState <= TX_STATE_OK;\r
- else if ( TxERROR )\r
- TxState <= TX_STATE_ERROR;\r
- else if ( TxValue )\r
- begin \r
- TxState <= TX_STATE_VALUE;\r
- TxIndex <= 0;\r
- end\r
- end\r
- endcase\r
-\r
- if ( (TxState != TX_STATE_IDLE) & TxReady_i )\r
- begin\r
- TxValid_o <= 1;\r
-\r
- if ( TxLast )\r
- begin\r
- if ( TxState == TX_STATE_LF )\r
- begin\r
- TxData_o <= 10; // LF\r
- TxState <= TX_STATE_IDLE;\r
- TxIndex <= 0;\r
- TxLast <= 0;\r
- end\r
- else\r
- begin\r
- TxData_o <= 13; // CR\r
- TxState <= TX_STATE_LF;\r
- end\r
- end\r
- else\r
- TxIndex <= TxIndex + 1;\r
- end\r
- end\r
- end\r
-\r
- assign TxHexDigit = (TxIndex==0) ? TxValue16[15:12] :\r
- (TxIndex==1) ? TxValue16[11: 8] :\r
- (TxIndex==2) ? TxValue16[ 7: 4] :\r
- TxValue16[ 3: 0];\r
-\r
- assign TxHexChar = (TxHexDigit <= 9) ? (TxHexDigit + "0") :\r
- (TxHexDigit + "A"-'hA);\r
-\r
- //--- Receive FSM ---------------------------------------------------------\r
-\r
- parameter RX_STATE_IDLE = 0;\r
- parameter RX_STATE_VALUE16_FIRST = 1;\r
- parameter RX_STATE_VALUE16 = 2;\r
- parameter RX_STATE_COMMENT = 3;\r
- parameter RX_STATE_CMD = 4;\r
-\r
- reg [2:0] RxState;\r
-\r
- wire IsWhiteSpace = ( RxData_i==" " ) |\r
- ( RxData_i=="\t" ) |\r
- ( RxData_i=="," ) |\r
- ( RxData_i==10 ) |\r
- ( RxData_i==13 );\r
- wire IsHexDigit = (( RxData_i >= "0" ) & ( RxData_i <= "9" )) |\r
- (( RxData_i >= "a" ) & ( RxData_i <= "f" )) |\r
- (( RxData_i >= "A" ) & ( RxData_i <= "F" ));\r
- wire [3:0] RxHexValue =\r
- (( RxData_i >= "0" ) & ( RxData_i <= "9" )) ? RxData_i[3:0] :\r
- (( RxData_i >= "a" ) & ( RxData_i <= "f" )) ? (RxData_i-"a"+'hA) :\r
- (( RxData_i >= "A" ) & ( RxData_i <= "F" )) ? (RxData_i-"A"+'hA) : 0;\r
-\r
- reg [15:0] RxValue16;\r
- reg RxWrite;\r
- reg RxWrData;\r
-\r
- reg [15:0] RegAddr;\r
- reg [15:0] RegRdData;\r
-\r
- assign TxValue16 = RegRdData;\r
-\r
- always @( negedge Reset_n or posedge Clk )\r
- if ( ~Reset_n )\r
- begin\r
- RxState <= RX_STATE_IDLE;\r
-\r
- RxValue16 <= 16'h0;\r
- RxWrite <= 0;\r
- RxWrData <= 0;\r
-\r
- RegAddr <= 'b0;\r
- RegRdData <= 'b0;\r
-\r
- STB_ETH_O <= 0;\r
- STB_PDM_O <= 0;\r
- STB_PG_O <= 0;\r
- CYC_O <= 0;\r
- ADR_O <= 0;\r
- WE_O <= 0;\r
- DAT_O <= 0;\r
-\r
- TxOK <= 0;\r
- TxERROR <= 0;\r
- TxValue <= 0;\r
- end\r
- else\r
- begin\r
- TxOK <= 0;\r
- TxERROR <= 0;\r
- TxValue <= 0;\r
-\r
- if ( RxState == RX_STATE_CMD )\r
- begin\r
- STB_ETH_O <= ( RegAddr[15:12] == 4'h0 );\r
- STB_PG_O <= ( RegAddr[15:12] == 4'h1 );\r
- STB_PDM_O <= ( RegAddr[15] == 1'b1 );\r
-\r
- CYC_O <= 1;\r
- ADR_O <= RegAddr[14:0];\r
- WE_O <= RxWrite;\r
-\r
- if ( ACK_I )\r
- begin\r
- // Register transaction is completing!\r
- CYC_O <= 0;\r
- STB_ETH_O <= 0;\r
- STB_PDM_O <= 0;\r
- STB_PG_O <= 0;\r
-\r
- // Latch data read in case of a read\r
- RegRdData <= DAT_I;\r
-\r
- if ( RxWrite )\r
- // Transaction was a register write\r
- TxOK <= 1;\r
- else\r
- TxValue <= 1;\r
-\r
- RxState <= RX_STATE_IDLE;\r
- end\r
- end\r
- else if ( (TxState == TX_STATE_IDLE) & RxValid_i )\r
- begin\r
- // A byte has been received!\r
-\r
- casez ( RxState )\r
- RX_STATE_IDLE:\r
- if ( (RxData_i == "w") | (RxData_i == "W") )\r
- begin\r
- // Write Register Command: W rrrr dddd\r
- RxState <= RX_STATE_VALUE16_FIRST;\r
- RxWrite <= 1;\r
- RxWrData <= 0;\r
- end\r
- else if ( (RxData_i == "r") | (RxData_i == "R") )\r
- begin\r
- // Read Register Command: R rrrr\r
- RxState <= RX_STATE_VALUE16_FIRST;\r
- RxWrite <= 0;\r
- end\r
- else if ( RxData_i == "/" )\r
- begin\r
- // Comment!\r
- RxState <= RX_STATE_COMMENT;\r
- end\r
- else if ( ~IsWhiteSpace )\r
- // Unknown command!\r
- TxERROR <= 1;\r
-\r
- RX_STATE_COMMENT:\r
- if ( (RxData_i == 13) | (RxData_i == 10) )\r
- // CR or LF - end of comment\r
- RxState <= RX_STATE_IDLE;\r
-\r
- RX_STATE_VALUE16_FIRST:\r
- if ( IsHexDigit )\r
- begin\r
- RxValue16 <= { 12'b0, RxHexValue };\r
- RxState <= RX_STATE_VALUE16;\r
- end\r
- else if ( ~IsWhiteSpace )\r
- begin\r
- // Unexpected character!\r
- TxERROR <= 1;\r
- RxState <= RX_STATE_IDLE;\r
- end\r
-\r
- RX_STATE_VALUE16:\r
- if ( IsHexDigit )\r
- RxValue16 <= { RxValue16[11:0], RxHexValue };\r
- else if ( IsWhiteSpace )\r
- begin\r
- // Done collecting 16-bit value\r
- if ( RxWrite )\r
- begin\r
- // This is a register write\r
- if ( RxWrData )\r
- begin\r
- // Second time around - just received write data\r
- DAT_O <= RxValue16;\r
- RxState <= RX_STATE_CMD;\r
- end\r
- else\r
- begin\r
- // Just received register address - expecting second argument\r
- RegAddr <= RxValue16;\r
- RxState <= RX_STATE_VALUE16_FIRST;\r
- RxWrData <= 1; // Now receive the write data\r
- end\r
- end\r
- else\r
- begin\r
- // This is a register read\r
- RegAddr <= RxValue16;\r
- RxState <= RX_STATE_CMD;\r
- end\r
- end\r
- else\r
- begin\r
- // Unexpected character!\r
- TxERROR <= 1;\r
- RxState <= RX_STATE_IDLE;\r
- end\r
-\r
- default:\r
- TxERROR <= 1;\r
- endcase\r
- end\r
- end\r
- \r
-endmodule\r
+++ /dev/null
-`timescale 1ns / 1ns\r
-\r
-module tb_demo;\r
-\r
- //-------------------- Instantiate Xilinx glbl module ----------------------\r
- // - this is needed to get ModelSim to work because e.g. I/O buffer models\r
- // refer directly to glbl.GTS and similar signals\r
-\r
- wire GSR;\r
- wire GTS;\r
- xlnx_glbl glbl( .GSR( GSR ), .GTS( GTS ) );\r
-\r
- reg VLOG_ExitSignal = 0;\r
- reg Done = 0;\r
- reg Error = 0;\r
-\r
- //-------------------------------------------------------------------------\r
-\r
- reg Reset_n;\r
- reg Clk_100M;\r
- reg Clk_125M;\r
-\r
- wire RS232_TXD;\r
- wire RS232_RXD;\r
-\r
- wire USB_TXD;\r
- wire USB_RXD;\r
-\r
- //--- 10/100/1000BASE-T Ethernet PHY (MII/GMII)\r
- wire PHY_RESET_n;\r
-\r
- wire PHY_RXC;\r
- wire [7:0] PHY_RXD;\r
- wire PHY_RXDV;\r
- wire PHY_RXER;\r
-\r
- wire PHY_GTX_CLK; // GMII only\r
- wire PHY_TXC;\r
- wire [7:0] PHY_TXD;\r
- wire PHY_TXEN;\r
- wire PHY_TXER;\r
-\r
- wire PHY_COL = 0;\r
- wire PHY_CRS = 0;\r
-\r
- wire PHY_MDC;\r
- wire PHY_MDIO;\r
-\r
- wire [1:4] LED;\r
-\r
- reg [1:4] Button = 4'b0000;\r
-\r
- //-------------------------------------------------------------------------\r
- // Local declarations\r
- //-------------------------------------------------------------------------\r
-\r
- //-------------------------------------------------------------------------\r
- // Instantiation of sub-modules\r
- //-------------------------------------------------------------------------\r
-\r
- //--- DUT\r
-\r
- demo demo(\r
- .Reset_n ( Reset_n ),\r
- .Clk_100M( Clk_100M ),\r
- .Clk_125M( Clk_125M ),\r
-\r
- .RS232_TXD( RS232_TXD ),\r
- .RS232_RXD( RS232_RXD ),\r
-\r
- .USB_TXD( USB_TXD ),\r
- .USB_RXD( USB_RXD ),\r
-\r
- //--- 10/100/1000BASE-T Ethernet PHY (MII/GMII)\r
- .PHY_RESET_n( PHY_RESET_n ),\r
-\r
- .PHY_RXC ( PHY_RXC ),\r
- .PHY_RXD ( PHY_RXD ),\r
- .PHY_RXDV( PHY_RXDV ),\r
- .PHY_RXER( PHY_RXER ),\r
-\r
- .PHY_GTX_CLK( PHY_GTX_CLK ), // GMII only\r
- .PHY_TXC ( PHY_TXC ),\r
- .PHY_TXD ( PHY_TXD ),\r
- .PHY_TXEN ( PHY_TXEN ),\r
- .PHY_TXER ( PHY_TXER ),\r
-\r
- .PHY_COL( PHY_COL ),\r
- .PHY_CRS( PHY_CRS ),\r
-\r
- .PHY_MDC ( PHY_MDC ),\r
- .PHY_MDIO( PHY_MDIO ),\r
-\r
- // Misc. I/Os\r
- .LED ( LED ),\r
- .Button( Button )\r
- );\r
-\r
- //-------------------------------------------------------------------------\r
- // MII/GMII Ethernet PHY model\r
-\r
- reg [2:0] Speed = 3'b000;\r
-\r
- Phy_sim U_Phy_sim(\r
- .Gtx_clk( PHY_GTX_CLK ),\r
- .Rx_clk ( PHY_RXC ),\r
- .Tx_clk ( PHY_TXC ),\r
- .Tx_er ( PHY_TXER ),\r
- .Tx_en ( PHY_TXEN ),\r
- .Txd ( PHY_TXD ),\r
- .Rx_er ( PHY_RXER ),\r
- .Rx_dv ( PHY_RXDV ),\r
- .Rxd ( PHY_RXD ),\r
- .Crs ( PHY_CRS ),\r
- .Col ( PHY_COL ),\r
- .Speed ( Speed ),\r
- .Done ( Done )\r
- );\r
-\r
- //-------------------------------------------------------------------------\r
- // Generate all clocks & reset\r
- //-------------------------------------------------------------------------\r
-\r
- // Core master clock (100 MHz)\r
- initial \r
- begin\r
- #10;\r
- while ( !Done )\r
- begin\r
- #5 Clk_100M = 0;\r
- #5 Clk_100M = 1;\r
- end\r
- end\r
-\r
- // GMII master clock (125 MHz)\r
- initial \r
- begin\r
- #10;\r
- while ( !Done )\r
- begin\r
- #4 Clk_125M = 0;\r
- #4 Clk_125M = 1;\r
- end\r
- end\r
-\r
- initial\r
- begin\r
- Reset_n = 0;\r
-\r
- #103;\r
- Reset_n = 1;\r
- end\r
-\r
- //--- Emulate UART Transmitter --------------------------------------------\r
-\r
- parameter PRESCALER_16X = 3;\r
- integer Prescaler;\r
- integer TxLen = 0;\r
- reg [2:0] TxState;\r
- integer TxBit;\r
- reg [1023:0] TxMsg;\r
- reg TXD;\r
- reg TxDone;\r
-\r
- always @( negedge Reset_n or posedge Clk_100M )\r
- if ( ~Reset_n )\r
- begin\r
- Prescaler <= 0;\r
- TxState = 0;\r
- TXD = 1;\r
- TxBit = 0;\r
- TxDone <= 0;\r
- end\r
- else\r
- begin\r
- TxDone <= 0;\r
-\r
- if ( Prescaler == ((PRESCALER_16X + 1)*16 -1) )\r
- Prescaler <= 0;\r
- else\r
- Prescaler <= Prescaler + 1;\r
-\r
- if ( Prescaler==0 )\r
- begin\r
- casez ( TxState )\r
- 0: // IDLE\r
- begin\r
- if ( TxLen != 0 )\r
- begin // Send start bit!\r
- TxBit = (TxLen-1)*8;\r
- TxLen = TxLen - 1;\r
- TXD = 0;\r
- TxState = 1;\r
- end\r
- end\r
-\r
- 1: // Send next data bit\r
- begin\r
- // Send next data bit\r
- TXD = TxMsg[ TxBit ];\r
- TxBit = TxBit + 1;\r
- if ( (TxBit % 8)==0 )\r
- // Next send two stop bits\r
- TxState = 2;\r
- end\r
-\r
- 2: // First of two stop bits\r
- begin\r
- TXD = 1;\r
- TxState = 3;\r
- end\r
-\r
- 3: // Second of two stop bits\r
- begin\r
- TXD = 1;\r
- TxState = 0;\r
- if ( TxLen == 0 )\r
- // Done with transmission!\r
- TxDone <= 1;\r
- end\r
- endcase\r
- end\r
- end\r
-\r
- assign RS232_RXD = TXD;\r
- assign USB_RXD = 1;\r
-\r
- //--- Send commands to the DUT --------------------------------------------\r
-\r
- initial\r
- begin\r
- #10;\r
- while ( ~Reset_n ) #10;\r
-\r
- // Wait a couple of clock edges before continuing to allow\r
- // internal logic to get out of reset\r
- repeat ( 5 )\r
- @( posedge Clk_100M );\r
-\r
- // Wait for the "READY" message to complete transmission\r
- #60000;\r
-\r
- // Select 100 Mbps\r
- Speed = 3'b010;\r
- TxMsg = "W 0022 0002 ";\r
- TxLen = 12;\r
- while ( ~TxDone )\r
- @( posedge Clk_100M );\r
-\r
- #50000;\r
-\r
- TxMsg = "W 8000 8003 ";\r
- TxLen = 12;\r
- while ( ~TxDone )\r
- @( posedge Clk_100M );\r
-\r
- #50000;\r
-\r
- TxMsg = "W 8001 0011 ";\r
- TxLen = 12;\r
- while ( ~TxDone )\r
- @( posedge Clk_100M );\r
-\r
- #50000;\r
-\r
- TxMsg = "W 8002 1234 ";\r
- TxLen = 12;\r
- while ( ~TxDone )\r
- @( posedge Clk_100M );\r
-\r
- #50000;\r
-\r
- TxMsg = "W 8003 5678 ";\r
- TxLen = 12;\r
- while ( ~TxDone )\r
- @( posedge Clk_100M );\r
-\r
- #50000;\r
-\r
- TxMsg = "W 8004 9ABC ";\r
- TxLen = 12;\r
- while ( ~TxDone )\r
- @( posedge Clk_100M );\r
-\r
- #50000;\r
-\r
- TxMsg = "W 8005 DEF0 ";\r
- TxLen = 12;\r
- while ( ~TxDone )\r
- @( posedge Clk_100M );\r
-\r
- #50000;\r
-\r
- TxMsg = "W 8006 C5C0 ";\r
- TxLen = 12;\r
- while ( ~TxDone )\r
- @( posedge Clk_100M );\r
-\r
- #50000;\r
-\r
- TxMsg = "W 8007 BABE ";\r
- TxLen = 12;\r
- while ( ~TxDone )\r
- @( posedge Clk_100M );\r
-\r
- #50000;\r
-\r
- TxMsg = "R 8006 ";\r
- TxLen = 7;\r
- while ( ~TxDone )\r
- @( posedge Clk_100M );\r
-\r
- #50000;\r
-\r
- // Enable PG!\r
- TxMsg = "W 1000 0001 ";\r
- TxLen = 12;\r
- while ( ~TxDone )\r
- @( posedge Clk_100M );\r
-\r
- #50000;\r
-\r
- // Read back that PG has been enabled!\r
- TxMsg = "R 1000 ";\r
- TxLen = 7;\r
- while ( ~TxDone )\r
- @( posedge Clk_100M );\r
-\r
- #50000;\r
-\r
- #50000;\r
-\r
- Done = 1; #10;\r
-\r
- $stop;\r
- end\r
-\r
- //--- Directly accesses a register on the internal Wishbone bus, bypassing the UART interface\r
-\r
- task WrReg;\r
- input [15:0] Reg;\r
- input [15:0] Data;\r
-\r
- begin\r
- end\r
- endtask\r
-\r
-endmodule\r
+++ /dev/null
-
-module header_ram
- #(parameter REGNUM=0,
- parameter WIDTH=32)
- (input clk,
- input set_stb,
- input [7:0] set_addr,
- input [31:0] set_data,
-
- input [3:0] addr,
- output [31:0] q
- );
-
- reg [WIDTH-1:0] mini_ram[0:15];
- wire write_to_ram = (set_stb & (set_addr[7:4]==REGNUM[7:4]));
- wire [3:0] ram_addr = write_to_ram ? set_addr[3:0] : addr;
-
- always @(posedge clk)
- if(write_to_ram)
- mini_ram[ram_addr] <= set_data;
-
- assign q = mini_ram[ram_addr];
-
-endmodule // header_ram
+++ /dev/null
-
-module mac_rxfifo_int
- (input clk, input rst,
-
- input Rx_mac_empty,
- output Rx_mac_rd,
- input [31:0] Rx_mac_data,
- input [1:0] Rx_mac_BE,
- input Rx_mac_sop,
- input Rx_mac_eop,
- input Rx_mac_err,
-
- output [31:0] wr_dat_o,
- output wr_write_o,
- output wr_done_o,
- output wr_error_o,
- input wr_ready_i,
- input wr_full_i,
-
- // FIFO Status
- output [15:0] fifo_occupied,
- output fifo_full,
- output fifo_empty
- );
-
- // Write side of short FIFO
- // Inputs: full, Rx_mac_empty, Rx_mac_sop, Rx_mac_eop, Rx_mac_err, Rx_mac_data/BE
- // Controls: write, datain, Rx_mac_rd
-
- wire write, full, read, empty, sop_o, eop_o, error_o;
-
- // Write side of short FIFO
- assign write = ~full & ~Rx_mac_empty;
- assign Rx_mac_rd = write;
-
-`define LONGFIFO 0
-
-`ifdef LONGFIFO
- cascadefifo2 #(.WIDTH(35),.SIZE(10)) mac_rx_longfifo
- (.clk(clk),.rst(rst),.clear(0),
- .datain({Rx_mac_sop,Rx_mac_eop,Rx_mac_err,Rx_mac_data}),.write(write),.full(full),
- .dataout({sop_o,eop_o,error_o,wr_dat_o}),.read(read),.empty(empty),
- .space(), .occupied(fifo_occupied) );
-`else
- shortfifo #(.WIDTH(35)) mac_rx_sfifo
- (.clk(clk),.rst(rst),.clear(0),
- .datain({Rx_mac_sop,Rx_mac_eop,Rx_mac_err,Rx_mac_data}),.write(write),.full(full),
- .dataout({sop_o,eop_o,error_o,wr_dat_o}),.read(read),.empty(empty),
- .space(), .occupied(fifo_occupied[4:0]) );
- assign fifo_occupied[15:5] = 0;
-`endif
-
- assign fifo_full = full;
- assign fifo_empty = empty;
-
- // Read side of short FIFO
- // Inputs: empty, dataout, wr_ready_i, wr_full_i
- // Controls: read, wr_dat_o, wr_write_o, wr_done_o, wr_error_o
-
- reg [1:0] rd_state;
- localparam RD_IDLE = 0;
- localparam RD_HAVEPKT = 1;
- localparam RD_XFER = 2;
- localparam RD_ERROR = 3;
-
- always @(posedge clk)
- if(rst)
- rd_state <= RD_IDLE;
- else
- case(rd_state)
- RD_IDLE :
- if(sop_o & ~empty)
- rd_state <= RD_HAVEPKT;
- RD_HAVEPKT :
- if(wr_ready_i)
- rd_state <= RD_XFER;
- RD_XFER :
- if(eop_o & ~empty)
- rd_state <= RD_IDLE;
- else if(wr_full_i)
- rd_state <= RD_HAVEPKT;
- RD_ERROR :
- rd_state <= RD_IDLE;
- endcase // case(rd_state)
-
- assign read = ~empty & ((rd_state == RD_XFER) | ((rd_state==RD_IDLE)&~sop_o));
- assign wr_write_o = ~empty & (rd_state == RD_XFER);
- assign wr_done_o = ~empty & (rd_state == RD_XFER) & eop_o;
- assign wr_error_o = ~empty & (rd_state == RD_XFER) & error_o;
-
-endmodule // mac_rxfifo_int
+++ /dev/null
-
-module mac_txfifo_int
- (input clk, input rst, input mac_clk,
-
- // To MAC
- input Tx_mac_wa,
- output Tx_mac_wr,
- output [31:0] Tx_mac_data,
- output [1:0] Tx_mac_BE,
- output Tx_mac_sop,
- output Tx_mac_eop,
-
- // To buffer interface
- input [31:0] rd_dat_i,
- output rd_read_o,
- output rd_done_o,
- output rd_error_o,
- input rd_sop_i,
- input rd_eop_i,
-
- // FIFO Status
- output [15:0] fifo_occupied,
- output fifo_full,
- output fifo_empty );
-
- wire empty, full, sfifo_write, sfifo_read;
- wire [33:0] sfifo_in, sfifo_out;
-
- /*
- shortfifo #(.WIDTH(34)) txmac_sfifo
- (.clk(clk),.rst(rst),.clear(0),
- .datain(sfifo_in),.write(sfifo_write),.full(full),
- .dataout(sfifo_out),.read(sfifo_read),.empty(empty));
- */
- fifo_xlnx_512x36_2clk mac_tx_fifo_2clk
- (.rst(rst),
- .wr_clk(clk),.din({2'b0,sfifo_in}),.full(full),.wr_en(sfifo_write),.wr_data_count(fifo_occupied[8:0]),
- .rd_clk(mac_clk),.dout(sfifo_out),.empty(empty),.rd_en(sfifo_read),.rd_data_count() );
- assign fifo_occupied[15:9] = 0;
- assign fifo_full = full;
- assign fifo_empty = empty; // Note empty is in wrong clock domain
-
- // MAC side signals
- // We are allowed to do one more write after we are told the FIFO is full
- // This allows us to register the _wa signal and speed up timing.
-
- reg tx_mac_wa_d1;
- always @(posedge clk)
- tx_mac_wa_d1 <= Tx_mac_wa;
-
- assign sfifo_read = ~empty & tx_mac_wa_d1;
-
- assign Tx_mac_wr = sfifo_read;
- assign Tx_mac_data = sfifo_out[31:0];
- assign Tx_mac_BE = 0; // Since we only deal with packets that are multiples of 32 bits long
- assign Tx_mac_sop = sfifo_out[33];
- assign Tx_mac_eop = sfifo_out[32];
-
-
- // BUFFER side signals
- reg xfer_active;
- always @(posedge clk)
- if(rst)
- xfer_active <= 0;
- else if(rd_eop_i & ~full)
- xfer_active <= 0;
- else if(rd_sop_i)
- xfer_active <= 1;
-
- assign sfifo_in = {rd_sop_i, rd_eop_i, rd_dat_i};
- assign sfifo_write = xfer_active & ~full;
-
- assign rd_read_o = sfifo_write;
- assign rd_done_o = 0; // Always send everything we're given?
- assign rd_error_o = 0; // No possible error situations?
-
-endmodule // mac_txfifo_int
+++ /dev/null
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// Clk_ctrl.v ////\r
-//// ////\r
-//// This file is part of the Ethernet IP core project ////\r
-//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////\r
-//// ////\r
-//// Author(s): ////\r
-//// - Jon Gao (gaojon@yahoo.com) ////\r
-//// ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// Copyright (C) 2001 Authors ////\r
-//// ////\r
-//// This source file may be used and distributed without ////\r
-//// restriction provided that this copyright statement is not ////\r
-//// removed from the file and that any derivative work contains ////\r
-//// the original copyright notice and the associated disclaimer. ////\r
-//// ////\r
-//// This source file is free software; you can redistribute it ////\r
-//// and/or modify it under the terms of the GNU Lesser General ////\r
-//// Public License as published by the Free Software Foundation; ////\r
-//// either version 2.1 of the License, or (at your option) any ////\r
-//// later version. ////\r
-//// ////\r
-//// This source is distributed in the hope that it will be ////\r
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\r
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\r
-//// PURPOSE. See the GNU Lesser General Public License for more ////\r
-//// details. ////\r
-//// ////\r
-//// You should have received a copy of the GNU Lesser General ////\r
-//// Public License along with this source; if not, download it ////\r
-//// from http://www.opencores.org/lgpl.shtml ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-// \r
-// CVS Revision History \r
-// \r
-// $Log: Clk_ctrl.v,v $\r
-// Revision 1.3 2006/01/19 14:07:52 maverickist\r
-// verification is complete.\r
-//\r
-// Revision 1.2 2005/12/16 06:44:13 Administrator\r
-// replaced tab with space.\r
-// passed 9.6k length frame test.\r
-//\r
-// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator\r
-// no message\r
-// \r
-\r
-module Clk_ctrl( \r
-Reset ,\r
-Clk_125M ,\r
-//host interface,\r
-Speed ,\r
-//Phy interface ,\r
-Gtx_clk ,\r
-Rx_clk ,\r
-Tx_clk ,\r
-//interface clk ,\r
-MAC_tx_clk ,\r
-MAC_rx_clk ,\r
-MAC_tx_clk_div ,\r
-MAC_rx_clk_div \r
-);\r
-input Reset ;\r
-input Clk_125M ;\r
- //host interface\r
-input [2:0] Speed ; \r
- //Phy interface \r
-output Gtx_clk ;//used only in GMII mode\r
-input Rx_clk ;\r
-input Tx_clk ;//used only in MII mode\r
- //interface clk signals\r
-output MAC_tx_clk ;\r
-output MAC_rx_clk ;\r
-output MAC_tx_clk_div ;\r
-output MAC_rx_clk_div ;\r
-\r
-\r
-// ******************************************************************************\r
-// internal signals \r
-// ******************************************************************************\r
-wire Rx_clk_div2 ;\r
-wire Tx_clk_div2 ;\r
-// ******************************************************************************\r
-// \r
-// ******************************************************************************\r
- assign Gtx_clk = Clk_125M ;\r
- assign MAC_rx_clk = Rx_clk ;\r
- assign MAC_rx_clk_div = Rx_clk ;\r
- assign MAC_tx_clk = Clk_125M;\r
- assign MAC_tx_clk_div = Clk_125M;\r
- \r
-\r
- /* \r
-eth_clk_div2 U_0_CLK_DIV2(\r
-.Reset (Reset ),\r
-.IN (Rx_clk ),\r
-.OUT (Rx_clk_div2 )\r
-);\r
-\r
-eth_clk_div2 U_1_CLK_DIV2(\r
-.Reset (Reset ),\r
-.IN (Tx_clk ),\r
-.OUT (Tx_clk_div2 )\r
-);\r
-\r
-eth_clk_switch U_0_CLK_SWITCH(\r
-.IN_0 (Rx_clk_div2 ),\r
-.IN_1 (Rx_clk ),\r
-.SW (Speed[2] ),\r
-.OUT (MAC_rx_clk_div )\r
-);\r
-\r
-eth_clk_switch U_1_CLK_SWITCH(\r
-.IN_0 (Tx_clk ),\r
-.IN_1 (Clk_125M ),\r
-.SW (Speed[2] ),\r
-.OUT (MAC_tx_clk )\r
-);\r
-\r
-eth_clk_switch U_2_CLK_SWITCH(\r
-.IN_0 (Tx_clk_div2 ),\r
-.IN_1 (Clk_125M ),\r
-.SW (Speed[2] ),\r
-.OUT (MAC_tx_clk_div )\r
-);\r
-\r
- */\r
-endmodule\r
+++ /dev/null
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// MAC_rx.v ////\r
-//// ////\r
-//// This file is part of the Ethernet IP core project ////\r
-//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////\r
-//// ////\r
-//// Author(s): ////\r
-//// - Jon Gao (gaojon@yahoo.com) ////\r
-//// ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// Copyright (C) 2001 Authors ////\r
-//// ////\r
-//// This source file may be used and distributed without ////\r
-//// restriction provided that this copyright statement is not ////\r
-//// removed from the file and that any derivative work contains ////\r
-//// the original copyright notice and the associated disclaimer. ////\r
-//// ////\r
-//// This source file is free software; you can redistribute it ////\r
-//// and/or modify it under the terms of the GNU Lesser General ////\r
-//// Public License as published by the Free Software Foundation; ////\r
-//// either version 2.1 of the License, or (at your option) any ////\r
-//// later version. ////\r
-//// ////\r
-//// This source is distributed in the hope that it will be ////\r
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\r
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\r
-//// PURPOSE. See the GNU Lesser General Public License for more ////\r
-//// details. ////\r
-//// ////\r
-//// You should have received a copy of the GNU Lesser General ////\r
-//// Public License along with this source; if not, download it ////\r
-//// from http://www.opencores.org/lgpl.shtml ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-// \r
-// CVS Revision History \r
-// \r
-// $Log: MAC_rx.v,v $\r
-// Revision 1.4 2006/11/17 17:53:07 maverickist\r
-// no message\r
-//\r
-// Revision 1.3 2006/01/19 14:07:52 maverickist\r
-// verification is complete.\r
-//\r
-// Revision 1.2 2005/12/16 06:44:13 Administrator\r
-// replaced tab with space.\r
-// passed 9.6k length frame test.\r
-//\r
-// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator\r
-// no message\r
-// \r
-\r
-module MAC_rx \r
- #(parameter RX_FF_DEPTH = 9)\r
- (\r
-input Reset ,\r
-input Clk_user,\r
-input Clk ,\r
- //RMII interface\r
-input MCrs_dv , \r
-input [7:0] MRxD , \r
-input MRxErr , \r
- //flow_control signals \r
-output [15:0] pause_quanta, \r
-output pause_quanta_val, \r
-output [15:0] rx_fifo_space,\r
- //user interface \r
-output Rx_mac_empty,\r
-input Rx_mac_rd ,\r
-output [31:0] Rx_mac_data ,\r
-output [1:0] Rx_mac_BE ,\r
-output Rx_mac_sop ,\r
-output Rx_mac_eop ,\r
-output Rx_mac_err ,\r
- //CPU\r
-input MAC_rx_add_chk_en , \r
-input [7:0] MAC_add_prom_data , \r
-input [2:0] MAC_add_prom_add , \r
-input MAC_add_prom_wr , \r
-input broadcast_filter_en ,\r
-input [15:0] broadcast_bucket_depth , \r
-input [15:0] broadcast_bucket_interval ,\r
-input RX_APPEND_CRC,\r
-input [4:0] Rx_Hwmark ,\r
-input [4:0] Rx_Lwmark ,\r
-input CRC_chk_en , \r
-input [5:0] RX_IFG_SET ,\r
-input [15:0] RX_MAX_LENGTH ,// 1518\r
-input [6:0] RX_MIN_LENGTH ,// 64\r
- //RMON interface\r
-output [15:0] Rx_pkt_length_rmon ,\r
-output Rx_apply_rmon ,\r
-output [2:0] Rx_pkt_err_type_rmon ,\r
-output [2:0] Rx_pkt_type_rmon ,\r
-\r
- output [15:0] rx_fifo_occupied,\r
- output rx_fifo_full,\r
- output rx_fifo_empty,\r
- output [31:0] debug\r
-);\r
-//******************************************************************************\r
-//internal signals \r
-//******************************************************************************\r
- //CRC_chk interface\r
-wire CRC_en ; \r
-wire [7:0] CRC_data;\r
-wire CRC_init; \r
-wire CRC_err ;\r
- //MAC_rx_add_chk interface\r
-wire MAC_add_en ;\r
-wire [7:0] MAC_add_data;\r
-wire MAC_rx_add_chk_err ;\r
- //broadcast_filter\r
-wire broadcast_ptr ;\r
-wire broadcast_drop ;\r
- //MAC_rx_ctrl interface \r
-wire [7:0] Fifo_data ;\r
-wire Fifo_data_en ;\r
-wire Fifo_full ;\r
-wire Fifo_data_err ;\r
-wire Fifo_data_drop ;\r
-wire Fifo_data_end ;\r
-\r
-\r
-//******************************************************************************\r
-//instantiation \r
-//******************************************************************************\r
-\r
-\r
-MAC_rx_ctrl U_MAC_rx_ctrl(\r
-.Reset (Reset ), \r
-.Clk (Clk ), \r
- //RMII interface ( //RMII interface ), \r
-.MCrs_dv (MCrs_dv ), \r
-.MRxD (MRxD ), \r
-.MRxErr (MRxErr ), \r
- //CRC_chk interface (//CRC_chk interface ), \r
-.CRC_en (CRC_en ), \r
-.CRC_data (CRC_data ), \r
-.CRC_init (CRC_init ), \r
-.CRC_err (CRC_err ), \r
- //MAC_rx_add_chk interface (//MAC_rx_add_chk interface), \r
-.MAC_add_en (MAC_add_en ), \r
-.MAC_add_data (MAC_add_data ),\r
-.MAC_rx_add_chk_err (MAC_rx_add_chk_err ), \r
- //broadcast_filter (//broadcast_filter ), \r
-.broadcast_ptr (broadcast_ptr ), \r
-.broadcast_drop (broadcast_drop ), \r
- //flow_control signals (//flow_control signals ), \r
-.pause_quanta (pause_quanta ), \r
-.pause_quanta_val (pause_quanta_val ), \r
- //MAC_rx_FF interface (//MAC_rx_FF interface ), \r
-.Fifo_data (Fifo_data ), \r
-.Fifo_data_en (Fifo_data_en ), \r
-.Fifo_data_err (Fifo_data_err ), \r
-.Fifo_data_drop (Fifo_data_drop ), \r
-.Fifo_data_end (Fifo_data_end ), \r
-.Fifo_full (Fifo_full ), \r
- //RMON interface (//RMON interface ), \r
-.Rx_pkt_type_rmon (Rx_pkt_type_rmon ), \r
-.Rx_pkt_length_rmon (Rx_pkt_length_rmon ), \r
-.Rx_apply_rmon (Rx_apply_rmon ), \r
-.Rx_pkt_err_type_rmon (Rx_pkt_err_type_rmon ), \r
- //CPU (//CPU ), \r
-.RX_IFG_SET (RX_IFG_SET ), \r
-.RX_MAX_LENGTH (RX_MAX_LENGTH ), \r
-.RX_MIN_LENGTH (RX_MIN_LENGTH ) \r
-);\r
-\r
- assign debug = {28'd0, Fifo_data_en, Fifo_data_err, Fifo_data_end,Fifo_full};\r
- \r
-MAC_rx_FF #(.RX_FF_DEPTH(RX_FF_DEPTH)) U_MAC_rx_FF (\r
-.Reset (Reset ),\r
-.Clk_MAC (Clk ), \r
-.Clk_SYS (Clk_user ), \r
- //MAC_rx_ctrl interface (//MAC_rx_ctrl interface ),\r
-.Fifo_data (Fifo_data ),\r
-.Fifo_data_en (Fifo_data_en ),\r
-.Fifo_full (Fifo_full ),\r
-.Fifo_data_err (Fifo_data_err ),\r
-//.Fifo_data_drop (Fifo_data_drop ),\r
-.Fifo_data_end (Fifo_data_end ),\r
-.Fifo_space (rx_fifo_space ), \r
- //CPU (//CPU ),\r
-.Rx_Hwmark (Rx_Hwmark ),\r
-.Rx_Lwmark (Rx_Lwmark ),\r
-.RX_APPEND_CRC (RX_APPEND_CRC ),\r
- //user interface (//user interface ),\r
-.Rx_mac_empty (Rx_mac_empty ),\r
-.Rx_mac_rd (Rx_mac_rd ),\r
-.Rx_mac_data (Rx_mac_data ), \r
-.Rx_mac_BE (Rx_mac_BE ),\r
-.Rx_mac_sop (Rx_mac_sop ), \r
-.Rx_mac_eop (Rx_mac_eop ),\r
-.Rx_mac_err (Rx_mac_err ),\r
-\r
-.fifo_occupied(rx_fifo_occupied),\r
-.fifo_full_dbg(rx_fifo_full),\r
-.fifo_empty(rx_fifo_empty)\r
-); \r
-\r
- Broadcast_filter U_Broadcast_filter\r
- (.Reset (Reset ),\r
- .Clk (Clk ),\r
- //MAC_rx_ctrl (//MAC_rx_ctrl ),\r
- .broadcast_ptr (broadcast_ptr ),\r
- .broadcast_drop (broadcast_drop ),\r
- //FromCPU (//FromCPU ),\r
- .broadcast_filter_en (broadcast_filter_en ),\r
- .broadcast_bucket_depth (broadcast_bucket_depth ), \r
- .broadcast_bucket_interval (broadcast_bucket_interval )\r
- ); \r
- \r
-CRC_chk U_CRC_chk(\r
-.Reset (Reset ),\r
-.Clk (Clk ),\r
-.CRC_data (CRC_data ),\r
-.CRC_init (CRC_init ),\r
-.CRC_en (CRC_en ),\r
- //From CPU (//From CPU ),\r
-.CRC_chk_en (CRC_chk_en ),\r
-.CRC_err (CRC_err )\r
-); \r
- \r
- MAC_rx_add_chk U_MAC_rx_add_chk\r
- (.Reset (Reset ),\r
- .Clk (Clk ),\r
- .Init (CRC_init ),\r
- .data (MAC_add_data ),\r
- .MAC_add_en (MAC_add_en ),\r
- .MAC_rx_add_chk_err (MAC_rx_add_chk_err ),\r
- //From CPU (//From CPU ),\r
- .MAC_rx_add_chk_en (MAC_rx_add_chk_en ),\r
- .MAC_add_prom_data (MAC_add_prom_data ),\r
- .MAC_add_prom_add (MAC_add_prom_add ),\r
- .MAC_add_prom_wr (MAC_add_prom_wr )\r
- );\r
- \r
-endmodule // MAC_rx\r
+++ /dev/null
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// Broadcast_filter.v ////\r
-//// ////\r
-//// This file is part of the Ethernet IP core project ////\r
-//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////\r
-//// ////\r
-//// Author(s): ////\r
-//// - Jon Gao (gaojon@yahoo.com) ////\r
-//// ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// Copyright (C) 2001 Authors ////\r
-//// ////\r
-//// This source file may be used and distributed without ////\r
-//// restriction provided that this copyright statement is not ////\r
-//// removed from the file and that any derivative work contains ////\r
-//// the original copyright notice and the associated disclaimer. ////\r
-//// ////\r
-//// This source file is free software; you can redistribute it ////\r
-//// and/or modify it under the terms of the GNU Lesser General ////\r
-//// Public License as published by the Free Software Foundation; ////\r
-//// either version 2.1 of the License, or (at your option) any ////\r
-//// later version. ////\r
-//// ////\r
-//// This source is distributed in the hope that it will be ////\r
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\r
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\r
-//// PURPOSE. See the GNU Lesser General Public License for more ////\r
-//// details. ////\r
-//// ////\r
-//// You should have received a copy of the GNU Lesser General ////\r
-//// Public License along with this source; if not, download it ////\r
-//// from http://www.opencores.org/lgpl.shtml ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-// \r
-// CVS Revision History \r
-// \r
-// $Log: Broadcast_filter.v,v $\r
-// Revision 1.3 2006/01/19 14:07:54 maverickist\r
-// verification is complete.\r
-//\r
-// Revision 1.2 2005/12/16 06:44:16 Administrator\r
-// replaced tab with space.\r
-// passed 9.6k length frame test.\r
-//\r
-// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator\r
-// no message\r
-// \r
-\r
-module Broadcast_filter ( \r
-Reset ,\r
-Clk ,\r
-//MAC_rx_ctrl ,\r
-broadcast_ptr ,\r
-broadcast_drop ,\r
-//FromCPU ,\r
-broadcast_filter_en ,\r
-broadcast_bucket_depth ,\r
-broadcast_bucket_interval \r
-);\r
-input Reset ;\r
-input Clk ;\r
- //MAC_rx_ctrl \r
-input broadcast_ptr ;\r
-output broadcast_drop ;\r
- //FromCPU ;\r
-input broadcast_filter_en ;\r
-input [15:0] broadcast_bucket_depth ;\r
-input [15:0] broadcast_bucket_interval ;\r
-\r
-//****************************************************************************** \r
-//internal signals \r
-//****************************************************************************** \r
-reg [15:0] time_counter ;\r
-reg [15:0] broadcast_counter ;\r
-reg broadcast_drop ;\r
-//****************************************************************************** \r
-// \r
-//****************************************************************************** \r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- time_counter <=0;\r
- else if (time_counter==broadcast_bucket_interval)\r
- time_counter <=0;\r
- else\r
- time_counter <=time_counter+1;\r
-\r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- broadcast_counter <=0;\r
- else if (time_counter==broadcast_bucket_interval)\r
- broadcast_counter <=0;\r
- else if (broadcast_ptr&&broadcast_counter!=broadcast_bucket_depth)\r
- broadcast_counter <=broadcast_counter+1;\r
- \r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- broadcast_drop <=0;\r
- else if(broadcast_filter_en&&broadcast_counter==broadcast_bucket_depth)\r
- broadcast_drop <=1;\r
- else\r
- broadcast_drop <=0;\r
-\r
-endmodule
\ No newline at end of file
+++ /dev/null
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// CRC_chk.v ////\r
-//// ////\r
-//// This file is part of the Ethernet IP core project ////\r
-//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////\r
-//// ////\r
-//// Author(s): ////\r
-//// - Jon Gao (gaojon@yahoo.com) ////\r
-//// ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// Copyright (C) 2001 Authors ////\r
-//// ////\r
-//// This source file may be used and distributed without ////\r
-//// restriction provided that this copyright statement is not ////\r
-//// removed from the file and that any derivative work contains ////\r
-//// the original copyright notice and the associated disclaimer. ////\r
-//// ////\r
-//// This source file is free software; you can redistribute it ////\r
-//// and/or modify it under the terms of the GNU Lesser General ////\r
-//// Public License as published by the Free Software Foundation; ////\r
-//// either version 2.1 of the License, or (at your option) any ////\r
-//// later version. ////\r
-//// ////\r
-//// This source is distributed in the hope that it will be ////\r
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\r
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\r
-//// PURPOSE. See the GNU Lesser General Public License for more ////\r
-//// details. ////\r
-//// ////\r
-//// You should have received a copy of the GNU Lesser General ////\r
-//// Public License along with this source; if not, download it ////\r
-//// from http://www.opencores.org/lgpl.shtml ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-// \r
-// CVS Revision History \r
-// \r
-// $Log: CRC_chk.v,v $\r
-// Revision 1.3 2006/01/19 14:07:54 maverickist\r
-// verification is complete.\r
-//\r
-// Revision 1.2 2005/12/16 06:44:16 Administrator\r
-// replaced tab with space.\r
-// passed 9.6k length frame test.\r
-//\r
-// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator\r
-// no message\r
-// \r
-\r
-module CRC_chk(\r
-Reset ,\r
-Clk ,\r
-CRC_data ,\r
-CRC_init ,\r
-CRC_en ,\r
-//From CPU \r
-CRC_chk_en ,\r
-CRC_err \r
-);\r
-input Reset ;\r
-input Clk ;\r
-input[7:0] CRC_data ;\r
-input CRC_init ;\r
-input CRC_en ;\r
- //From CPU\r
-input CRC_chk_en ;\r
-output CRC_err ; \r
-//****************************************************************************** \r
-//internal signals \r
-//******************************************************************************\r
-reg [31:0] CRC_reg;\r
-//******************************************************************************\r
-//input data width is 8bit, and the first bit is bit[0]\r
-function[31:0] NextCRC;\r
- input[7:0] D;\r
- input[31:0] C;\r
- reg[31:0] NewCRC;\r
- begin\r
- NewCRC[0]=C[24]^C[30]^D[1]^D[7];\r
- NewCRC[1]=C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];\r
- NewCRC[2]=C[26]^D[5]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];\r
- NewCRC[3]=C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];\r
- NewCRC[4]=C[28]^D[3]^C[27]^D[4]^C[26]^D[5]^C[24]^C[30]^D[1]^D[7];\r
- NewCRC[5]=C[29]^D[2]^C[28]^D[3]^C[27]^D[4]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];\r
- NewCRC[6]=C[30]^D[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];\r
- NewCRC[7]=C[31]^D[0]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];\r
- NewCRC[8]=C[0]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];\r
- NewCRC[9]=C[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6];\r
- NewCRC[10]=C[2]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];\r
- NewCRC[11]=C[3]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];\r
- NewCRC[12]=C[4]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];\r
- NewCRC[13]=C[5]^C[30]^D[1]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];\r
- NewCRC[14]=C[6]^C[31]^D[0]^C[30]^D[1]^C[28]^D[3]^C[27]^D[4]^C[26]^D[5];\r
- NewCRC[15]=C[7]^C[31]^D[0]^C[29]^D[2]^C[28]^D[3]^C[27]^D[4];\r
- NewCRC[16]=C[8]^C[29]^D[2]^C[28]^D[3]^C[24]^D[7];\r
- NewCRC[17]=C[9]^C[30]^D[1]^C[29]^D[2]^C[25]^D[6];\r
- NewCRC[18]=C[10]^C[31]^D[0]^C[30]^D[1]^C[26]^D[5];\r
- NewCRC[19]=C[11]^C[31]^D[0]^C[27]^D[4];\r
- NewCRC[20]=C[12]^C[28]^D[3];\r
- NewCRC[21]=C[13]^C[29]^D[2];\r
- NewCRC[22]=C[14]^C[24]^D[7];\r
- NewCRC[23]=C[15]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];\r
- NewCRC[24]=C[16]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];\r
- NewCRC[25]=C[17]^C[27]^D[4]^C[26]^D[5];\r
- NewCRC[26]=C[18]^C[28]^D[3]^C[27]^D[4]^C[24]^C[30]^D[1]^D[7];\r
- NewCRC[27]=C[19]^C[29]^D[2]^C[28]^D[3]^C[25]^C[31]^D[0]^D[6];\r
- NewCRC[28]=C[20]^C[30]^D[1]^C[29]^D[2]^C[26]^D[5];\r
- NewCRC[29]=C[21]^C[31]^D[0]^C[30]^D[1]^C[27]^D[4];\r
- NewCRC[30]=C[22]^C[31]^D[0]^C[28]^D[3];\r
- NewCRC[31]=C[23]^C[29]^D[2];\r
- NextCRC=NewCRC;\r
- end\r
- endfunction\r
-\r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- CRC_reg <=32'hffffffff;\r
- else if (CRC_init)\r
- CRC_reg <=32'hffffffff;\r
- else if (CRC_en)\r
- CRC_reg <=NextCRC(CRC_data,CRC_reg);\r
-\r
-assign CRC_err = CRC_chk_en&(CRC_reg[31:0] != 32'hc704dd7b);\r
-\r
-endmodule\r
+++ /dev/null
-\r
-// ////////////////////////////////////////////////////////////////////\r
-// Completely Rewritten by M. Ettus, no John Gao code left\r
-// ////////////////////////////////////////////////////////////////////\r
-\r
-module MAC_rx_FF \r
- #(parameter RX_FF_DEPTH = 9)\r
- (input Reset,\r
- input Clk_MAC,\r
- input Clk_SYS,\r
- \r
- // MAC_rx_ctrl interface \r
- input [7:0] Fifo_data,\r
- input Fifo_data_en,\r
- output Fifo_full,\r
- input Fifo_data_err,\r
- input Fifo_data_end,\r
- output [15:0] Fifo_space,\r
-\r
- // CPU\r
- input RX_APPEND_CRC,\r
- input [4:0] Rx_Hwmark,\r
- input [4:0] Rx_Lwmark,\r
- \r
- // User interface \r
- output Rx_mac_empty,\r
- input Rx_mac_rd,\r
- output [31:0] Rx_mac_data,\r
- output [1:0] Rx_mac_BE,\r
- output Rx_mac_sop,\r
- output Rx_mac_eop,\r
- output Rx_mac_err,\r
-\r
- // FIFO Levels\r
- output [15:0] fifo_occupied,\r
- output fifo_full_dbg,\r
- output fifo_empty\r
- );\r
-\r
- reg [1:0] FF_state; \r
- reg [2:0] PKT_state;\r
- reg [31:0] staging;\r
- reg [35:0] staging2;\r
- reg line_ready, line_ready_d1;\r
- wire sop_i, eop_i;\r
- reg [1:0] be;\r
- \r
- always @(posedge Clk_MAC or posedge Reset)\r
- if(Reset)\r
- FF_state <= 0;\r
- else\r
- if(Fifo_data_err | Fifo_data_end)\r
- FF_state <= 0;\r
- else if(Fifo_data_en)\r
- FF_state <= FF_state + 1;\r
- \r
- always @(posedge Clk_MAC or posedge Reset)\r
- if(Reset)\r
- staging[31:0] <= 0;\r
- else if(Fifo_data_en)\r
- case(FF_state)\r
- 0 : staging[31:24] <= Fifo_data;\r
- 1 : staging[23:16] <= Fifo_data;\r
- 2 : staging[15:8] <= Fifo_data;\r
- 3 : staging[7:0] <= Fifo_data;\r
- endcase // case(FF_state)\r
-\r
- localparam PKT_idle = 0;\r
- localparam PKT_sop = 1;\r
- localparam PKT_pkt = 2;\r
- localparam PKT_end = 3;\r
- localparam PKT_err = 4;\r
-\r
- always @(posedge Clk_MAC or posedge Reset)\r
- if(Reset)\r
- PKT_state <= 0;\r
- else\r
- case(PKT_state)\r
- PKT_idle :\r
- if(Fifo_data_en)\r
- PKT_state <= PKT_sop;\r
- PKT_sop, PKT_pkt :\r
- if(Fifo_data_err | (line_ready & Fifo_full))\r
- PKT_state <= PKT_err;\r
- else if(Fifo_data_end)\r
- PKT_state <= PKT_end;\r
- else if(line_ready & ~Fifo_full)\r
- PKT_state <= PKT_pkt;\r
- PKT_end :\r
- PKT_state <= PKT_idle;\r
- PKT_err :\r
- if(~Fifo_full)\r
- PKT_state <= PKT_idle;\r
- endcase // case(PKT_state)\r
-\r
- assign sop_i = (PKT_state == PKT_sop);\r
- assign eop_i = (PKT_state == PKT_end);\r
- \r
- always @(posedge Clk_MAC)\r
- if(line_ready)\r
- staging2 <= {sop_i, eop_i, be[1:0], staging};\r
- \r
- always @(posedge Clk_MAC)\r
- if(Reset)\r
- line_ready <= 0;\r
- else if((Fifo_data_en & (FF_state==2'd3)) | Fifo_data_end | Fifo_data_err)\r
- line_ready <= 1;\r
- else\r
- line_ready <= 0;\r
-\r
- always @(posedge Clk_MAC)\r
- line_ready_d1 <= line_ready;\r
- \r
- always @(posedge Clk_MAC)\r
- if(Fifo_data_end | Fifo_data_err)\r
- be <= FF_state;\r
- else\r
- be <= 0;\r
- \r
- wire sop_o, eop_o, empty;\r
- wire [1:0] be_o;\r
- wire [RX_FF_DEPTH-1:0] occupied, occupied_sysclk;\r
- wire [31:0] dataout;\r
-\r
-/*\r
- fifo_2clock #(.DWIDTH(36),.AWIDTH(RX_FF_DEPTH)) mac_rx_fifo\r
- (.wclk(Clk_MAC),.datain((PKT_state==PKT_err) ? 36'hF_FFFF_FFFF : staging2),.write(~Fifo_full & (line_ready_d1|(PKT_state==PKT_err))),\r
- .full(Fifo_full),.level_wclk(occupied),\r
- .rclk(Clk_SYS),.dataout({sop_o,eop_o,be_o[1:0],dataout}),.read(Rx_mac_rd),\r
- .empty(empty),.level_rclk(),\r
- .arst(Reset) );\r
- */\r
-\r
- fifo_xlnx_2Kx36_2clk mac_rx_ff_core\r
- (\r
- .din((PKT_state==PKT_err) ? 36'hF_FFFF_FFFF : staging2), // Bus [35 : 0] \r
- .rd_clk(Clk_SYS),\r
- .rd_en(Rx_mac_rd),\r
- .rst(Reset),\r
- .wr_clk(Clk_MAC),\r
- .wr_en(~Fifo_full & (line_ready_d1|(PKT_state==PKT_err))),\r
- .dout({sop_o,eop_o,be_o[1:0],dataout}), // Bus [35 : 0] \r
- .empty(empty),\r
- .full(Fifo_full),\r
- .rd_data_count(occupied_sysclk), // Bus [11 : 0] \r
- .wr_data_count(occupied)); // Bus [11 : 0] \r
- \r
- assign Fifo_space[15:RX_FF_DEPTH] = 0;\r
- assign Fifo_space[RX_FF_DEPTH-1:0] = ~occupied;\r
- assign fifo_occupied = occupied_sysclk;\r
- assign fifo_full_dbg = Fifo_full; // FIXME -- in wrong clock domain\r
- assign fifo_empty = empty;\r
- \r
- // mac side fifo interface\r
- // Input - Rx_mac_rd\r
- // Output - Rx_mac_empty, Rx_mac_sop, Rx_mac_eop, Rx_mac_err, Rx_mac_data, Rx_mac_BE\r
-\r
- assign Rx_mac_BE = be_o;\r
- assign Rx_mac_sop = sop_o & ~eop_o;\r
- assign Rx_mac_eop = eop_o;\r
- assign Rx_mac_err = sop_o & eop_o;\r
- assign Rx_mac_empty = empty;\r
- assign Rx_mac_data = dataout;\r
- \r
-endmodule // MAC_rx_FF\r
-\r
-// FIXME Should we send out an "almost full" signal instead of full?\r
+++ /dev/null
-// ////////////////////////////////////////////////////////////////////\r
-// // ////\r
-// // MAC_rx_add_chk.v ////\r
-// // ////\r
-// // This file is part of the Ethernet IP core project ////\r
-// // http://www.opencores.org/projects.cgi/wr_en/ethernet_tri_mode/////\r
-// // ////\r
-// // Author(s): ////\r
-// // - Jon Gao (gaojon@yahoo.com) ////\r
-// // ////\r
-// // ////\r
-// ////////////////////////////////////////////////////////////////////\r
-// // ////\r
-// // Copyright (C) 2001 Authors ////\r
-// // ////\r
-// // This source file may be used and distributed without ////\r
-// // restriction provided that this copyright statement is not ////\r
-// // removed from the file and that any derivative work contains ////\r
-// // the original copyright notice and the associated disclaimer. ////\r
-// // ////\r
-// // This source file is free software; you can redistribute it ////\r
-// // and/or modify it under the terms of the GNU Lesser General ////\r
-// // Public License as published by the Free Software Foundation; ////\r
-// // either version 2.1 of the License, or (at your option) any ////\r
-// // later version. ////\r
-// // ////\r
-// // This source is distributed in the hope that it will be ////\r
-// // useful, but WITHOUT ANY WARRANTY; without even the implied ////\r
-// // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\r
-// // PURPOSE. See the GNU Lesser General Public License for more ////\r
-// // details. ////\r
-// // ////\r
-// // You should have received a copy of the GNU Lesser General ////\r
-// // Public License along with this source; if not, download it ////\r
-// // from http://www.opencores.org/lgpl.shtml ////\r
-// // ////\r
-// ////////////////////////////////////////////////////////////////////\r
-// \r
-// CVS Revision History \r
-// \r
-// $Log: MAC_rx_add_chk.v,v $\r
-// Revision 1.3 2006/01/19 14:07:54 maverickist\r
-// verification is complete.\r
-//\r
-// Revision 1.2 2005/12/16 06:44:17 Administrator\r
-// replaced tab with space.\r
-// passed 9.6k length frame test.\r
-//\r
-// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator\r
-// no message\r
-// \r
-\r
-module MAC_rx_add_chk \r
- (Reset , \r
- Clk , \r
- Init , \r
- data , \r
- MAC_add_en , \r
- MAC_rx_add_chk_err , \r
- //From CPU \r
- MAC_rx_add_chk_en , \r
- MAC_add_prom_data , \r
- MAC_add_prom_add , \r
- MAC_add_prom_wr \r
- );\r
-\r
- input Reset ;\r
- input Clk ;\r
- input Init ;\r
- input [7:0] data ;\r
- input MAC_add_en ;\r
- output MAC_rx_add_chk_err ;\r
- //From CPU\r
- input MAC_rx_add_chk_en ; \r
- input [7:0] MAC_add_prom_data ; \r
- input [2:0] MAC_add_prom_add ; \r
- input MAC_add_prom_wr ; \r
- \r
- // ****************************************************************************** \r
- // internal signals \r
- // ******************************************************************************\r
- reg [2:0] addr_rd;\r
- wire [2:0] addr_wr;\r
- wire [7:0] din;\r
- //wire [7:0] dout;\r
- reg [7:0] dout;\r
- wire wr_en;\r
- \r
- reg MAC_rx_add_chk_err;\r
- reg MAC_add_prom_wr_dl1;\r
- reg MAC_add_prom_wr_dl2;\r
- reg [7:0] data_dl1 ;\r
- reg MAC_add_en_dl1 ;\r
-\r
- // ****************************************************************************** \r
- // write data from cpu to prom \r
- // ******************************************************************************\r
- always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- begin\r
- data_dl1 <=0;\r
- MAC_add_en_dl1 <=0;\r
- end\r
- else\r
- begin\r
- data_dl1 <=data;\r
- MAC_add_en_dl1 <=MAC_add_en;\r
- end \r
- \r
- always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- begin\r
- MAC_add_prom_wr_dl1 <=0;\r
- MAC_add_prom_wr_dl2 <=0;\r
- end\r
- else\r
- begin\r
- MAC_add_prom_wr_dl1 <=MAC_add_prom_wr;\r
- MAC_add_prom_wr_dl2 <=MAC_add_prom_wr_dl1;\r
- end \r
- \r
- assign wr_en =MAC_add_prom_wr_dl1&!MAC_add_prom_wr_dl2;\r
- assign addr_wr =MAC_add_prom_add;\r
- assign din =MAC_add_prom_data;\r
- \r
- // ****************************************************************************** \r
- // mac add verify \r
- // ******************************************************************************\r
- always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- addr_rd <=0;\r
- else if (Init)\r
- addr_rd <=0;\r
- else if (MAC_add_en)\r
- addr_rd <=addr_rd + 1;\r
- \r
- always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- MAC_rx_add_chk_err <=0;\r
- else if (Init)\r
- MAC_rx_add_chk_err <=0;\r
- else if (MAC_rx_add_chk_en && MAC_add_en_dl1 && (dout!=data_dl1) )\r
- MAC_rx_add_chk_err <=1;\r
- \r
- \r
- // ****************************************************************************** \r
- // a port for read ,b port for write .\r
- // ****************************************************************************** \r
-\r
- reg [7:0] address_ram [0:7];\r
- always @(posedge Clk)\r
- if(wr_en)\r
- address_ram[addr_wr] <= din;\r
- \r
- always @(posedge Clk)\r
- dout <= address_ram[addr_rd];\r
-\r
-endmodule // MAC_rx_add_chk\r
+++ /dev/null
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// MAC_rx_ctrl.v ////\r
-//// ////\r
-//// This file is part of the Ethernet IP core project ////\r
-//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////\r
-//// ////\r
-//// Author(s): ////\r
-//// - Jon Gao (gaojon@yahoo.com) ////\r
-//// ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// Copyright (C) 2001 Authors ////\r
-//// ////\r
-//// This source file may be used and distributed without ////\r
-//// restriction provided that this copyright statement is not ////\r
-//// removed from the file and that any derivative work contains ////\r
-//// the original copyright notice and the associated disclaimer. ////\r
-//// ////\r
-//// This source file is free software; you can redistribute it ////\r
-//// and/or modify it under the terms of the GNU Lesser General ////\r
-//// Public License as published by the Free Software Foundation; ////\r
-//// either version 2.1 of the License, or (at your option) any ////\r
-//// later version. ////\r
-//// ////\r
-//// This source is distributed in the hope that it will be ////\r
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\r
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\r
-//// PURPOSE. See the GNU Lesser General Public License for more ////\r
-//// details. ////\r
-//// ////\r
-//// You should have received a copy of the GNU Lesser General ////\r
-//// Public License along with this source; if not, download it ////\r
-//// from http://www.opencores.org/lgpl.shtml ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-// \r
-// CVS Revision History \r
-// \r
-// $Log: MAC_rx_ctrl.v,v $\r
-// Revision 1.4 2006/06/25 04:58:56 maverickist\r
-// no message\r
-//\r
-// Revision 1.3 2006/01/19 14:07:54 maverickist\r
-// verification is complete.\r
-//\r
-// Revision 1.3 2005/12/16 06:44:17 Administrator\r
-// replaced tab with space.\r
-// passed 9.6k length frame test.\r
-//\r
-// Revision 1.2 2005/12/13 12:15:37 Administrator\r
-// no message\r
-//\r
-// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator\r
-// no message\r
-// \r
-\r
-module MAC_rx_ctrl (\r
-Reset , \r
-Clk , \r
-//RMII interface \r
-MCrs_dv , //\r
-MRxD , // \r
-MRxErr , // \r
-//CRC_chk interface \r
-CRC_en , \r
-CRC_data,\r
-CRC_init ,\r
-CRC_err , \r
-//MAC_rx_add_chk interface \r
-MAC_add_en , \r
-MAC_add_data,\r
-MAC_rx_add_chk_err , \r
-//broadcast_filter \r
-broadcast_ptr , \r
-broadcast_drop , \r
-//flow_control signals \r
-pause_quanta , \r
-pause_quanta_val , \r
-//MAC_rx_FF interface \r
-Fifo_data , \r
-Fifo_data_en , \r
-Fifo_data_err , \r
-Fifo_data_drop ,\r
-Fifo_data_end , \r
-Fifo_full , \r
-//RMON interface \r
-Rx_pkt_type_rmon , \r
-Rx_pkt_length_rmon , \r
-Rx_apply_rmon , \r
-Rx_pkt_err_type_rmon , \r
-//CPU \r
-RX_IFG_SET ,\r
-RX_MAX_LENGTH,\r
-RX_MIN_LENGTH\r
-);\r
-\r
-input Reset ; \r
-input Clk ; \r
- //RMII interface \r
-input MCrs_dv ; \r
-input [7:0] MRxD ; \r
-input MRxErr ; \r
- //CRC_chk interface\r
-output CRC_en ; \r
-output CRC_init; \r
-output [7:0] CRC_data;\r
-input CRC_err ;\r
- //MAC_rx_add_chk interface\r
-output MAC_add_en ;\r
-output [7:0] MAC_add_data;\r
-input MAC_rx_add_chk_err ;\r
- //broadcast_filter\r
-output broadcast_ptr ;\r
-input broadcast_drop ;\r
- //flow_control signals \r
-output [15:0] pause_quanta ; \r
-output pause_quanta_val ; \r
- //MAC_rx_FF interface\r
-output [7:0] Fifo_data ;\r
-output Fifo_data_en ;\r
-output Fifo_data_err ;\r
-output Fifo_data_drop ;\r
-output Fifo_data_end ;\r
-input Fifo_full;\r
- //RMON interface\r
-output [15:0] Rx_pkt_length_rmon ;\r
-output Rx_apply_rmon ;\r
-output [2:0] Rx_pkt_err_type_rmon ;\r
-output [2:0] Rx_pkt_type_rmon ;\r
- //CPU\r
-input [5:0] RX_IFG_SET ;\r
-input [15:0] RX_MAX_LENGTH ;// 1518\r
-input [6:0] RX_MIN_LENGTH ;// 64\r
-\r
-//******************************************************************************\r
-//internal signals\r
-//******************************************************************************\r
-parameter State_idle =4'd00;\r
-parameter State_preamble =4'd01;\r
-parameter State_SFD =4'd02;\r
-parameter State_data =4'd03;\r
-parameter State_checkCRC =4'd04;\r
-parameter State_OkEnd =4'd07;\r
-parameter State_DropEnd =4'd08;\r
-parameter State_ErrEnd =4'd09;\r
-parameter State_CRCErrEnd =4'd10;\r
-parameter State_FFFullDrop =4'd11;\r
-parameter State_FFFullErrEnd =4'd12;\r
-parameter State_IFG =4'd13;\r
-parameter State_Drop2End =4'd14;\r
-\r
-parameter Pause_idle =4'd0; \r
-parameter Pause_pre_syn =4'd1; \r
-parameter Pause_quanta_hi =4'd2; \r
-parameter Pause_quanta_lo =4'd3; \r
-parameter Pause_syn =4'd4; \r
- \r
-reg [3:0] Current_state /* synthesis syn_keep=1 */; \r
-reg [3:0] Next_state; \r
-reg [3:0] Pause_current /* synthesis syn_keep=1 */; \r
-reg [3:0] Pause_next; \r
-reg [5:0] IFG_counter; \r
-reg Crs_dv ; \r
-reg [7:0] RxD ;\r
-reg [7:0] RxD_dl1 ;\r
-reg RxErr ;\r
-reg [15:0] Frame_length_counter;\r
-reg Too_long;\r
-reg Too_short;\r
-reg ProcessingHeader;\r
-//reg Fifo_data_en;\r
-//reg Fifo_data_err;\r
-//reg Fifo_data_drop;\r
-//reg Fifo_data_end;\r
-reg CRC_en;\r
-reg CRC_init;\r
-reg Rx_apply_rmon;\r
-reg [2:0] Rx_pkt_err_type_rmon;\r
-reg MAC_add_en;\r
-reg [2:0] Rx_pkt_type_rmon;\r
-reg [7:0] pause_quanta_h ;\r
-reg [15:0] pause_quanta ;\r
-reg pause_quanta_val ;\r
-reg pause_quanta_val_tmp;\r
-reg pause_frame_ptr ;\r
-reg broadcast_ptr ;\r
-//******************************************************************************\r
-//delay signals \r
-//******************************************************************************\r
- \r
-always @ (posedge Reset or posedge Clk) \r
- if (Reset) \r
- begin \r
- Crs_dv <=0;\r
- RxD <=0; \r
- RxErr <=0; \r
- end\r
- else\r
- begin \r
- Crs_dv <=MCrs_dv ;\r
- RxD <=MRxD ; \r
- RxErr <=MRxErr ; \r
- end\r
-\r
-always @ (posedge Reset or posedge Clk) \r
- if (Reset) \r
- RxD_dl1 <=0;\r
- else \r
- RxD_dl1 <=RxD;\r
- \r
-//---------------------------------------------------------------------------\r
-// Small pre-FIFO (acutally a synchronously clearable shift-register) for\r
-// storing the first part of a packet before writing it to the "real" FIFO\r
-// in MAC_rx_FF. This allows a packet to be dropped safely if an error\r
-// happens in the beginning of a packet (or if the MAC address doesn't pass\r
-// the receive filter!)\r
-//---------------------------------------------------------------------------\r
-\r
- reg pre_fifo_data_drop;\r
- reg pre_fifo_data_en;\r
- reg pre_fifo_data_err;\r
- reg pre_fifo_data_end;\r
- wire [7:0] pre_fifo_wrdata;\r
-\r
- reg [8+3-1:0] pre_fifo_element_0;\r
- reg [8+3-1:0] pre_fifo_element_1;\r
- reg [8+3-1:0] pre_fifo_element_2;\r
- reg [8+3-1:0] pre_fifo_element_3;\r
- reg [8+3-1:0] pre_fifo_element_4;\r
- reg [8+3-1:0] pre_fifo_element_5;\r
- reg [8+3-1:0] pre_fifo_element_6;\r
- reg [8+3-1:0] pre_fifo_element_7;\r
- reg [8+3-1:0] pre_fifo_element_8;\r
- reg [8+3-1:0] pre_fifo_element_9;\r
-\r
- always @( posedge Reset or posedge Clk )\r
- if ( Reset )\r
- begin\r
- pre_fifo_element_0 <= 'b0;\r
- pre_fifo_element_1 <= 'b0;\r
- pre_fifo_element_2 <= 'b0;\r
- pre_fifo_element_3 <= 'b0;\r
- pre_fifo_element_4 <= 'b0;\r
- pre_fifo_element_5 <= 'b0;\r
- pre_fifo_element_6 <= 'b0;\r
- pre_fifo_element_7 <= 'b0;\r
- pre_fifo_element_8 <= 'b0;\r
- pre_fifo_element_9 <= 'b0;\r
- end\r
- else\r
- begin\r
- if ( pre_fifo_data_drop )\r
- begin\r
- pre_fifo_element_0 <= 'b0;\r
- pre_fifo_element_1 <= 'b0;\r
- pre_fifo_element_2 <= 'b0;\r
- pre_fifo_element_3 <= 'b0;\r
- pre_fifo_element_4 <= 'b0;\r
- pre_fifo_element_5 <= 'b0;\r
- pre_fifo_element_6 <= 'b0;\r
- pre_fifo_element_7 <= 'b0;\r
- pre_fifo_element_8 <= 'b0;\r
- pre_fifo_element_9 <= 'b0;\r
- end\r
- else\r
- begin\r
- pre_fifo_element_0 <= pre_fifo_element_1;\r
- pre_fifo_element_1 <= pre_fifo_element_2;\r
- pre_fifo_element_2 <= pre_fifo_element_3;\r
- pre_fifo_element_3 <= pre_fifo_element_4;\r
- pre_fifo_element_4 <= pre_fifo_element_5;\r
- pre_fifo_element_5 <= pre_fifo_element_6;\r
- pre_fifo_element_6 <= pre_fifo_element_7;\r
- pre_fifo_element_7 <= pre_fifo_element_8;\r
- pre_fifo_element_8 <= pre_fifo_element_9;\r
- pre_fifo_element_9 <= { pre_fifo_data_en,\r
- pre_fifo_data_err,\r
- pre_fifo_data_end,\r
- pre_fifo_wrdata };\r
- end\r
- end\r
-\r
- assign Fifo_data = pre_fifo_element_0[7:0];\r
- assign Fifo_data_end = pre_fifo_element_0[8];\r
- assign Fifo_data_err = pre_fifo_element_0[9];\r
- assign Fifo_data_en = pre_fifo_element_0[10];\r
-\r
- assign CRC_data = pre_fifo_wrdata;\r
- assign MAC_add_data = pre_fifo_wrdata;\r
-\r
-//******************************************************************************\r
-//State_machine \r
-//******************************************************************************\r
- \r
-always @( posedge Reset or posedge Clk )\r
- if ( Reset )\r
- Current_state <= State_idle;\r
- else\r
- Current_state <= Next_state;\r
-\r
-always @ (*)\r
- case (Current_state)\r
- State_idle:\r
- if ( Crs_dv&&RxD==8'h55 )\r
- Next_state = State_preamble;\r
- else\r
- Next_state = Current_state;\r
-\r
- State_preamble:\r
- if ( !Crs_dv )\r
- Next_state = State_DropEnd;\r
- else if ( RxErr )\r
- Next_state = State_DropEnd;\r
- else if ( RxD==8'hd5 )\r
- Next_state = State_SFD;\r
- else if ( RxD==8'h55 )\r
- Next_state =Current_state;\r
- else\r
- Next_state = State_DropEnd;\r
-\r
- State_SFD:\r
- if ( !Crs_dv )\r
- Next_state = State_DropEnd;\r
- else if ( RxErr )\r
- Next_state = State_DropEnd;\r
- else\r
- Next_state = State_data;\r
-\r
- State_data:\r
- if ( !Crs_dv && !ProcessingHeader && !Too_short && !Too_long )\r
- Next_state = State_checkCRC;\r
- else if ( !Crs_dv && ProcessingHeader )\r
- Next_state = State_Drop2End;\r
- else if ( !Crs_dv && (Too_short | Too_long) )\r
- Next_state = State_ErrEnd;\r
- else if ( Fifo_full )\r
- Next_state = State_FFFullErrEnd;\r
- else if ( RxErr && ProcessingHeader )\r
- Next_state = State_Drop2End;\r
- else if ( RxErr || Too_long )\r
- Next_state = State_ErrEnd;\r
- else if ( MAC_rx_add_chk_err || broadcast_drop )\r
- Next_state = State_DropEnd;\r
- else\r
- Next_state = State_data;\r
-\r
- State_checkCRC:\r
- if ( CRC_err )\r
- Next_state = State_CRCErrEnd;\r
- else\r
- Next_state = State_OkEnd;\r
-\r
- State_OkEnd:\r
- Next_state = State_IFG;\r
-\r
- State_ErrEnd:\r
- Next_state = State_IFG;\r
-\r
- State_DropEnd:\r
- Next_state = State_IFG;\r
-\r
- State_Drop2End:\r
- Next_state = State_IFG;\r
-\r
- State_CRCErrEnd:\r
- Next_state = State_IFG;\r
-\r
- State_FFFullErrEnd:\r
- Next_state = State_FFFullDrop;\r
-\r
- State_FFFullDrop:\r
- if ( !Crs_dv )\r
- Next_state =State_IFG; \r
- else \r
- Next_state =Current_state; \r
-\r
- State_IFG:\r
- if ( IFG_counter==RX_IFG_SET-4 ) // Remove some additional time?\r
- Next_state = State_idle;\r
- else\r
- Next_state = Current_state;\r
-\r
- default:\r
- Next_state = State_idle;\r
- endcase\r
-\r
-always @( posedge Reset or posedge Clk )\r
- if ( Reset )\r
- IFG_counter <= 0;\r
- else if ( Current_state!=State_IFG )\r
- IFG_counter <= 0;\r
- else\r
- IFG_counter <= IFG_counter + 1;\r
-\r
-//******************************************************************************\r
-//gen fifo interface signals \r
-//****************************************************************************** \r
-\r
-assign pre_fifo_wrdata = RxD_dl1;\r
-\r
-always @( Current_state )\r
- if ( Current_state==State_data )\r
- pre_fifo_data_en = 1;\r
- else\r
- pre_fifo_data_en = 0;\r
- \r
-always @( Current_state )\r
- if ( (Current_state==State_ErrEnd ) ||\r
- (Current_state==State_OkEnd ) ||\r
- (Current_state==State_CRCErrEnd ) ||\r
- (Current_state==State_FFFullErrEnd) ||\r
- (Current_state==State_DropEnd ) ||\r
- (Current_state==State_Drop2End ) )\r
- pre_fifo_data_end = 1;\r
- else\r
- pre_fifo_data_end = 0;\r
-\r
-always @( Current_state )\r
- if ( (Current_state==State_ErrEnd ) ||\r
- (Current_state==State_CRCErrEnd ) ||\r
- (Current_state==State_FFFullErrEnd) ||\r
- (Current_state==State_DropEnd ) ||\r
- (Current_state==State_Drop2End ) )\r
- pre_fifo_data_err = 1;\r
- else\r
- pre_fifo_data_err = 0;\r
-\r
-always @( Current_state )\r
- if ( (Current_state==State_DropEnd ) ||\r
- (Current_state==State_Drop2End) )\r
- pre_fifo_data_drop = 1;\r
- else\r
- pre_fifo_data_drop = 0;\r
-\r
- // Drop in main Rx FIFO is no longer supported!\r
- assign Fifo_data_drop = 0;\r
-\r
-//******************************************************************************\r
-//CRC_chk interface \r
-//****************************************************************************** \r
-\r
-always @(Current_state)\r
- if (Current_state==State_data)\r
- CRC_en =1;\r
- else\r
- CRC_en =0;\r
- \r
-always @(Current_state)\r
- if (Current_state==State_SFD)\r
- CRC_init =1;\r
- else\r
- CRC_init =0;\r
- \r
-//******************************************************************************\r
-//gen rmon signals \r
-//****************************************************************************** \r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset) \r
- Frame_length_counter <=0;\r
- else if (Current_state==State_SFD)\r
- Frame_length_counter <=1;\r
- else if (Current_state==State_data)\r
- Frame_length_counter <=Frame_length_counter+ 1'b1;\r
- \r
-always @( Frame_length_counter )\r
- if ( Frame_length_counter < 8 )\r
- ProcessingHeader = 1;\r
- else\r
- ProcessingHeader = 0;\r
-\r
-always @ (Frame_length_counter or RX_MIN_LENGTH)\r
- if (Frame_length_counter<RX_MIN_LENGTH)\r
- Too_short =1;\r
- else\r
- Too_short =0;\r
- \r
-always @ (*)\r
- if (Frame_length_counter>RX_MAX_LENGTH)\r
- Too_long =1;\r
- else\r
- Too_long =0;\r
- \r
-assign Rx_pkt_length_rmon = Frame_length_counter-1'b1;\r
-\r
-reg [2:0] Rx_apply_rmon_reg;\r
-\r
-always @( posedge Clk or posedge Reset )\r
- if ( Reset )\r
- begin\r
- Rx_apply_rmon <= 0;\r
- Rx_apply_rmon_reg <= 'b0;\r
- end\r
- else\r
- begin\r
- if ( (Current_state==State_OkEnd ) ||\r
- (Current_state==State_ErrEnd ) ||\r
- (Current_state==State_CRCErrEnd ) ||\r
- (Current_state==State_Drop2End ) ||\r
- (Current_state==State_FFFullErrEnd) )\r
- Rx_apply_rmon <= 1;\r
- else\r
- if ( Rx_apply_rmon_reg[2] )\r
- Rx_apply_rmon <= 0;\r
-\r
- Rx_apply_rmon_reg <= { Rx_apply_rmon_reg[1:0], Rx_apply_rmon };\r
- end\r
- \r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- Rx_pkt_err_type_rmon <=0;\r
- else if (Current_state==State_CRCErrEnd)\r
- Rx_pkt_err_type_rmon <=3'b001 ;//\r
- else if (Current_state==State_FFFullErrEnd)\r
- Rx_pkt_err_type_rmon <=3'b010 ;// \r
- else if ( (Current_state==State_ErrEnd) || (Current_state==State_Drop2End) )\r
- Rx_pkt_err_type_rmon <=3'b011 ;//\r
- else if(Current_state==State_OkEnd)\r
- Rx_pkt_err_type_rmon <=3'b100 ;\r
-\r
-\r
- \r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- Rx_pkt_type_rmon <=0;\r
- else if (Current_state==State_OkEnd&&pause_frame_ptr)\r
- Rx_pkt_type_rmon <=3'b100 ;//\r
- else if(Current_state==State_SFD&&Next_state==State_data)\r
- Rx_pkt_type_rmon <={1'b0,MRxD[7:6]};\r
-\r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- broadcast_ptr <=0;\r
- else if(Current_state==State_IFG)\r
- broadcast_ptr <=0;\r
- else if(Current_state==State_SFD&&Next_state==State_data&&MRxD[7:6]==2'b11)\r
- broadcast_ptr <=1;\r
-\r
- \r
- \r
-//******************************************************************************\r
-//MAC add checker signals \r
-//******************************************************************************\r
-always @ (Frame_length_counter or pre_fifo_data_en)\r
- if(Frame_length_counter>=1&&Frame_length_counter<=6)\r
- MAC_add_en <=pre_fifo_data_en;\r
- else\r
- MAC_add_en <=0;\r
-\r
-//******************************************************************************\r
-//flow control signals \r
-//******************************************************************************\r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- Pause_current <=Pause_idle;\r
- else\r
- Pause_current <=Pause_next;\r
- \r
-always @ (*)\r
- case (Pause_current)\r
- Pause_idle : \r
- if(Current_state==State_SFD)\r
- Pause_next =Pause_pre_syn;\r
- else\r
- Pause_next =Pause_current;\r
- Pause_pre_syn:\r
- case (Frame_length_counter)\r
- 16'd1: if (RxD_dl1==8'h01)\r
- Pause_next =Pause_current;\r
- else\r
- Pause_next =Pause_idle;\r
- 16'd2: if (RxD_dl1==8'h80)\r
- Pause_next =Pause_current;\r
- else\r
- Pause_next =Pause_idle; \r
- 16'd3: if (RxD_dl1==8'hc2)\r
- Pause_next =Pause_current;\r
- else\r
- Pause_next =Pause_idle;\r
- 16'd4: if (RxD_dl1==8'h00)\r
- Pause_next =Pause_current;\r
- else\r
- Pause_next =Pause_idle;\r
- 16'd5: if (RxD_dl1==8'h00)\r
- Pause_next =Pause_current;\r
- else\r
- Pause_next =Pause_idle;\r
- 16'd6: if (RxD_dl1==8'h01)\r
- Pause_next =Pause_current;\r
- else\r
- Pause_next =Pause_idle;\r
- 16'd13: if (RxD_dl1==8'h88)\r
- Pause_next =Pause_current;\r
- else\r
- Pause_next =Pause_idle;\r
- 16'd14: if (RxD_dl1==8'h08)\r
- Pause_next =Pause_current;\r
- else\r
- Pause_next =Pause_idle;\r
- 16'd15: if (RxD_dl1==8'h00)\r
- Pause_next =Pause_current;\r
- else\r
- Pause_next =Pause_idle;\r
- 16'd16: if (RxD_dl1==8'h01)\r
- Pause_next =Pause_quanta_hi;\r
- else\r
- Pause_next =Pause_idle;\r
- default: Pause_next =Pause_current;\r
- endcase\r
- Pause_quanta_hi :\r
- Pause_next =Pause_quanta_lo;\r
- Pause_quanta_lo :\r
- Pause_next =Pause_syn; \r
- Pause_syn :\r
- if (Current_state==State_IFG)\r
- Pause_next =Pause_idle;\r
- else\r
- Pause_next =Pause_current;\r
- default\r
- Pause_next =Pause_idle;\r
- endcase\r
-\r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- pause_quanta_h <=0;\r
- else if(Pause_current==Pause_quanta_hi)\r
- pause_quanta_h <=RxD_dl1;\r
- \r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- pause_quanta <=0;\r
- else if(Pause_current==Pause_quanta_lo)\r
- pause_quanta <={pause_quanta_h,RxD_dl1};\r
-\r
- // The following 2 always blocks are a strange way of holding\r
- // pause_quanta_val high for 2 cycles\r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset) \r
- pause_quanta_val_tmp <=0;\r
- else if(Current_state==State_OkEnd&&Pause_current==Pause_syn)\r
- pause_quanta_val_tmp <=1;\r
- else\r
- pause_quanta_val_tmp <=0;\r
- \r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset) \r
- pause_quanta_val <=0;\r
- else if(Current_state==State_OkEnd&&Pause_current==Pause_syn||pause_quanta_val_tmp)\r
- pause_quanta_val <=1;\r
- else\r
- pause_quanta_val <=0; \r
- \r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset) \r
- pause_frame_ptr <=0;\r
- else if(Pause_current==Pause_syn)\r
- pause_frame_ptr <=1;\r
- else\r
- pause_frame_ptr <=0;\r
- \r
-endmodule\r
- \r
- \r
+++ /dev/null
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// MAC_top.v ////\r
-//// ////\r
-//// This file is part of the Ethernet IP core project ////\r
-//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////\r
-//// ////\r
-//// Author(s): ////\r
-//// - Jon Gao (gaojon@yahoo.com) ////\r
-//// ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// Copyright (C) 2001 Authors ////\r
-//// ////\r
-//// This source file may be used and distributed without ////\r
-//// restriction provided that this copyright statement is not ////\r
-//// removed from the file and that any derivative work contains ////\r
-//// the original copyright notice and the associated disclaimer. ////\r
-//// ////\r
-//// This source file is free software; you can redistribute it ////\r
-//// and/or modify it under the terms of the GNU Lesser General ////\r
-//// Public License as published by the Free Software Foundation; ////\r
-//// either version 2.1 of the License, or (at your option) any ////\r
-//// later version. ////\r
-//// ////\r
-//// This source is distributed in the hope that it will be ////\r
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\r
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\r
-//// PURPOSE. See the GNU Lesser General Public License for more ////\r
-//// details. ////\r
-//// ////\r
-//// You should have received a copy of the GNU Lesser General ////\r
-//// Public License along with this source; if not, download it ////\r
-//// from http://www.opencores.org/lgpl.shtml ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-\r
-module MAC_top\r
- #(parameter TX_FF_DEPTH = 9, \r
- parameter RX_FF_DEPTH = 9)\r
- (\r
- // System signals\r
- input Clk_125M,\r
- input Clk_user,\r
-\r
- input rst_mac,\r
- input rst_user,\r
- \r
- // Wishbone compliant core host interface\r
- input RST_I, // Active high (async) reset of the Wishbone interface\r
- input CLK_I, // Wishbone interface clock (nominally 50 MHz)\r
- input STB_I, // Active high module-select\r
- input CYC_I, // Active high cycle-enable\r
- input [6:0] ADR_I, // Module register address\r
- input WE_I, // Active high for writes, low for reads\r
- input [31:0] DAT_I, // Write data\r
- output [31:0] DAT_O, // Read data\r
- output ACK_O, // Acknowledge output \96 single high pulse\r
-\r
- // User (packet) interface\r
- output Rx_mac_empty,\r
- input Rx_mac_rd,\r
- output [31:0] Rx_mac_data,\r
- output [1:0] Rx_mac_BE,\r
- output Rx_mac_sop,\r
- output Rx_mac_eop,\r
- output Rx_mac_err,\r
-\r
- output Tx_mac_wa,\r
- input Tx_mac_wr,\r
- input [31:0] Tx_mac_data,\r
- input [1:0] Tx_mac_BE,\r
- input Tx_mac_sop,\r
- input Tx_mac_eop,\r
-\r
- // PHY interface (GMII/MII)\r
- output Gtx_clk, // Used only in GMII mode\r
- input Rx_clk,\r
- input Tx_clk, // Used only in MII mode\r
- output Tx_er,\r
- output Tx_en,\r
- output [7:0] Txd,\r
- input Rx_er,\r
- input Rx_dv,\r
- input [7:0] Rxd,\r
- input Crs,\r
- input Col,\r
-\r
- // MDIO interface (to PHY)\r
- inout Mdio,\r
- output Mdc,\r
-\r
- // FIFO levels\r
- output [15:0] rx_fifo_occupied,\r
- output rx_fifo_full,\r
- output rx_fifo_empty,\r
- output [15:0] tx_fifo_occupied,\r
- output tx_fifo_full,\r
- output tx_fifo_empty,\r
- \r
- // Debug Interface\r
- output [31:0] debug0,\r
- output [31:0] debug1\r
-);\r
-\r
- wire rst_mac_rx = rst_mac;\r
- wire rst_mac_tx = rst_mac;\r
- wire [2:0] Speed;\r
- \r
- wire [31:0] debug_rx;\r
- wire [31:0] debug_tx0;\r
- wire [31:0] debug_tx1;\r
- \r
- //-------------------------------------------------------------------------\r
- // Local declarations\r
- //-------------------------------------------------------------------------\r
-\r
- // RMON interface\r
- wire [15:0] Rx_pkt_length_rmon;\r
- wire Rx_apply_rmon;\r
- wire [2:0] Rx_pkt_err_type_rmon;\r
- wire [2:0] Rx_pkt_type_rmon;\r
- wire [2:0] Tx_pkt_type_rmon;\r
- wire [15:0] Tx_pkt_length_rmon;\r
- wire Tx_apply_rmon;\r
- wire [2:0] Tx_pkt_err_type_rmon;\r
-\r
- // PHY interface\r
- wire MCrs_dv;\r
- wire [7:0] MRxD;\r
- wire MRxErr;\r
-\r
- // Flow-control signals\r
- wire [15:0] pause_quanta;\r
- wire pause_quanta_val;\r
- wire [15:0] rx_fifo_space;\r
- wire pause_apply, pause_quanta_sub;\r
- wire xon_gen, xoff_gen, xon_gen_complete, xoff_gen_complete;\r
- wire [15:0] fc_hwmark, fc_lwmark, fc_padtime;\r
- \r
- //PHY interface\r
- wire [7:0] MTxD;\r
- wire MTxEn;\r
- wire MCRS;\r
-\r
- // Interface clk signals\r
- wire MAC_tx_clk;\r
- wire MAC_rx_clk;\r
- wire MAC_tx_clk_div;\r
- wire MAC_rx_clk_div;\r
-\r
- // Reg signals\r
- wire [4:0] Tx_Hwmark;\r
- wire [4:0] Tx_Lwmark;\r
- wire pause_frame_send_en;\r
- wire [15:0] pause_quanta_set;\r
- wire MAC_tx_add_en;\r
- wire FullDuplex;\r
- wire [3:0] MaxRetry;\r
- wire [5:0] IFGset;\r
- wire [7:0] MAC_tx_add_prom_data;\r
- wire [2:0] MAC_tx_add_prom_add;\r
- wire MAC_tx_add_prom_wr;\r
- wire tx_pause_en;\r
-\r
- // Rx host interface\r
- wire MAC_rx_add_chk_en;\r
- wire [7:0] MAC_rx_add_prom_data;\r
- wire [2:0] MAC_rx_add_prom_add;\r
- wire MAC_rx_add_prom_wr;\r
- wire broadcast_filter_en;\r
- wire RX_APPEND_CRC;\r
- wire [4:0] Rx_Hwmark;\r
- wire [4:0] Rx_Lwmark;\r
- wire CRC_chk_en;\r
- wire [5:0] RX_IFG_SET;\r
- wire [15:0] RX_MAX_LENGTH;\r
- wire [6:0] RX_MIN_LENGTH;\r
-\r
- // RMON host interface\r
- wire [5:0] CPU_rd_addr;\r
- wire CPU_rd_apply;\r
- wire CPU_rd_grant;\r
- wire [31:0] CPU_rd_dout;\r
-\r
- // PHY int host interface\r
- wire Line_loop_en;\r
-\r
- // MII to CPU \r
- wire [7:0] Divider;\r
- wire [15:0] CtrlData;\r
- wire [4:0] Rgad;\r
- wire [4:0] Fiad;\r
- wire NoPre;\r
- wire WCtrlData;\r
- wire RStat;\r
- wire ScanStat;\r
- wire Busy;\r
- wire LinkFail;\r
- wire Nvalid;\r
- wire [15:0] Prsd;\r
- wire WCtrlDataStart;\r
- wire RStatStart;\r
- wire UpdateMIIRX_DATAReg;\r
- wire [15:0] broadcast_bucket_depth;\r
- wire [15:0] broadcast_bucket_interval;\r
-\r
- //-------------------------------------------------------------------------\r
- // Instantiation of sub-modules\r
- //-------------------------------------------------------------------------\r
-\r
- MAC_rx #(.RX_FF_DEPTH(RX_FF_DEPTH))\r
- U_MAC_rx(\r
- .Reset ( rst_mac_rx ),\r
- .Clk_user ( Clk_user ),\r
- .Clk ( MAC_rx_clk_div ),\r
-\r
- // RMII interface\r
- .MCrs_dv ( MCrs_dv ),\r
- .MRxD ( MRxD ),\r
- .MRxErr ( MRxErr ),\r
-\r
- // Flow-control signals\r
- .pause_quanta ( pause_quanta ),\r
- .pause_quanta_val ( pause_quanta_val ),\r
- .rx_fifo_space ( rx_fifo_space ),\r
- \r
- // User interface\r
- .Rx_mac_empty ( Rx_mac_empty ),\r
- .Rx_mac_rd ( Rx_mac_rd ),\r
- .Rx_mac_data ( Rx_mac_data ),\r
- .Rx_mac_BE ( Rx_mac_BE ),\r
- .Rx_mac_sop ( Rx_mac_sop ),\r
- .Rx_mac_eop ( Rx_mac_eop ),\r
- .Rx_mac_err ( Rx_mac_err ),\r
-\r
- // CPU\r
- .MAC_rx_add_chk_en ( MAC_rx_add_chk_en ),\r
- .MAC_add_prom_data ( MAC_rx_add_prom_data ),\r
- .MAC_add_prom_add ( MAC_rx_add_prom_add ),\r
- .MAC_add_prom_wr ( MAC_rx_add_prom_wr ),\r
- .broadcast_filter_en ( broadcast_filter_en ),\r
- .broadcast_bucket_depth ( broadcast_bucket_depth ),\r
- .broadcast_bucket_interval( broadcast_bucket_interval ),\r
- .RX_APPEND_CRC ( RX_APPEND_CRC ),\r
- .Rx_Hwmark ( Rx_Hwmark ),\r
- .Rx_Lwmark ( Rx_Lwmark ),\r
- .CRC_chk_en ( CRC_chk_en ),\r
- .RX_IFG_SET ( RX_IFG_SET ),\r
- .RX_MAX_LENGTH ( RX_MAX_LENGTH ),\r
- .RX_MIN_LENGTH ( RX_MIN_LENGTH ),\r
-\r
- // RMON interface\r
- .Rx_pkt_length_rmon ( Rx_pkt_length_rmon ),\r
- .Rx_apply_rmon ( Rx_apply_rmon ),\r
- .Rx_pkt_err_type_rmon ( Rx_pkt_err_type_rmon ),\r
- .Rx_pkt_type_rmon ( Rx_pkt_type_rmon ),\r
-\r
- .rx_fifo_occupied(rx_fifo_occupied),\r
- .rx_fifo_full(rx_fifo_full),\r
- .rx_fifo_empty(rx_fifo_empty),\r
- .debug(debug_rx)\r
- );\r
-\r
- MAC_tx #(.TX_FF_DEPTH(TX_FF_DEPTH))\r
- U_MAC_tx(\r
- .Reset ( rst_mac_tx ),\r
- .Clk ( MAC_tx_clk_div ),\r
- //.Clk_user ( Clk_user ),\r
- .Clk_user ( MAC_tx_clk_div ),\r
-\r
- // PHY interface\r
- .TxD ( MTxD ),\r
- .TxEn ( MTxEn ),\r
- .CRS ( MCRS ),\r
-\r
- // RMON\r
- .Tx_pkt_type_rmon ( Tx_pkt_type_rmon ),\r
- .Tx_pkt_length_rmon ( Tx_pkt_length_rmon ),\r
- .Tx_apply_rmon ( Tx_apply_rmon ),\r
- .Tx_pkt_err_type_rmon( Tx_pkt_err_type_rmon ),\r
-\r
- // User interface\r
- .Tx_mac_wa ( Tx_mac_wa ),\r
- .Tx_mac_wr ( Tx_mac_wr ),\r
- .Tx_mac_data ( Tx_mac_data ),\r
- .Tx_mac_BE ( Tx_mac_BE ),\r
- .Tx_mac_sop ( Tx_mac_sop ),\r
- .Tx_mac_eop ( Tx_mac_eop ),\r
-\r
- // Host interface\r
- .Tx_Hwmark ( Tx_Hwmark ),\r
- .Tx_Lwmark ( Tx_Lwmark ),\r
- .MAC_tx_add_en ( MAC_tx_add_en ),\r
- .FullDuplex ( FullDuplex ),\r
- .MaxRetry ( MaxRetry ),\r
- .IFGset ( IFGset ),\r
- .MAC_add_prom_data ( MAC_tx_add_prom_data ),\r
- .MAC_add_prom_add ( MAC_tx_add_prom_add ),\r
- .MAC_add_prom_wr ( MAC_tx_add_prom_wr ),\r
-\r
- .pause_apply ( pause_apply ),\r
- .pause_quanta_sub ( pause_quanta_sub ),\r
- .pause_quanta_set ( pause_quanta_set ),\r
- .xoff_gen ( xoff_gen ),\r
- .xon_gen ( xon_gen ),\r
- .xoff_gen_complete ( xoff_gen_complete ),\r
- .xon_gen_complete ( xon_gen_complete ),\r
- .debug0(debug_tx0),\r
- .debug1(debug_tx1)\r
- );\r
-\r
- // Flow control outbound -- when other side sends PAUSE, we wait\r
- flow_ctrl_tx flow_ctrl_tx\r
- (.rst(rst_mac_tx), \r
- .tx_clk(MAC_tx_clk_div), \r
- // Setting\r
- .tx_pause_en ( tx_pause_en ),\r
- // From RX side\r
- .pause_quanta (pause_quanta), \r
- .pause_quanta_val(pause_quanta_val), // Other guy sent a PAUSE\r
- // To TX side\r
- .pause_apply (pause_apply), // To TX, stop sending new frames\r
- .pause_quanta_sub (pause_quanta_sub) // From TX, indicates we have used up 1 quanta\r
- );\r
- \r
- flow_ctrl_rx flow_ctrl_rx // When we are running out of RX space, send a PAUSE\r
- (.rst(rst_mac_rx), // FIXME\r
- // Settings\r
- .pause_frame_send_en ( pause_frame_send_en ),\r
- .pause_quanta_set ( pause_quanta_set ),\r
- .fc_hwmark (fc_hwmark),\r
- .fc_lwmark (fc_lwmark),\r
- .fc_padtime (fc_padtime),\r
- // From RX side\r
- .rx_clk(MAC_rx_clk_div),\r
- .rx_fifo_space (rx_fifo_space), // Decide if we need to send a PAUSE\r
- // To TX side\r
- .tx_clk(MAC_tx_clk_div), \r
- .xoff_gen (xoff_gen), \r
- .xon_gen(xon_gen), // Tell our TX to send PAUSE frames\r
- .xoff_gen_complete (xoff_gen_complete), \r
- .xon_gen_complete(xon_gen_complete)\r
- );\r
-\r
- RMON U_RMON(\r
- .Clk ( CLK_I ),\r
- .Reset ( RST_I ),\r
-\r
- // Tx RMON\r
- .Tx_pkt_type_rmon ( Tx_pkt_type_rmon ),\r
- .Tx_pkt_length_rmon ( Tx_pkt_length_rmon ),\r
- .Tx_apply_rmon ( Tx_apply_rmon ),\r
- .Tx_pkt_err_type_rmon( Tx_pkt_err_type_rmon ),\r
-\r
- // Rx RMON\r
- .Rx_pkt_type_rmon ( Rx_pkt_type_rmon ),\r
- .Rx_pkt_length_rmon ( Rx_pkt_length_rmon ),\r
- .Rx_apply_rmon ( Rx_apply_rmon ),\r
- .Rx_pkt_err_type_rmon( Rx_pkt_err_type_rmon ),\r
-\r
- // CPU\r
- .CPU_rd_addr ( CPU_rd_addr ),\r
- .CPU_rd_apply ( CPU_rd_apply ),\r
- .CPU_rd_grant ( CPU_rd_grant ),\r
- .CPU_rd_dout ( CPU_rd_dout )\r
- );\r
-\r
- Phy_int U_Phy_int(\r
- .rst_mac_rx ( rst_mac_rx ),\r
- .rst_mac_tx ( rst_mac_tx ),\r
- .MAC_rx_clk ( MAC_rx_clk ),\r
- .MAC_tx_clk ( MAC_tx_clk ),\r
- // Rx interface\r
- .MCrs_dv ( MCrs_dv ),\r
- .MRxD ( MRxD ),\r
- .MRxErr ( MRxErr ),\r
- // Tx interface\r
- .MTxD ( MTxD ),\r
- .MTxEn ( MTxEn ),\r
- .MCRS ( MCRS ),\r
- // PHY interface\r
- .Tx_er ( Tx_er ),\r
- .Tx_en ( Tx_en ),\r
- .Txd ( Txd ),\r
- .Rx_er ( Rx_er ),\r
- .Rx_dv ( Rx_dv ),\r
- .Rxd ( Rxd ),\r
- .Crs ( Crs ),\r
- .Col ( Col ),\r
- // Host interface\r
- .Line_loop_en( Line_loop_en ),\r
- .Speed ( Speed ) );\r
-\r
- Clk_ctrl U_Clk_ctrl(\r
- .Reset ( rst_mac ),\r
- .Clk_125M ( Clk_125M ),\r
-\r
- // Host interface\r
- .Speed ( Speed ),\r
-\r
- // Phy interface\r
- .Gtx_clk ( Gtx_clk ),\r
- .Rx_clk ( Rx_clk ),\r
- .Tx_clk ( Tx_clk ),\r
-\r
- // Interface clocks\r
- .MAC_tx_clk ( MAC_tx_clk ),\r
- .MAC_rx_clk ( MAC_rx_clk ),\r
- .MAC_tx_clk_div( MAC_tx_clk_div ),\r
- .MAC_rx_clk_div( MAC_rx_clk_div )\r
- );\r
-\r
- eth_miim U_eth_miim(\r
- .Clk ( CLK_I ),\r
- .Reset ( RST_I ),\r
- .Divider ( Divider ),\r
- .NoPre ( NoPre ),\r
- .CtrlData ( CtrlData ),\r
- .Rgad ( Rgad ),\r
- .Fiad ( Fiad ),\r
- .WCtrlData ( WCtrlData ),\r
- .RStat ( RStat ),\r
- .ScanStat ( ScanStat ),\r
- .Mdio ( Mdio ),\r
- .Mdc ( Mdc ),\r
- .Busy ( Busy ),\r
- .Prsd ( Prsd ),\r
- .LinkFail ( LinkFail ),\r
- .Nvalid ( Nvalid ),\r
- .WCtrlDataStart ( WCtrlDataStart ),\r
- .RStatStart ( RStatStart ),\r
- .UpdateMIIRX_DATAReg( UpdateMIIRX_DATAReg )\r
- );\r
-\r
- Reg_int U_Reg_int(\r
- // Wishbone compliant core host interface\r
- .CLK_I( CLK_I ),\r
- .RST_I( RST_I ),\r
- .STB_I( STB_I ),\r
- .CYC_I( CYC_I ),\r
- .ADR_I( ADR_I ),\r
- .WE_I ( WE_I ),\r
- .DAT_I( DAT_I ),\r
- .DAT_O( DAT_O ),\r
- .ACK_O( ACK_O ),\r
-\r
- // Tx host interface\r
- .Tx_Hwmark ( Tx_Hwmark ),\r
- .Tx_Lwmark ( Tx_Lwmark ),\r
- .MAC_tx_add_en ( MAC_tx_add_en ),\r
- .FullDuplex ( FullDuplex ),\r
- .MaxRetry ( MaxRetry ),\r
- .IFGset ( IFGset ),\r
- .MAC_tx_add_prom_data ( MAC_tx_add_prom_data ),\r
- .MAC_tx_add_prom_add ( MAC_tx_add_prom_add ),\r
- .MAC_tx_add_prom_wr ( MAC_tx_add_prom_wr ),\r
-\r
- // Rx host interface\r
- .MAC_rx_add_chk_en ( MAC_rx_add_chk_en ),\r
- .MAC_rx_add_prom_data ( MAC_rx_add_prom_data ),\r
- .MAC_rx_add_prom_add ( MAC_rx_add_prom_add ),\r
- .MAC_rx_add_prom_wr ( MAC_rx_add_prom_wr ),\r
- .broadcast_filter_en ( broadcast_filter_en ),\r
- .broadcast_bucket_depth ( broadcast_bucket_depth ),\r
- .broadcast_bucket_interval( broadcast_bucket_interval ),\r
- .RX_APPEND_CRC ( RX_APPEND_CRC ),\r
- .Rx_Hwmark ( Rx_Hwmark ),\r
- .Rx_Lwmark ( Rx_Lwmark ),\r
- .CRC_chk_en ( CRC_chk_en ),\r
- .RX_IFG_SET ( RX_IFG_SET ),\r
- .RX_MAX_LENGTH ( RX_MAX_LENGTH ),\r
- .RX_MIN_LENGTH ( RX_MIN_LENGTH ),\r
-\r
- // Flow Control settings\r
- .pause_frame_send_en ( pause_frame_send_en ),\r
- .pause_quanta_set ( pause_quanta_set ),\r
- .tx_pause_en ( tx_pause_en ),\r
- .fc_hwmark ( fc_hwmark ),\r
- .fc_lwmark ( fc_lwmark ),\r
- .fc_padtime ( fc_padtime ),\r
- \r
- // RMON host interface\r
- .CPU_rd_addr ( CPU_rd_addr ),\r
- .CPU_rd_apply ( CPU_rd_apply ),\r
- .CPU_rd_grant ( CPU_rd_grant ),\r
- .CPU_rd_dout ( CPU_rd_dout ),\r
-\r
- // PHY int host interface\r
- .Line_loop_en ( Line_loop_en ),\r
- .Speed ( Speed ),\r
-\r
- // MII to CPU\r
- .Divider ( Divider ),\r
- .CtrlData ( CtrlData ),\r
- .Rgad ( Rgad ),\r
- .Fiad ( Fiad ),\r
- .NoPre ( NoPre ),\r
- .WCtrlData ( WCtrlData ),\r
- .RStat ( RStat ),\r
- .ScanStat ( ScanStat ),\r
- .Busy ( Busy ),\r
- .LinkFail ( LinkFail ),\r
- .Nvalid ( Nvalid ),\r
- .Prsd ( Prsd ),\r
- .WCtrlDataStart ( WCtrlDataStart ),\r
- .RStatStart ( RStatStart ),\r
- .UpdateMIIRX_DATAReg ( UpdateMIIRX_DATAReg )\r
- );\r
-\r
- assign debug0 = {xon_gen, xoff_gen, xon_gen_complete, xoff_gen_complete, debug_rx[3:0]};\r
- //assign debug0 = {{debug_rx[3:0], xon_gen, xon_gen_complete, xoff_gen, xoff_gen_complete},\r
- // {1'b0,Rx_mac_err,Rx_mac_empty,Rx_mac_rd,Rx_mac_sop,Rx_mac_eop,Rx_mac_BE[1:0]},\r
- // {rx_fifo_space}};\r
- //assign debug0 = debug_tx0;\r
- //assign debug1 = debug_tx1;\r
-endmodule\r
+++ /dev/null
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// MAC_tx.v ////\r
-//// ////\r
-//// This file is part of the Ethernet IP core project ////\r
-//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////\r
-//// ////\r
-//// Author(s): ////\r
-//// - Jon Gao (gaojon@yahoo.com) ////\r
-//// ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// Copyright (C) 2001 Authors ////\r
-//// ////\r
-//// This source file may be used and distributed without ////\r
-//// restriction provided that this copyright statement is not ////\r
-//// removed from the file and that any derivative work contains ////\r
-//// the original copyright notice and the associated disclaimer. ////\r
-//// ////\r
-//// This source file is free software; you can redistribute it ////\r
-//// and/or modify it under the terms of the GNU Lesser General ////\r
-//// Public License as published by the Free Software Foundation; ////\r
-//// either version 2.1 of the License, or (at your option) any ////\r
-//// later version. ////\r
-//// ////\r
-//// This source is distributed in the hope that it will be ////\r
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\r
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\r
-//// PURPOSE. See the GNU Lesser General Public License for more ////\r
-//// details. ////\r
-//// ////\r
-//// You should have received a copy of the GNU Lesser General ////\r
-//// Public License along with this source; if not, download it ////\r
-//// from http://www.opencores.org/lgpl.shtml ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-// \r
-// CVS Revision History \r
-// \r
-// $Log: MAC_tx.v,v $\r
-// Revision 1.4 2006/11/17 17:53:07 maverickist\r
-// no message\r
-//\r
-// Revision 1.3 2006/01/19 14:07:53 maverickist\r
-// verification is complete.\r
-//\r
-// Revision 1.2 2005/12/16 06:44:14 Administrator\r
-// replaced tab with space.\r
-// passed 9.6k length frame test.\r
-//\r
-// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator\r
-// no message\r
-// \r
-\r
-module MAC_tx\r
- #(parameter TX_FF_DEPTH = 9)\r
- (\r
-input Reset ,\r
-input Clk ,\r
-input Clk_user ,\r
- //PHY interface\r
-output [7:0] TxD ,\r
-output TxEn , \r
-input CRS ,\r
- //RMON\r
-output [2:0] Tx_pkt_type_rmon ,\r
-output [15:0] Tx_pkt_length_rmon ,\r
-output Tx_apply_rmon ,\r
-output [2:0] Tx_pkt_err_type_rmon,\r
- //user interface \r
-output Tx_mac_wa ,\r
-input Tx_mac_wr ,\r
-input [31:0] Tx_mac_data ,\r
-input [1:0] Tx_mac_BE ,//big endian\r
-input Tx_mac_sop ,\r
-input Tx_mac_eop ,\r
- //host interface \r
-input [4:0] Tx_Hwmark ,\r
-input [4:0] Tx_Lwmark , \r
-input MAC_tx_add_en , \r
-input FullDuplex ,\r
-input [3:0] MaxRetry ,\r
-input [5:0] IFGset ,\r
-input [7:0] MAC_add_prom_data ,\r
-input [2:0] MAC_add_prom_add ,\r
-input MAC_add_prom_wr ,\r
- // Flow control stuff\r
-input pause_apply ,\r
-output pause_quanta_sub,\r
-input [15:0] pause_quanta_set ,\r
-input xoff_gen,\r
-input xon_gen,\r
-output xoff_gen_complete,\r
-output xon_gen_complete,\r
- output [31:0] debug0,\r
- output [31:0] debug1\r
-);\r
-\r
- // ****************************************************************************** \r
- // internal signals \r
- // ****************************************************************************** \r
- //CRC_gen Interface \r
-wire CRC_init ;\r
-wire[7:0] Frame_data ;\r
-wire Data_en ;\r
-wire CRC_rd ;\r
-wire CRC_end ;\r
-wire[7:0] CRC_out ;\r
- //Random_gen interface\r
-wire Random_init ;\r
-wire[3:0] RetryCnt ;\r
-wire Random_time_meet ;//levle hight indicate random time passed away\r
- //flow control\r
- //MAC_rx_FF\r
-wire[7:0] Fifo_data ;\r
-wire Fifo_rd ;\r
-wire Fifo_eop ;\r
-wire Fifo_da ;\r
-wire Fifo_rd_finish ;\r
-wire Fifo_rd_retry ;\r
-wire Fifo_ra ;\r
-wire Fifo_data_err_empty ;\r
-wire Fifo_data_err_full ;\r
- //MAC_tx_addr_add\r
-wire MAC_tx_addr_init ;\r
-wire MAC_tx_addr_rd ;\r
-wire[7:0] MAC_tx_addr_data ;\r
-\r
-\r
- reg xon_gen_d1, xoff_gen_d1;\r
- always @(posedge Clk) xon_gen_d1 <= xon_gen;\r
- always @(posedge Clk) xoff_gen_d1 <= xoff_gen;\r
- \r
-//****************************************************************************** \r
-//instantiation \r
-//****************************************************************************** \r
-MAC_tx_ctrl U_MAC_tx_ctrl(\r
-.Reset (Reset ), \r
-.Clk (Clk ), \r
- //CRC_gen Interface (//CRC_gen Interface ), \r
-.CRC_init (CRC_init ), \r
-.Frame_data (Frame_data ), \r
-.Data_en (Data_en ), \r
-.CRC_rd (CRC_rd ), \r
-.CRC_end (CRC_end ), \r
-.CRC_out (CRC_out ), \r
- //Random_gen interfac (//Random_gen interfac ), \r
-.Random_init (Random_init ), \r
-.RetryCnt (RetryCnt ), \r
-.Random_time_meet (Random_time_meet ), \r
- //flow control (//flow control ), \r
-.pause_apply (pause_apply ), \r
-.pause_quanta_sub (pause_quanta_sub ), \r
-.xoff_gen (xoff_gen_d1 ), \r
-.xoff_gen_complete (xoff_gen_complete ), \r
-.xon_gen (xon_gen_d1 ), \r
-.xon_gen_complete (xon_gen_complete ), \r
- //MAC_tx_FF (//MAC_tx_FF ), \r
-.Fifo_data (Fifo_data ), \r
-.Fifo_rd (Fifo_rd ), \r
-.Fifo_eop (Fifo_eop ), \r
-.Fifo_da (Fifo_da ), \r
-.Fifo_rd_finish (Fifo_rd_finish ), \r
-.Fifo_rd_retry (Fifo_rd_retry ), \r
-.Fifo_ra (Fifo_ra ), \r
-.Fifo_data_err_empty (Fifo_data_err_empty ), \r
-.Fifo_data_err_full (Fifo_data_err_full ), \r
- //RMII (//RMII ), \r
-.TxD (TxD ), \r
-.TxEn (TxEn ), \r
-.CRS (CRS ), \r
- //MAC_tx_addr_add (//MAC_tx_addr_add ), \r
-.MAC_tx_addr_rd (MAC_tx_addr_rd ), \r
-.MAC_tx_addr_data (MAC_tx_addr_data ), \r
-.MAC_tx_addr_init (MAC_tx_addr_init ), \r
- //RMON (//RMON ), \r
-.Tx_pkt_type_rmon (Tx_pkt_type_rmon ), \r
-.Tx_pkt_length_rmon (Tx_pkt_length_rmon ), \r
-.Tx_apply_rmon (Tx_apply_rmon ), \r
-.Tx_pkt_err_type_rmon (Tx_pkt_err_type_rmon ), \r
- //CPU (//CPU ), \r
-.pause_quanta_set (pause_quanta_set ), \r
-.MAC_tx_add_en (MAC_tx_add_en ), \r
-.FullDuplex (FullDuplex ), \r
-.MaxRetry (MaxRetry ), \r
-.IFGset (IFGset ) \r
-);\r
-\r
-CRC_gen U_CRC_gen(\r
-.Reset (Reset ),\r
-.Clk (Clk ),\r
-.Init (CRC_init ),\r
-.Frame_data (Frame_data ),\r
-.Data_en (Data_en ),\r
-.CRC_rd (CRC_rd ),\r
-.CRC_out (CRC_out ),\r
-.CRC_end (CRC_end )\r
-);\r
-\r
- MAC_tx_addr_add U_MAC_tx_addr_add\r
- (.Reset (Reset ),\r
- .Clk (Clk ),\r
- .MAC_tx_addr_rd (MAC_tx_addr_rd ),\r
- .MAC_tx_addr_init (MAC_tx_addr_init ),\r
- .MAC_tx_addr_data (MAC_tx_addr_data ),\r
- //CPU\r
- .MAC_add_prom_data (MAC_add_prom_data ),\r
- .MAC_add_prom_add (MAC_add_prom_add ),\r
- .MAC_add_prom_wr (MAC_add_prom_wr )\r
- );\r
- \r
-MAC_tx_FF #(.TX_FF_DEPTH(TX_FF_DEPTH)) U_MAC_tx_FF(\r
-.Reset (Reset ),\r
-.Clk_MAC (Clk ),\r
-.Clk_SYS (Clk_user ),\r
- //MAC_rx_ctrl interf (//MAC_rx_ctrl interf ),\r
-.Fifo_data (Fifo_data ),\r
-.Fifo_rd (Fifo_rd ),\r
-.Fifo_rd_finish (Fifo_rd_finish ),\r
-.Fifo_rd_retry (Fifo_rd_retry ),\r
-.Fifo_eop (Fifo_eop ),\r
-.Fifo_da (Fifo_da ),\r
-.Fifo_ra (Fifo_ra ),\r
-.Fifo_data_err_empty (Fifo_data_err_empty ),\r
-.Fifo_data_err_full (Fifo_data_err_full ),\r
- //user interface (//user interface ),\r
-.Tx_mac_wa (Tx_mac_wa ),\r
-.Tx_mac_wr (Tx_mac_wr ),\r
-.Tx_mac_data (Tx_mac_data ),\r
-.Tx_mac_BE (Tx_mac_BE ),\r
-.Tx_mac_sop (Tx_mac_sop ),\r
-.Tx_mac_eop (Tx_mac_eop ),\r
- //host interface (//host interface ),\r
-.FullDuplex (FullDuplex ),\r
-.Tx_Hwmark (Tx_Hwmark ),\r
-.Tx_Lwmark (Tx_Lwmark ),\r
-.debug0(debug0), \r
-.debug1(debug1) \r
-);\r
-\r
-Random_gen U_Random_gen(\r
-.Reset (Reset ),\r
-.Clk (Clk ),\r
-.Init (Random_init ),\r
-.RetryCnt (RetryCnt ),\r
-.Random_time_meet (Random_time_meet ) \r
-);\r
-\r
-endmodule\r
+++ /dev/null
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// CRC_gen.v ////\r
-//// ////\r
-//// This file is part of the Ethernet IP core project ////\r
-//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////\r
-//// ////\r
-//// Author(s): ////\r
-//// - Jon Gao (gaojon@yahoo.com) ////\r
-//// ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// Copyright (C) 2001 Authors ////\r
-//// ////\r
-//// This source file may be used and distributed without ////\r
-//// restriction provided that this copyright statement is not ////\r
-//// removed from the file and that any derivative work contains ////\r
-//// the original copyright notice and the associated disclaimer. ////\r
-//// ////\r
-//// This source file is free software; you can redistribute it ////\r
-//// and/or modify it under the terms of the GNU Lesser General ////\r
-//// Public License as published by the Free Software Foundation; ////\r
-//// either version 2.1 of the License, or (at your option) any ////\r
-//// later version. ////\r
-//// ////\r
-//// This source is distributed in the hope that it will be ////\r
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\r
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\r
-//// PURPOSE. See the GNU Lesser General Public License for more ////\r
-//// details. ////\r
-//// ////\r
-//// You should have received a copy of the GNU Lesser General ////\r
-//// Public License along with this source; if not, download it ////\r
-//// from http://www.opencores.org/lgpl.shtml ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-// \r
-// CVS Revision History \r
-// \r
-// $Log: CRC_gen.v,v $\r
-// Revision 1.3 2006/01/19 14:07:54 maverickist\r
-// verification is complete.\r
-//\r
-// Revision 1.2 2005/12/16 06:44:17 Administrator\r
-// replaced tab with space.\r
-// passed 9.6k length frame test.\r
-//\r
-// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator\r
-// no message\r
-// \r
-\r
-module CRC_gen (\r
-Reset ,\r
-Clk ,\r
-Init ,\r
-Frame_data ,\r
-Data_en ,\r
-CRC_rd ,\r
-CRC_end ,\r
-CRC_out \r
-\r
-);\r
-input Reset ;\r
-input Clk ;\r
-input Init ;\r
-input [7:0] Frame_data ;\r
-input Data_en ;\r
-input CRC_rd ;\r
-output [7:0] CRC_out ;\r
-output CRC_end ;\r
-\r
-//****************************************************************************** \r
-//internal signals \r
-//******************************************************************************\r
-reg [7:0] CRC_out ;\r
-reg [31:0] CRC_reg;\r
-reg CRC_end;\r
-reg [3:0] Counter;\r
-//******************************************************************************\r
-//******************************************************************************\r
-//input data width is 8bit, and the first bit is bit[0]\r
-function[31:0] NextCRC;\r
- input[7:0] D;\r
- input[31:0] C;\r
- reg[31:0] NewCRC;\r
- begin\r
- NewCRC[0]=C[24]^C[30]^D[1]^D[7];\r
- NewCRC[1]=C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];\r
- NewCRC[2]=C[26]^D[5]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];\r
- NewCRC[3]=C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];\r
- NewCRC[4]=C[28]^D[3]^C[27]^D[4]^C[26]^D[5]^C[24]^C[30]^D[1]^D[7];\r
- NewCRC[5]=C[29]^D[2]^C[28]^D[3]^C[27]^D[4]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];\r
- NewCRC[6]=C[30]^D[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];\r
- NewCRC[7]=C[31]^D[0]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];\r
- NewCRC[8]=C[0]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];\r
- NewCRC[9]=C[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6];\r
- NewCRC[10]=C[2]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];\r
- NewCRC[11]=C[3]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];\r
- NewCRC[12]=C[4]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];\r
- NewCRC[13]=C[5]^C[30]^D[1]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];\r
- NewCRC[14]=C[6]^C[31]^D[0]^C[30]^D[1]^C[28]^D[3]^C[27]^D[4]^C[26]^D[5];\r
- NewCRC[15]=C[7]^C[31]^D[0]^C[29]^D[2]^C[28]^D[3]^C[27]^D[4];\r
- NewCRC[16]=C[8]^C[29]^D[2]^C[28]^D[3]^C[24]^D[7];\r
- NewCRC[17]=C[9]^C[30]^D[1]^C[29]^D[2]^C[25]^D[6];\r
- NewCRC[18]=C[10]^C[31]^D[0]^C[30]^D[1]^C[26]^D[5];\r
- NewCRC[19]=C[11]^C[31]^D[0]^C[27]^D[4];\r
- NewCRC[20]=C[12]^C[28]^D[3];\r
- NewCRC[21]=C[13]^C[29]^D[2];\r
- NewCRC[22]=C[14]^C[24]^D[7];\r
- NewCRC[23]=C[15]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];\r
- NewCRC[24]=C[16]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];\r
- NewCRC[25]=C[17]^C[27]^D[4]^C[26]^D[5];\r
- NewCRC[26]=C[18]^C[28]^D[3]^C[27]^D[4]^C[24]^C[30]^D[1]^D[7];\r
- NewCRC[27]=C[19]^C[29]^D[2]^C[28]^D[3]^C[25]^C[31]^D[0]^D[6];\r
- NewCRC[28]=C[20]^C[30]^D[1]^C[29]^D[2]^C[26]^D[5];\r
- NewCRC[29]=C[21]^C[31]^D[0]^C[30]^D[1]^C[27]^D[4];\r
- NewCRC[30]=C[22]^C[31]^D[0]^C[28]^D[3];\r
- NewCRC[31]=C[23]^C[29]^D[2];\r
- NextCRC=NewCRC;\r
- end\r
- endfunction\r
-//******************************************************************************\r
-\r
-always @ (posedge Clk) // or posedge Reset)\r
-// if (Reset)\r
-// CRC_reg <=32'hffffffff;\r
-// else \r
- if (Init)\r
- CRC_reg <=32'hffffffff;\r
- else if (Data_en)\r
- CRC_reg <=NextCRC(Frame_data,CRC_reg);\r
- else if (CRC_rd)\r
- CRC_reg <={CRC_reg[23:0],8'hff};\r
- \r
-always @ (CRC_rd or CRC_reg)\r
-// if (CRC_rd)\r
- CRC_out <=~{\r
- CRC_reg[24],\r
- CRC_reg[25],\r
- CRC_reg[26],\r
- CRC_reg[27],\r
- CRC_reg[28],\r
- CRC_reg[29],\r
- CRC_reg[30],\r
- CRC_reg[31]\r
- };\r
-// else\r
-// CRC_out <=0;\r
- \r
-//caculate CRC out length ,4 cycles \r
-//CRC_end aligned to last CRC checksum data\r
-always @(posedge Clk or posedge Reset)\r
- if (Reset)\r
- Counter <=0;\r
- else if (!CRC_rd)\r
- Counter <=0;\r
- else \r
- Counter <=Counter + 1;\r
- \r
-always @ (Counter)\r
- if (Counter==3)\r
- CRC_end=1;\r
- else\r
- CRC_end=0;\r
-\r
-endmodule\r
-\r
-\r
+++ /dev/null
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// MAC_tx_FF.v ////\r
-//// ////\r
-//// This file is part of the Ethernet IP core project ////\r
-//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////\r
-//// ////\r
-//// Author(s): ////\r
-//// - Jon Gao (gaojon@yahoo.com) ////\r
-//// ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// Copyright (C) 2001 Authors ////\r
-//// ////\r
-//// This source file may be used and distributed without ////\r
-//// restriction provided that this copyright statement is not ////\r
-//// removed from the file and that any derivative work contains ////\r
-//// the original copyright notice and the associated disclaimer. ////\r
-//// ////\r
-//// This source file is free software; you can redistribute it ////\r
-//// and/or modify it under the terms of the GNU Lesser General ////\r
-//// Public License as published by the Free Software Foundation; ////\r
-//// either version 2.1 of the License, or (at your option) any ////\r
-//// later version. ////\r
-//// ////\r
-//// This source is distributed in the hope that it will be ////\r
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\r
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\r
-//// PURPOSE. See the GNU Lesser General Public License for more ////\r
-//// details. ////\r
-//// ////\r
-//// You should have received a copy of the GNU Lesser General ////\r
-//// Public License along with this source; if not, download it ////\r
-//// from http://www.opencores.org/lgpl.shtml ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-\r
-module MAC_tx_FF \r
- #(parameter TX_FF_DEPTH = 9)\r
- (input Reset ,\r
- input Clk_MAC ,\r
- input Clk_SYS ,\r
- //MAC_tx_ctrl\r
- output reg [7:0]Fifo_data ,\r
- input Fifo_rd ,\r
- input Fifo_rd_finish ,\r
- input Fifo_rd_retry ,\r
- output reg Fifo_eop ,\r
- output reg Fifo_da ,\r
- output reg Fifo_ra ,\r
- output reg Fifo_data_err_empty ,\r
- output Fifo_data_err_full ,\r
- //user interface \r
- output reg Tx_mac_wa ,\r
- input Tx_mac_wr ,\r
- input [31:0] Tx_mac_data ,\r
- input [1:0] Tx_mac_BE ,//big endian\r
- input Tx_mac_sop ,\r
- input Tx_mac_eop ,\r
- //host interface \r
- input FullDuplex ,\r
- input [4:0] Tx_Hwmark ,\r
- input [4:0] Tx_Lwmark ,\r
- output [31:0] debug0,\r
- output [31:0] debug1\r
- );\r
-\r
-//******************************************************************************\r
-//internal signals \r
-//******************************************************************************\r
-localparam MAC_byte3 =4'd00; \r
-localparam MAC_byte2 =4'd01;\r
-localparam MAC_byte1 =4'd02; \r
-localparam MAC_byte0 =4'd03; \r
-localparam MAC_wait_finish =4'd04;\r
-localparam MAC_retry =4'd08;\r
-localparam MAC_idle =4'd09;\r
-localparam MAC_FFEmpty =4'd10;\r
-localparam MAC_FFEmpty_drop =4'd11;\r
-localparam MAC_pkt_sub =4'd12;\r
-localparam MAC_FF_Err =4'd13;\r
-\r
-\r
-reg [3:0] Next_state_MAC ;\r
-\r
-\r
-localparam SYS_idle =4'd0;\r
-localparam SYS_WaitSop =4'd1;\r
-localparam SYS_SOP =4'd2;\r
-localparam SYS_MOP =4'd3;\r
-localparam SYS_DROP =4'd4;\r
-localparam SYS_EOP_ok =4'd5; \r
-localparam SYS_FFEmpty =4'd6; \r
-localparam SYS_EOP_err =4'd7;\r
-localparam SYS_SOP_err =4'd8;\r
-\r
-reg [3:0] Next_state_SYS;\r
-\r
-reg [TX_FF_DEPTH-1:0] Add_wr ;\r
-reg [TX_FF_DEPTH-1:0] Add_wr_ungray ;\r
-reg [TX_FF_DEPTH-1:0] Add_wr_gray ;\r
-reg [TX_FF_DEPTH-1:0] Add_wr_gray_dl1 ;\r
-reg [TX_FF_DEPTH-1:0] Add_wr_gray_dl2 ;\r
-\r
-reg [TX_FF_DEPTH-1:0] Add_rd ;\r
-reg [TX_FF_DEPTH-1:0] Add_rd_reg ;\r
-reg [TX_FF_DEPTH-1:0] Add_rd_gray ;\r
-reg [TX_FF_DEPTH-1:0] Add_rd_gray_dl1 ;\r
-reg [TX_FF_DEPTH-1:0] Add_rd_gray_dl2 ;\r
-reg [TX_FF_DEPTH-1:0] Add_rd_ungray ;\r
-wire[35:0] Din ;\r
-wire[35:0] Dout ;\r
-reg Wr_en ;\r
-wire[TX_FF_DEPTH-1:0] Add_wr_pluse;\r
-wire[TX_FF_DEPTH-1:0] Add_wr_pluse_pluse;\r
-reg [TX_FF_DEPTH-1:TX_FF_DEPTH-5] Add_rd_reg_dl1;\r
-\r
-reg [3:0] Current_state_MAC;\r
-reg [3:0] Current_state_MAC_reg;\r
-reg [3:0] Current_state_SYS;\r
-reg Full;\r
-reg AlmostFull;\r
-reg Empty;\r
-reg [35:0] Dout_reg;\r
-reg Packet_number_sub_edge;\r
-reg Packet_number_add;\r
-reg [5:0] Packet_number_inFF;\r
-reg [5:0] Packet_number_inFF_reg;\r
-reg Dout_reg_en;\r
-reg Add_rd_add;\r
-\r
-\r
-reg Tx_mac_wr_dl1 ;\r
-reg [31:0] Tx_mac_data_dl1 ;\r
-reg [1:0] Tx_mac_BE_dl1 ;\r
-reg FF_FullErr ;\r
-wire[1:0] Dout_BE ;\r
-wire Dout_eop ;\r
-wire Dout_err ;\r
-wire[31:0] Dout_data ; \r
-reg Packet_number_sub_dl1 ;\r
-reg Packet_number_sub_dl2 ;\r
-reg [4:0] Fifo_data_count ;\r
-reg Fifo_ra_tmp ; \r
-reg Pkt_sub_apply_tmp ;\r
-reg Pkt_sub_apply ;\r
-reg Add_rd_reg_rdy_tmp ;\r
-reg Add_rd_reg_rdy ; \r
-reg Add_rd_reg_rdy_dl1 ; \r
-reg Add_rd_reg_rdy_dl2 ;\r
-reg [4:0] Tx_Hwmark_pl ;\r
-reg [4:0] Tx_Lwmark_pl ;\r
-reg Add_rd_jump_tmp ;\r
-reg Add_rd_jump_tmp_pl1 ;\r
-reg Add_rd_jump ;\r
-reg Add_rd_jump_wr_pl1 ;\r
-\r
-//******************************************************************************\r
-//write data to from FF .\r
-//domain Clk_SYS\r
-//******************************************************************************\r
-always @ (posedge Clk_SYS or posedge Reset)\r
- if (Reset)\r
- Current_state_SYS <=SYS_idle;\r
- else\r
- Current_state_SYS <=Next_state_SYS;\r
- \r
-always @ (Current_state_SYS or Tx_mac_wr or Tx_mac_sop or Full or AlmostFull \r
- or Tx_mac_eop )\r
- case (Current_state_SYS)\r
- SYS_idle:\r
- if (Tx_mac_wr&&Tx_mac_sop&&!Full)\r
- Next_state_SYS =SYS_SOP;\r
- else\r
- Next_state_SYS =Current_state_SYS ;\r
- SYS_SOP:\r
- Next_state_SYS =SYS_MOP;\r
- SYS_MOP:\r
- if (AlmostFull)\r
- Next_state_SYS =SYS_DROP;\r
- else if (Tx_mac_wr&&Tx_mac_sop)\r
- Next_state_SYS =SYS_SOP_err;\r
- else if (Tx_mac_wr&&Tx_mac_eop)\r
- Next_state_SYS =SYS_EOP_ok;\r
- else\r
- Next_state_SYS =Current_state_SYS ;\r
- SYS_EOP_ok:\r
- if (Tx_mac_wr&&Tx_mac_sop)\r
- Next_state_SYS =SYS_SOP;\r
- else\r
- Next_state_SYS =SYS_idle;\r
- SYS_EOP_err:\r
- if (Tx_mac_wr&&Tx_mac_sop)\r
- Next_state_SYS =SYS_SOP;\r
- else\r
- Next_state_SYS =SYS_idle;\r
- SYS_SOP_err:\r
- Next_state_SYS =SYS_DROP;\r
- SYS_DROP: //FIFO overflow \r
- if (Tx_mac_wr&&Tx_mac_eop)\r
- Next_state_SYS =SYS_EOP_err;\r
- else \r
- Next_state_SYS =Current_state_SYS ;\r
- default:\r
- Next_state_SYS =SYS_idle;\r
- endcase\r
- \r
-//delay signals \r
-always @ (posedge Clk_SYS or posedge Reset)\r
- if (Reset)\r
- begin \r
- Tx_mac_wr_dl1 <=0;\r
- Tx_mac_data_dl1 <=0;\r
- Tx_mac_BE_dl1 <=0;\r
- end \r
- else\r
- begin \r
- Tx_mac_wr_dl1 <=Tx_mac_wr ;\r
- Tx_mac_data_dl1 <=Tx_mac_data ;\r
- Tx_mac_BE_dl1 <=Tx_mac_BE ;\r
- end \r
-\r
-always @(Current_state_SYS) \r
- if (Current_state_SYS==SYS_EOP_err)\r
- FF_FullErr =1;\r
- else\r
- FF_FullErr =0; \r
-\r
-reg Tx_mac_eop_gen;\r
-\r
-always @(Current_state_SYS) \r
- if (Current_state_SYS==SYS_EOP_err||Current_state_SYS==SYS_EOP_ok)\r
- Tx_mac_eop_gen =1;\r
- else\r
- Tx_mac_eop_gen =0; \r
- \r
-assign Din={Tx_mac_eop_gen,FF_FullErr,Tx_mac_BE_dl1,Tx_mac_data_dl1};\r
-\r
-always @(Current_state_SYS or Tx_mac_wr_dl1)\r
- if ((Current_state_SYS==SYS_SOP||Current_state_SYS==SYS_EOP_ok||\r
- Current_state_SYS==SYS_MOP||Current_state_SYS==SYS_EOP_err)&&Tx_mac_wr_dl1)\r
- Wr_en = 1;\r
- else\r
- Wr_en = 0;\r
- \r
- \r
-//\r
- \r
- \r
-always @ (posedge Reset or posedge Clk_SYS)\r
- if (Reset)\r
- Add_wr_gray <=0;\r
- else \r
- begin : Add_wr_gray_loop\r
- integer i;\r
- Add_wr_gray[TX_FF_DEPTH-1] <=Add_wr[TX_FF_DEPTH-1];\r
- for (i=TX_FF_DEPTH-2;i>=0;i=i-1)\r
- Add_wr_gray[i] <=Add_wr[i+1]^Add_wr[i];\r
- end\r
-\r
-always @ (posedge Clk_SYS or posedge Reset)\r
- if (Reset)\r
- Add_rd_gray_dl1 <=0;\r
- else\r
- Add_rd_gray_dl1 <=Add_rd_gray;\r
-\r
- always @(posedge Clk_SYS or posedge Reset)\r
- if (Reset)\r
- Add_rd_gray_dl2 <= 0;\r
- else\r
- Add_rd_gray_dl2 <= Add_rd_gray_dl1;\r
- \r
-always @ (posedge Clk_SYS or posedge Reset)\r
- if (Reset)\r
- Add_rd_jump_wr_pl1 <=0;\r
- else \r
- Add_rd_jump_wr_pl1 <=Add_rd_jump;\r
- \r
-always @ (posedge Clk_SYS or posedge Reset)\r
- if (Reset)\r
- Add_rd_ungray =0;\r
- else if (!Add_rd_jump_wr_pl1) \r
- begin : Add_rd_ungray_loop\r
- integer i;\r
- Add_rd_ungray[TX_FF_DEPTH-1] = Add_rd_gray_dl2[TX_FF_DEPTH-1];\r
- for (i=TX_FF_DEPTH-2;i>=0;i=i-1)\r
- Add_rd_ungray[i] = Add_rd_ungray[i+1]^Add_rd_gray_dl2[i];\r
- end\r
-\r
-assign Add_wr_pluse =Add_wr+1;\r
-assign Add_wr_pluse_pluse =Add_wr+4;\r
-\r
-always @ (Add_wr_pluse or Add_rd_ungray)\r
- if (Add_wr_pluse==Add_rd_ungray)\r
- Full =1;\r
- else\r
- Full =0;\r
-\r
-always @ (posedge Clk_SYS or posedge Reset)\r
- if (Reset)\r
- AlmostFull <=0;\r
- else if (Add_wr_pluse_pluse==Add_rd_ungray)\r
- AlmostFull <=1;\r
- else\r
- AlmostFull <=0;\r
- \r
-always @ (posedge Clk_SYS or posedge Reset)\r
- if (Reset)\r
- Add_wr <= 0;\r
- else if (Wr_en&&!Full)\r
- Add_wr <= Add_wr +1;\r
- \r
-always @ (posedge Clk_SYS or posedge Reset)\r
- if (Reset)\r
- begin\r
- Packet_number_sub_dl1 <=0;\r
- Packet_number_sub_dl2 <=0;\r
- end\r
- else \r
- begin\r
- Packet_number_sub_dl1 <=Pkt_sub_apply;\r
- Packet_number_sub_dl2 <=Packet_number_sub_dl1;\r
- end\r
- \r
-always @ (posedge Clk_SYS or posedge Reset)\r
- if (Reset)\r
- Packet_number_sub_edge <=0;\r
- else if (Packet_number_sub_dl1&!Packet_number_sub_dl2)\r
- Packet_number_sub_edge <=1;\r
- else\r
- Packet_number_sub_edge <=0;\r
-\r
-always @ (posedge Clk_SYS or posedge Reset)\r
- if (Reset)\r
- Packet_number_add <=0; \r
- else if (Current_state_SYS==SYS_EOP_ok||Current_state_SYS==SYS_EOP_err)\r
- Packet_number_add <=1;\r
- else\r
- Packet_number_add <=0; \r
- \r
-\r
-always @ (posedge Clk_SYS or posedge Reset)\r
- if (Reset)\r
- Packet_number_inFF <=0;\r
- else if (Packet_number_add&&!Packet_number_sub_edge)\r
- Packet_number_inFF <=Packet_number_inFF + 1'b1;\r
- else if (!Packet_number_add&&Packet_number_sub_edge)\r
- Packet_number_inFF <=Packet_number_inFF - 1'b1;\r
-\r
-\r
-always @ (posedge Clk_SYS or posedge Reset)\r
- if (Reset)\r
- Packet_number_inFF_reg <=0;\r
- else\r
- Packet_number_inFF_reg <=Packet_number_inFF;\r
-\r
-always @ (posedge Clk_SYS or posedge Reset)\r
- if (Reset)\r
- begin\r
- Add_rd_reg_rdy_dl1 <=0;\r
- Add_rd_reg_rdy_dl2 <=0;\r
- end\r
- else\r
- begin\r
- Add_rd_reg_rdy_dl1 <=Add_rd_reg_rdy;\r
- Add_rd_reg_rdy_dl2 <=Add_rd_reg_rdy_dl1;\r
- end \r
-\r
-always @ (posedge Clk_SYS or posedge Reset)\r
- if (Reset)\r
- Add_rd_reg_dl1 <=0;\r
- else if (Add_rd_reg_rdy_dl1&!Add_rd_reg_rdy_dl2)\r
- Add_rd_reg_dl1 <=Add_rd_reg[TX_FF_DEPTH-1:TX_FF_DEPTH-5];\r
-\r
-\r
-\r
-always @ (posedge Clk_SYS or posedge Reset)\r
- if (Reset)\r
- Fifo_data_count <=0;\r
- else if (FullDuplex)\r
- Fifo_data_count <=Add_wr[TX_FF_DEPTH-1:TX_FF_DEPTH-5]-Add_rd_ungray[TX_FF_DEPTH-1:TX_FF_DEPTH-5];\r
- else\r
- Fifo_data_count <=Add_wr[TX_FF_DEPTH-1:TX_FF_DEPTH-5]-Add_rd_reg_dl1[TX_FF_DEPTH-1:TX_FF_DEPTH-5]; //for half duplex backoff requirement\r
- \r
-\r
-always @ (posedge Clk_SYS or posedge Reset)\r
- if (Reset)\r
- Fifo_ra_tmp <=0; \r
- else if (Packet_number_inFF_reg>=1||Fifo_data_count>=Tx_Lwmark)\r
- Fifo_ra_tmp <=1; \r
- else \r
- Fifo_ra_tmp <=0;\r
-\r
-always @ (posedge Clk_SYS or posedge Reset)\r
- if (Reset)\r
- begin \r
- Tx_Hwmark_pl <=0;\r
- Tx_Lwmark_pl <=0; \r
- end\r
- else\r
- begin \r
- Tx_Hwmark_pl <=Tx_Hwmark;\r
- Tx_Lwmark_pl <=Tx_Lwmark; \r
- end \r
- \r
-always @ (posedge Clk_SYS or posedge Reset)\r
- if (Reset)\r
- Tx_mac_wa <=0; \r
- else if (Fifo_data_count>=Tx_Hwmark_pl)\r
- Tx_mac_wa <=0;\r
- else if (Fifo_data_count<Tx_Lwmark_pl)\r
- Tx_mac_wa <=1;\r
-\r
-//******************************************************************************\r
-//rd data to from FF .\r
-//domain Clk_MAC\r
-//******************************************************************************\r
-reg[35:0] Dout_dl1;\r
-\r
-always @ (posedge Clk_MAC or posedge Reset)\r
- if (Reset)\r
- Dout_dl1 <=0;\r
- else\r
- Dout_dl1 <=Dout;\r
-\r
-always @ (Current_state_MAC or Next_state_MAC)\r
- if ((Current_state_MAC==MAC_idle||Current_state_MAC==MAC_byte0)&&Next_state_MAC==MAC_byte3)\r
- Dout_reg_en =1;\r
- else\r
- Dout_reg_en =0; \r
- \r
-always @ (posedge Clk_MAC or posedge Reset)\r
- if (Reset)\r
- Dout_reg <=0;\r
- else if (Dout_reg_en)\r
- Dout_reg <=Dout_dl1; \r
- \r
-assign {Dout_eop,Dout_err,Dout_BE,Dout_data}=Dout_reg;\r
-\r
-always @ (posedge Clk_MAC or posedge Reset)\r
- if (Reset)\r
- Current_state_MAC <=MAC_idle;\r
- else\r
- Current_state_MAC <=Next_state_MAC; \r
- \r
-always @ (Current_state_MAC or Fifo_rd or Dout_BE or Dout_eop or Fifo_rd_retry\r
- or Fifo_rd_finish or Empty or Fifo_rd or Fifo_eop)\r
- case (Current_state_MAC)\r
- MAC_idle:\r
- if (Empty&&Fifo_rd)\r
- Next_state_MAC=MAC_FF_Err;\r
- else if (Fifo_rd)\r
- Next_state_MAC=MAC_byte3;\r
- else\r
- Next_state_MAC=Current_state_MAC;\r
- MAC_byte3:\r
- if (Fifo_rd_retry)\r
- Next_state_MAC=MAC_retry; \r
- else if (Fifo_eop)\r
- Next_state_MAC=MAC_wait_finish;\r
- else if (Fifo_rd&&!Fifo_eop)\r
- Next_state_MAC=MAC_byte2;\r
- else\r
- Next_state_MAC=Current_state_MAC;\r
- MAC_byte2:\r
- if (Fifo_rd_retry)\r
- Next_state_MAC=MAC_retry;\r
- else if (Fifo_eop)\r
- Next_state_MAC=MAC_wait_finish;\r
- else if (Fifo_rd&&!Fifo_eop)\r
- Next_state_MAC=MAC_byte1;\r
- else\r
- Next_state_MAC=Current_state_MAC; \r
- MAC_byte1:\r
- if (Fifo_rd_retry)\r
- Next_state_MAC=MAC_retry;\r
- else if (Fifo_eop)\r
- Next_state_MAC=MAC_wait_finish;\r
- else if (Fifo_rd&&!Fifo_eop)\r
- Next_state_MAC=MAC_byte0;\r
- else\r
- Next_state_MAC=Current_state_MAC; \r
- MAC_byte0:\r
- if (Empty&&Fifo_rd&&!Fifo_eop)\r
- Next_state_MAC=MAC_FFEmpty;\r
- else if (Fifo_rd_retry)\r
- Next_state_MAC=MAC_retry;\r
- else if (Fifo_eop)\r
- Next_state_MAC=MAC_wait_finish; \r
- else if (Fifo_rd&&!Fifo_eop)\r
- Next_state_MAC=MAC_byte3;\r
- else\r
- Next_state_MAC=Current_state_MAC; \r
- MAC_retry:\r
- Next_state_MAC=MAC_idle;\r
- MAC_wait_finish:\r
- if (Fifo_rd_finish)\r
- Next_state_MAC=MAC_pkt_sub;\r
- else\r
- Next_state_MAC=Current_state_MAC;\r
- MAC_pkt_sub:\r
- Next_state_MAC=MAC_idle;\r
- MAC_FFEmpty:\r
- if (!Empty)\r
- Next_state_MAC=MAC_byte3;\r
- else\r
- Next_state_MAC=Current_state_MAC;\r
- MAC_FF_Err: //stopped state-machine need change \r
- Next_state_MAC=Current_state_MAC;\r
- default\r
- Next_state_MAC=MAC_idle; \r
- endcase\r
-//\r
-always @ (posedge Reset or posedge Clk_MAC)\r
- if (Reset)\r
- Add_rd_gray <=0;\r
- else \r
- begin : Add_rd_gray_loop\r
- integer i;\r
- Add_rd_gray[TX_FF_DEPTH-1] <=Add_rd[TX_FF_DEPTH-1];\r
- for (i=TX_FF_DEPTH-2;i>=0;i=i-1)\r
- Add_rd_gray[i] <= Add_rd[i+1]^Add_rd[i];\r
- end\r
-//\r
-\r
-always @ (posedge Clk_MAC or posedge Reset)\r
- if (Reset)\r
- Add_wr_gray_dl1 <=0;\r
- else\r
- Add_wr_gray_dl1 <=Add_wr_gray;\r
-\r
-always @ (posedge Clk_MAC or posedge Reset)\r
- if (Reset)\r
- Add_wr_gray_dl2 <=0;\r
- else\r
- Add_wr_gray_dl2 <=Add_wr_gray_dl1;\r
- \r
-always @ (posedge Clk_MAC or posedge Reset)\r
- if (Reset)\r
- Add_wr_ungray =0;\r
- else \r
- begin : Add_wr_ungray_loop\r
- integer i;\r
- Add_wr_ungray[TX_FF_DEPTH-1] = Add_wr_gray_dl2[TX_FF_DEPTH-1];\r
- for (i=TX_FF_DEPTH-2;i>=0;i=i-1)\r
- Add_wr_ungray[i] = Add_wr_ungray[i+1]^Add_wr_gray_dl2[i]; \r
- end \r
-\r
-//empty \r
-always @ (posedge Clk_MAC or posedge Reset)\r
- if (Reset) \r
- Empty <=1;\r
- else if (Add_rd==Add_wr_ungray)\r
- Empty <=1;\r
- else\r
- Empty <=0; \r
- \r
-//ra\r
-always @ (posedge Clk_MAC or posedge Reset)\r
- if (Reset)\r
- Fifo_ra <=0;\r
- else\r
- Fifo_ra <=Fifo_ra_tmp;\r
-\r
-\r
-\r
-always @ (posedge Clk_MAC or posedge Reset) \r
- if (Reset) \r
- Pkt_sub_apply_tmp <=0;\r
- else if (Current_state_MAC==MAC_pkt_sub)\r
- Pkt_sub_apply_tmp <=1;\r
- else\r
- Pkt_sub_apply_tmp <=0;\r
- \r
-always @ (posedge Clk_MAC or posedge Reset) \r
- if (Reset)\r
- Pkt_sub_apply <=0;\r
- else if ((Current_state_MAC==MAC_pkt_sub)||Pkt_sub_apply_tmp)\r
- Pkt_sub_apply <=1;\r
- else \r
- Pkt_sub_apply <=0;\r
-\r
-//reg Add_rd for collison retry\r
-always @ (posedge Clk_MAC or posedge Reset)\r
- if (Reset)\r
- Add_rd_reg <=0;\r
- else if (Fifo_rd_finish)\r
- Add_rd_reg <=Add_rd;\r
-\r
-always @ (posedge Clk_MAC or posedge Reset)\r
- if (Reset)\r
- Add_rd_reg_rdy_tmp <=0;\r
- else if (Fifo_rd_finish)\r
- Add_rd_reg_rdy_tmp <=1;\r
- else\r
- Add_rd_reg_rdy_tmp <=0;\r
- \r
-always @ (posedge Clk_MAC or posedge Reset)\r
- if (Reset)\r
- Add_rd_reg_rdy <=0;\r
- else if (Fifo_rd_finish||Add_rd_reg_rdy_tmp)\r
- Add_rd_reg_rdy <=1;\r
- else\r
- Add_rd_reg_rdy <=0; \r
- \r
-\r
-always @ (Current_state_MAC or Next_state_MAC)\r
- if ((Current_state_MAC==MAC_idle||Current_state_MAC==MAC_byte0)&&Next_state_MAC==MAC_byte3)\r
- Add_rd_add =1;\r
- else\r
- Add_rd_add =0;\r
- \r
- \r
-always @ (posedge Clk_MAC or posedge Reset)\r
- if (Reset)\r
- Add_rd <=0;\r
- else if (Current_state_MAC==MAC_retry)\r
- Add_rd <= Add_rd_reg;\r
- else if (Add_rd_add)\r
- Add_rd <= Add_rd + 1; \r
- \r
-always @ (posedge Clk_MAC or posedge Reset)\r
- if (Reset)\r
- Add_rd_jump_tmp <=0;\r
- else if (Current_state_MAC==MAC_retry)\r
- Add_rd_jump_tmp <=1;\r
- else\r
- Add_rd_jump_tmp <=0;\r
-\r
-always @ (posedge Clk_MAC or posedge Reset)\r
- if (Reset)\r
- Add_rd_jump_tmp_pl1 <=0;\r
- else\r
- Add_rd_jump_tmp_pl1 <=Add_rd_jump_tmp; \r
- \r
-always @ (posedge Clk_MAC or posedge Reset)\r
- if (Reset)\r
- Add_rd_jump <=0;\r
- else if (Current_state_MAC==MAC_retry)\r
- Add_rd_jump <=1;\r
- else if (Add_rd_jump_tmp_pl1)\r
- Add_rd_jump <=0; \r
- \r
-//gen Fifo_data \r
-\r
- \r
-always @ (Dout_data or Current_state_MAC)\r
- case (Current_state_MAC)\r
- MAC_byte3:\r
- Fifo_data =Dout_data[31:24];\r
- MAC_byte2:\r
- Fifo_data =Dout_data[23:16];\r
- MAC_byte1:\r
- Fifo_data =Dout_data[15:8];\r
- MAC_byte0:\r
- Fifo_data =Dout_data[7:0];\r
- default:\r
- Fifo_data =0; \r
- endcase\r
- \r
-always @ (posedge Clk_MAC or posedge Reset)\r
- if (Reset)\r
- Fifo_da <=0;\r
- else if ((Current_state_MAC==MAC_byte0||Current_state_MAC==MAC_byte1||\r
- Current_state_MAC==MAC_byte2||Current_state_MAC==MAC_byte3)&&Fifo_rd&&!Fifo_eop)\r
- Fifo_da <=1;\r
- else\r
- Fifo_da <=0;\r
-\r
-//gen Fifo_data_err_empty\r
-assign Fifo_data_err_full=Dout_err;\r
-//gen Fifo_data_err_empty\r
-always @ (posedge Clk_MAC or posedge Reset)\r
- if (Reset)\r
- Current_state_MAC_reg <=0;\r
- else\r
- Current_state_MAC_reg <=Current_state_MAC;\r
- \r
-always @ (posedge Clk_MAC or posedge Reset)\r
- if (Reset)\r
- Fifo_data_err_empty <=0;\r
- else if (Current_state_MAC_reg==MAC_FFEmpty)\r
- Fifo_data_err_empty <=1;\r
- else\r
- Fifo_data_err_empty <=0;\r
- \r
-//always @ (posedge Clk_MAC)\r
-// if (Current_state_MAC_reg==MAC_FF_Err) \r
-// begin\r
-// $finish(2); \r
-// $display("mac_tx_FF meet error status at time :%t",$time);\r
-// end\r
-\r
-//gen Fifo_eop aligned to last valid data byte\r
-always @ ( Current_state_MAC or Dout_eop or Dout_BE )\r
- if ( ( ( Current_state_MAC==MAC_byte0 && Dout_BE==2'b00 ) ||\r
- ( Current_state_MAC==MAC_byte1 && Dout_BE==2'b11 ) ||\r
- ( Current_state_MAC==MAC_byte2 && Dout_BE==2'b10 ) ||\r
- ( Current_state_MAC==MAC_byte3 && Dout_BE==2'b01 ) ) && Dout_eop )\r
- Fifo_eop = 1;\r
- else\r
- Fifo_eop = 0;\r
- \r
- // Dual port RAM for FIFO\r
- ram_2port #(.DWIDTH(36),.AWIDTH(TX_FF_DEPTH)) mac_tx_ff_ram\r
- (.clka(Clk_SYS),.ena(1'b1),.wea(Wr_en),.addra(Add_wr),.dia(Din),.doa(),\r
- .clkb(Clk_MAC),.enb(1'b1),.web(1'b0),.addrb(Add_rd),.dib(36'b0),.dob(Dout) );\r
-\r
- assign debug0 = \r
- { { 5'd0, Empty, Full, AlmostFull },\r
- { Current_state_SYS, Current_state_MAC },\r
- { Fifo_rd, Fifo_rd_finish, Fifo_rd_retry, Fifo_eop, Fifo_da, Fifo_ra, Fifo_data_err_empty, Fifo_data_err_full },\r
- { 2'b0, Dout_BE, Tx_mac_wa, Tx_mac_wr, Tx_mac_sop, Tx_mac_eop} };\r
- \r
- assign debug1 = \r
- { { 8'd0 },\r
- { 8'd0 },\r
- { 8'd0 },\r
- { 8'd0 } };\r
- \r
-endmodule // MAC_tx_FF\r
+++ /dev/null
-// ////////////////////////////////////////////////////////////////////\r
-// // ////\r
-// // MAC_tx_addr_add.v ////\r
-// // ////\r
-// // This file is part of the Ethernet IP core project ////\r
-// // http://www.opencores.org/projects.cgi/wr_en/ethernet_tri_mode/////\r
-// // ////\r
-// // Author(s): ////\r
-// // - Jon Gao (gaojon@yahoo.com) ////\r
-// // ////\r
-// // ////\r
-// ////////////////////////////////////////////////////////////////////\r
-// // ////\r
-// // Copyright (C) 2001 Authors ////\r
-// // ////\r
-// // This source file may be used and distributed without ////\r
-// // restriction provided that this copyright statement is not ////\r
-// // removed from the file and that any derivative work contains ////\r
-// // the original copyright notice and the associated disclaimer. ////\r
-// // ////\r
-// // This source file is free software; you can redistribute it ////\r
-// // and/or modify it under the terms of the GNU Lesser General ////\r
-// // Public License as published by the Free Software Foundation; ////\r
-// // either version 2.1 of the License, or (at your option) any ////\r
-// // later version. ////\r
-// // ////\r
-// // This source is distributed in the hope that it will be ////\r
-// // useful, but WITHOUT ANY WARRANTY; without even the implied ////\r
-// // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\r
-// // PURPOSE. See the GNU Lesser General Public License for more ////\r
-// // details. ////\r
-// // ////\r
-// // You should have received a copy of the GNU Lesser General ////\r
-// // Public License along with this source; if not, download it ////\r
-// // from http://www.opencores.org/lgpl.shtml ////\r
-// // ////\r
-// ////////////////////////////////////////////////////////////////////\r
-// \r
-// CVS Revision History \r
-// \r
-// $Log: MAC_tx_addr_add.v,v $\r
-// Revision 1.3 2006/01/19 14:07:54 maverickist\r
-// verification is complete.\r
-//\r
-// Revision 1.2 2005/12/16 06:44:18 Administrator\r
-// replaced tab with space.\r
-// passed 9.6k length frame test.\r
-//\r
-// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator\r
-// no message\r
-// \r
-\r
-module MAC_tx_addr_add \r
- (Reset ,\r
- Clk ,\r
- MAC_tx_addr_init ,\r
- MAC_tx_addr_rd ,\r
- MAC_tx_addr_data ,\r
- //CPU ,\r
- MAC_add_prom_data ,\r
- MAC_add_prom_add ,\r
- MAC_add_prom_wr \r
- );\r
- \r
- input Reset ;\r
- input Clk ;\r
- input MAC_tx_addr_rd ;\r
- input MAC_tx_addr_init ;\r
- output [7:0] MAC_tx_addr_data ;\r
- //CPU ;\r
- input [7:0] MAC_add_prom_data ;\r
- input [2:0] MAC_add_prom_add ;\r
- input MAC_add_prom_wr ;\r
- \r
- // ****************************************************************************** \r
- // internal signals \r
- // ******************************************************************************\r
- reg [2:0] add_rd;\r
- wire [2:0] add_wr;\r
- wire [7:0] din;\r
- //wire [7:0] dout;\r
- reg [7:0] dout;\r
- wire wr_en;\r
- reg MAC_add_prom_wr_dl1;\r
- reg MAC_add_prom_wr_dl2;\r
- // ****************************************************************************** \r
- // write data from cpu to prom \r
- // ******************************************************************************\r
- always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- begin\r
- MAC_add_prom_wr_dl1 <=0;\r
- MAC_add_prom_wr_dl2 <=0;\r
- end\r
- else\r
- begin\r
- MAC_add_prom_wr_dl1 <=MAC_add_prom_wr;\r
- MAC_add_prom_wr_dl2 <=MAC_add_prom_wr_dl1;\r
- end \r
- \r
- assign wr_en =MAC_add_prom_wr_dl1&!MAC_add_prom_wr_dl2;\r
- assign add_wr =MAC_add_prom_add;\r
- assign din =MAC_add_prom_data;\r
- \r
- // ****************************************************************************** \r
- // read data from cpu to prom \r
- // ******************************************************************************\r
- always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- add_rd <=0;\r
- else if (MAC_tx_addr_init)\r
- add_rd <=0;\r
- else if (MAC_tx_addr_rd)\r
- add_rd <=add_rd + 1;\r
- assign MAC_tx_addr_data=dout; \r
- // ****************************************************************************** \r
- // b port for read ,a port for write .\r
- // ******************************************************************************\r
- \r
- reg [7:0] address_ram [0:7];\r
- always @(posedge Clk)\r
- if(wr_en)\r
- address_ram[add_wr] <= din;\r
-\r
- always @(posedge Clk)\r
- dout <= address_ram[add_rd];\r
-\r
-endmodule // MAC_tx_addr_add\r
+++ /dev/null
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// MAC_tx_ctrl.v ////\r
-//// ////\r
-//// This file is part of the Ethernet IP core project ////\r
-//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////\r
-//// ////\r
-//// Author(s): ////\r
-//// - Jon Gao (gaojon@yahoo.com) ////\r
-//// ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// Copyright (C) 2001 Authors ////\r
-//// ////\r
-//// This source file may be used and distributed without ////\r
-//// restriction provided that this copyright statement is not ////\r
-//// removed from the file and that any derivative work contains ////\r
-//// the original copyright notice and the associated disclaimer. ////\r
-//// ////\r
-//// This source file is free software; you can redistribute it ////\r
-//// and/or modify it under the terms of the GNU Lesser General ////\r
-//// Public License as published by the Free Software Foundation; ////\r
-//// either version 2.1 of the License, or (at your option) any ////\r
-//// later version. ////\r
-//// ////\r
-//// This source is distributed in the hope that it will be ////\r
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\r
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\r
-//// PURPOSE. See the GNU Lesser General Public License for more ////\r
-//// details. ////\r
-//// ////\r
-//// You should have received a copy of the GNU Lesser General ////\r
-//// Public License along with this source; if not, download it ////\r
-//// from http://www.opencores.org/lgpl.shtml ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-// \r
-// CVS Revision History \r
-// \r
-// $Log: MAC_tx_Ctrl.v,v $\r
-// Revision 1.4 2006/06/25 04:58:56 maverickist\r
-// no message\r
-//\r
-// Revision 1.3 2006/01/19 14:07:54 maverickist\r
-// verification is complete.\r
-//\r
-// Revision 1.3 2005/12/16 06:44:17 Administrator\r
-// replaced tab with space.\r
-// passed 9.6k length frame test.\r
-//\r
-// Revision 1.2 2005/12/13 12:15:38 Administrator\r
-// no message\r
-//\r
-// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator\r
-// no message\r
-// \r
-\r
-module MAC_tx_ctrl ( \r
-Reset ,\r
-Clk ,\r
-//CRC_gen Interface \r
-CRC_init ,\r
-Frame_data ,\r
-Data_en ,\r
-CRC_rd ,\r
-CRC_end ,\r
-CRC_out ,\r
-//Ramdon_gen interfac\r
-Random_init ,\r
-RetryCnt ,\r
-Random_time_meet ,\r
-//flow control \r
-pause_apply ,\r
-pause_quanta_sub ,\r
-xoff_gen ,\r
-xoff_gen_complete ,\r
-xon_gen ,\r
-xon_gen_complete ,\r
-//MAC_tx_FF \r
-Fifo_data ,\r
-Fifo_rd ,\r
-Fifo_eop ,\r
-Fifo_da ,\r
-Fifo_rd_finish ,\r
-Fifo_rd_retry ,\r
-Fifo_ra ,\r
-Fifo_data_err_empty ,\r
-Fifo_data_err_full ,\r
-//RMII \r
-TxD ,\r
-TxEn ,\r
-CRS , \r
-//MAC_tx_addr_add \r
-MAC_tx_addr_rd ,\r
-MAC_tx_addr_data ,\r
-MAC_tx_addr_init ,\r
-//RMON \r
-Tx_pkt_type_rmon ,\r
-Tx_pkt_length_rmon ,\r
-Tx_apply_rmon ,\r
-Tx_pkt_err_type_rmon,\r
-//CPU \r
-pause_quanta_set , \r
-MAC_tx_add_en , \r
-FullDuplex ,\r
-MaxRetry ,\r
-IFGset \r
-);\r
-\r
-input Reset ;\r
-input Clk ;\r
- //CRC_gen Interface \r
-output CRC_init ;\r
-output [7:0] Frame_data ;\r
-output Data_en ;\r
-output CRC_rd ;\r
-input CRC_end ;\r
-input [7:0] CRC_out ;\r
- //Ramdon_gen interface\r
-output Random_init ;\r
-output [3:0] RetryCnt ;\r
-input Random_time_meet ;//levle hight indicate random time passed away\r
- //flow control\r
-input pause_apply ;\r
-output pause_quanta_sub ;\r
-input xoff_gen ;\r
-output xoff_gen_complete ;\r
-input xon_gen ;\r
-output xon_gen_complete ; \r
- //MAC_rx_FF\r
-input [7:0] Fifo_data ;\r
-output Fifo_rd ;\r
-input Fifo_eop ;\r
-input Fifo_da ;\r
-output Fifo_rd_finish ;\r
-output Fifo_rd_retry ;\r
-input Fifo_ra ;\r
-input Fifo_data_err_empty ;\r
-input Fifo_data_err_full ;\r
- //RMII\r
-output [7:0] TxD ;\r
-output TxEn ; \r
-input CRS ;\r
- //MAC_tx_addr_add\r
-output MAC_tx_addr_init ;\r
-output MAC_tx_addr_rd ;\r
-input [7:0] MAC_tx_addr_data ;\r
- //RMON\r
-output [2:0] Tx_pkt_type_rmon ;\r
-output [15:0] Tx_pkt_length_rmon ;\r
-output Tx_apply_rmon ;\r
-output [2:0] Tx_pkt_err_type_rmon; \r
- //CPU\r
-input [15:0] pause_quanta_set ;\r
-input MAC_tx_add_en ; \r
-input FullDuplex ;\r
-input [3:0] MaxRetry ;\r
-input [5:0] IFGset ;\r
-//****************************************************************************** \r
-//internal signals \r
-//****************************************************************************** \r
-parameter StateIdle =4'd00;\r
-parameter StatePreamble =4'd01;\r
-parameter StateSFD =4'd02;\r
-parameter StateData =4'd03;\r
-parameter StatePause =4'd04;\r
-parameter StatePAD =4'd05;\r
-parameter StateFCS =4'd06;\r
-parameter StateIFG =4'd07;\r
-parameter StateJam =4'd08;\r
-parameter StateBackOff =4'd09;\r
-parameter StateJamDrop =4'd10;\r
-parameter StateFFEmptyDrop =4'd11;\r
-parameter StateSwitchNext =4'd12;\r
-parameter StateDefer =4'd13;\r
-parameter StateSendPauseFrame =4'd14;\r
-\r
-reg [3:0] Current_state;\r
-reg [3:0] Next_state;\r
-reg [5:0] IFG_counter;\r
-reg [4:0] Preamble_counter;//\r
-reg [7:0] TxD_tmp ; \r
-reg TxEn_tmp ; \r
-reg [15:0] Tx_pkt_length_rmon ;\r
-reg Tx_apply_rmon ;\r
-reg [2:0] Tx_pkt_err_type_rmon; \r
-reg [3:0] RetryCnt ;\r
-reg Random_init ;\r
-reg Fifo_rd_finish ;\r
-reg Fifo_rd_retry ;\r
-reg [7:0] TxD ; \r
-reg TxEn ; \r
-reg CRC_init ;\r
-reg Data_en ;\r
-reg CRC_rd ;\r
-reg Fifo_rd ;\r
-reg MAC_tx_addr_rd ;\r
-reg MAC_header_slot ;\r
-reg MAC_header_slot_tmp ;\r
-reg [2:0] Tx_pkt_type_rmon ;\r
-wire Collision ; \r
-reg MAC_tx_addr_init ;\r
-reg Src_MAC_ptr ;\r
-reg [7:0] IPLengthCounter ;//for pad append\r
-reg [1:0] PADCounter ;\r
-reg [7:0] JamCounter ;\r
-reg PktDrpEvenPtr ;\r
-reg [7:0] pause_counter ;\r
-reg pause_quanta_sub ;\r
-reg [15:0] pause_quanta_set_dl1 ;\r
-reg xoff_gen_complete ;\r
-reg xon_gen_complete ;\r
-//****************************************************************************** \r
-//boundery signal processing \r
-//****************************************************************************** \r
-always @(posedge Clk or posedge Reset)\r
- if (Reset)\r
- begin \r
- pause_quanta_set_dl1 <=0;\r
- end\r
- else\r
- begin \r
- pause_quanta_set_dl1 <=pause_quanta_set ;\r
- end \r
-//****************************************************************************** \r
-//state machine \r
-//****************************************************************************** \r
-assign Collision=TxEn&CRS;\r
-\r
-always @(posedge Clk or posedge Reset)\r
- if (Reset)\r
- IPLengthCounter <=0;\r
- else if (Current_state==StateDefer)\r
- IPLengthCounter <=0; \r
- else if (IPLengthCounter!=8'hff&&(Current_state==StateData||Current_state==StateSendPauseFrame||Current_state==StatePAD))\r
- IPLengthCounter <=IPLengthCounter+1;\r
-\r
-always @(posedge Clk or posedge Reset)\r
- if (Reset)\r
- PADCounter <=0;\r
- else if (Current_state!=StatePAD)\r
- PADCounter <=0;\r
- else\r
- PADCounter <=PADCounter+1;\r
-\r
-always @(posedge Clk or posedge Reset)\r
- if (Reset)\r
- Current_state <=StateDefer;\r
- else \r
- Current_state <=Next_state; \r
- \r
-always @ (*)\r
- case (Current_state) \r
- StateDefer:\r
- if ((FullDuplex)||(!FullDuplex&&!CRS))\r
- Next_state=StateIFG;\r
- else\r
- Next_state=Current_state; \r
- StateIFG:\r
- if (!FullDuplex&&CRS)\r
- Next_state=StateDefer;\r
- else if ((FullDuplex&&IFG_counter==IFGset-4)||(!FullDuplex&&!CRS&&IFG_counter==IFGset-4))//remove some additional time\r
- Next_state=StateIdle;\r
- else\r
- Next_state=Current_state; \r
- StateIdle:\r
- if (!FullDuplex&&CRS)\r
- Next_state=StateDefer;\r
- else if (xoff_gen||xon_gen)\r
- Next_state=StatePreamble;\r
- else if (pause_apply)\r
- Next_state=StatePause; \r
- else if ((FullDuplex||~CRS)&&Fifo_ra)\r
- Next_state=StatePreamble;\r
- else\r
- Next_state=Current_state; \r
- StatePause:\r
- if (pause_counter==512/8)\r
- Next_state=StateDefer;\r
- else if (xoff_gen||xon_gen)\r
- Next_state=StateIdle;\r
- else\r
- Next_state=Current_state; \r
- StatePreamble:\r
- if (!FullDuplex&&Collision)\r
- Next_state=StateJam;\r
- else if ((FullDuplex&&Preamble_counter==6)||(!FullDuplex&&!Collision&&Preamble_counter==6))\r
- Next_state=StateSFD;\r
- else\r
- Next_state=Current_state;\r
- StateSFD:\r
- if (!FullDuplex&&Collision)\r
- Next_state=StateJam;\r
- else if (xoff_gen||xon_gen)\r
- Next_state=StateSendPauseFrame;\r
- else \r
- Next_state=StateData;\r
- StateSendPauseFrame:\r
- if (IPLengthCounter==17)\r
- Next_state=StatePAD;\r
- else\r
- Next_state=Current_state;\r
- StateData:\r
- if (!FullDuplex&&Collision)\r
- Next_state=StateJam;\r
- else if (Fifo_data_err_empty)\r
- Next_state=StateFFEmptyDrop; \r
- else if (Fifo_eop&&IPLengthCounter>=59)//IP+MAC+TYPE=60 ,start from 0\r
- Next_state=StateFCS;\r
- else if (Fifo_eop)\r
- Next_state=StatePAD;\r
- else \r
- Next_state=StateData; \r
- StatePAD:\r
- if (!FullDuplex&&Collision)\r
- Next_state=StateJam; \r
- else if (IPLengthCounter>=59)\r
- Next_state=StateFCS; \r
- else \r
- Next_state=Current_state;\r
- StateJam:\r
- if (RetryCnt<=MaxRetry&&JamCounter==16) \r
- Next_state=StateBackOff;\r
- else if (RetryCnt>MaxRetry)\r
- Next_state=StateJamDrop;\r
- else\r
- Next_state=Current_state;\r
- StateBackOff:\r
- if (Random_time_meet)\r
- Next_state =StateDefer;\r
- else \r
- Next_state =Current_state;\r
- StateFCS:\r
- if (!FullDuplex&&Collision)\r
- Next_state =StateJam;\r
- else if (CRC_end)\r
- Next_state =StateSwitchNext;\r
- else\r
- Next_state =Current_state;\r
- StateFFEmptyDrop:\r
- if (Fifo_eop)\r
- Next_state =StateSwitchNext;\r
- else\r
- Next_state =Current_state; \r
- StateJamDrop:\r
- if (Fifo_eop)\r
- Next_state =StateSwitchNext;\r
- else\r
- Next_state =Current_state;\r
- StateSwitchNext:\r
- Next_state =StateDefer; \r
- default:\r
- Next_state =StateDefer;\r
- endcase\r
-\r
- \r
- \r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- JamCounter <=0;\r
- else if (Current_state!=StateJam)\r
- JamCounter <=0;\r
- else if (Current_state==StateJam)\r
- JamCounter <=JamCounter+1;\r
- \r
- \r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- RetryCnt <=0;\r
- else if (Current_state==StateSwitchNext)\r
- RetryCnt <=0;\r
- else if (Current_state==StateJam&&Next_state==StateBackOff)\r
- RetryCnt <=RetryCnt + 1;\r
- \r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- IFG_counter <=0;\r
- else if (Current_state!=StateIFG)\r
- IFG_counter <=0;\r
- else \r
- IFG_counter <=IFG_counter + 1;\r
-\r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- Preamble_counter <=0;\r
- else if (Current_state!=StatePreamble)\r
- Preamble_counter <=0;\r
- else\r
- Preamble_counter <=Preamble_counter+ 1;\r
- \r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset) \r
- PktDrpEvenPtr <=0;\r
- else if(Current_state==StateJamDrop||Current_state==StateFFEmptyDrop)\r
- PktDrpEvenPtr <=~PktDrpEvenPtr;\r
-//****************************************************************************** \r
-//generate output signals \r
-//****************************************************************************** \r
-//CRC related\r
-always @(Current_state)\r
- if (Current_state==StateSFD)\r
- CRC_init =1;\r
- else\r
- CRC_init =0;\r
- \r
-assign Frame_data=TxD_tmp;\r
-\r
-always @(Current_state)\r
- if (Current_state==StateData||Current_state==StateSendPauseFrame||Current_state==StatePAD)\r
- Data_en =1;\r
- else\r
- Data_en =0;\r
- \r
-always @(Current_state)\r
- if (Current_state==StateFCS)\r
- CRC_rd =1;\r
- else\r
- CRC_rd =0; \r
- \r
-//Ramdon_gen interface\r
-always @(Current_state or Next_state)\r
- if (Current_state==StateJam&&Next_state==StateBackOff)\r
- Random_init =1;\r
- else\r
- Random_init =0; \r
-\r
-//MAC_rx_FF\r
-//data have one cycle delay after fifo read signals \r
-always @ (*)\r
- if (Current_state==StateData ||\r
- Current_state==StateSFD&&!(xoff_gen||xon_gen) ||\r
- Current_state==StateJamDrop&&PktDrpEvenPtr||\r
- Current_state==StateFFEmptyDrop&&PktDrpEvenPtr )\r
- Fifo_rd =1;\r
- else\r
- Fifo_rd =0; \r
- \r
-always @ (Current_state)\r
- if (Current_state==StateSwitchNext) \r
- Fifo_rd_finish =1;\r
- else\r
- Fifo_rd_finish =0;\r
- \r
-always @ (Current_state)\r
- if (Current_state==StateJam) \r
- Fifo_rd_retry =1;\r
- else\r
- Fifo_rd_retry =0; \r
-//RMII\r
-always @(Current_state)\r
- if (Current_state==StatePreamble||Current_state==StateSFD||\r
- Current_state==StateData||Current_state==StateSendPauseFrame||\r
- Current_state==StateFCS||Current_state==StatePAD||Current_state==StateJam)\r
- TxEn_tmp =1;\r
- else\r
- TxEn_tmp =0;\r
-\r
-//gen txd data \r
-always @(*)\r
- case (Current_state)\r
- StatePreamble:\r
- TxD_tmp =8'h55;\r
- StateSFD:\r
- TxD_tmp =8'hd5;\r
- StateData:\r
- if (Src_MAC_ptr&&MAC_tx_add_en) \r
- TxD_tmp =MAC_tx_addr_data;\r
- else\r
- TxD_tmp =Fifo_data;\r
- StateSendPauseFrame:\r
- if (Src_MAC_ptr&&MAC_tx_add_en) \r
- TxD_tmp =MAC_tx_addr_data;\r
- else \r
- case (IPLengthCounter)\r
- 8'd0: TxD_tmp =8'h01;\r
- 8'd1: TxD_tmp =8'h80;\r
- 8'd2: TxD_tmp =8'hc2;\r
- 8'd3: TxD_tmp =8'h00;\r
- 8'd4: TxD_tmp =8'h00;\r
- 8'd5: TxD_tmp =8'h01;\r
- 8'd12: TxD_tmp =8'h88;//type\r
- 8'd13: TxD_tmp =8'h08;//\r
- 8'd14: TxD_tmp =8'h00;//opcode\r
- 8'd15: TxD_tmp =8'h01;\r
- 8'd16: TxD_tmp =xon_gen?8'b0:pause_quanta_set_dl1[15:8];\r
- 8'd17: TxD_tmp =xon_gen?8'b0:pause_quanta_set_dl1[7:0];\r
-// 8'd60: TxD_tmp =8'h26;\r
-// 8'd61: TxD_tmp =8'h6b;\r
-// 8'd62: TxD_tmp =8'hae;\r
-// 8'd63: TxD_tmp =8'h0a;\r
- default:TxD_tmp =0;\r
- endcase\r
- \r
- StatePAD:\r
- TxD_tmp =8'h00; \r
- StateJam:\r
- TxD_tmp =8'h01; //jam sequence\r
- StateFCS:\r
- TxD_tmp =CRC_out;\r
- default:\r
- TxD_tmp =2'b0;\r
- endcase\r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- begin\r
- TxD <=0;\r
- TxEn <=0;\r
- end\r
- else\r
- begin\r
- TxD <=TxD_tmp;\r
- TxEn <=TxEn_tmp;\r
- end \r
-//RMON\r
-\r
-\r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- Tx_pkt_length_rmon <=0;\r
- else if (Current_state==StateSFD)\r
- Tx_pkt_length_rmon <=0;\r
- else if (Current_state==StateData||Current_state==StateSendPauseFrame||Current_state==StatePAD||Current_state==StateFCS)\r
- Tx_pkt_length_rmon <=Tx_pkt_length_rmon+1;\r
- \r
-\r
-reg [2:0] Tx_apply_rmon_reg;\r
-\r
-always @( posedge Clk or posedge Reset )\r
- if ( Reset )\r
- begin\r
- Tx_apply_rmon <= 0;\r
- Tx_apply_rmon_reg <= 'b0;\r
- end\r
- else\r
- begin\r
- if ( (Fifo_eop&&Current_state==StateJamDrop) ||\r
- (Fifo_eop&&Current_state==StateFFEmptyDrop) ||\r
- CRC_end )\r
- Tx_apply_rmon <= 1;\r
- else\r
- if ( Tx_apply_rmon_reg[2] )\r
- Tx_apply_rmon <= 0;\r
-\r
- Tx_apply_rmon_reg <= { Tx_apply_rmon_reg[1:0], Tx_apply_rmon };\r
- end\r
-\r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- Tx_pkt_err_type_rmon <=0; \r
- else if(Fifo_eop&&Current_state==StateJamDrop)\r
- Tx_pkt_err_type_rmon <=3'b001;//\r
- else if(Fifo_eop&&Current_state==StateFFEmptyDrop)\r
- Tx_pkt_err_type_rmon <=3'b010;//underflow\r
- else if(Fifo_eop&&Fifo_data_err_full)\r
- Tx_pkt_err_type_rmon <=3'b011;//overflow\r
- else if(CRC_end)\r
- Tx_pkt_err_type_rmon <=3'b100;//normal\r
- \r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- MAC_header_slot_tmp <=0;\r
- else if(Current_state==StateSFD&&Next_state==StateData)\r
- MAC_header_slot_tmp <=1; \r
- else\r
- MAC_header_slot_tmp <=0;\r
- \r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- MAC_header_slot <=0;\r
- else \r
- MAC_header_slot <=MAC_header_slot_tmp;\r
-\r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- Tx_pkt_type_rmon <=0;\r
- else if (Current_state==StateSendPauseFrame)\r
- Tx_pkt_type_rmon <=3'b100;\r
- else if(MAC_header_slot)\r
- Tx_pkt_type_rmon <={1'b0,TxD[7:6]};\r
-\r
- \r
-always @(Tx_pkt_length_rmon)\r
- if (Tx_pkt_length_rmon>=6&&Tx_pkt_length_rmon<=11)\r
- Src_MAC_ptr =1;\r
- else\r
- Src_MAC_ptr =0; \r
-\r
-//MAC_tx_addr_add \r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- MAC_tx_addr_rd <=0;\r
- else if ((Tx_pkt_length_rmon>=4&&Tx_pkt_length_rmon<=9)&&(MAC_tx_add_en||Current_state==StateSendPauseFrame))\r
- MAC_tx_addr_rd <=1;\r
- else\r
- MAC_tx_addr_rd <=0;\r
-\r
- always @*\r
- //if ((Tx_pkt_length_rmon==3)&&Fifo_rd)\r
- if (Current_state==StatePreamble)\r
- MAC_tx_addr_init=1;\r
- else\r
- MAC_tx_addr_init=0;\r
-\r
-//**************************************************************************************************************\r
-// CFH: this implementation delays the time it sends an entire Ethernet frame with 512 bits for every pause\r
-// request of 512 bits. Actually, it should only delay the time it takes to transmit 512 bits, not counting\r
-// Ethernet header, CRC, Interframe Gap etc.\r
-// Hence the current implementation waits longer than the pause frame actually requests (~20% more)\r
-//**************************************************************************************************************\r
-\r
-//flow control\r
-always @(posedge Clk or posedge Reset)\r
- if (Reset)\r
- pause_counter <=0;\r
- else if (Current_state!=StatePause)\r
- pause_counter <=0;\r
- else \r
- pause_counter <=pause_counter+1;\r
- \r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- pause_quanta_sub <=0;\r
- else if(pause_counter==512/8)\r
- pause_quanta_sub <=1;\r
- else\r
- pause_quanta_sub <=0;\r
-\r
-// FIXME The below probably won't work if the pause request comes when we are in the wrong state\r
- reg clear_xonxoff;\r
- always @(posedge Clk or posedge Reset)\r
- if(Reset)\r
- clear_xonxoff <= 0;\r
- else if((Current_state==StateSendPauseFrame) & (IPLengthCounter==17))\r
- clear_xonxoff <= 1;\r
- else if(~xon_gen & ~xoff_gen)\r
- clear_xonxoff <= 0;\r
- \r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset) \r
- xoff_gen_complete <=0;\r
- else if(clear_xonxoff & xoff_gen)\r
- xoff_gen_complete <=1;\r
- else\r
- xoff_gen_complete <=0;\r
- \r
- \r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset) \r
- xon_gen_complete <=0;\r
- else if(clear_xonxoff & xon_gen)\r
- xon_gen_complete <=1;\r
- else\r
- xon_gen_complete <=0;\r
-\r
-endmodule\r
+++ /dev/null
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// Random_gen.v ////\r
-//// ////\r
-//// This file is part of the Ethernet IP core project ////\r
-//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////\r
-//// ////\r
-//// Author(s): ////\r
-//// - Jon Gao (gaojon@yahoo.com) ////\r
-//// ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// Copyright (C) 2001 Authors ////\r
-//// ////\r
-//// This source file may be used and distributed without ////\r
-//// restriction provided that this copyright statement is not ////\r
-//// removed from the file and that any derivative work contains ////\r
-//// the original copyright notice and the associated disclaimer. ////\r
-//// ////\r
-//// This source file is free software; you can redistribute it ////\r
-//// and/or modify it under the terms of the GNU Lesser General ////\r
-//// Public License as published by the Free Software Foundation; ////\r
-//// either version 2.1 of the License, or (at your option) any ////\r
-//// later version. ////\r
-//// ////\r
-//// This source is distributed in the hope that it will be ////\r
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\r
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\r
-//// PURPOSE. See the GNU Lesser General Public License for more ////\r
-//// details. ////\r
-//// ////\r
-//// You should have received a copy of the GNU Lesser General ////\r
-//// Public License along with this source; if not, download it ////\r
-//// from http://www.opencores.org/lgpl.shtml ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-\r
-module Random_gen( \r
-Reset ,\r
-Clk ,\r
-Init ,\r
-RetryCnt ,\r
-Random_time_meet\r
-);\r
-input Reset ;\r
-input Clk ;\r
-input Init ;\r
-input [3:0] RetryCnt ;\r
-output Random_time_meet; \r
-\r
-//******************************************************************************\r
-//internal signals \r
-//******************************************************************************\r
-reg [9:0] Random_sequence ;\r
-reg [9:0] Random ;\r
-reg [9:0] Random_counter ;\r
-reg [7:0] Slot_time_counter; //256*2=512bit=1 slot time\r
-reg Random_time_meet;\r
-\r
-//******************************************************************************\r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- Random_sequence <=0;\r
- else\r
- Random_sequence <={Random_sequence[8:0],~(Random_sequence[2]^Random_sequence[9])};\r
- \r
-always @ (RetryCnt or Random_sequence)\r
- case (RetryCnt)\r
- 4'h0 : Random={9'b0,Random_sequence[0]};\r
- 4'h1 : Random={8'b0,Random_sequence[1:0]}; \r
- 4'h2 : Random={7'b0,Random_sequence[2:0]};\r
- 4'h3 : Random={6'b0,Random_sequence[3:0]};\r
- 4'h4 : Random={5'b0,Random_sequence[4:0]};\r
- 4'h5 : Random={4'b0,Random_sequence[5:0]};\r
- 4'h6 : Random={3'b0,Random_sequence[6:0]};\r
- 4'h7 : Random={2'b0,Random_sequence[7:0]};\r
- 4'h8 : Random={1'b0,Random_sequence[8:0]};\r
- 4'h9 : Random={ Random_sequence[9:0]}; \r
- default : Random={ Random_sequence[9:0]};\r
- endcase\r
-\r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- Slot_time_counter <=0;\r
- else if(Init)\r
- Slot_time_counter <=0;\r
- else if(!Random_time_meet)\r
- Slot_time_counter <=Slot_time_counter+1;\r
- \r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- Random_counter <=0;\r
- else if (Init)\r
- Random_counter <=Random;\r
- else if (Random_counter!=0&&Slot_time_counter==255)\r
- Random_counter <=Random_counter -1 ;\r
- \r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- Random_time_meet <=1;\r
- else if (Init)\r
- Random_time_meet <=0;\r
- else if (Random_counter==0)\r
- Random_time_meet <=1;\r
- \r
-endmodule\r
-\r
-\r
+++ /dev/null
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// Phy_int.v ////\r
-//// ////\r
-//// This file is part of the Ethernet IP core project ////\r
-//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////\r
-//// ////\r
-//// Author(s): ////\r
-//// - Jon Gao (gaojon@yahoo.com) ////\r
-//// ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// Copyright (C) 2001 Authors ////\r
-//// ////\r
-//// This source file may be used and distributed without ////\r
-//// restriction provided that this copyright statement is not ////\r
-//// removed from the file and that any derivative work contains ////\r
-//// the original copyright notice and the associated disclaimer. ////\r
-//// ////\r
-//// This source file is free software; you can redistribute it ////\r
-//// and/or modify it under the terms of the GNU Lesser General ////\r
-//// Public License as published by the Free Software Foundation; ////\r
-//// either version 2.1 of the License, or (at your option) any ////\r
-//// later version. ////\r
-//// ////\r
-//// This source is distributed in the hope that it will be ////\r
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\r
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\r
-//// PURPOSE. See the GNU Lesser General Public License for more ////\r
-//// details. ////\r
-//// ////\r
-//// You should have received a copy of the GNU Lesser General ////\r
-//// Public License along with this source; if not, download it ////\r
-//// from http://www.opencores.org/lgpl.shtml ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-// \r
-// CVS Revision History \r
-// \r
-// $Log: Phy_int.v,v $\r
-// Revision 1.3 2006/01/19 14:07:53 maverickist\r
-// verification is complete.\r
-//\r
-// Revision 1.3 2005/12/16 06:44:14 Administrator\r
-// replaced tab with space.\r
-// passed 9.6k length frame test.\r
-//\r
-// Revision 1.2 2005/12/13 12:15:36 Administrator\r
-// no message\r
-//\r
-// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator\r
-// no message\r
-// \r
-\r
-module Phy_int \r
- (input rst_mac_rx,\r
- input rst_mac_tx,\r
- input MAC_rx_clk,\r
- input MAC_tx_clk,\r
-\r
- // Rx interface\r
- output reg MCrs_dv,\r
- output reg [7:0] MRxD,\r
- output MRxErr,\r
-\r
- // Tx interface\r
- input [7:0] MTxD,\r
- input MTxEn,\r
- output MCRS,\r
-\r
- // PHY interface\r
- output Tx_er,\r
- output reg Tx_en,\r
- output reg [7:0] Txd,\r
- input Rx_er,\r
- input Rx_dv,\r
- input [7:0] Rxd,\r
- input Crs,\r
- input Col,\r
-\r
- // Host interface\r
- input Line_loop_en,\r
- input [2:0] Speed );\r
-\r
- //-------------------------------------------------------------------------\r
- // Local declarations\r
- //-------------------------------------------------------------------------\r
-\r
- reg [7:0] MTxD_dl1;\r
- reg MTxEn_dl1;\r
- reg Tx_odd_data_ptr;\r
- reg Rx_odd_data_ptr;\r
- reg Rx_er_dl1;\r
- reg Rx_dv_dl1;\r
- reg Rx_dv_dl2;\r
- reg [7:0] Rxd_dl1;\r
- reg [7:0] Rxd_dl2;\r
- reg Crs_dl1;\r
-\r
- //-------------------------------------------------------------------------\r
- // Tx control\r
- //-------------------------------------------------------------------------\r
-\r
- // Reg boundary signals\r
- always @( posedge MAC_tx_clk or posedge rst_mac_tx )\r
- if ( rst_mac_tx )\r
- begin\r
- MTxD_dl1 <= 0;\r
- MTxEn_dl1 <= 0;\r
- end \r
- else\r
- begin\r
- MTxD_dl1 <= MTxD;\r
- MTxEn_dl1 <= MTxEn;\r
- end \r
- \r
- always @( posedge MAC_tx_clk or posedge rst_mac_tx )\r
- if ( rst_mac_tx ) \r
- Tx_odd_data_ptr <= 0;\r
- else if ( !MTxD_dl1 )\r
- Tx_odd_data_ptr <= 0;\r
- else \r
- Tx_odd_data_ptr <= !Tx_odd_data_ptr;\r
- \r
-\r
- always @( posedge MAC_tx_clk or posedge rst_mac_tx )\r
- if ( rst_mac_tx )\r
- Txd <= 0;\r
- else if ( Speed[2] && MTxEn_dl1 )\r
- Txd <= MTxD_dl1;\r
- else if ( MTxEn_dl1 && !Tx_odd_data_ptr )\r
- Txd <= { 4'b0, MTxD_dl1[3:0] };\r
- else if ( MTxEn_dl1 && Tx_odd_data_ptr )\r
- Txd <= { 4'b0, MTxD_dl1[7:4] };\r
- else\r
- Txd <=0;\r
-\r
- always @( posedge MAC_tx_clk or posedge rst_mac_tx )\r
- if ( rst_mac_tx )\r
- Tx_en <= 0;\r
- else if ( MTxEn_dl1 )\r
- Tx_en <= 1; \r
- else\r
- Tx_en <= 0;\r
-\r
- assign Tx_er = 0;\r
-\r
- //-------------------------------------------------------------------------\r
- // Rx control\r
- //-------------------------------------------------------------------------\r
-\r
- // Reg boundery signals\r
- always @( posedge MAC_rx_clk or posedge rst_mac_rx )\r
- if ( rst_mac_rx )\r
- begin\r
- Rx_er_dl1 <= 0;\r
- Rx_dv_dl1 <= 0;\r
- Rx_dv_dl2 <= 0;\r
- Rxd_dl1 <= 0;\r
- Rxd_dl2 <= 0;\r
- Crs_dl1 <= 0;\r
- end\r
- else\r
- begin\r
- Rx_er_dl1 <= Rx_er;\r
- Rx_dv_dl1 <= Rx_dv;\r
- Rx_dv_dl2 <= Rx_dv_dl1;\r
- Rxd_dl1 <= Rxd;\r
- Rxd_dl2 <= Rxd_dl1;\r
- Crs_dl1 <= Crs;\r
- end\r
-\r
- assign MRxErr = Rx_er_dl1;\r
- assign MCRS = Crs_dl1;\r
-\r
- always @( posedge MAC_rx_clk or posedge rst_mac_rx )\r
- if ( rst_mac_rx )\r
- MCrs_dv <= 0;\r
- else if ( Line_loop_en )\r
- MCrs_dv <= Tx_en;\r
- else if( Rx_dv_dl2 )\r
- MCrs_dv <= 1;\r
- else\r
- MCrs_dv <= 0;\r
-\r
- always @ ( posedge MAC_rx_clk or posedge rst_mac_rx )\r
- if ( rst_mac_rx )\r
- Rx_odd_data_ptr <= 0;\r
- else if ( !Rx_dv_dl1 )\r
- Rx_odd_data_ptr <= 0;\r
- else \r
- Rx_odd_data_ptr <= !Rx_odd_data_ptr;\r
-\r
- always @ ( posedge MAC_rx_clk or posedge rst_mac_rx )\r
- if ( rst_mac_rx ) \r
- MRxD <= 0;\r
- else if( Line_loop_en )\r
- MRxD <= Txd;\r
- else if( Speed[2] && Rx_dv_dl2 )\r
- MRxD <= Rxd_dl2;\r
- else if( Rx_dv_dl1 && Rx_odd_data_ptr )\r
- MRxD <={ Rxd_dl1[3:0], Rxd_dl2[3:0] };\r
-\r
-endmodule \r
+++ /dev/null
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// RMON.v ////\r
-//// ////\r
-//// This file is part of the Ethernet IP core project ////\r
-//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////\r
-//// ////\r
-//// Author(s): ////\r
-//// - Jon Gao (gaojon@yahoo.com) ////\r
-//// ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// Copyright (C) 2001 Authors ////\r
-//// ////\r
-//// This source file may be used and distributed without ////\r
-//// restriction provided that this copyright statement is not ////\r
-//// removed from the file and that any derivative work contains ////\r
-//// the original copyright notice and the associated disclaimer. ////\r
-//// ////\r
-//// This source file is free software; you can redistribute it ////\r
-//// and/or modify it under the terms of the GNU Lesser General ////\r
-//// Public License as published by the Free Software Foundation; ////\r
-//// either version 2.1 of the License, or (at your option) any ////\r
-//// later version. ////\r
-//// ////\r
-//// This source is distributed in the hope that it will be ////\r
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\r
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\r
-//// PURPOSE. See the GNU Lesser General Public License for more ////\r
-//// details. ////\r
-//// ////\r
-//// You should have received a copy of the GNU Lesser General ////\r
-//// Public License along with this source; if not, download it ////\r
-//// from http://www.opencores.org/lgpl.shtml ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-// \r
-// CVS Revision History \r
-// \r
-// $Log: RMON.v,v $\r
-// Revision 1.4 2006/06/25 04:58:56 maverickist\r
-// no message\r
-//\r
-// Revision 1.3 2006/01/19 14:07:53 maverickist\r
-// verification is complete.\r
-//\r
-// Revision 1.2 2005/12/16 06:44:16 Administrator\r
-// replaced tab with space.\r
-// passed 9.6k length frame test.\r
-//\r
-// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator\r
-// no message\r
-// \r
-\r
-module RMON \r
- (input Clk ,\r
- input Reset ,\r
- //Tx_RMON\r
- input [2:0] Tx_pkt_type_rmon ,\r
- input [15:0] Tx_pkt_length_rmon ,\r
- input Tx_apply_rmon ,\r
- input [2:0] Tx_pkt_err_type_rmon,\r
- //Tx_RMON\r
- input [2:0] Rx_pkt_type_rmon ,\r
- input [15:0] Rx_pkt_length_rmon ,\r
- input Rx_apply_rmon ,\r
- input [2:0] Rx_pkt_err_type_rmon,\r
- //CPU\r
- input [5:0] CPU_rd_addr ,\r
- input CPU_rd_apply ,\r
- output CPU_rd_grant ,\r
- output [31:0] CPU_rd_dout\r
- );\r
- \r
- // ****************************************************************************** \r
- // interface signals\r
- // ****************************************************************************** \r
- wire Reg_apply_0 ;\r
- wire [4:0] Reg_addr_0 ;\r
- wire [15:0] Reg_data_0 ;\r
- wire Reg_next_0 ;\r
- wire Reg_apply_1 ;\r
- wire [4:0] Reg_addr_1 ;\r
- wire [15:0] Reg_data_1 ;\r
- wire Reg_next_1 ;\r
- wire [5:0] Addra ;\r
- wire [31:0] Dina ;\r
- reg [31:0] Douta ;\r
- wire Wea ;\r
-\r
- // ****************************************************************************** \r
- \r
- RMON_addr_gen U_0_Rx_RMON_addr_gen\r
- (.Clk (Clk ), \r
- .Reset (Reset ), \r
- //RMON \r
- .Pkt_type_rmon (Rx_pkt_type_rmon ), \r
- .Pkt_length_rmon (Rx_pkt_length_rmon ), \r
- .Apply_rmon (Rx_apply_rmon ),\r
- .Pkt_err_type_rmon (Rx_pkt_err_type_rmon ), \r
- //Rmon_ctrl\r
- .Reg_apply (Reg_apply_0 ), \r
- .Reg_addr (Reg_addr_0 ), \r
- .Reg_data (Reg_data_0 ), \r
- .Reg_next (Reg_next_0 ), \r
- //CPU\r
- .Reg_drop_apply ( ) );\r
- \r
- RMON_addr_gen U_0_Tx_RMON_addr_gen\r
- (.Clk (Clk ), \r
- .Reset (Reset ), \r
- //RMON\r
- .Pkt_type_rmon (Tx_pkt_type_rmon ), \r
- .Pkt_length_rmon (Tx_pkt_length_rmon ), \r
- .Apply_rmon (Tx_apply_rmon ),\r
- .Pkt_err_type_rmon (Tx_pkt_err_type_rmon ), \r
- //Rmon_ctrl\r
- .Reg_apply (Reg_apply_1 ), \r
- .Reg_addr (Reg_addr_1 ), \r
- .Reg_data (Reg_data_1 ), \r
- .Reg_next (Reg_next_1 ), \r
- //CPU\r
- .Reg_drop_apply ( ) );\r
- \r
- RMON_ctrl U_RMON_ctrl\r
- (.Clk (Clk ), \r
- .Reset (Reset ), \r
- //RMON_ctrl\r
- .Reg_apply_0 (Reg_apply_0 ), \r
- .Reg_addr_0 (Reg_addr_0 ), \r
- .Reg_data_0 (Reg_data_0 ), \r
- .Reg_next_0 (Reg_next_0 ), \r
- .Reg_apply_1 (Reg_apply_1 ), \r
- .Reg_addr_1 (Reg_addr_1 ), \r
- .Reg_data_1 (Reg_data_1 ), \r
- .Reg_next_1 (Reg_next_1 ), \r
- //dual-port ram\r
- .Addra (Addra ), \r
- .Dina (Dina ), \r
- .Douta (Douta ), \r
- .Wea (Wea ), \r
- //CPU\r
- .CPU_rd_addr (CPU_rd_addr ), \r
- .CPU_rd_apply (CPU_rd_apply ), \r
- .CPU_rd_grant (CPU_rd_grant ), \r
- .CPU_rd_dout (CPU_rd_dout ) );\r
- \r
- reg [31:0] RMON_ram [0:63];\r
- wire [31:0] Douta_imm = RMON_ram[Addra];\r
- integer i;\r
- initial\r
- for(i=0;i<64;i=i+1)\r
- RMON_ram[i] = 32'd0;\r
- \r
- always @(posedge Clk)\r
- if(Wea)\r
- RMON_ram[Addra] <= Dina;\r
-\r
- always @(posedge Clk)\r
- Douta <= Douta_imm;\r
- \r
-endmodule // RMON\r
+++ /dev/null
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// RMON_addr_gen.v ////\r
-//// ////\r
-//// This file is part of the Ethernet IP core project ////\r
-//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////\r
-//// ////\r
-//// Author(s): ////\r
-//// - Jon Gao (gaojon@yahoo.com) ////\r
-//// ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// Copyright (C) 2001 Authors ////\r
-//// ////\r
-//// This source file may be used and distributed without ////\r
-//// restriction provided that this copyright statement is not ////\r
-//// removed from the file and that any derivative work contains ////\r
-//// the original copyright notice and the associated disclaimer. ////\r
-//// ////\r
-//// This source file is free software; you can redistribute it ////\r
-//// and/or modify it under the terms of the GNU Lesser General ////\r
-//// Public License as published by the Free Software Foundation; ////\r
-//// either version 2.1 of the License, or (at your option) any ////\r
-//// later version. ////\r
-//// ////\r
-//// This source is distributed in the hope that it will be ////\r
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\r
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\r
-//// PURPOSE. See the GNU Lesser General Public License for more ////\r
-//// details. ////\r
-//// ////\r
-//// You should have received a copy of the GNU Lesser General ////\r
-//// Public License along with this source; if not, download it ////\r
-//// from http://www.opencores.org/lgpl.shtml ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-// \r
-// CVS Revision History \r
-// \r
-// $Log: RMON_addr_gen.v,v $\r
-// Revision 1.4 2006/06/25 04:58:57 maverickist\r
-// no message\r
-//\r
-// Revision 1.3 2006/01/19 14:07:55 maverickist\r
-// verification is complete.\r
-//\r
-// Revision 1.2 2005/12/16 06:44:19 Administrator\r
-// replaced tab with space.\r
-// passed 9.6k length frame test.\r
-//\r
-// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator\r
-// no message\r
-// \r
-module RMON_addr_gen(\r
-Clk , \r
-Reset , \r
-//RMON \r
-Pkt_type_rmon , \r
-Pkt_length_rmon , \r
-Apply_rmon ,//pluse signal looks like eop \r
-Pkt_err_type_rmon , \r
-// \r
-Reg_apply , \r
-Reg_addr , \r
-Reg_data , \r
-Reg_next , \r
-//CPU \r
-Reg_drop_apply \r
-);\r
-input Clk ;\r
-input Reset ;\r
- //RMON\r
-input [2:0] Pkt_type_rmon ;\r
-input [15:0] Pkt_length_rmon ;\r
-input Apply_rmon ;//pluse signal looks like eop\r
-input [2:0] Pkt_err_type_rmon ;\r
- //RMON_ctrl\r
-output Reg_apply ;\r
-output [4:0] Reg_addr ;\r
-output [15:0] Reg_data ;\r
-input Reg_next ;\r
- //CPU\r
-output Reg_drop_apply ;\r
-\r
-//******************************************************************************\r
-//internal signals \r
-//******************************************************************************\r
-parameter StateIdle =4'd0;\r
-parameter StatePktLength =4'd1;\r
-parameter StatePktNumber =4'd2;\r
-parameter StatePktType =4'd3;\r
-parameter StatePktRange =4'd4;\r
-\r
-reg [3:0] CurrentState /* synthesys syn_keep=1 */;\r
-reg [3:0] NextState;\r
- \r
-reg [2:0] PktTypeReg ;\r
-reg [15:0] PktLengthReg ;\r
-reg [2:0] PktErrTypeReg ;\r
- \r
-reg Reg_apply ;\r
-reg [4:0] Reg_addr ;\r
-reg [15:0] Reg_data ;\r
-reg Reg_drop_apply ;\r
-//******************************************************************************\r
-//register boundery signals \r
- \r
-//******************************************************************************\r
-reg Apply_rmon_dl1;\r
-reg Apply_rmon_dl2;\r
-reg Apply_rmon_pulse;\r
-reg [2:0] Pkt_type_rmon_dl1 ;\r
-reg [15:0] Pkt_length_rmon_dl1 ;\r
-reg [2:0] Pkt_err_type_rmon_dl1 ;\r
-\r
-always @(posedge Clk or posedge Reset)\r
- if (Reset)\r
- begin\r
- Pkt_type_rmon_dl1 <=0;\r
- Pkt_length_rmon_dl1 <=0;\r
- Pkt_err_type_rmon_dl1 <=0;\r
- end \r
- else\r
- begin\r
- Pkt_type_rmon_dl1 <=Pkt_type_rmon ; \r
- Pkt_length_rmon_dl1 <=Pkt_length_rmon ;\r
- Pkt_err_type_rmon_dl1 <=Pkt_err_type_rmon ;\r
- end \r
-\r
-always @(posedge Clk or posedge Reset)\r
- if (Reset)\r
- begin\r
- Apply_rmon_dl1 <=0;\r
- Apply_rmon_dl2 <=0;\r
- end\r
- else\r
- begin\r
- Apply_rmon_dl1 <=Apply_rmon;\r
- Apply_rmon_dl2 <=Apply_rmon_dl1;\r
- end \r
- \r
-always @(Apply_rmon_dl1 or Apply_rmon_dl2)\r
- if (Apply_rmon_dl1&!Apply_rmon_dl2)\r
- Apply_rmon_pulse =1;\r
- else\r
- Apply_rmon_pulse =0;\r
-\r
-\r
- \r
-always @(posedge Clk or posedge Reset)\r
- if (Reset)\r
- begin\r
- PktTypeReg <=0;\r
- PktLengthReg <=0;\r
- PktErrTypeReg <=0; \r
- end\r
- else if (Apply_rmon_pulse&&CurrentState==StateIdle)\r
- begin\r
- PktTypeReg <=Pkt_type_rmon_dl1 ;\r
- PktLengthReg <=Pkt_length_rmon_dl1 ;\r
- PktErrTypeReg <=Pkt_err_type_rmon_dl1 ; \r
- end \r
- \r
-\r
-//******************************************************************************\r
-//State Machine \r
-//******************************************************************************\r
-always @(posedge Clk or posedge Reset)\r
- if (Reset)\r
- CurrentState <=StateIdle;\r
- else\r
- CurrentState <=NextState;\r
- \r
-always @(CurrentState or Apply_rmon_pulse or Reg_next)\r
- case (CurrentState)\r
- StateIdle:\r
- if (Apply_rmon_pulse)\r
- NextState =StatePktLength;\r
- else\r
- NextState =StateIdle;\r
- StatePktLength:\r
- if (Reg_next)\r
- NextState =StatePktNumber;\r
- else\r
- NextState =CurrentState;\r
- StatePktNumber:\r
- if (Reg_next)\r
- NextState =StatePktType;\r
- else\r
- NextState =CurrentState;\r
- StatePktType:\r
- if (Reg_next)\r
- NextState =StatePktRange;\r
- else\r
- NextState =CurrentState;\r
- StatePktRange:\r
- if (Reg_next)\r
- NextState =StateIdle;\r
- else\r
- NextState =CurrentState;\r
- default:\r
- NextState =StateIdle;\r
- endcase \r
- \r
-//******************************************************************************\r
-//gen output signals \r
-//******************************************************************************\r
-//Reg_apply\r
-always @ (CurrentState)\r
- if (CurrentState==StatePktLength||CurrentState==StatePktNumber||\r
- CurrentState==StatePktType||CurrentState==StatePktRange)\r
- Reg_apply =1;\r
- else\r
- Reg_apply =0;\r
- \r
-//Reg_addr\r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- Reg_addr <=0;\r
- else case (CurrentState)\r
- StatePktLength:\r
- Reg_addr <=5'd00;\r
- StatePktNumber:\r
- Reg_addr <=5'd01;\r
- StatePktType:\r
- case(PktTypeReg)\r
- 3'b011:\r
- Reg_addr <=5'd02; //broadcast\r
- 3'b001:\r
- Reg_addr <=5'd03; //multicast \r
- 3'b100:\r
- Reg_addr <=5'd16; //pause frame \r
- default:\r
- Reg_addr <=5'd04; //unicast\r
- endcase\r
- StatePktRange:\r
- case(PktErrTypeReg)\r
- 3'b001:\r
- Reg_addr <=5'd05; \r
- 3'b010:\r
- Reg_addr <=5'd06; \r
- 3'b011:\r
- Reg_addr <=5'd07; \r
- 3'b100:\r
- if (PktLengthReg<64) \r
- Reg_addr <=5'd08; \r
- else if (PktLengthReg==64)\r
- Reg_addr <=5'd09; \r
- else if (PktLengthReg<128)\r
- Reg_addr <=5'd10; \r
- else if (PktLengthReg<256)\r
- Reg_addr <=5'd11; \r
- else if (PktLengthReg<512)\r
- Reg_addr <=5'd12; \r
- else if (PktLengthReg<1024)\r
- Reg_addr <=5'd13; \r
- else if (PktLengthReg<1519)\r
- Reg_addr <=5'd14; \r
- else\r
- Reg_addr <=5'd15; \r
- default:\r
- Reg_addr <=5'd05;\r
- endcase\r
- default:\r
- Reg_addr <=5'd05;\r
- endcase\r
- \r
-//Reg_data\r
-always @ (CurrentState or PktLengthReg)\r
- case (CurrentState)\r
- StatePktLength:\r
- Reg_data =PktLengthReg;\r
- StatePktNumber:\r
- Reg_data =1;\r
- StatePktType:\r
- Reg_data =1;\r
- StatePktRange:\r
- Reg_data =1;\r
- default:\r
- Reg_data =0;\r
- endcase\r
- \r
-//Reg_drop_apply\r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- Reg_drop_apply <=0;\r
- else if (CurrentState!=StateIdle&&Apply_rmon_pulse)\r
- Reg_drop_apply <=1;\r
- else\r
- Reg_drop_apply <=0;\r
- \r
-\r
-endmodule \r
- \r
+++ /dev/null
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// RMON_ctrl.v ////\r
-//// ////\r
-//// This file is part of the Ethernet IP core project ////\r
-//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////\r
-//// ////\r
-//// Author(s): ////\r
-//// - Jon Gao (gaojon@yahoo.com) ////\r
-//// ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// Copyright (C) 2001 Authors ////\r
-//// ////\r
-//// This source file may be used and distributed without ////\r
-//// restriction provided that this copyright statement is not ////\r
-//// removed from the file and that any derivative work contains ////\r
-//// the original copyright notice and the associated disclaimer. ////\r
-//// ////\r
-//// This source file is free software; you can redistribute it ////\r
-//// and/or modify it under the terms of the GNU Lesser General ////\r
-//// Public License as published by the Free Software Foundation; ////\r
-//// either version 2.1 of the License, or (at your option) any ////\r
-//// later version. ////\r
-//// ////\r
-//// This source is distributed in the hope that it will be ////\r
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\r
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\r
-//// PURPOSE. See the GNU Lesser General Public License for more ////\r
-//// details. ////\r
-//// ////\r
-//// You should have received a copy of the GNU Lesser General ////\r
-//// Public License along with this source; if not, download it ////\r
-//// from http://www.opencores.org/lgpl.shtml ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-// \r
-// CVS Revision History \r
-// \r
-// $Log: RMON_ctrl.v,v $\r
-// Revision 1.4 2006/06/25 04:58:57 maverickist\r
-// no message\r
-//\r
-// Revision 1.3 2006/01/19 14:07:55 maverickist\r
-// verification is complete.\r
-//\r
-// Revision 1.2 2005/12/16 06:44:19 Administrator\r
-// replaced tab with space.\r
-// passed 9.6k length frame test.\r
-//\r
-// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator\r
-// no message\r
-// \r
-module RMON_ctrl (\r
-Clk , \r
-Reset , \r
-//RMON_ctrl \r
-Reg_apply_0 , \r
-Reg_addr_0 , \r
-Reg_data_0 , \r
-Reg_next_0 , \r
-Reg_apply_1 , \r
-Reg_addr_1 , \r
-Reg_data_1 , \r
-Reg_next_1 , \r
-//dual-port ram\r
-Addra , \r
-Dina , \r
-Douta , \r
-Wea , \r
-//CPU \r
-CPU_rd_addr , \r
-CPU_rd_apply , \r
-CPU_rd_grant ,\r
-CPU_rd_dout\r
-\r
-);\r
-input Clk ;\r
-input Reset ;\r
- //RMON_ctrl\r
-input Reg_apply_0 ;\r
-input [4:0] Reg_addr_0 ;\r
-input [15:0] Reg_data_0 ;\r
-output Reg_next_0 ;\r
-input Reg_apply_1 ;\r
-input [4:0] Reg_addr_1 ;\r
-input [15:0] Reg_data_1 ;\r
-output Reg_next_1 ;\r
- //dual-port ram \r
- //port-a for Rmon \r
-output [5:0] Addra ;\r
-output [31:0] Dina ;\r
-input [31:0] Douta ;\r
-output Wea ;\r
- //CPU\r
-input [5:0] CPU_rd_addr ;\r
-input CPU_rd_apply ;\r
-output CPU_rd_grant ;\r
-output [31:0] CPU_rd_dout ;\r
-\r
-\r
-\r
-\r
-//******************************************************************************\r
-//internal signals \r
-//******************************************************************************\r
-\r
-parameter StateCPU =4'd00;\r
-parameter StateMAC0 =4'd01;\r
-parameter StateMAC1 =4'd02;\r
-\r
-\r
-reg [3:0] CurrentState /* synthesys syn_keep=1 */;\r
-reg [3:0] NextState;\r
-reg [3:0] CurrentState_reg;\r
-\r
-reg [4:0] StepCounter;\r
-reg [5:0] Addra ;\r
-reg [31:0] Dina;\r
-reg Reg_next_0 ;\r
-reg Reg_next_1 ;\r
-reg Write;\r
-reg Read;\r
-reg Pipeline;\r
-reg [31:0] CPU_rd_dout ;\r
-reg CPU_rd_apply_reg ;\r
-//******************************************************************************\r
-//State Machine \r
-//******************************************************************************\r
-\r
-always @(posedge Clk or posedge Reset)\r
- if (Reset)\r
- CurrentState <=StateMAC0;\r
- else\r
- CurrentState <=NextState;\r
- \r
-always @(posedge Clk or posedge Reset)\r
- if (Reset) \r
- CurrentState_reg <=StateMAC0;\r
- else if(CurrentState!=StateCPU)\r
- CurrentState_reg <=CurrentState;\r
- \r
-always @(CurrentState or CPU_rd_apply_reg or Reg_apply_0 or CurrentState_reg\r
- or Reg_apply_1 \r
- or StepCounter\r
- )\r
- case(CurrentState)\r
- StateMAC0:\r
- if(!Reg_apply_0&&CPU_rd_apply_reg)\r
- NextState =StateCPU;\r
- else if(!Reg_apply_0)\r
- NextState =StateMAC1;\r
- else\r
- NextState =CurrentState;\r
- StateMAC1:\r
- if(!Reg_apply_1&&CPU_rd_apply_reg)\r
- NextState =StateCPU;\r
- else if(!Reg_apply_1)\r
- NextState =StateMAC0;\r
- else\r
- NextState =CurrentState;\r
- StateCPU:\r
- if (StepCounter==3)\r
- case (CurrentState_reg)\r
- StateMAC0 :NextState =StateMAC0 ;\r
- StateMAC1 :NextState =StateMAC1 ;\r
- default :NextState =StateMAC0;\r
- endcase\r
- else\r
- NextState =CurrentState;\r
- \r
- default:\r
- NextState =StateMAC0;\r
- endcase\r
- \r
-\r
-\r
-always @(posedge Clk or posedge Reset)\r
- if (Reset)\r
- StepCounter <=0;\r
- else if(NextState!=CurrentState)\r
- StepCounter <=0;\r
- else if (StepCounter!=4'hf)\r
- StepCounter <=StepCounter + 1;\r
-\r
-//******************************************************************************\r
-//temp signals \r
-//******************************************************************************\r
-always @(StepCounter)\r
- if( StepCounter==1||StepCounter==4||\r
- StepCounter==7||StepCounter==10)\r
- Read =1;\r
- else\r
- Read =0;\r
-\r
-always @(StepCounter or CurrentState)\r
- if( StepCounter==2||StepCounter==5||\r
- StepCounter==8||StepCounter==11)\r
- Pipeline =1;\r
- else\r
- Pipeline =0;\r
- \r
-always @(StepCounter or CurrentState)\r
- if( StepCounter==3||StepCounter==6||\r
- StepCounter==9||StepCounter==12)\r
- Write =1;\r
- else\r
- Write =0;\r
- \r
- \r
-//******************************************************************************\r
-//gen output signals \r
-//****************************************************************************** \r
-//Addra \r
-always @(*)\r
- case(CurrentState)\r
- StateMAC0 : Addra={1'd0 ,Reg_addr_0 };\r
- StateMAC1 : Addra={1'd1 ,Reg_addr_1 };\r
- StateCPU: Addra=CPU_rd_addr;\r
- default: Addra=0;\r
- endcase\r
- \r
-//Dina\r
-always @(posedge Clk or posedge Reset)\r
- if (Reset)\r
- Dina <=0;\r
- else \r
- case(CurrentState)\r
- StateMAC0 : Dina<=Douta+Reg_data_0 ;\r
- StateMAC1 : Dina<=Douta+Reg_data_1 ;\r
- StateCPU: Dina<=0;\r
- default: Dina<=0;\r
- endcase\r
- \r
-assign Wea =Write;\r
-//Reg_next\r
-always @(CurrentState or Pipeline)\r
- if(CurrentState==StateMAC0)\r
- Reg_next_0 =Pipeline;\r
- else\r
- Reg_next_0 =0;\r
- \r
-always @(CurrentState or Pipeline)\r
- if(CurrentState==StateMAC1)\r
- Reg_next_1 =Pipeline;\r
- else\r
- Reg_next_1 =0; \r
-\r
-\r
-//CPU_rd_grant \r
-reg CPU_rd_apply_dl1;\r
-reg CPU_rd_apply_dl2;\r
-//rising edge\r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- begin\r
- CPU_rd_apply_dl1 <=0;\r
- CPU_rd_apply_dl2 <=0;\r
- end\r
- else\r
- begin\r
- CPU_rd_apply_dl1 <=CPU_rd_apply;\r
- CPU_rd_apply_dl2 <=CPU_rd_apply_dl1;\r
- end \r
-\r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- CPU_rd_apply_reg <=0;\r
- else if (CPU_rd_apply_dl1&!CPU_rd_apply_dl2)\r
- CPU_rd_apply_reg <=1;\r
- else if (CurrentState==StateCPU&&Write)\r
- CPU_rd_apply_reg <=0;\r
-\r
-assign CPU_rd_grant = CPU_rd_apply & CPU_rd_apply_dl1 & CPU_rd_apply_dl2 & !CPU_rd_apply_reg;\r
-\r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- CPU_rd_dout <=0;\r
- else if (Pipeline&&CurrentState==StateCPU)\r
- CPU_rd_dout <=Douta; \r
-\r
-endmodule \r
+++ /dev/null
-module Reg_int (\r
- // Wishbone compliant core host interface\r
- input CLK_I, // Wishbone interface clock (nominally 50 MHz)\r
- input RST_I, // Active high (async) reset of the Wishbone interface\r
- input STB_I, // Active high module-select\r
- input CYC_I, // Active high cycle-enable\r
- input [6:0] ADR_I, // Module register address\r
- input WE_I, // Active high for writes, low for reads\r
- input [31:0] DAT_I, // Write data\r
- output reg [31:0] DAT_O, // Read data\r
- output reg ACK_O, // Acknowledge output \96 single high pulse\r
-\r
- // Tx host interface \r
- output [4:0] Tx_Hwmark,\r
- output [4:0] Tx_Lwmark, \r
- output MAC_tx_add_en,\r
- output FullDuplex,\r
- output [3:0] MaxRetry,\r
- output [5:0] IFGset,\r
- output [7:0] MAC_tx_add_prom_data,\r
- output [2:0] MAC_tx_add_prom_add,\r
- output MAC_tx_add_prom_wr,\r
-\r
- // Rx host interface \r
- output MAC_rx_add_chk_en,\r
- output [7:0] MAC_rx_add_prom_data,\r
- output [2:0] MAC_rx_add_prom_add,\r
- output MAC_rx_add_prom_wr,\r
- output broadcast_filter_en,\r
- output [15:0] broadcast_bucket_depth,\r
- output [15:0] broadcast_bucket_interval,\r
- output RX_APPEND_CRC,\r
- output [4:0] Rx_Hwmark,\r
- output [4:0] Rx_Lwmark,\r
- output CRC_chk_en,\r
- output [5:0] RX_IFG_SET,\r
- output [15:0] RX_MAX_LENGTH, // Default 1518\r
- output [6:0] RX_MIN_LENGTH, // Default 64\r
-\r
- // Flow control settings\r
- output pause_frame_send_en,\r
- output [15:0] pause_quanta_set,\r
- output tx_pause_en,\r
- output [15:0] fc_hwmark,\r
- output [15:0] fc_lwmark,\r
- output [15:0] fc_padtime,\r
- \r
- // RMON host interface\r
- output [5:0] CPU_rd_addr,\r
- output CPU_rd_apply,\r
- input CPU_rd_grant,\r
- input [31:0] CPU_rd_dout,\r
-\r
- //Phy int host interface \r
- output Line_loop_en,\r
- output [2:0] Speed,\r
-\r
- //MII to CPU \r
- output [7:0] Divider, // Divider for the host clock\r
- output [15:0] CtrlData, // Control Data (to be written to the PHY reg.)\r
- output [4:0] Rgad, // Register Address (within the PHY)\r
- output [4:0] Fiad, // PHY Address\r
- output NoPre, // No Preamble (no 32-bit preamble)\r
- output WCtrlData, // Write Control Data operation\r
- output RStat, // Read Status operation\r
- output ScanStat, // Scan Status operation\r
- input Busy, // Busy Signal\r
- input LinkFail, // Link Integrity Signal\r
- input Nvalid, // Invalid Status (qualifier for the valid scan result)\r
- input [15:0] Prsd, // Read Status Data (data read from the PHY)\r
- input WCtrlDataStart, // This signals resets the WCTRLDATA bit in the MIIM Command register\r
- input RStatStart, // This signal resets the RSTAT BIT in the MIIM Command register\r
- input UpdateMIIRX_DATAReg // Updates MII RX_DATA register with read data\r
-);\r
-\r
- // New registers for controlling the MII interface\r
- wire [8:0] MIIMODER;\r
- reg [2:0] MIICOMMAND;\r
- wire [12:0] MIIADDRESS;\r
- wire [15:0] MIITX_DATA;\r
- reg [15:0] MIIRX_DATA;\r
- wire [2:0] MIISTATUS;\r
-\r
- // New registers for controlling the MII interface\r
-\r
- // MIIMODER\r
- assign NoPre = MIIMODER[8];\r
- assign Divider = MIIMODER[7:0];\r
- // MIICOMMAND\r
- assign WCtrlData = MIICOMMAND[2];\r
- assign RStat = MIICOMMAND[1];\r
- assign ScanStat = MIICOMMAND[0];\r
- // MIIADDRESS\r
- assign Rgad = MIIADDRESS[12:8];\r
- assign Fiad = MIIADDRESS[4:0];\r
- // MIITX_DATA\r
- assign CtrlData = MIITX_DATA[15:0];\r
- // MIISTATUS\r
- assign MIISTATUS[2:0] = { 13'b0, Nvalid, Busy, LinkFail };\r
-\r
- wire Wr;\r
- \r
- RegCPUData #( 5 ) U_0_000( Tx_Hwmark , 7'd000, 5'h09, RST_I, CLK_I, Wr, ADR_I, DAT_I[4:0] );\r
- RegCPUData #( 5 ) U_0_001( Tx_Lwmark , 7'd001, 5'h08, RST_I, CLK_I, Wr, ADR_I, DAT_I[4:0] );\r
- RegCPUData #( 1 ) U_0_002( pause_frame_send_en , 7'd002, 1'h0, RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] );\r
- RegCPUData #( 16 ) U_0_003( pause_quanta_set , 7'd003, 16'h01af, RST_I, CLK_I, Wr, ADR_I, DAT_I[15:0] );\r
- RegCPUData #( 6 ) U_0_004( IFGset , 7'd004, 6'h0c, RST_I, CLK_I, Wr, ADR_I, DAT_I[5:0] );\r
- RegCPUData #( 1 ) U_0_005( FullDuplex , 7'd005, 1'h1, RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] );\r
- RegCPUData #( 4 ) U_0_006( MaxRetry , 7'd006, 4'h2, RST_I, CLK_I, Wr, ADR_I, DAT_I[3:0] );\r
- RegCPUData #( 1 ) U_0_007( MAC_tx_add_en , 7'd007, 1'h0, RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] );\r
- RegCPUData #( 8 ) U_0_008( MAC_tx_add_prom_data , 7'd008, 8'h00, RST_I, CLK_I, Wr, ADR_I, DAT_I[7:0] );\r
- RegCPUData #( 3 ) U_0_009( MAC_tx_add_prom_add , 7'd009, 3'h0, RST_I, CLK_I, Wr, ADR_I, DAT_I[2:0] );\r
- RegCPUData #( 1 ) U_0_010( MAC_tx_add_prom_wr , 7'd010, 1'h0, RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] );\r
- RegCPUData #( 1 ) U_0_011( tx_pause_en , 7'd011, 1'h1, RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] );\r
- RegCPUData #( 16 ) U_0_012( fc_hwmark , 7'd012, 1'h0, RST_I, CLK_I, Wr, ADR_I, DAT_I[15:0] );\r
- RegCPUData #( 16 ) U_0_013( fc_lwmark , 7'd013, 1'h0, RST_I, CLK_I, Wr, ADR_I, DAT_I[15:0] );\r
- RegCPUData #( 1 ) U_0_014( MAC_rx_add_chk_en , 7'd014, 1'h0, RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] );\r
- RegCPUData #( 8 ) U_0_015( MAC_rx_add_prom_data , 7'd015, 8'h00, RST_I, CLK_I, Wr, ADR_I, DAT_I[7:0] );\r
- RegCPUData #( 3 ) U_0_016( MAC_rx_add_prom_add , 7'd016, 3'h0, RST_I, CLK_I, Wr, ADR_I, DAT_I[2:0] );\r
- RegCPUData #( 1 ) U_0_017( MAC_rx_add_prom_wr , 7'd017, 1'h0, RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] );\r
- RegCPUData #( 1 ) U_0_018( broadcast_filter_en , 7'd018, 1'h0, RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] );\r
- RegCPUData #( 16 ) U_0_019( broadcast_bucket_depth , 7'd019, 16'h0000, RST_I, CLK_I, Wr, ADR_I, DAT_I[15:0] );\r
- RegCPUData #( 16 ) U_0_020( broadcast_bucket_interval , 7'd020, 16'h0000, RST_I, CLK_I, Wr, ADR_I, DAT_I[15:0] );\r
- RegCPUData #( 1 ) U_0_021( RX_APPEND_CRC , 7'd021, 1'h0, RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] );\r
- RegCPUData #( 5 ) U_0_022( Rx_Hwmark , 7'd022, 5'h1a, RST_I, CLK_I, Wr, ADR_I, DAT_I[4:0] );\r
- RegCPUData #( 5 ) U_0_023( Rx_Lwmark , 7'd023, 5'h10, RST_I, CLK_I, Wr, ADR_I, DAT_I[4:0] );\r
- RegCPUData #( 1 ) U_0_024( CRC_chk_en , 7'd024, 1'h1, RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] );\r
- RegCPUData #( 6 ) U_0_025( RX_IFG_SET , 7'd025, 6'h0c, RST_I, CLK_I, Wr, ADR_I, DAT_I[5:0] );\r
- RegCPUData #( 16 ) U_0_026( RX_MAX_LENGTH , 7'd026, 16'h2710, RST_I, CLK_I, Wr, ADR_I, DAT_I[15:0] );\r
- RegCPUData #( 7 ) U_0_027( RX_MIN_LENGTH , 7'd027, 7'h40, RST_I, CLK_I, Wr, ADR_I, DAT_I[6:0] );\r
- RegCPUData #( 6 ) U_0_028( CPU_rd_addr , 7'd028, 6'h00, RST_I, CLK_I, Wr, ADR_I, DAT_I[5:0] );\r
- RegCPUData #( 1 ) U_0_029( CPU_rd_apply , 7'd029, 1'h0, RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] );\r
-//RegCPUData #( 1 ) U_0_030( CPU_rd_grant , 7'd030, 1'h0, RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] );\r
-//RegCPUData #( 16 ) U_0_031( CPU_rd_dout_l , 7'd031, 16'h0000, RST_I, CLK_I, Wr, ADR_I, DAT_I[15:0] );\r
-//RegCPUData #( 16 ) U_0_032( CPU_rd_dout_h , 7'd032, 16'h0000, RST_I, CLK_I, Wr, ADR_I, DAT_I[15:0] );\r
- RegCPUData #( 1 ) U_0_033( Line_loop_en , 7'd033, 1'h0, RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] );\r
- RegCPUData #( 3 ) U_0_034( Speed , 7'd034, 3'h0, RST_I, CLK_I, Wr, ADR_I, DAT_I[2:0] );\r
-\r
- // New registers for controlling the MDIO interface\r
- RegCPUData #( 9 ) U_0_035( MIIMODER , 7'd035, 9'h064, RST_I, CLK_I, Wr, ADR_I, DAT_I[8:0] );\r
- // Reg #36 is MIICOMMAND - implemented separately below\r
- RegCPUData #( 13 ) U_0_037( MIIADDRESS , 7'd037, 13'h0000, RST_I, CLK_I, Wr, ADR_I, DAT_I[12:0] );\r
- RegCPUData #( 16 ) U_0_038( MIITX_DATA , 7'd038, 16'h0000, RST_I, CLK_I, Wr, ADR_I, DAT_I[15:0] );\r
-\r
- // New FC register\r
- RegCPUData #( 16 ) U_0_041( fc_padtime , 7'd041, 1'h0, RST_I, CLK_I, Wr, ADR_I, DAT_I[15:0] );\r
-\r
- // Asserted in first clock of 2-cycle access, negated otherwise\r
- wire Access = ~ACK_O & STB_I & CYC_I;\r
-\r
- // Asserted in first clock of 2-cycle write access, negated otherwise\r
- assign Wr = Access & WE_I;\r
-\r
- // MIICOMMAND register - needs special treatment because of auto-resetting bits\r
- always @ ( posedge RST_I or posedge CLK_I )\r
- if ( RST_I )\r
- MIICOMMAND <= 0;\r
- else\r
- begin\r
- if ( Wr & ( ADR_I == 7'd036 ) )\r
- // Write access\r
- MIICOMMAND <= DAT_I;\r
- else\r
- begin\r
- if ( WCtrlDataStart )\r
- MIICOMMAND[2] <= 0;\r
- if ( RStatStart )\r
- MIICOMMAND[1] <= 0;\r
- end\r
- end\r
-\r
- // MIIRX_DATA register\r
- always @ ( posedge RST_I or posedge CLK_I )\r
- if ( RST_I )\r
- MIIRX_DATA <= 0;\r
- else\r
- if ( UpdateMIIRX_DATAReg )\r
- MIIRX_DATA <= Prsd;\r
-\r
- // ACK_O is asserted in second clock of 2-cycle access, negated otherwise\r
- always @ ( posedge RST_I or posedge CLK_I )\r
- if ( RST_I )\r
- ACK_O <= 0;\r
- else\r
- ACK_O <= Access;\r
-\r
- always @ ( posedge RST_I or posedge CLK_I )\r
- if(RST_I)\r
- DAT_O <= 0;\r
- else\r
- begin\r
- DAT_O <=0;\r
- if ( Access & ~WE_I )\r
- casez ( ADR_I )\r
- 7'd00: DAT_O <= Tx_Hwmark;\r
- 7'd01: DAT_O <= Tx_Lwmark;\r
- 7'd02: DAT_O <= pause_frame_send_en;\r
- 7'd03: DAT_O <= pause_quanta_set;\r
- 7'd04: DAT_O <= IFGset;\r
- 7'd05: DAT_O <= FullDuplex;\r
- 7'd06: DAT_O <= MaxRetry;\r
- 7'd07: DAT_O <= MAC_tx_add_en;\r
- 7'd08: DAT_O <= MAC_tx_add_prom_data;\r
- 7'd09: DAT_O <= MAC_tx_add_prom_add;\r
- 7'd10: DAT_O <= MAC_tx_add_prom_wr;\r
- 7'd11: DAT_O <= tx_pause_en;\r
- 7'd12: DAT_O <= fc_hwmark;\r
- 7'd13: DAT_O <= fc_lwmark;\r
- 7'd14: DAT_O <= MAC_rx_add_chk_en;\r
- 7'd15: DAT_O <= MAC_rx_add_prom_data;\r
- 7'd16: DAT_O <= MAC_rx_add_prom_add;\r
- 7'd17: DAT_O <= MAC_rx_add_prom_wr;\r
- 7'd18: DAT_O <= broadcast_filter_en;\r
- 7'd19: DAT_O <= broadcast_bucket_depth;\r
- 7'd20: DAT_O <= broadcast_bucket_interval;\r
- 7'd21: DAT_O <= RX_APPEND_CRC;\r
- 7'd22: DAT_O <= Rx_Hwmark;\r
- 7'd23: DAT_O <= Rx_Lwmark;\r
- 7'd24: DAT_O <= CRC_chk_en;\r
- 7'd25: DAT_O <= RX_IFG_SET;\r
- 7'd26: DAT_O <= RX_MAX_LENGTH;\r
- 7'd27: DAT_O <= RX_MIN_LENGTH;\r
- 7'd28: DAT_O <= CPU_rd_addr;\r
- 7'd29: DAT_O <= CPU_rd_apply;\r
- 7'd30: DAT_O <= CPU_rd_grant;\r
- 7'd31: DAT_O <= CPU_rd_dout;\r
- //7'd32: DAT_O <= CPU_rd_dout[31:16];\r
- 7'd33: DAT_O <= Line_loop_en;\r
- 7'd34: DAT_O <= Speed;\r
-\r
- // New registers for controlling MII interface\r
- 7'd35: DAT_O <= MIIMODER;\r
- 7'd36: DAT_O <= MIICOMMAND;\r
- 7'd37: DAT_O <= MIIADDRESS;\r
- 7'd38: DAT_O <= MIITX_DATA;\r
- 7'd39: DAT_O <= MIIRX_DATA;\r
- 7'd40: DAT_O <= MIISTATUS;\r
- 7'd41: DAT_O <= fc_padtime;\r
- endcase\r
- end\r
-\r
-endmodule \r
-\r
-module RegCPUData(\r
- RegOut,\r
- RegAddr,\r
- RegInit,\r
-\r
- Reset,\r
- Clk,\r
- Wr,\r
- Addr,\r
- WrData\r
-);\r
-\r
- parameter WIDTH = 16;\r
-\r
- output reg [WIDTH-1:0] RegOut;\r
- input [6:0] RegAddr;\r
- input [WIDTH-1:0] RegInit;\r
-\r
- input Reset;\r
- input Clk;\r
- input Wr;\r
- input [6:0] Addr;\r
- input [WIDTH-1:0] WrData;\r
-\r
- always @( posedge Reset or posedge Clk )\r
- if ( Reset )\r
- RegOut <= RegInit;\r
- else\r
- if ( Wr && ( Addr == RegAddr ) )\r
- RegOut <= WrData;\r
-\r
-endmodule \r
+++ /dev/null
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// eth_clk_div2.v ////\r
-//// ////\r
-//// This file is part of the Ethernet IP core project ////\r
-//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////\r
-//// ////\r
-//// Author(s): ////\r
-//// - Jon Gao (gaojon@yahoo.com) ////\r
-//// ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// Copyright (C) 2001 Authors ////\r
-//// ////\r
-//// This source file may be used and distributed without ////\r
-//// restriction provided that this copyright statement is not ////\r
-//// removed from the file and that any derivative work contains ////\r
-//// the original copyright notice and the associated disclaimer. ////\r
-//// ////\r
-//// This source file is free software; you can redistribute it ////\r
-//// and/or modify it under the terms of the GNU Lesser General ////\r
-//// Public License as published by the Free Software Foundation; ////\r
-//// either version 2.1 of the License, or (at your option) any ////\r
-//// later version. ////\r
-//// ////\r
-//// This source is distributed in the hope that it will be ////\r
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\r
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\r
-//// PURPOSE. See the GNU Lesser General Public License for more ////\r
-//// details. ////\r
-//// ////\r
-//// You should have received a copy of the GNU Lesser General ////\r
-//// Public License along with this source; if not, download it ////\r
-//// from http://www.opencores.org/lgpl.shtml ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-// \r
-// CVS Revision History \r
-// \r
-// $Log: CLK_DIV2.v,v $\r
-// Revision 1.3 2006/01/19 14:07:56 maverickist\r
-// verification is complete.\r
-//\r
-// Revision 1.2 2005/12/16 06:44:20 Administrator\r
-// replaced tab with space.\r
-// passed 9.6k length frame test.\r
-//\r
-// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator\r
-// no message\r
-// \r
-\r
-\r
-//////////////////////////////////////////////////////////////////////\r
-// This file can only used for simulation .\r
-// You need to replace it with your own element according to technology\r
-//////////////////////////////////////////////////////////////////////\r
-\r
-module eth_clk_div2 (\r
- input Reset,\r
- input IN,\r
- output reg OUT\r
-);\r
-\r
-always @ (posedge IN or posedge Reset)\r
- if (Reset)\r
- OUT <= 0;\r
- else\r
- OUT <= ~OUT;\r
- \r
-endmodule\r
+++ /dev/null
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// eth_clk_switch.v ////\r
-//// ////\r
-//// This file is part of the Ethernet IP core project ////\r
-//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////\r
-//// ////\r
-//// Author(s): ////\r
-//// - Jon Gao (gaojon@yahoo.com) ////\r
-//// ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// Copyright (C) 2001 Authors ////\r
-//// ////\r
-//// This source file may be used and distributed without ////\r
-//// restriction provided that this copyright statement is not ////\r
-//// removed from the file and that any derivative work contains ////\r
-//// the original copyright notice and the associated disclaimer. ////\r
-//// ////\r
-//// This source file is free software; you can redistribute it ////\r
-//// and/or modify it under the terms of the GNU Lesser General ////\r
-//// Public License as published by the Free Software Foundation; ////\r
-//// either version 2.1 of the License, or (at your option) any ////\r
-//// later version. ////\r
-//// ////\r
-//// This source is distributed in the hope that it will be ////\r
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\r
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\r
-//// PURPOSE. See the GNU Lesser General Public License for more ////\r
-//// details. ////\r
-//// ////\r
-//// You should have received a copy of the GNU Lesser General ////\r
-//// Public License along with this source; if not, download it ////\r
-//// from http://www.opencores.org/lgpl.shtml ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-// \r
-// CVS Revision History \r
-// \r
-// $Log: CLK_SWITCH.v,v $\r
-// Revision 1.3 2006/01/19 14:07:56 maverickist\r
-// verification is complete.\r
-//\r
-// Revision 1.2 2005/12/16 06:44:20 Administrator\r
-// replaced tab with space.\r
-// passed 9.6k length frame test.\r
-//\r
-// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator\r
-// no message\r
-// \r
-\r
-`include "header.vh"\r
-\r
-//////////////////////////////////////////////////////////////////////\r
-// This file can only used for simulation .\r
-// You need to replace it with your own element according to technology\r
-//////////////////////////////////////////////////////////////////////\r
-module eth_clk_switch (\r
- input IN_0,\r
- input IN_1,\r
- input SW,\r
- output OUT \r
-);\r
-\r
-`ifdef MAC_TARGET_XILINX\r
-\r
- BUFGMUX U_BUFGMUX (\r
- .O ( OUT ),\r
- .I0( IN_0 ),\r
- .I1( IN_1 ),\r
- .S ( SW )\r
- );\r
-\r
-`else\r
-\r
- assign OUT = SW ? IN_1 : IN_0;\r
-\r
-`endif\r
-\r
-endmodule\r
+++ /dev/null
-// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/BUFGMUX.v,v 1.9.34.2 2005/10/21 20:45:30 wloo Exp $
-///////////////////////////////////////////////////////////////////////////////
-// Copyright (c) 1995/2004 Xilinx, Inc.
-// All Right Reserved.
-///////////////////////////////////////////////////////////////////////////////
-// ____ ____
-// / /\/ /
-// /___/ \ / Vendor : Xilinx
-// \ \ \/ Version : 7.1i (H.19)
-// \ \ Description : Xilinx Functional Simulation Library Component
-// / / Global Clock Mux Buffer with Output State 0
-// /___/ /\ Filename : BUFGMUX.v
-// \ \ / \ Timestamp : Thu Mar 25 16:42:14 PST 2004
-// \___\/\___\
-//
-// Revision:
-// 03/23/04 - Initial version.
-
-`timescale 100 ps / 10 ps
-
-module BUFGMUX (O, I0, I1, S);
-
- output O;
-
- input I0, I1, S;
-
- reg q0, q1;
- reg q0_enable, q1_enable;
-
- tri0 GSR = glbl.GSR;
-
- bufif1 B0 (O, I0, q0);
- bufif1 B1 (O, I1, q1);
- pulldown P1 (O);
-
- always @(GSR or I0 or S or q0_enable)
- if (GSR)
- q0 <= 1;
- else if (!I0)
- q0 <= !S && q0_enable;
-
- always @(GSR or I1 or S or q1_enable)
- if (GSR)
- q1 <= 0;
- else if (!I1)
- q1 <= S && q1_enable;
-
- always @(GSR or q1 or I0)
- if (GSR)
- q0_enable <= 1;
- else if (q1)
- q0_enable <= 0;
- else if (I0)
- q0_enable <= !q1;
-
- always @(GSR or q0 or I1)
- if (GSR)
- q1_enable <= 0;
- else if (q0)
- q1_enable <= 0;
- else if (I1)
- q1_enable <= !q0;
-
-endmodule
+++ /dev/null
-// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S36_S36.v,v 1.9 2005/03/14 22:54:41 wloo Exp $
-///////////////////////////////////////////////////////////////////////////////
-// Copyright (c) 1995/2005 Xilinx, Inc.
-// All Right Reserved.
-///////////////////////////////////////////////////////////////////////////////
-// ____ ____
-// / /\/ /
-// /___/ \ / Vendor : Xilinx
-// \ \ \/ Version : 8.1i (I.13)
-// \ \ Description : Xilinx Functional Simulation Library Component
-// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
-// /___/ /\ Filename : RAMB16_S36_S36.v
-// \ \ / \ Timestamp : Thu Mar 10 16:43:36 PST 2005
-// \___\/\___\
-//
-// Revision:
-// 03/23/04 - Initial version.
-// End Revision
-
-`ifdef legacy_model
-
-`timescale 1 ps / 1 ps
-
-module RAMB16_S36_S36 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
-
- parameter INIT_A = 36'h0;
- parameter INIT_B = 36'h0;
- parameter SRVAL_A = 36'h0;
- parameter SRVAL_B = 36'h0;
- parameter WRITE_MODE_A = "WRITE_FIRST";
- parameter WRITE_MODE_B = "WRITE_FIRST";
- parameter SIM_COLLISION_CHECK = "ALL";
- localparam SETUP_ALL = 1000;
- localparam SETUP_READ_FIRST = 3000;
-
- parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-
- output [31:0] DOA;
- output [3:0] DOPA;
- reg [31:0] doa_out;
- reg [3:0] dopa_out;
- wire doa_out0, doa_out1, doa_out2, doa_out3, doa_out4, doa_out5, doa_out6, doa_out7, doa_out8, doa_out9, doa_out10, doa_out11, doa_out12, doa_out13, doa_out14, doa_out15, doa_out16, doa_out17, doa_out18, doa_out19, doa_out20, doa_out21, doa_out22, doa_out23, doa_out24, doa_out25, doa_out26, doa_out27, doa_out28, doa_out29, doa_out30, doa_out31;
- wire dopa0_out, dopa1_out, dopa2_out, dopa3_out;
-
- input [8:0] ADDRA;
- input [31:0] DIA;
- input [3:0] DIPA;
- input ENA, CLKA, WEA, SSRA;
-
- output [31:0] DOB;
- output [3:0] DOPB;
- reg [31:0] dob_out;
- reg [3:0] dopb_out;
- wire dob_out0, dob_out1, dob_out2, dob_out3, dob_out4, dob_out5, dob_out6, dob_out7, dob_out8, dob_out9, dob_out10, dob_out11, dob_out12, dob_out13, dob_out14, dob_out15, dob_out16, dob_out17, dob_out18, dob_out19, dob_out20, dob_out21, dob_out22, dob_out23, dob_out24, dob_out25, dob_out26, dob_out27, dob_out28, dob_out29, dob_out30, dob_out31;
- wire dopb0_out, dopb1_out, dopb2_out, dopb3_out;
-
- input [8:0] ADDRB;
- input [31:0] DIB;
- input [3:0] DIPB;
- input ENB, CLKB, WEB, SSRB;
-
- reg [18431:0] mem;
- reg [8:0] count;
- reg [1:0] wr_mode_a, wr_mode_b;
-
- reg [5:0] dmi, dbi;
- reg [5:0] pmi, pbi;
-
- wire [8:0] addra_int;
- reg [8:0] addra_reg;
- wire [31:0] dia_int;
- wire [3:0] dipa_int;
- wire ena_int, clka_int, wea_int, ssra_int;
- reg ena_reg, wea_reg, ssra_reg;
- wire [8:0] addrb_int;
- reg [8:0] addrb_reg;
- wire [31:0] dib_int;
- wire [3:0] dipb_int;
- wire enb_int, clkb_int, web_int, ssrb_int;
- reg display_flag;
- reg enb_reg, web_reg, ssrb_reg;
-
- time time_clka, time_clkb;
- time time_clka_clkb;
- time time_clkb_clka;
-
- reg setup_all_a_b;
- reg setup_all_b_a;
- reg setup_zero;
- reg setup_rf_a_b;
- reg setup_rf_b_a;
- reg [1:0] data_collision, data_collision_a_b, data_collision_b_a;
- reg memory_collision, memory_collision_a_b, memory_collision_b_a;
- reg address_collision, address_collision_a_b, address_collision_b_a;
- reg change_clka;
- reg change_clkb;
-
- wire [14:0] data_addra_int;
- wire [14:0] data_addra_reg;
- wire [14:0] data_addrb_int;
- wire [14:0] data_addrb_reg;
- wire [15:0] parity_addra_int;
- wire [15:0] parity_addra_reg;
- wire [15:0] parity_addrb_int;
- wire [15:0] parity_addrb_reg;
-
- tri0 GSR = glbl.GSR;
-
- always @(GSR)
- if (GSR) begin
- assign doa_out = INIT_A[31:0];
- assign dopa_out = INIT_A[35:32];
- assign dob_out = INIT_B[31:0];
- assign dopb_out = INIT_B[35:32];
- end
- else begin
- deassign doa_out;
- deassign dopa_out;
- deassign dob_out;
- deassign dopb_out;
- end
-
- buf b_doa_out0 (doa_out0, doa_out[0]);
- buf b_doa_out1 (doa_out1, doa_out[1]);
- buf b_doa_out2 (doa_out2, doa_out[2]);
- buf b_doa_out3 (doa_out3, doa_out[3]);
- buf b_doa_out4 (doa_out4, doa_out[4]);
- buf b_doa_out5 (doa_out5, doa_out[5]);
- buf b_doa_out6 (doa_out6, doa_out[6]);
- buf b_doa_out7 (doa_out7, doa_out[7]);
- buf b_doa_out8 (doa_out8, doa_out[8]);
- buf b_doa_out9 (doa_out9, doa_out[9]);
- buf b_doa_out10 (doa_out10, doa_out[10]);
- buf b_doa_out11 (doa_out11, doa_out[11]);
- buf b_doa_out12 (doa_out12, doa_out[12]);
- buf b_doa_out13 (doa_out13, doa_out[13]);
- buf b_doa_out14 (doa_out14, doa_out[14]);
- buf b_doa_out15 (doa_out15, doa_out[15]);
- buf b_doa_out16 (doa_out16, doa_out[16]);
- buf b_doa_out17 (doa_out17, doa_out[17]);
- buf b_doa_out18 (doa_out18, doa_out[18]);
- buf b_doa_out19 (doa_out19, doa_out[19]);
- buf b_doa_out20 (doa_out20, doa_out[20]);
- buf b_doa_out21 (doa_out21, doa_out[21]);
- buf b_doa_out22 (doa_out22, doa_out[22]);
- buf b_doa_out23 (doa_out23, doa_out[23]);
- buf b_doa_out24 (doa_out24, doa_out[24]);
- buf b_doa_out25 (doa_out25, doa_out[25]);
- buf b_doa_out26 (doa_out26, doa_out[26]);
- buf b_doa_out27 (doa_out27, doa_out[27]);
- buf b_doa_out28 (doa_out28, doa_out[28]);
- buf b_doa_out29 (doa_out29, doa_out[29]);
- buf b_doa_out30 (doa_out30, doa_out[30]);
- buf b_doa_out31 (doa_out31, doa_out[31]);
- buf b_dopa_out0 (dopa_out0, dopa_out[0]);
- buf b_dopa_out1 (dopa_out1, dopa_out[1]);
- buf b_dopa_out2 (dopa_out2, dopa_out[2]);
- buf b_dopa_out3 (dopa_out3, dopa_out[3]);
- buf b_dob_out0 (dob_out0, dob_out[0]);
- buf b_dob_out1 (dob_out1, dob_out[1]);
- buf b_dob_out2 (dob_out2, dob_out[2]);
- buf b_dob_out3 (dob_out3, dob_out[3]);
- buf b_dob_out4 (dob_out4, dob_out[4]);
- buf b_dob_out5 (dob_out5, dob_out[5]);
- buf b_dob_out6 (dob_out6, dob_out[6]);
- buf b_dob_out7 (dob_out7, dob_out[7]);
- buf b_dob_out8 (dob_out8, dob_out[8]);
- buf b_dob_out9 (dob_out9, dob_out[9]);
- buf b_dob_out10 (dob_out10, dob_out[10]);
- buf b_dob_out11 (dob_out11, dob_out[11]);
- buf b_dob_out12 (dob_out12, dob_out[12]);
- buf b_dob_out13 (dob_out13, dob_out[13]);
- buf b_dob_out14 (dob_out14, dob_out[14]);
- buf b_dob_out15 (dob_out15, dob_out[15]);
- buf b_dob_out16 (dob_out16, dob_out[16]);
- buf b_dob_out17 (dob_out17, dob_out[17]);
- buf b_dob_out18 (dob_out18, dob_out[18]);
- buf b_dob_out19 (dob_out19, dob_out[19]);
- buf b_dob_out20 (dob_out20, dob_out[20]);
- buf b_dob_out21 (dob_out21, dob_out[21]);
- buf b_dob_out22 (dob_out22, dob_out[22]);
- buf b_dob_out23 (dob_out23, dob_out[23]);
- buf b_dob_out24 (dob_out24, dob_out[24]);
- buf b_dob_out25 (dob_out25, dob_out[25]);
- buf b_dob_out26 (dob_out26, dob_out[26]);
- buf b_dob_out27 (dob_out27, dob_out[27]);
- buf b_dob_out28 (dob_out28, dob_out[28]);
- buf b_dob_out29 (dob_out29, dob_out[29]);
- buf b_dob_out30 (dob_out30, dob_out[30]);
- buf b_dob_out31 (dob_out31, dob_out[31]);
- buf b_dopb_out0 (dopb_out0, dopb_out[0]);
- buf b_dopb_out1 (dopb_out1, dopb_out[1]);
- buf b_dopb_out2 (dopb_out2, dopb_out[2]);
- buf b_dopb_out3 (dopb_out3, dopb_out[3]);
-
- buf b_doa0 (DOA[0], doa_out0);
- buf b_doa1 (DOA[1], doa_out1);
- buf b_doa2 (DOA[2], doa_out2);
- buf b_doa3 (DOA[3], doa_out3);
- buf b_doa4 (DOA[4], doa_out4);
- buf b_doa5 (DOA[5], doa_out5);
- buf b_doa6 (DOA[6], doa_out6);
- buf b_doa7 (DOA[7], doa_out7);
- buf b_doa8 (DOA[8], doa_out8);
- buf b_doa9 (DOA[9], doa_out9);
- buf b_doa10 (DOA[10], doa_out10);
- buf b_doa11 (DOA[11], doa_out11);
- buf b_doa12 (DOA[12], doa_out12);
- buf b_doa13 (DOA[13], doa_out13);
- buf b_doa14 (DOA[14], doa_out14);
- buf b_doa15 (DOA[15], doa_out15);
- buf b_doa16 (DOA[16], doa_out16);
- buf b_doa17 (DOA[17], doa_out17);
- buf b_doa18 (DOA[18], doa_out18);
- buf b_doa19 (DOA[19], doa_out19);
- buf b_doa20 (DOA[20], doa_out20);
- buf b_doa21 (DOA[21], doa_out21);
- buf b_doa22 (DOA[22], doa_out22);
- buf b_doa23 (DOA[23], doa_out23);
- buf b_doa24 (DOA[24], doa_out24);
- buf b_doa25 (DOA[25], doa_out25);
- buf b_doa26 (DOA[26], doa_out26);
- buf b_doa27 (DOA[27], doa_out27);
- buf b_doa28 (DOA[28], doa_out28);
- buf b_doa29 (DOA[29], doa_out29);
- buf b_doa30 (DOA[30], doa_out30);
- buf b_doa31 (DOA[31], doa_out31);
- buf b_dopa0 (DOPA[0], dopa_out0);
- buf b_dopa1 (DOPA[1], dopa_out1);
- buf b_dopa2 (DOPA[2], dopa_out2);
- buf b_dopa3 (DOPA[3], dopa_out3);
- buf b_dob0 (DOB[0], dob_out0);
- buf b_dob1 (DOB[1], dob_out1);
- buf b_dob2 (DOB[2], dob_out2);
- buf b_dob3 (DOB[3], dob_out3);
- buf b_dob4 (DOB[4], dob_out4);
- buf b_dob5 (DOB[5], dob_out5);
- buf b_dob6 (DOB[6], dob_out6);
- buf b_dob7 (DOB[7], dob_out7);
- buf b_dob8 (DOB[8], dob_out8);
- buf b_dob9 (DOB[9], dob_out9);
- buf b_dob10 (DOB[10], dob_out10);
- buf b_dob11 (DOB[11], dob_out11);
- buf b_dob12 (DOB[12], dob_out12);
- buf b_dob13 (DOB[13], dob_out13);
- buf b_dob14 (DOB[14], dob_out14);
- buf b_dob15 (DOB[15], dob_out15);
- buf b_dob16 (DOB[16], dob_out16);
- buf b_dob17 (DOB[17], dob_out17);
- buf b_dob18 (DOB[18], dob_out18);
- buf b_dob19 (DOB[19], dob_out19);
- buf b_dob20 (DOB[20], dob_out20);
- buf b_dob21 (DOB[21], dob_out21);
- buf b_dob22 (DOB[22], dob_out22);
- buf b_dob23 (DOB[23], dob_out23);
- buf b_dob24 (DOB[24], dob_out24);
- buf b_dob25 (DOB[25], dob_out25);
- buf b_dob26 (DOB[26], dob_out26);
- buf b_dob27 (DOB[27], dob_out27);
- buf b_dob28 (DOB[28], dob_out28);
- buf b_dob29 (DOB[29], dob_out29);
- buf b_dob30 (DOB[30], dob_out30);
- buf b_dob31 (DOB[31], dob_out31);
- buf b_dopb0 (DOPB[0], dopb_out0);
- buf b_dopb1 (DOPB[1], dopb_out1);
- buf b_dopb2 (DOPB[2], dopb_out2);
- buf b_dopb3 (DOPB[3], dopb_out3);
-
- buf b_addra_0 (addra_int[0], ADDRA[0]);
- buf b_addra_1 (addra_int[1], ADDRA[1]);
- buf b_addra_2 (addra_int[2], ADDRA[2]);
- buf b_addra_3 (addra_int[3], ADDRA[3]);
- buf b_addra_4 (addra_int[4], ADDRA[4]);
- buf b_addra_5 (addra_int[5], ADDRA[5]);
- buf b_addra_6 (addra_int[6], ADDRA[6]);
- buf b_addra_7 (addra_int[7], ADDRA[7]);
- buf b_addra_8 (addra_int[8], ADDRA[8]);
- buf b_dia_0 (dia_int[0], DIA[0]);
- buf b_dia_1 (dia_int[1], DIA[1]);
- buf b_dia_2 (dia_int[2], DIA[2]);
- buf b_dia_3 (dia_int[3], DIA[3]);
- buf b_dia_4 (dia_int[4], DIA[4]);
- buf b_dia_5 (dia_int[5], DIA[5]);
- buf b_dia_6 (dia_int[6], DIA[6]);
- buf b_dia_7 (dia_int[7], DIA[7]);
- buf b_dia_8 (dia_int[8], DIA[8]);
- buf b_dia_9 (dia_int[9], DIA[9]);
- buf b_dia_10 (dia_int[10], DIA[10]);
- buf b_dia_11 (dia_int[11], DIA[11]);
- buf b_dia_12 (dia_int[12], DIA[12]);
- buf b_dia_13 (dia_int[13], DIA[13]);
- buf b_dia_14 (dia_int[14], DIA[14]);
- buf b_dia_15 (dia_int[15], DIA[15]);
- buf b_dia_16 (dia_int[16], DIA[16]);
- buf b_dia_17 (dia_int[17], DIA[17]);
- buf b_dia_18 (dia_int[18], DIA[18]);
- buf b_dia_19 (dia_int[19], DIA[19]);
- buf b_dia_20 (dia_int[20], DIA[20]);
- buf b_dia_21 (dia_int[21], DIA[21]);
- buf b_dia_22 (dia_int[22], DIA[22]);
- buf b_dia_23 (dia_int[23], DIA[23]);
- buf b_dia_24 (dia_int[24], DIA[24]);
- buf b_dia_25 (dia_int[25], DIA[25]);
- buf b_dia_26 (dia_int[26], DIA[26]);
- buf b_dia_27 (dia_int[27], DIA[27]);
- buf b_dia_28 (dia_int[28], DIA[28]);
- buf b_dia_29 (dia_int[29], DIA[29]);
- buf b_dia_30 (dia_int[30], DIA[30]);
- buf b_dia_31 (dia_int[31], DIA[31]);
- buf b_dipa_0 (dipa_int[0], DIPA[0]);
- buf b_dipa_1 (dipa_int[1], DIPA[1]);
- buf b_dipa_2 (dipa_int[2], DIPA[2]);
- buf b_dipa_3 (dipa_int[3], DIPA[3]);
- buf b_ena (ena_int, ENA);
- buf b_clka (clka_int, CLKA);
- buf b_ssra (ssra_int, SSRA);
- buf b_wea (wea_int, WEA);
- buf b_addrb_0 (addrb_int[0], ADDRB[0]);
- buf b_addrb_1 (addrb_int[1], ADDRB[1]);
- buf b_addrb_2 (addrb_int[2], ADDRB[2]);
- buf b_addrb_3 (addrb_int[3], ADDRB[3]);
- buf b_addrb_4 (addrb_int[4], ADDRB[4]);
- buf b_addrb_5 (addrb_int[5], ADDRB[5]);
- buf b_addrb_6 (addrb_int[6], ADDRB[6]);
- buf b_addrb_7 (addrb_int[7], ADDRB[7]);
- buf b_addrb_8 (addrb_int[8], ADDRB[8]);
- buf b_dib_0 (dib_int[0], DIB[0]);
- buf b_dib_1 (dib_int[1], DIB[1]);
- buf b_dib_2 (dib_int[2], DIB[2]);
- buf b_dib_3 (dib_int[3], DIB[3]);
- buf b_dib_4 (dib_int[4], DIB[4]);
- buf b_dib_5 (dib_int[5], DIB[5]);
- buf b_dib_6 (dib_int[6], DIB[6]);
- buf b_dib_7 (dib_int[7], DIB[7]);
- buf b_dib_8 (dib_int[8], DIB[8]);
- buf b_dib_9 (dib_int[9], DIB[9]);
- buf b_dib_10 (dib_int[10], DIB[10]);
- buf b_dib_11 (dib_int[11], DIB[11]);
- buf b_dib_12 (dib_int[12], DIB[12]);
- buf b_dib_13 (dib_int[13], DIB[13]);
- buf b_dib_14 (dib_int[14], DIB[14]);
- buf b_dib_15 (dib_int[15], DIB[15]);
- buf b_dib_16 (dib_int[16], DIB[16]);
- buf b_dib_17 (dib_int[17], DIB[17]);
- buf b_dib_18 (dib_int[18], DIB[18]);
- buf b_dib_19 (dib_int[19], DIB[19]);
- buf b_dib_20 (dib_int[20], DIB[20]);
- buf b_dib_21 (dib_int[21], DIB[21]);
- buf b_dib_22 (dib_int[22], DIB[22]);
- buf b_dib_23 (dib_int[23], DIB[23]);
- buf b_dib_24 (dib_int[24], DIB[24]);
- buf b_dib_25 (dib_int[25], DIB[25]);
- buf b_dib_26 (dib_int[26], DIB[26]);
- buf b_dib_27 (dib_int[27], DIB[27]);
- buf b_dib_28 (dib_int[28], DIB[28]);
- buf b_dib_29 (dib_int[29], DIB[29]);
- buf b_dib_30 (dib_int[30], DIB[30]);
- buf b_dib_31 (dib_int[31], DIB[31]);
- buf b_dipb_0 (dipb_int[0], DIPB[0]);
- buf b_dipb_1 (dipb_int[1], DIPB[1]);
- buf b_dipb_2 (dipb_int[2], DIPB[2]);
- buf b_dipb_3 (dipb_int[3], DIPB[3]);
- buf b_enb (enb_int, ENB);
- buf b_clkb (clkb_int, CLKB);
- buf b_ssrb (ssrb_int, SSRB);
- buf b_web (web_int, WEB);
-
- initial begin
- for (count = 0; count < 256; count = count + 1) begin
- mem[count] <= INIT_00[count];
- mem[256 * 1 + count] <= INIT_01[count];
- mem[256 * 2 + count] <= INIT_02[count];
- mem[256 * 3 + count] <= INIT_03[count];
- mem[256 * 4 + count] <= INIT_04[count];
- mem[256 * 5 + count] <= INIT_05[count];
- mem[256 * 6 + count] <= INIT_06[count];
- mem[256 * 7 + count] <= INIT_07[count];
- mem[256 * 8 + count] <= INIT_08[count];
- mem[256 * 9 + count] <= INIT_09[count];
- mem[256 * 10 + count] <= INIT_0A[count];
- mem[256 * 11 + count] <= INIT_0B[count];
- mem[256 * 12 + count] <= INIT_0C[count];
- mem[256 * 13 + count] <= INIT_0D[count];
- mem[256 * 14 + count] <= INIT_0E[count];
- mem[256 * 15 + count] <= INIT_0F[count];
- mem[256 * 16 + count] <= INIT_10[count];
- mem[256 * 17 + count] <= INIT_11[count];
- mem[256 * 18 + count] <= INIT_12[count];
- mem[256 * 19 + count] <= INIT_13[count];
- mem[256 * 20 + count] <= INIT_14[count];
- mem[256 * 21 + count] <= INIT_15[count];
- mem[256 * 22 + count] <= INIT_16[count];
- mem[256 * 23 + count] <= INIT_17[count];
- mem[256 * 24 + count] <= INIT_18[count];
- mem[256 * 25 + count] <= INIT_19[count];
- mem[256 * 26 + count] <= INIT_1A[count];
- mem[256 * 27 + count] <= INIT_1B[count];
- mem[256 * 28 + count] <= INIT_1C[count];
- mem[256 * 29 + count] <= INIT_1D[count];
- mem[256 * 30 + count] <= INIT_1E[count];
- mem[256 * 31 + count] <= INIT_1F[count];
- mem[256 * 32 + count] <= INIT_20[count];
- mem[256 * 33 + count] <= INIT_21[count];
- mem[256 * 34 + count] <= INIT_22[count];
- mem[256 * 35 + count] <= INIT_23[count];
- mem[256 * 36 + count] <= INIT_24[count];
- mem[256 * 37 + count] <= INIT_25[count];
- mem[256 * 38 + count] <= INIT_26[count];
- mem[256 * 39 + count] <= INIT_27[count];
- mem[256 * 40 + count] <= INIT_28[count];
- mem[256 * 41 + count] <= INIT_29[count];
- mem[256 * 42 + count] <= INIT_2A[count];
- mem[256 * 43 + count] <= INIT_2B[count];
- mem[256 * 44 + count] <= INIT_2C[count];
- mem[256 * 45 + count] <= INIT_2D[count];
- mem[256 * 46 + count] <= INIT_2E[count];
- mem[256 * 47 + count] <= INIT_2F[count];
- mem[256 * 48 + count] <= INIT_30[count];
- mem[256 * 49 + count] <= INIT_31[count];
- mem[256 * 50 + count] <= INIT_32[count];
- mem[256 * 51 + count] <= INIT_33[count];
- mem[256 * 52 + count] <= INIT_34[count];
- mem[256 * 53 + count] <= INIT_35[count];
- mem[256 * 54 + count] <= INIT_36[count];
- mem[256 * 55 + count] <= INIT_37[count];
- mem[256 * 56 + count] <= INIT_38[count];
- mem[256 * 57 + count] <= INIT_39[count];
- mem[256 * 58 + count] <= INIT_3A[count];
- mem[256 * 59 + count] <= INIT_3B[count];
- mem[256 * 60 + count] <= INIT_3C[count];
- mem[256 * 61 + count] <= INIT_3D[count];
- mem[256 * 62 + count] <= INIT_3E[count];
- mem[256 * 63 + count] <= INIT_3F[count];
- mem[256 * 64 + count] <= INITP_00[count];
- mem[256 * 65 + count] <= INITP_01[count];
- mem[256 * 66 + count] <= INITP_02[count];
- mem[256 * 67 + count] <= INITP_03[count];
- mem[256 * 68 + count] <= INITP_04[count];
- mem[256 * 69 + count] <= INITP_05[count];
- mem[256 * 70 + count] <= INITP_06[count];
- mem[256 * 71 + count] <= INITP_07[count];
- end
- address_collision <= 0;
- address_collision_a_b <= 0;
- address_collision_b_a <= 0;
- change_clka <= 0;
- change_clkb <= 0;
- data_collision <= 0;
- data_collision_a_b <= 0;
- data_collision_b_a <= 0;
- memory_collision <= 0;
- memory_collision_a_b <= 0;
- memory_collision_b_a <= 0;
- setup_all_a_b <= 0;
- setup_all_b_a <= 0;
- setup_zero <= 0;
- setup_rf_a_b <= 0;
- setup_rf_b_a <= 0;
- end
-
- assign data_addra_int = addra_int * 32;
- assign data_addra_reg = addra_reg * 32;
- assign data_addrb_int = addrb_int * 32;
- assign data_addrb_reg = addrb_reg * 32;
- assign parity_addra_int = 16384 + addra_int * 4;
- assign parity_addra_reg = 16384 + addra_reg * 4;
- assign parity_addrb_int = 16384 + addrb_int * 4;
- assign parity_addrb_reg = 16384 + addrb_reg * 4;
-
-
- initial begin
-
- display_flag = 1;
-
- case (SIM_COLLISION_CHECK)
-
- "NONE" : begin
- assign setup_all_a_b = 1'b0;
- assign setup_all_b_a = 1'b0;
- assign setup_zero = 1'b0;
- assign setup_rf_a_b = 1'b0;
- assign setup_rf_b_a = 1'b0;
- assign display_flag = 0;
- end
- "WARNING_ONLY" : begin
- assign data_collision = 2'b00;
- assign data_collision_a_b = 2'b00;
- assign data_collision_b_a = 2'b00;
- assign memory_collision = 1'b0;
- assign memory_collision_a_b = 1'b0;
- assign memory_collision_b_a = 1'b0;
- end
- "GENERATE_X_ONLY" : begin
- assign display_flag = 0;
- end
- "ALL" : ;
- default : begin
- $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK);
- $finish;
- end
-
- endcase // case(SIM_COLLISION_CHECK)
-
- end // initial begin
-
-
- always @(posedge clka_int) begin
- time_clka = $time;
- #0 time_clkb_clka = time_clka - time_clkb;
- change_clka = ~change_clka;
- end
-
- always @(posedge clkb_int) begin
- time_clkb = $time;
- #0 time_clka_clkb = time_clkb - time_clka;
- change_clkb = ~change_clkb;
- end
-
- always @(change_clkb) begin
- if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL))
- setup_all_a_b = 1;
- if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST))
- setup_rf_a_b = 1;
- end
-
- always @(change_clka) begin
- if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL))
- setup_all_b_a = 1;
- if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST))
- setup_rf_b_a = 1;
- end
-
- always @(change_clkb or change_clka) begin
- if ((time_clkb_clka == 0) && (time_clka_clkb == 0))
- setup_zero = 1;
- end
-
- always @(posedge setup_zero) begin
- if ((ena_int == 1) && (wea_int == 1) &&
- (enb_int == 1) && (web_int == 1) &&
- (data_addra_int[14:5] == data_addrb_int[14:5]))
- memory_collision <= 1;
- end
-
- always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin
- if ((ena_reg == 1) && (wea_reg == 1) &&
- (enb_int == 1) && (web_int == 1) &&
- (data_addra_reg[14:5] == data_addrb_int[14:5]))
- memory_collision_a_b <= 1;
- end
-
- always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin
- if ((ena_int == 1) && (wea_int == 1) &&
- (enb_reg == 1) && (web_reg == 1) &&
- (data_addra_int[14:5] == data_addrb_reg[14:5]))
- memory_collision_b_a <= 1;
- end
-
- always @(posedge setup_all_a_b) begin
- if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin
- if ((ena_reg == 1) && (enb_int == 1)) begin
- case ({wr_mode_a, wr_mode_b, wea_reg, web_int})
- 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
- 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
- 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end
-// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
-// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
-// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
- 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end
- 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end
- 6'b101011 : begin display_wa_wb; end
- 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
-// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
- 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
- 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
-// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
- 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
- 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
-// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
- 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
- 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
- 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
- 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
-// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
-// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
-// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
- 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
- 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
- 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
- endcase
- end
- end
- setup_all_a_b <= 0;
- end
-
-
- always @(posedge setup_all_b_a) begin
- if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin
- if ((ena_int == 1) && (enb_reg == 1)) begin
- case ({wr_mode_a, wr_mode_b, wea_int, web_reg})
- 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
-// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
- 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end
- 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
-// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
- 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end
- 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
- 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
- 6'b101011 : begin display_wa_wb; end
- 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
- 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
- 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
- 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
- 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
- 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
- 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
- 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
- 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
- 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
- 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
- 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
-// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
-// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
-// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
- 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
- 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
- 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
- endcase
- end
- end
- setup_all_b_a <= 0;
- end
-
-
- always @(posedge setup_zero) begin
- if (data_addra_int[14:5] == data_addrb_int[14:5]) begin
- if ((ena_int == 1) && (enb_int == 1)) begin
- case ({wr_mode_a, wr_mode_b, wea_int, web_int})
- 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end
- 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end
- 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end
- 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end
- 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end
- 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end
- 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end
- 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end
- 6'b101011 : begin display_wa_wb; end
- 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end
-// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end
- 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end
- 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end
-// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end
- 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end
- 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end
-// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end
- 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end
- 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end
- 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end
- 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end
-// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end
-// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end
-// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end
- 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end
- 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end
- 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end
- endcase
- end
- end
- setup_zero <= 0;
- end
-
- task display_ra_wb;
- begin
- if (display_flag)
- $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int);
- end
- endtask
-
- task display_wa_rb;
- begin
- if (display_flag)
- $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int);
- end
- endtask
-
- task display_wa_wb;
- begin
- if (display_flag)
- $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int);
- end
- endtask
-
-
- always @(posedge setup_rf_a_b) begin
- if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin
- if ((ena_reg == 1) && (enb_int == 1)) begin
- case ({wr_mode_a, wr_mode_b, wea_reg, web_int})
-// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
-// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
-// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
- 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
- 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
- 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end
-// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
-// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
-// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
-// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
-// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
-// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
-// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
-// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
-// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
-// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
-// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
-// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
-// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
-// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
-// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
- 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
- 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
- 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
-// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
-// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
-// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
- endcase
- end
- end
- setup_rf_a_b <= 0;
- end
-
-
- always @(posedge setup_rf_b_a) begin
- if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin
- if ((ena_int == 1) && (enb_reg == 1)) begin
- case ({wr_mode_a, wr_mode_b, wea_int, web_reg})
-// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
- 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
-// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
-// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
- 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
-// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
-// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
- 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
-// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
-// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
- 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
-// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
-// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
- 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
-// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
-// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
- 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
-// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
-// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
-// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
-// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
-// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
-// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
-// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
-// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
-// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
-// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
- endcase
- end
- end
- setup_rf_b_a <= 0;
- end
-
-
- always @(posedge clka_int) begin
- addra_reg <= addra_int;
- ena_reg <= ena_int;
- ssra_reg <= ssra_int;
- wea_reg <= wea_int;
- end
-
- always @(posedge clkb_int) begin
- addrb_reg <= addrb_int;
- enb_reg <= enb_int;
- ssrb_reg <= ssrb_int;
- web_reg <= web_int;
- end
-
- // Data
- always @(posedge memory_collision) begin
- for (dmi = 0; dmi < 32; dmi = dmi + 1) begin
- mem[data_addra_int + dmi] <= 1'bX;
- end
- memory_collision <= 0;
- end
-
- always @(posedge memory_collision_a_b) begin
- for (dmi = 0; dmi < 32; dmi = dmi + 1) begin
- mem[data_addra_reg + dmi] <= 1'bX;
- end
- memory_collision_a_b <= 0;
- end
-
- always @(posedge memory_collision_b_a) begin
- for (dmi = 0; dmi < 32; dmi = dmi + 1) begin
- mem[data_addra_int + dmi] <= 1'bX;
- end
- memory_collision_b_a <= 0;
- end
-
- always @(posedge data_collision[1]) begin
- if (ssra_int == 0) begin
- doa_out <= 32'bX;
- end
- data_collision[1] <= 0;
- end
-
- always @(posedge data_collision[0]) begin
- if (ssrb_int == 0) begin
- dob_out <= 32'bX;
- end
- data_collision[0] <= 0;
- end
-
- always @(posedge data_collision_a_b[1]) begin
- if (ssra_reg == 0) begin
- doa_out <= 32'bX;
- end
- data_collision_a_b[1] <= 0;
- end
-
- always @(posedge data_collision_a_b[0]) begin
- if (ssrb_int == 0) begin
- dob_out <= 32'bX;
- end
- data_collision_a_b[0] <= 0;
- end
-
- always @(posedge data_collision_b_a[1]) begin
- if (ssra_int == 0) begin
- doa_out <= 32'bX;
- end
- data_collision_b_a[1] <= 0;
- end
-
- always @(posedge data_collision_b_a[0]) begin
- if (ssrb_reg == 0) begin
- dob_out <= 32'bX;
- end
- data_collision_b_a[0] <= 0;
- end
-
-
- // Parity
- always @(posedge memory_collision) begin
- for (pmi = 0; pmi < 4; pmi = pmi + 1) begin
- mem[parity_addra_int + pmi] <= 1'bX;
- end
- end
-
- always @(posedge memory_collision_a_b) begin
- for (pmi = 0; pmi < 4; pmi = pmi + 1) begin
- mem[parity_addra_reg + pmi] <= 1'bX;
- end
- end
-
- always @(posedge memory_collision_b_a) begin
- for (pmi = 0; pmi < 4; pmi = pmi + 1) begin
- mem[parity_addra_int + pmi] <= 1'bX;
- end
- end
-
- always @(posedge data_collision[1]) begin
- if (ssra_int == 0) begin
- dopa_out <= 4'bX;
- end
- end
-
- always @(posedge data_collision[0]) begin
- if (ssrb_int == 0) begin
- dopb_out <= 4'bX;
- end
- end
-
- always @(posedge data_collision_a_b[1]) begin
- if (ssra_reg == 0) begin
- dopa_out <= 4'bX;
- end
- end
-
- always @(posedge data_collision_a_b[0]) begin
- if (ssrb_int == 0) begin
- dopb_out <= 4'bX;
- end
- end
-
- always @(posedge data_collision_b_a[1]) begin
- if (ssra_int == 0) begin
- dopa_out <= 4'bX;
- end
- end
-
- always @(posedge data_collision_b_a[0]) begin
- if (ssrb_reg == 0) begin
- dopb_out <= 4'bX;
- end
- end
-
-
- initial begin
- case (WRITE_MODE_A)
- "WRITE_FIRST" : wr_mode_a <= 2'b00;
- "READ_FIRST" : wr_mode_a <= 2'b01;
- "NO_CHANGE" : wr_mode_a <= 2'b10;
- default : begin
- $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A);
- $finish;
- end
- endcase
- end
-
- initial begin
- case (WRITE_MODE_B)
- "WRITE_FIRST" : wr_mode_b <= 2'b00;
- "READ_FIRST" : wr_mode_b <= 2'b01;
- "NO_CHANGE" : wr_mode_b <= 2'b10;
- default : begin
- $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B);
- $finish;
- end
- endcase
- end
-
- // Port A
- always @(posedge clka_int) begin
- if (ena_int == 1'b1) begin
- if (ssra_int == 1'b1) begin
- doa_out[0] <= SRVAL_A[0];
- doa_out[1] <= SRVAL_A[1];
- doa_out[2] <= SRVAL_A[2];
- doa_out[3] <= SRVAL_A[3];
- doa_out[4] <= SRVAL_A[4];
- doa_out[5] <= SRVAL_A[5];
- doa_out[6] <= SRVAL_A[6];
- doa_out[7] <= SRVAL_A[7];
- doa_out[8] <= SRVAL_A[8];
- doa_out[9] <= SRVAL_A[9];
- doa_out[10] <= SRVAL_A[10];
- doa_out[11] <= SRVAL_A[11];
- doa_out[12] <= SRVAL_A[12];
- doa_out[13] <= SRVAL_A[13];
- doa_out[14] <= SRVAL_A[14];
- doa_out[15] <= SRVAL_A[15];
- doa_out[16] <= SRVAL_A[16];
- doa_out[17] <= SRVAL_A[17];
- doa_out[18] <= SRVAL_A[18];
- doa_out[19] <= SRVAL_A[19];
- doa_out[20] <= SRVAL_A[20];
- doa_out[21] <= SRVAL_A[21];
- doa_out[22] <= SRVAL_A[22];
- doa_out[23] <= SRVAL_A[23];
- doa_out[24] <= SRVAL_A[24];
- doa_out[25] <= SRVAL_A[25];
- doa_out[26] <= SRVAL_A[26];
- doa_out[27] <= SRVAL_A[27];
- doa_out[28] <= SRVAL_A[28];
- doa_out[29] <= SRVAL_A[29];
- doa_out[30] <= SRVAL_A[30];
- doa_out[31] <= SRVAL_A[31];
- dopa_out[0] <= SRVAL_A[32];
- dopa_out[1] <= SRVAL_A[33];
- dopa_out[2] <= SRVAL_A[34];
- dopa_out[3] <= SRVAL_A[35];
- end
- else begin
- if (wea_int == 1'b1) begin
- if (wr_mode_a == 2'b00) begin
- doa_out <= dia_int;
- dopa_out <= dipa_int;
- end
- else if (wr_mode_a == 2'b01) begin
- doa_out[0] <= mem[data_addra_int + 0];
- doa_out[1] <= mem[data_addra_int + 1];
- doa_out[2] <= mem[data_addra_int + 2];
- doa_out[3] <= mem[data_addra_int + 3];
- doa_out[4] <= mem[data_addra_int + 4];
- doa_out[5] <= mem[data_addra_int + 5];
- doa_out[6] <= mem[data_addra_int + 6];
- doa_out[7] <= mem[data_addra_int + 7];
- doa_out[8] <= mem[data_addra_int + 8];
- doa_out[9] <= mem[data_addra_int + 9];
- doa_out[10] <= mem[data_addra_int + 10];
- doa_out[11] <= mem[data_addra_int + 11];
- doa_out[12] <= mem[data_addra_int + 12];
- doa_out[13] <= mem[data_addra_int + 13];
- doa_out[14] <= mem[data_addra_int + 14];
- doa_out[15] <= mem[data_addra_int + 15];
- doa_out[16] <= mem[data_addra_int + 16];
- doa_out[17] <= mem[data_addra_int + 17];
- doa_out[18] <= mem[data_addra_int + 18];
- doa_out[19] <= mem[data_addra_int + 19];
- doa_out[20] <= mem[data_addra_int + 20];
- doa_out[21] <= mem[data_addra_int + 21];
- doa_out[22] <= mem[data_addra_int + 22];
- doa_out[23] <= mem[data_addra_int + 23];
- doa_out[24] <= mem[data_addra_int + 24];
- doa_out[25] <= mem[data_addra_int + 25];
- doa_out[26] <= mem[data_addra_int + 26];
- doa_out[27] <= mem[data_addra_int + 27];
- doa_out[28] <= mem[data_addra_int + 28];
- doa_out[29] <= mem[data_addra_int + 29];
- doa_out[30] <= mem[data_addra_int + 30];
- doa_out[31] <= mem[data_addra_int + 31];
- dopa_out[0] <= mem[parity_addra_int + 0];
- dopa_out[1] <= mem[parity_addra_int + 1];
- dopa_out[2] <= mem[parity_addra_int + 2];
- dopa_out[3] <= mem[parity_addra_int + 3];
- end
- end
- else begin
- doa_out[0] <= mem[data_addra_int + 0];
- doa_out[1] <= mem[data_addra_int + 1];
- doa_out[2] <= mem[data_addra_int + 2];
- doa_out[3] <= mem[data_addra_int + 3];
- doa_out[4] <= mem[data_addra_int + 4];
- doa_out[5] <= mem[data_addra_int + 5];
- doa_out[6] <= mem[data_addra_int + 6];
- doa_out[7] <= mem[data_addra_int + 7];
- doa_out[8] <= mem[data_addra_int + 8];
- doa_out[9] <= mem[data_addra_int + 9];
- doa_out[10] <= mem[data_addra_int + 10];
- doa_out[11] <= mem[data_addra_int + 11];
- doa_out[12] <= mem[data_addra_int + 12];
- doa_out[13] <= mem[data_addra_int + 13];
- doa_out[14] <= mem[data_addra_int + 14];
- doa_out[15] <= mem[data_addra_int + 15];
- doa_out[16] <= mem[data_addra_int + 16];
- doa_out[17] <= mem[data_addra_int + 17];
- doa_out[18] <= mem[data_addra_int + 18];
- doa_out[19] <= mem[data_addra_int + 19];
- doa_out[20] <= mem[data_addra_int + 20];
- doa_out[21] <= mem[data_addra_int + 21];
- doa_out[22] <= mem[data_addra_int + 22];
- doa_out[23] <= mem[data_addra_int + 23];
- doa_out[24] <= mem[data_addra_int + 24];
- doa_out[25] <= mem[data_addra_int + 25];
- doa_out[26] <= mem[data_addra_int + 26];
- doa_out[27] <= mem[data_addra_int + 27];
- doa_out[28] <= mem[data_addra_int + 28];
- doa_out[29] <= mem[data_addra_int + 29];
- doa_out[30] <= mem[data_addra_int + 30];
- doa_out[31] <= mem[data_addra_int + 31];
- dopa_out[0] <= mem[parity_addra_int + 0];
- dopa_out[1] <= mem[parity_addra_int + 1];
- dopa_out[2] <= mem[parity_addra_int + 2];
- dopa_out[3] <= mem[parity_addra_int + 3];
- end
- end
- end
- end
-
- always @(posedge clka_int) begin
- if (ena_int == 1'b1 && wea_int == 1'b1) begin
- mem[data_addra_int + 0] <= dia_int[0];
- mem[data_addra_int + 1] <= dia_int[1];
- mem[data_addra_int + 2] <= dia_int[2];
- mem[data_addra_int + 3] <= dia_int[3];
- mem[data_addra_int + 4] <= dia_int[4];
- mem[data_addra_int + 5] <= dia_int[5];
- mem[data_addra_int + 6] <= dia_int[6];
- mem[data_addra_int + 7] <= dia_int[7];
- mem[data_addra_int + 8] <= dia_int[8];
- mem[data_addra_int + 9] <= dia_int[9];
- mem[data_addra_int + 10] <= dia_int[10];
- mem[data_addra_int + 11] <= dia_int[11];
- mem[data_addra_int + 12] <= dia_int[12];
- mem[data_addra_int + 13] <= dia_int[13];
- mem[data_addra_int + 14] <= dia_int[14];
- mem[data_addra_int + 15] <= dia_int[15];
- mem[data_addra_int + 16] <= dia_int[16];
- mem[data_addra_int + 17] <= dia_int[17];
- mem[data_addra_int + 18] <= dia_int[18];
- mem[data_addra_int + 19] <= dia_int[19];
- mem[data_addra_int + 20] <= dia_int[20];
- mem[data_addra_int + 21] <= dia_int[21];
- mem[data_addra_int + 22] <= dia_int[22];
- mem[data_addra_int + 23] <= dia_int[23];
- mem[data_addra_int + 24] <= dia_int[24];
- mem[data_addra_int + 25] <= dia_int[25];
- mem[data_addra_int + 26] <= dia_int[26];
- mem[data_addra_int + 27] <= dia_int[27];
- mem[data_addra_int + 28] <= dia_int[28];
- mem[data_addra_int + 29] <= dia_int[29];
- mem[data_addra_int + 30] <= dia_int[30];
- mem[data_addra_int + 31] <= dia_int[31];
- mem[parity_addra_int + 0] <= dipa_int[0];
- mem[parity_addra_int + 1] <= dipa_int[1];
- mem[parity_addra_int + 2] <= dipa_int[2];
- mem[parity_addra_int + 3] <= dipa_int[3];
- end
- end
-
- // Port B
- always @(posedge clkb_int) begin
- if (enb_int == 1'b1) begin
- if (ssrb_int == 1'b1) begin
- dob_out[0] <= SRVAL_B[0];
- dob_out[1] <= SRVAL_B[1];
- dob_out[2] <= SRVAL_B[2];
- dob_out[3] <= SRVAL_B[3];
- dob_out[4] <= SRVAL_B[4];
- dob_out[5] <= SRVAL_B[5];
- dob_out[6] <= SRVAL_B[6];
- dob_out[7] <= SRVAL_B[7];
- dob_out[8] <= SRVAL_B[8];
- dob_out[9] <= SRVAL_B[9];
- dob_out[10] <= SRVAL_B[10];
- dob_out[11] <= SRVAL_B[11];
- dob_out[12] <= SRVAL_B[12];
- dob_out[13] <= SRVAL_B[13];
- dob_out[14] <= SRVAL_B[14];
- dob_out[15] <= SRVAL_B[15];
- dob_out[16] <= SRVAL_B[16];
- dob_out[17] <= SRVAL_B[17];
- dob_out[18] <= SRVAL_B[18];
- dob_out[19] <= SRVAL_B[19];
- dob_out[20] <= SRVAL_B[20];
- dob_out[21] <= SRVAL_B[21];
- dob_out[22] <= SRVAL_B[22];
- dob_out[23] <= SRVAL_B[23];
- dob_out[24] <= SRVAL_B[24];
- dob_out[25] <= SRVAL_B[25];
- dob_out[26] <= SRVAL_B[26];
- dob_out[27] <= SRVAL_B[27];
- dob_out[28] <= SRVAL_B[28];
- dob_out[29] <= SRVAL_B[29];
- dob_out[30] <= SRVAL_B[30];
- dob_out[31] <= SRVAL_B[31];
- dopb_out[0] <= SRVAL_B[32];
- dopb_out[1] <= SRVAL_B[33];
- dopb_out[2] <= SRVAL_B[34];
- dopb_out[3] <= SRVAL_B[35];
- end
- else begin
- if (web_int == 1'b1) begin
- if (wr_mode_b == 2'b00) begin
- dob_out <= dib_int;
- dopb_out <= dipb_int;
- end
- else if (wr_mode_b == 2'b01) begin
- dob_out[0] <= mem[data_addrb_int + 0];
- dob_out[1] <= mem[data_addrb_int + 1];
- dob_out[2] <= mem[data_addrb_int + 2];
- dob_out[3] <= mem[data_addrb_int + 3];
- dob_out[4] <= mem[data_addrb_int + 4];
- dob_out[5] <= mem[data_addrb_int + 5];
- dob_out[6] <= mem[data_addrb_int + 6];
- dob_out[7] <= mem[data_addrb_int + 7];
- dob_out[8] <= mem[data_addrb_int + 8];
- dob_out[9] <= mem[data_addrb_int + 9];
- dob_out[10] <= mem[data_addrb_int + 10];
- dob_out[11] <= mem[data_addrb_int + 11];
- dob_out[12] <= mem[data_addrb_int + 12];
- dob_out[13] <= mem[data_addrb_int + 13];
- dob_out[14] <= mem[data_addrb_int + 14];
- dob_out[15] <= mem[data_addrb_int + 15];
- dob_out[16] <= mem[data_addrb_int + 16];
- dob_out[17] <= mem[data_addrb_int + 17];
- dob_out[18] <= mem[data_addrb_int + 18];
- dob_out[19] <= mem[data_addrb_int + 19];
- dob_out[20] <= mem[data_addrb_int + 20];
- dob_out[21] <= mem[data_addrb_int + 21];
- dob_out[22] <= mem[data_addrb_int + 22];
- dob_out[23] <= mem[data_addrb_int + 23];
- dob_out[24] <= mem[data_addrb_int + 24];
- dob_out[25] <= mem[data_addrb_int + 25];
- dob_out[26] <= mem[data_addrb_int + 26];
- dob_out[27] <= mem[data_addrb_int + 27];
- dob_out[28] <= mem[data_addrb_int + 28];
- dob_out[29] <= mem[data_addrb_int + 29];
- dob_out[30] <= mem[data_addrb_int + 30];
- dob_out[31] <= mem[data_addrb_int + 31];
- dopb_out[0] <= mem[parity_addrb_int + 0];
- dopb_out[1] <= mem[parity_addrb_int + 1];
- dopb_out[2] <= mem[parity_addrb_int + 2];
- dopb_out[3] <= mem[parity_addrb_int + 3];
- end
- end
- else begin
- dob_out[0] <= mem[data_addrb_int + 0];
- dob_out[1] <= mem[data_addrb_int + 1];
- dob_out[2] <= mem[data_addrb_int + 2];
- dob_out[3] <= mem[data_addrb_int + 3];
- dob_out[4] <= mem[data_addrb_int + 4];
- dob_out[5] <= mem[data_addrb_int + 5];
- dob_out[6] <= mem[data_addrb_int + 6];
- dob_out[7] <= mem[data_addrb_int + 7];
- dob_out[8] <= mem[data_addrb_int + 8];
- dob_out[9] <= mem[data_addrb_int + 9];
- dob_out[10] <= mem[data_addrb_int + 10];
- dob_out[11] <= mem[data_addrb_int + 11];
- dob_out[12] <= mem[data_addrb_int + 12];
- dob_out[13] <= mem[data_addrb_int + 13];
- dob_out[14] <= mem[data_addrb_int + 14];
- dob_out[15] <= mem[data_addrb_int + 15];
- dob_out[16] <= mem[data_addrb_int + 16];
- dob_out[17] <= mem[data_addrb_int + 17];
- dob_out[18] <= mem[data_addrb_int + 18];
- dob_out[19] <= mem[data_addrb_int + 19];
- dob_out[20] <= mem[data_addrb_int + 20];
- dob_out[21] <= mem[data_addrb_int + 21];
- dob_out[22] <= mem[data_addrb_int + 22];
- dob_out[23] <= mem[data_addrb_int + 23];
- dob_out[24] <= mem[data_addrb_int + 24];
- dob_out[25] <= mem[data_addrb_int + 25];
- dob_out[26] <= mem[data_addrb_int + 26];
- dob_out[27] <= mem[data_addrb_int + 27];
- dob_out[28] <= mem[data_addrb_int + 28];
- dob_out[29] <= mem[data_addrb_int + 29];
- dob_out[30] <= mem[data_addrb_int + 30];
- dob_out[31] <= mem[data_addrb_int + 31];
- dopb_out[0] <= mem[parity_addrb_int + 0];
- dopb_out[1] <= mem[parity_addrb_int + 1];
- dopb_out[2] <= mem[parity_addrb_int + 2];
- dopb_out[3] <= mem[parity_addrb_int + 3];
- end
- end
- end
- end
-
- always @(posedge clkb_int) begin
- if (enb_int == 1'b1 && web_int == 1'b1) begin
- mem[data_addrb_int + 0] <= dib_int[0];
- mem[data_addrb_int + 1] <= dib_int[1];
- mem[data_addrb_int + 2] <= dib_int[2];
- mem[data_addrb_int + 3] <= dib_int[3];
- mem[data_addrb_int + 4] <= dib_int[4];
- mem[data_addrb_int + 5] <= dib_int[5];
- mem[data_addrb_int + 6] <= dib_int[6];
- mem[data_addrb_int + 7] <= dib_int[7];
- mem[data_addrb_int + 8] <= dib_int[8];
- mem[data_addrb_int + 9] <= dib_int[9];
- mem[data_addrb_int + 10] <= dib_int[10];
- mem[data_addrb_int + 11] <= dib_int[11];
- mem[data_addrb_int + 12] <= dib_int[12];
- mem[data_addrb_int + 13] <= dib_int[13];
- mem[data_addrb_int + 14] <= dib_int[14];
- mem[data_addrb_int + 15] <= dib_int[15];
- mem[data_addrb_int + 16] <= dib_int[16];
- mem[data_addrb_int + 17] <= dib_int[17];
- mem[data_addrb_int + 18] <= dib_int[18];
- mem[data_addrb_int + 19] <= dib_int[19];
- mem[data_addrb_int + 20] <= dib_int[20];
- mem[data_addrb_int + 21] <= dib_int[21];
- mem[data_addrb_int + 22] <= dib_int[22];
- mem[data_addrb_int + 23] <= dib_int[23];
- mem[data_addrb_int + 24] <= dib_int[24];
- mem[data_addrb_int + 25] <= dib_int[25];
- mem[data_addrb_int + 26] <= dib_int[26];
- mem[data_addrb_int + 27] <= dib_int[27];
- mem[data_addrb_int + 28] <= dib_int[28];
- mem[data_addrb_int + 29] <= dib_int[29];
- mem[data_addrb_int + 30] <= dib_int[30];
- mem[data_addrb_int + 31] <= dib_int[31];
- mem[parity_addrb_int + 0] <= dipb_int[0];
- mem[parity_addrb_int + 1] <= dipb_int[1];
- mem[parity_addrb_int + 2] <= dipb_int[2];
- mem[parity_addrb_int + 3] <= dipb_int[3];
- end
- end
-
- specify
- (CLKA *> DOA) = (100, 100);
- (CLKA *> DOPA) = (100, 100);
- (CLKB *> DOB) = (100, 100);
- (CLKB *> DOPB) = (100, 100);
- endspecify
-
-endmodule
-
-`else
-
-// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S36_S36.v,v 1.9 2005/03/14 22:54:41 wloo Exp $
-///////////////////////////////////////////////////////////////////////////////
-// Copyright (c) 1995/2005 Xilinx, Inc.
-// All Right Reserved.
-///////////////////////////////////////////////////////////////////////////////
-// ____ ____
-// / /\/ /
-// /___/ \ / Vendor : Xilinx
-// \ \ \/ Version : 8.1i (I.13)
-// \ \ Description : Xilinx Timing Simulation Library Component
-// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
-// /___/ /\ Filename : RAMB16_S36_S36.v
-// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005
-// \___\/\___\
-//
-// Revision:
-// 03/23/04 - Initial version.
-// 03/10/05 - Initialized outputs.
-// End Revision
-
-`timescale 1 ps/1 ps
-
-module RAMB16_S36_S36 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
-
- parameter INIT_A = 36'h0;
- parameter INIT_B = 36'h0;
- parameter SRVAL_A = 36'h0;
- parameter SRVAL_B = 36'h0;
- parameter WRITE_MODE_A = "WRITE_FIRST";
- parameter WRITE_MODE_B = "WRITE_FIRST";
- parameter SIM_COLLISION_CHECK = "ALL";
- localparam SETUP_ALL = 1000;
- localparam SETUP_READ_FIRST = 3000;
-
- parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-
- output [31:0] DOA;
- output [3:0] DOPA;
- output [31:0] DOB;
- output [3:0] DOPB;
-
- input [8:0] ADDRA;
- input [31:0] DIA;
- input [3:0] DIPA;
- input ENA, CLKA, WEA, SSRA;
- input [8:0] ADDRB;
- input [31:0] DIB;
- input [3:0] DIPB;
- input ENB, CLKB, WEB, SSRB;
-
- reg [31:0] doa_out = INIT_A[31:0];
- reg [3:0] dopa_out = INIT_A[35:32];
- reg [31:0] dob_out = INIT_B[31:0];
- reg [3:0] dopb_out = INIT_B[35:32];
-
- reg [31:0] mem [511:0];
- reg [3:0] memp [511:0];
-
- reg [8:0] count, countp;
- reg [1:0] wr_mode_a, wr_mode_b;
-
- reg [5:0] dmi, dbi;
- reg [5:0] pmi, pbi;
-
- wire [8:0] addra_int;
- reg [8:0] addra_reg;
- wire [31:0] dia_int;
- wire [3:0] dipa_int;
- wire ena_int, clka_int, wea_int, ssra_int;
- reg ena_reg, wea_reg, ssra_reg;
- wire [8:0] addrb_int;
- reg [8:0] addrb_reg;
- wire [31:0] dib_int;
- wire [3:0] dipb_int;
- wire enb_int, clkb_int, web_int, ssrb_int;
- reg display_flag, output_flag;
- reg enb_reg, web_reg, ssrb_reg;
-
- time time_clka, time_clkb;
- time time_clka_clkb;
- time time_clkb_clka;
-
- reg setup_all_a_b;
- reg setup_all_b_a;
- reg setup_zero;
- reg setup_rf_a_b;
- reg setup_rf_b_a;
- reg [1:0] data_collision, data_collision_a_b, data_collision_b_a;
- reg memory_collision, memory_collision_a_b, memory_collision_b_a;
- reg change_clka;
- reg change_clkb;
-
- wire [14:0] data_addra_int;
- wire [14:0] data_addra_reg;
- wire [14:0] data_addrb_int;
- wire [14:0] data_addrb_reg;
-
- wire dia_enable = ena_int && wea_int;
- wire dib_enable = enb_int && web_int;
-
- tri0 GSR = glbl.GSR;
- wire gsr_int;
-
- buf b_gsr (gsr_int, GSR);
-
- buf b_doa [31:0] (DOA, doa_out);
- buf b_dopa [3:0] (DOPA, dopa_out);
- buf b_addra [8:0] (addra_int, ADDRA);
- buf b_dia [31:0] (dia_int, DIA);
- buf b_dipa [3:0] (dipa_int, DIPA);
- buf b_ena (ena_int, ENA);
- buf b_clka (clka_int, CLKA);
- buf b_ssra (ssra_int, SSRA);
- buf b_wea (wea_int, WEA);
-
- buf b_dob [31:0] (DOB, dob_out);
- buf b_dopb [3:0] (DOPB, dopb_out);
- buf b_addrb [8:0] (addrb_int, ADDRB);
- buf b_dib [31:0] (dib_int, DIB);
- buf b_dipb [3:0] (dipb_int, DIPB);
- buf b_enb (enb_int, ENB);
- buf b_clkb (clkb_int, CLKB);
- buf b_ssrb (ssrb_int, SSRB);
- buf b_web (web_int, WEB);
-
-
- always @(gsr_int)
- if (gsr_int) begin
- assign {dopa_out, doa_out} = INIT_A;
- assign {dopb_out, dob_out} = INIT_B;
- end
- else begin
- deassign doa_out;
- deassign dopa_out;
- deassign dob_out;
- deassign dopb_out;
- end
-
- initial begin : initialize_mems
-
-`ifdef UNDEFINED
- for (count = 0; count < 8; count = count + 1) begin
- mem[count] = INIT_00[(count * 32) +: 32];
- mem[8 * 1 + count] = INIT_01[(count * 32) +: 32];
- mem[8 * 2 + count] = INIT_02[(count * 32) +: 32];
- mem[8 * 3 + count] = INIT_03[(count * 32) +: 32];
- mem[8 * 4 + count] = INIT_04[(count * 32) +: 32];
- mem[8 * 5 + count] = INIT_05[(count * 32) +: 32];
- mem[8 * 6 + count] = INIT_06[(count * 32) +: 32];
- mem[8 * 7 + count] = INIT_07[(count * 32) +: 32];
- mem[8 * 8 + count] = INIT_08[(count * 32) +: 32];
- mem[8 * 9 + count] = INIT_09[(count * 32) +: 32];
- mem[8 * 10 + count] = INIT_0A[(count * 32) +: 32];
- mem[8 * 11 + count] = INIT_0B[(count * 32) +: 32];
- mem[8 * 12 + count] = INIT_0C[(count * 32) +: 32];
- mem[8 * 13 + count] = INIT_0D[(count * 32) +: 32];
- mem[8 * 14 + count] = INIT_0E[(count * 32) +: 32];
- mem[8 * 15 + count] = INIT_0F[(count * 32) +: 32];
- mem[8 * 16 + count] = INIT_10[(count * 32) +: 32];
- mem[8 * 17 + count] = INIT_11[(count * 32) +: 32];
- mem[8 * 18 + count] = INIT_12[(count * 32) +: 32];
- mem[8 * 19 + count] = INIT_13[(count * 32) +: 32];
- mem[8 * 20 + count] = INIT_14[(count * 32) +: 32];
- mem[8 * 21 + count] = INIT_15[(count * 32) +: 32];
- mem[8 * 22 + count] = INIT_16[(count * 32) +: 32];
- mem[8 * 23 + count] = INIT_17[(count * 32) +: 32];
- mem[8 * 24 + count] = INIT_18[(count * 32) +: 32];
- mem[8 * 25 + count] = INIT_19[(count * 32) +: 32];
- mem[8 * 26 + count] = INIT_1A[(count * 32) +: 32];
- mem[8 * 27 + count] = INIT_1B[(count * 32) +: 32];
- mem[8 * 28 + count] = INIT_1C[(count * 32) +: 32];
- mem[8 * 29 + count] = INIT_1D[(count * 32) +: 32];
- mem[8 * 30 + count] = INIT_1E[(count * 32) +: 32];
- mem[8 * 31 + count] = INIT_1F[(count * 32) +: 32];
- mem[8 * 32 + count] = INIT_20[(count * 32) +: 32];
- mem[8 * 33 + count] = INIT_21[(count * 32) +: 32];
- mem[8 * 34 + count] = INIT_22[(count * 32) +: 32];
- mem[8 * 35 + count] = INIT_23[(count * 32) +: 32];
- mem[8 * 36 + count] = INIT_24[(count * 32) +: 32];
- mem[8 * 37 + count] = INIT_25[(count * 32) +: 32];
- mem[8 * 38 + count] = INIT_26[(count * 32) +: 32];
- mem[8 * 39 + count] = INIT_27[(count * 32) +: 32];
- mem[8 * 40 + count] = INIT_28[(count * 32) +: 32];
- mem[8 * 41 + count] = INIT_29[(count * 32) +: 32];
- mem[8 * 42 + count] = INIT_2A[(count * 32) +: 32];
- mem[8 * 43 + count] = INIT_2B[(count * 32) +: 32];
- mem[8 * 44 + count] = INIT_2C[(count * 32) +: 32];
- mem[8 * 45 + count] = INIT_2D[(count * 32) +: 32];
- mem[8 * 46 + count] = INIT_2E[(count * 32) +: 32];
- mem[8 * 47 + count] = INIT_2F[(count * 32) +: 32];
- mem[8 * 48 + count] = INIT_30[(count * 32) +: 32];
- mem[8 * 49 + count] = INIT_31[(count * 32) +: 32];
- mem[8 * 50 + count] = INIT_32[(count * 32) +: 32];
- mem[8 * 51 + count] = INIT_33[(count * 32) +: 32];
- mem[8 * 52 + count] = INIT_34[(count * 32) +: 32];
- mem[8 * 53 + count] = INIT_35[(count * 32) +: 32];
- mem[8 * 54 + count] = INIT_36[(count * 32) +: 32];
- mem[8 * 55 + count] = INIT_37[(count * 32) +: 32];
- mem[8 * 56 + count] = INIT_38[(count * 32) +: 32];
- mem[8 * 57 + count] = INIT_39[(count * 32) +: 32];
- mem[8 * 58 + count] = INIT_3A[(count * 32) +: 32];
- mem[8 * 59 + count] = INIT_3B[(count * 32) +: 32];
- mem[8 * 60 + count] = INIT_3C[(count * 32) +: 32];
- mem[8 * 61 + count] = INIT_3D[(count * 32) +: 32];
- mem[8 * 62 + count] = INIT_3E[(count * 32) +: 32];
- mem[8 * 63 + count] = INIT_3F[(count * 32) +: 32];
- end
-`else
- integer i;
- for (i = 0; i < 512; i = i + 1)
- begin
- mem[i] = 0;
- memp[i] = 0;
- end
-
-`endif
-
-// initiate parity start
-`ifdef UNDEFINED
- for (countp = 0; countp < 64; countp = countp + 1) begin
- memp[countp] = INITP_00[(countp * 4) +: 4];
- memp[64 * 1 + countp] = INITP_01[(countp * 4) +: 4];
- memp[64 * 2 + countp] = INITP_02[(countp * 4) +: 4];
- memp[64 * 3 + countp] = INITP_03[(countp * 4) +: 4];
- memp[64 * 4 + countp] = INITP_04[(countp * 4) +: 4];
- memp[64 * 5 + countp] = INITP_05[(countp * 4) +: 4];
- memp[64 * 6 + countp] = INITP_06[(countp * 4) +: 4];
- memp[64 * 7 + countp] = INITP_07[(countp * 4) +: 4];
- end
-`endif
-// initiate parity end
-
- change_clka <= 0;
- change_clkb <= 0;
- data_collision <= 0;
- data_collision_a_b <= 0;
- data_collision_b_a <= 0;
- memory_collision <= 0;
- memory_collision_a_b <= 0;
- memory_collision_b_a <= 0;
- setup_all_a_b <= 0;
- setup_all_b_a <= 0;
- setup_zero <= 0;
- setup_rf_a_b <= 0;
- setup_rf_b_a <= 0;
- end
-
- assign data_addra_int = addra_int * 32;
- assign data_addra_reg = addra_reg * 32;
- assign data_addrb_int = addrb_int * 32;
- assign data_addrb_reg = addrb_reg * 32;
-
-
- initial begin
-
- display_flag = 1;
- output_flag = 1;
-
- case (SIM_COLLISION_CHECK)
-
- "NONE" : begin
- output_flag = 0;
- display_flag = 0;
- end
- "WARNING_ONLY" : output_flag = 0;
- "GENERATE_ONLY" : display_flag = 0;
- "ALL" : ;
-
- default : begin
- $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_ONLY.", SIM_COLLISION_CHECK);
- $finish;
- end
-
- endcase // case(SIM_COLLISION_CHECK)
-
- end // initial begin
-
-
- always @(posedge clka_int) begin
- if ((output_flag || display_flag)) begin
- time_clka = $time;
- #0 time_clkb_clka = time_clka - time_clkb;
- change_clka = ~change_clka;
- end
- end
-
- always @(posedge clkb_int) begin
- if ((output_flag || display_flag)) begin
- time_clkb = $time;
- #0 time_clka_clkb = time_clkb - time_clka;
- change_clkb = ~change_clkb;
- end
- end
-
- always @(change_clkb) begin
- if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL))
- setup_all_a_b = 1;
- if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST))
- setup_rf_a_b = 1;
- end
-
- always @(change_clka) begin
- if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL))
- setup_all_b_a = 1;
- if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST))
- setup_rf_b_a = 1;
- end
-
- always @(change_clkb or change_clka) begin
- if ((time_clkb_clka == 0) && (time_clka_clkb == 0))
- setup_zero = 1;
- end
-
- always @(posedge setup_zero) begin
- if ((ena_int == 1) && (wea_int == 1) &&
- (enb_int == 1) && (web_int == 1) &&
- (data_addra_int[14:5] == data_addrb_int[14:5]))
- memory_collision <= 1;
- end
-
- always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin
- if ((ena_reg == 1) && (wea_reg == 1) &&
- (enb_int == 1) && (web_int == 1) &&
- (data_addra_reg[14:5] == data_addrb_int[14:5]))
- memory_collision_a_b <= 1;
- end
-
- always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin
- if ((ena_int == 1) && (wea_int == 1) &&
- (enb_reg == 1) && (web_reg == 1) &&
- (data_addra_int[14:5] == data_addrb_reg[14:5]))
- memory_collision_b_a <= 1;
- end
-
- always @(posedge setup_all_a_b) begin
- if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin
- if ((ena_reg == 1) && (enb_int == 1)) begin
- case ({wr_mode_a, wr_mode_b, wea_reg, web_int})
- 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
- 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
- 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end
-// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
-// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
-// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
- 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end
- 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end
- 6'b101011 : begin display_wa_wb; end
- 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
-// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
- 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
- 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
-// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
- 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
- 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
-// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
- 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
- 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
- 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
- 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
-// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
-// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
-// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
- 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
- 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
- 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
- endcase
- end
- end
- setup_all_a_b <= 0;
- end
-
-
- always @(posedge setup_all_b_a) begin
- if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin
- if ((ena_int == 1) && (enb_reg == 1)) begin
- case ({wr_mode_a, wr_mode_b, wea_int, web_reg})
- 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
-// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
- 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end
- 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
-// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
- 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end
- 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
- 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
- 6'b101011 : begin display_wa_wb; end
- 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
- 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
- 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
- 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
- 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
- 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
- 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
- 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
- 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
- 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
- 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
- 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
-// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
-// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
-// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
- 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
- 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
- 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
- endcase
- end
- end
- setup_all_b_a <= 0;
- end
-
-
- always @(posedge setup_zero) begin
- if (data_addra_int[14:5] == data_addrb_int[14:5]) begin
- if ((ena_int == 1) && (enb_int == 1)) begin
- case ({wr_mode_a, wr_mode_b, wea_int, web_int})
- 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end
- 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end
- 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end
- 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end
- 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end
- 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end
- 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end
- 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end
- 6'b101011 : begin display_wa_wb; end
- 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end
-// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end
- 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end
- 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end
-// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end
- 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end
- 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end
-// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end
- 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end
- 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end
- 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end
- 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end
-// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end
-// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end
-// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end
- 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end
- 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end
- 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end
- endcase
- end
- end
- setup_zero <= 0;
- end
-
- task display_ra_wb;
- begin
- if (display_flag)
- $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int);
- end
- endtask
-
- task display_wa_rb;
- begin
- if (display_flag)
- $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int);
- end
- endtask
-
- task display_wa_wb;
- begin
- if (display_flag)
- $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int);
- end
- endtask
-
-
- always @(posedge setup_rf_a_b) begin
- if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin
- if ((ena_reg == 1) && (enb_int == 1)) begin
- case ({wr_mode_a, wr_mode_b, wea_reg, web_int})
-// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
-// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
-// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
- 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
- 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
- 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end
-// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
-// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
-// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
-// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
-// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
-// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
-// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
-// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
-// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
-// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
-// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
-// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
-// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
-// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
-// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
- 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
- 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
- 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
-// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
-// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
-// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
- endcase
- end
- end
- setup_rf_a_b <= 0;
- end
-
-
- always @(posedge setup_rf_b_a) begin
- if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin
- if ((ena_int == 1) && (enb_reg == 1)) begin
- case ({wr_mode_a, wr_mode_b, wea_int, web_reg})
-// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
- 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
-// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
-// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
- 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
-// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
-// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
- 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
-// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
-// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
- 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
-// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
-// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
- 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
-// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
-// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
- 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
-// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
-// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
-// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
-// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
-// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
-// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
-// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
-// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
-// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
-// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
- endcase
- end
- end
- setup_rf_b_a <= 0;
- end
-
-
- always @(posedge clka_int) begin
- if ((output_flag || display_flag)) begin
- addra_reg <= addra_int;
- ena_reg <= ena_int;
- ssra_reg <= ssra_int;
- wea_reg <= wea_int;
- end
- end
-
- always @(posedge clkb_int) begin
- if ((output_flag || display_flag)) begin
- addrb_reg <= addrb_int;
- enb_reg <= enb_int;
- ssrb_reg <= ssrb_int;
- web_reg <= web_int;
- end
- end
-
-
- // Data
- always @(posedge memory_collision) begin
- if ((output_flag || display_flag)) begin
- mem[addra_int] <= 32'bx;
- memory_collision <= 0;
- end
-
- end
-
- always @(posedge memory_collision_a_b) begin
- if ((output_flag || display_flag)) begin
- mem[addra_reg] <= 32'bx;
- memory_collision_a_b <= 0;
- end
- end
-
- always @(posedge memory_collision_b_a) begin
- if ((output_flag || display_flag)) begin
- mem[addra_int] <= 32'bx;
- memory_collision_b_a <= 0;
- end
- end
-
- always @(posedge data_collision[1]) begin
- if (ssra_int == 0 && output_flag) begin
- doa_out <= #100 32'bX;
- end
- data_collision[1] <= 0;
- end
-
- always @(posedge data_collision[0]) begin
- if (ssrb_int == 0 && output_flag) begin
- dob_out <= #100 32'bX;
- end
- data_collision[0] <= 0;
- end
-
- always @(posedge data_collision_a_b[1]) begin
- if (ssra_reg == 0 && output_flag) begin
- doa_out <= #100 32'bX;
- end
- data_collision_a_b[1] <= 0;
- end
-
- always @(posedge data_collision_a_b[0]) begin
- if (ssrb_int == 0 && output_flag) begin
- dob_out <= #100 32'bX;
- end
- data_collision_a_b[0] <= 0;
- end
-
- always @(posedge data_collision_b_a[1]) begin
- if (ssra_int == 0 && output_flag) begin
- doa_out <= #100 32'bX;
- end
- data_collision_b_a[1] <= 0;
- end
-
- always @(posedge data_collision_b_a[0]) begin
- if (ssrb_reg == 0 && output_flag) begin
- dob_out <= #100 32'bX;
- end
- data_collision_b_a[0] <= 0;
- end
-
-// x parity start
- always @(posedge memory_collision) begin
- if ((output_flag || display_flag))
- memp[addra_int] <= 4'bx;
- end
-
- always @(posedge memory_collision_a_b) begin
- if ((output_flag || display_flag))
- memp[addra_reg] <= 4'bx;
- end
-
- always @(posedge memory_collision_b_a) begin
- if ((output_flag || display_flag))
- memp[addra_int] <= 4'bx;
- end
-
- always @(posedge data_collision[1]) begin
- if (ssra_int == 0 && output_flag) begin
- dopa_out <= #100 4'bX;
- end
- end
-
- always @(posedge data_collision_a_b[1]) begin
- if (ssra_reg == 0 && output_flag) begin
- dopa_out <= #100 4'bX;
- end
- end
-
-
- always @(posedge data_collision_b_a[1]) begin
- if (ssra_int == 0 && output_flag) begin
- dopa_out <= #100 4'bX;
- end
- end
-
- always @(posedge data_collision[0]) begin
- if (ssrb_int == 0 && output_flag) begin
- dopb_out <= #100 4'bx;
- end
- end
-
- always @(posedge data_collision_a_b[0]) begin
- if (ssrb_int == 0 && output_flag) begin
- dopb_out <= #100 4'bx;
- end
- end
-
- always @(posedge data_collision_b_a[0]) begin
- if (ssrb_reg == 0 && output_flag) begin
- dopb_out <= #100 4'bx;
- end
- end
-// x parity end
-
- initial begin
- case (WRITE_MODE_A)
- "WRITE_FIRST" : wr_mode_a <= 2'b00;
- "READ_FIRST" : wr_mode_a <= 2'b01;
- "NO_CHANGE" : wr_mode_a <= 2'b10;
- default : begin
- $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A);
- $finish;
- end
- endcase
- end
-
- initial begin
- case (WRITE_MODE_B)
- "WRITE_FIRST" : wr_mode_b <= 2'b00;
- "READ_FIRST" : wr_mode_b <= 2'b01;
- "NO_CHANGE" : wr_mode_b <= 2'b10;
- default : begin
- $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B);
- $finish;
- end
- endcase
- end
-
-
- // Port A
- always @(posedge clka_int) begin
-
- if (ena_int == 1'b1) begin
-
- if (ssra_int == 1'b1) begin
- {dopa_out, doa_out} <= #100 SRVAL_A;
- end
- else begin
- if (wea_int == 1'b1) begin
- if (wr_mode_a == 2'b00) begin
- doa_out <= #100 dia_int;
- dopa_out <= #100 dipa_int;
- end
- else if (wr_mode_a == 2'b01) begin
-
- doa_out <= #100 mem[addra_int];
- dopa_out <= #100 memp[addra_int];
-
- end
- end
- else begin
-
- doa_out <= #100 mem[addra_int];
- dopa_out <= #100 memp[addra_int];
-
- end
- end
-
- // memory
- if (wea_int == 1'b1) begin
- mem[addra_int] <= dia_int;
- memp[addra_int] <= dipa_int;
- end
-
- end
- end
-
-
- // Port B
- always @(posedge clkb_int) begin
-
- if (enb_int == 1'b1) begin
-
- if (ssrb_int == 1'b1) begin
- {dopb_out, dob_out} <= #100 SRVAL_B;
- end
- else begin
- if (web_int == 1'b1) begin
- if (wr_mode_b == 2'b00) begin
- dob_out <= #100 dib_int;
- dopb_out <= #100 dipb_int;
- end
- else if (wr_mode_b == 2'b01) begin
- dob_out <= #100 mem[addrb_int];
- dopb_out <= #100 memp[addrb_int];
- end
- end
- else begin
- dob_out <= #100 mem[addrb_int];
- dopb_out <= #100 memp[addrb_int];
- end
- end
-
- // memory
- if (web_int == 1'b1) begin
- mem[addrb_int] <= dib_int;
- memp[addrb_int] <= dipb_int;
- end
-
- end
- end
-
-
-endmodule
-
-`endif
+++ /dev/null
-
-
-module elastic_buffer
- ( input rx_clk,
- input tx_clk,
- input rst,
-
- input [7:0] rxd,
- input rx_dv,
- input rx_er,
- input crs,
- input col,
-
- output [7:0] rxd_ret,
- output rx_dv_ret,
- output rx_er_ret,
- output crs_ret,
- output col_ret );
-
- reg [3:0] addr_wr,addr_wr_gray,awg_d1,awg_d2,addr_wr_gray_ret,awgr_d1,addr_wr_ungray,addr_rd;
-
- reg [11:0] buffer [0:15];
- integer i;
- initial
- for(i=0;i<16;i=i+1)
- buffer[i] <= 0;
-
- reg [7:0] rxd_d1, rxd_d2;
- reg rx_dv_d1,rx_er_d1,crs_d1,col_d1, rx_dv_d2,rx_er_d2,crs_d2,col_d2;
- wire rx_dv_ret_adv;
- reg rx_dv_ontime;
-
- always @(posedge rx_clk)
- {col_d1,crs_d1,rx_er_d1,rx_dv_d1,rxd_d1} <= {col,crs,rx_er,rx_dv,rxd};
-
- always @(posedge rx_clk)
- {col_d2,crs_d2,rx_er_d2,rx_dv_d2,rxd_d2} <= {col_d1,crs_d1,rx_er_d1,rx_dv_d1,rxd_d1};
-
- always @(posedge rx_clk)
- buffer[addr_wr] <= {col_d2,crs_d2,rx_er_d2,rx_dv_d1,rxd_d2};
-
- always @(posedge rx_clk or posedge rst)
- if(rst) addr_wr <= 0;
- else addr_wr <= addr_wr + 1;
-
- always @(posedge rx_clk)
- begin
- addr_wr_gray <= {addr_wr[3],^addr_wr[3:2],^addr_wr[2:1],^addr_wr[1:0]};
- awg_d1 <= addr_wr_gray;
- awg_d2 <= awg_d1;
- end
-
- always @(posedge tx_clk)
- begin
- addr_wr_gray_ret <= awg_d2;
- awgr_d1 <= addr_wr_gray_ret;
- addr_wr_ungray <= {awgr_d1[3],^awgr_d1[3:2],^awgr_d1[3:1],^awgr_d1[3:0]};
- end
-
- wire [3:0] addr_delta = addr_rd-addr_wr_ungray;
- reg [1:0] direction;
- localparam retard = 2'd0;
- localparam good = 2'd1;
- localparam advance = 2'd2;
- localparam wayoff = 2'd3;
-
- always @*
- case(addr_delta)
- 4'd1, 4'd2, 4'd3, 4'd4, 4'd5 : direction <= retard;
- 4'd15, 4'd14, 4'd13, 4'd12, 4'd11 : direction <= advance;
- 4'd0 : direction <= good;
- default : direction <= wayoff;
- endcase // case(addr_delta)
-
- always @(posedge tx_clk or posedge rst)
- if(rst)
- addr_rd <= 0;
- else if(rx_dv_ret_adv | rx_dv_ontime)
- addr_rd <= addr_rd + 1;
- else
- case(direction)
- retard : addr_rd <= addr_rd;
- advance : addr_rd <= addr_rd + 2;
- good : addr_rd <= addr_rd + 1;
- wayoff : addr_rd <= addr_wr_ungray;
- endcase // case(direction)
-
- assign {col_ret,crs_ret,rx_er_ret,rx_dv_ret_adv,rxd_ret} = buffer[addr_rd];
- always @(posedge tx_clk)
- rx_dv_ontime <= rx_dv_ret_adv;
-
- assign rx_dv_ret = rx_dv_ontime;
-endmodule // elastic_buffer
+++ /dev/null
-
-module elastic_buffer_tb;
-
- reg rx_clk = 0, tx_clk = 0, rst = 1;
-
- reg [7:0] rxd;
- wire [7:0] rxd_ret;
- reg rx_dv, rx_er, crs, col;
- wire rx_dv_ret, rx_er_ret, crs_ret, col_ret;
-
- elastic_buffer elastic_buffer
- (.rx_clk(rx_clk),.tx_clk(tx_clk),.rst(rst),
- .rxd(rxd),.rx_dv(rx_dv),.rx_er(rx_er),.crs(crs),.col(col),
- .rxd_ret(rxd_ret),.rx_dv_ret(rx_dv_ret),.rx_er_ret(rx_er_ret),
- .crs_ret(crs_ret),.col_ret(col_ret) );
-
- always #100 rx_clk = ~rx_clk;
- always #101 tx_clk = ~tx_clk;
- initial #950 rst = 0;
-
- initial
- begin
- {col,crs,rx_er,rx_dv,rxd} <= 0;
- @(negedge rst);
- @(posedge rx_clk);
-
- repeat (13)
- begin
- repeat (284)
- @(posedge rx_clk);
- SendPKT;
- end
- repeat (100)
- @(posedge rx_clk);
- $finish;
- end // initial begin
-
- reg [7:0] rxd_ret_d1;
- always @(posedge tx_clk)
- rxd_ret_d1 <= rxd_ret;
-
- wire [7:0] diff = rxd_ret_d1 - rxd_ret;
-
- wire error = rx_dv_ret && (diff != 8'hFF);
-
- task SendPKT;
- begin
- {col,crs,rx_er,rx_dv,rxd} <= 0;
- @(posedge rx_clk);
- {col,crs,rx_er,rx_dv,rxd} <= {4'hF,8'd1};
- @(posedge rx_clk);
- repeat (250)
- begin
- rxd <= rxd + 1;
- @(posedge rx_clk);
- end
- {col,crs,rx_er,rx_dv,rxd} <= 0;
- @(posedge rx_clk);
- end
- endtask // SendPKT
-
- initial begin
- $dumpfile("elastic_buffer_tb.vcd");
- $dumpvars(0,elastic_buffer_tb);
- end
-endmodule // elastic_buffer_tb
+++ /dev/null
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// eth_miim.v ////\r
-//// ////\r
-//// This file is part of the Ethernet IP core project ////\r
-//// http://www.opencores.org/projects/ethmac/ ////\r
-//// ////\r
-//// Author(s): ////\r
-//// - Igor Mohor (igorM@opencores.org) ////\r
-//// ////\r
-//// All additional information is avaliable in the Readme.txt ////\r
-//// file. ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// Copyright (C) 2001 Authors ////\r
-//// ////\r
-//// This source file may be used and distributed without ////\r
-//// restriction provided that this copyright statement is not ////\r
-//// removed from the file and that any derivative work contains ////\r
-//// the original copyright notice and the associated disclaimer. ////\r
-//// ////\r
-//// This source file is free software; you can redistribute it ////\r
-//// and/or modify it under the terms of the GNU Lesser General ////\r
-//// Public License as published by the Free Software Foundation; ////\r
-//// either version 2.1 of the License, or (at your option) any ////\r
-//// later version. ////\r
-//// ////\r
-//// This source is distributed in the hope that it will be ////\r
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\r
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\r
-//// PURPOSE. See the GNU Lesser General Public License for more ////\r
-//// details. ////\r
-//// ////\r
-//// You should have received a copy of the GNU Lesser General ////\r
-//// Public License along with this source; if not, download it ////\r
-//// from http://www.opencores.org/lgpl.shtml ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-//\r
-// CVS Revision History\r
-//\r
-// $Log: eth_miim.v,v $\r
-// Revision 1.3 2006/01/19 14:07:53 maverickist\r
-// verification is complete.\r
-//\r
-// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator\r
-// no message\r
-//\r
-// Revision 1.4 2005/08/16 12:07:57 Administrator\r
-// no message\r
-//\r
-// Revision 1.3 2005/05/19 07:04:29 Administrator\r
-// no message\r
-//\r
-// Revision 1.2 2005/04/27 15:58:46 Administrator\r
-// no message\r
-//\r
-// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator\r
-// no message\r
-//\r
-// Revision 1.5 2003/05/16 10:08:27 mohor\r
-// Busy was set 2 cycles too late. Reported by Dennis Scott.\r
-//\r
-// Revision 1.4 2002/08/14 18:32:10 mohor\r
-// - Busy signal was not set on time when scan status operation was performed\r
-// and clock was divided with more than 2.\r
-// - Nvalid remains valid two more clocks (was previously cleared too soon).\r
-//\r
-// Revision 1.3 2002/01/23 10:28:16 mohor\r
-// Link in the header changed.\r
-//\r
-// Revision 1.2 2001/10/19 08:43:51 mohor\r
-// eth_timescale.v changed to timescale.v This is done because of the\r
-// simulation of the few cores in a one joined project.\r
-//\r
-// Revision 1.1 2001/08/06 14:44:29 mohor\r
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).\r
-// Include files fixed to contain no path.\r
-// File names and module names changed ta have a eth_ prologue in the name.\r
-// File eth_timescale.v is used to define timescale\r
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.\r
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O\r
-// and Mdo_OE. The bidirectional signal must be created on the top level. This\r
-// is done due to the ASIC tools.\r
-//\r
-// Revision 1.2 2001/08/02 09:25:31 mohor\r
-// Unconnected signals are now connected.\r
-//\r
-// Revision 1.1 2001/07/30 21:23:42 mohor\r
-// Directory structure changed. Files checked and joind together.\r
-//\r
-// Revision 1.3 2001/06/01 22:28:56 mohor\r
-// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.\r
-//\r
-//\r
-\r
-module eth_miim\r
-(\r
- Clk,\r
- Reset,\r
- Divider,\r
- NoPre,\r
- CtrlData,\r
- Rgad,\r
- Fiad,\r
- WCtrlData,\r
- RStat,\r
- ScanStat,\r
- Mdio,\r
- Mdc,\r
- Busy,\r
- Prsd,\r
- LinkFail,\r
- Nvalid,\r
- WCtrlDataStart,\r
- RStatStart,\r
- UpdateMIIRX_DATAReg\r
-);\r
-\r
-input Clk; // Host Clock\r
-input Reset; // General Reset\r
-input [7:0] Divider; // Divider for the host clock\r
-input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)\r
-input [4:0] Rgad; // Register Address (within the PHY)\r
-input [4:0] Fiad; // PHY Address\r
-input NoPre; // No Preamble (no 32-bit preamble)\r
-input WCtrlData; // Write Control Data operation\r
-input RStat; // Read Status operation\r
-input ScanStat; // Scan Status operation\r
-inout Mdio; // MII Management Data In\r
-\r
-output Mdc; // MII Management Data Clock\r
-\r
-output Busy; // Busy Signal\r
-output LinkFail; // Link Integrity Signal\r
-output Nvalid; // Invalid Status (qualifier for the valid scan result)\r
-\r
-output [15:0] Prsd; // Read Status Data (data read from the PHY)\r
-\r
-output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register\r
-output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register\r
-output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data\r
-\r
-//parameter Tp = 1;\r
-\r
-\r
-reg Nvalid;\r
-reg EndBusy_d; // Pre-end Busy signal\r
-reg EndBusy; // End Busy signal (stops the operation in progress)\r
-\r
-reg WCtrlData_q1; // Write Control Data operation delayed 1 Clk cycle\r
-reg WCtrlData_q2; // Write Control Data operation delayed 2 Clk cycles\r
-reg WCtrlData_q3; // Write Control Data operation delayed 3 Clk cycles\r
-reg WCtrlDataStart; // Start Write Control Data Command (positive edge detected)\r
-reg WCtrlDataStart_q;\r
-reg WCtrlDataStart_q1; // Start Write Control Data Command delayed 1 Mdc cycle\r
-reg WCtrlDataStart_q2; // Start Write Control Data Command delayed 2 Mdc cycles\r
-\r
-reg RStat_q1; // Read Status operation delayed 1 Clk cycle\r
-reg RStat_q2; // Read Status operation delayed 2 Clk cycles\r
-reg RStat_q3; // Read Status operation delayed 3 Clk cycles\r
-reg RStatStart; // Start Read Status Command (positive edge detected)\r
-reg RStatStart_q1; // Start Read Status Command delayed 1 Mdc cycle\r
-reg RStatStart_q2; // Start Read Status Command delayed 2 Mdc cycles\r
-\r
-reg ScanStat_q1; // Scan Status operation delayed 1 cycle\r
-reg ScanStat_q2; // Scan Status operation delayed 2 cycles\r
-reg SyncStatMdcEn; // Scan Status operation delayed at least cycles and synchronized to MdcEn\r
-\r
-wire WriteDataOp; // Write Data Operation (positive edge detected)\r
-wire ReadStatusOp; // Read Status Operation (positive edge detected)\r
-wire ScanStatusOp; // Scan Status Operation (positive edge detected)\r
-wire StartOp; // Start Operation (start of any of the preceding operations)\r
-wire EndOp; // End of Operation\r
-\r
-reg InProgress; // Operation in progress\r
-reg InProgress_q1; // Operation in progress delayed 1 Mdc cycle\r
-reg InProgress_q2; // Operation in progress delayed 2 Mdc cycles\r
-reg InProgress_q3; // Operation in progress delayed 3 Mdc cycles\r
-\r
-reg WriteOp; // Write Operation Latch (When asserted, write operation is in progress)\r
-reg [6:0] BitCounter; // Bit Counter\r
-\r
-\r
-wire [3:0] ByteSelect; // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.\r
-wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.\r
-wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal\r
-\r
-\r
-wire LatchByte1_d2;\r
-wire LatchByte0_d2;\r
-reg LatchByte1_d;\r
-reg LatchByte0_d;\r
-reg [1:0] LatchByte; // Latch Byte selects which part of Read Status Data is updated from the shift register\r
-\r
-reg UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data\r
-\r
-wire Mdo; // MII Management Data Output\r
-wire MdoEn; // MII Management Data Output Enable\r
-wire Mdi;\r
-\r
-assign Mdi=Mdio;\r
-assign Mdio=MdoEn?Mdo:1'bz;\r
-\r
-\r
-\r
-// Generation of the EndBusy signal. It is used for ending the MII Management operation.\r
-always @ (posedge Clk or posedge Reset)\r
-begin\r
- if(Reset)\r
- begin\r
- EndBusy_d <= 1'b0;\r
- EndBusy <= 1'b0;\r
- end\r
- else\r
- begin\r
- EndBusy_d <= ~InProgress_q2 & InProgress_q3;\r
- EndBusy <= EndBusy_d;\r
- end\r
-end\r
-\r
-\r
-// Update MII RX_DATA register\r
-always @ (posedge Clk or posedge Reset)\r
-begin\r
- if(Reset)\r
- UpdateMIIRX_DATAReg <= 0;\r
- else\r
- if(EndBusy & ~WCtrlDataStart_q)\r
- UpdateMIIRX_DATAReg <= 1;\r
- else\r
- UpdateMIIRX_DATAReg <= 0; \r
-end\r
-\r
-\r
-\r
-// Generation of the delayed signals used for positive edge triggering.\r
-always @ (posedge Clk or posedge Reset)\r
-begin\r
- if(Reset)\r
- begin\r
- WCtrlData_q1 <= 1'b0;\r
- WCtrlData_q2 <= 1'b0;\r
- WCtrlData_q3 <= 1'b0;\r
- \r
- RStat_q1 <= 1'b0;\r
- RStat_q2 <= 1'b0;\r
- RStat_q3 <= 1'b0;\r
-\r
- ScanStat_q1 <= 1'b0;\r
- ScanStat_q2 <= 1'b0;\r
- SyncStatMdcEn <= 1'b0;\r
- end\r
- else\r
- begin\r
- WCtrlData_q1 <= WCtrlData;\r
- WCtrlData_q2 <= WCtrlData_q1;\r
- WCtrlData_q3 <= WCtrlData_q2;\r
-\r
- RStat_q1 <= RStat;\r
- RStat_q2 <= RStat_q1;\r
- RStat_q3 <= RStat_q2;\r
-\r
- ScanStat_q1 <= ScanStat;\r
- ScanStat_q2 <= ScanStat_q1;\r
- if(MdcEn)\r
- SyncStatMdcEn <= ScanStat_q2;\r
- end\r
-end\r
-\r
-\r
-// Generation of the Start Commands (Write Control Data or Read Status)\r
-always @ (posedge Clk or posedge Reset)\r
-begin\r
- if(Reset)\r
- begin\r
- WCtrlDataStart <= 1'b0;\r
- WCtrlDataStart_q <= 1'b0;\r
- RStatStart <= 1'b0;\r
- end\r
- else\r
- begin\r
- if(EndBusy)\r
- begin\r
- WCtrlDataStart <= 1'b0;\r
- RStatStart <= 1'b0;\r
- end\r
- else\r
- begin\r
- if(WCtrlData_q2 & ~WCtrlData_q3)\r
- WCtrlDataStart <= 1'b1;\r
- if(RStat_q2 & ~RStat_q3)\r
- RStatStart <= 1'b1;\r
- WCtrlDataStart_q <= WCtrlDataStart;\r
- end\r
- end\r
-end \r
-\r
-\r
-// Generation of the Nvalid signal (indicates when the status is invalid)\r
-always @ (posedge Clk or posedge Reset)\r
-begin\r
- if(Reset)\r
- Nvalid <= 1'b0;\r
- else\r
- begin\r
- if(~InProgress_q2 & InProgress_q3)\r
- begin\r
- Nvalid <= 1'b0;\r
- end\r
- else\r
- begin\r
- if(ScanStat_q2 & ~SyncStatMdcEn)\r
- Nvalid <= 1'b1;\r
- end\r
- end\r
-end \r
-\r
-// Signals used for the generation of the Operation signals (positive edge)\r
-always @ (posedge Clk or posedge Reset)\r
-begin\r
- if(Reset)\r
- begin\r
- WCtrlDataStart_q1 <= 1'b0;\r
- WCtrlDataStart_q2 <= 1'b0;\r
-\r
- RStatStart_q1 <= 1'b0;\r
- RStatStart_q2 <= 1'b0;\r
-\r
- InProgress_q1 <= 1'b0;\r
- InProgress_q2 <= 1'b0;\r
- InProgress_q3 <= 1'b0;\r
-\r
- LatchByte0_d <= 1'b0;\r
- LatchByte1_d <= 1'b0;\r
-\r
- LatchByte <= 2'b00;\r
- end\r
- else\r
- begin\r
- if(MdcEn)\r
- begin\r
- WCtrlDataStart_q1 <= WCtrlDataStart;\r
- WCtrlDataStart_q2 <= WCtrlDataStart_q1;\r
-\r
- RStatStart_q1 <= RStatStart;\r
- RStatStart_q2 <= RStatStart_q1;\r
-\r
- LatchByte[0] <= LatchByte0_d;\r
- LatchByte[1] <= LatchByte1_d;\r
-\r
- LatchByte0_d <= LatchByte0_d2;\r
- LatchByte1_d <= LatchByte1_d2;\r
-\r
- InProgress_q1 <= InProgress;\r
- InProgress_q2 <= InProgress_q1;\r
- InProgress_q3 <= InProgress_q2;\r
- end\r
- end\r
-end \r
-\r
-\r
-// Generation of the Operation signals\r
-assign WriteDataOp = WCtrlDataStart_q1 & ~WCtrlDataStart_q2; \r
-assign ReadStatusOp = RStatStart_q1 & ~RStatStart_q2;\r
-assign ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q1 & ~InProgress_q2;\r
-assign StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp;\r
-\r
-// Busy\r
-reg Busy;\r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- Busy <=0;\r
- else if(WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid)\r
- Busy <=1;\r
- else\r
- Busy <=0;\r
- \r
-//assign Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;\r
-\r
-\r
-// Generation of the InProgress signal (indicates when an operation is in progress)\r
-// Generation of the WriteOp signal (indicates when a write is in progress)\r
-always @ (posedge Clk or posedge Reset)\r
-begin\r
- if(Reset)\r
- begin\r
- InProgress <= 1'b0;\r
- WriteOp <= 1'b0;\r
- end\r
- else\r
- begin\r
- if(MdcEn)\r
- begin\r
- if(StartOp)\r
- begin\r
- if(~InProgress)\r
- WriteOp <= WriteDataOp;\r
- InProgress <= 1'b1;\r
- end\r
- else\r
- begin\r
- if(EndOp)\r
- begin\r
- InProgress <= 1'b0;\r
- WriteOp <= 1'b0;\r
- end\r
- end\r
- end\r
- end\r
-end\r
-\r
-\r
-\r
-// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)\r
-always @ (posedge Clk or posedge Reset)\r
-begin\r
- if(Reset)\r
- BitCounter[6:0] <= 7'h0;\r
- else\r
- begin\r
- if(MdcEn)\r
- begin\r
- if(InProgress)\r
- begin\r
- if(NoPre & ( BitCounter == 7'h0 ))\r
- BitCounter[6:0] <= 7'h21;\r
- else\r
- BitCounter[6:0] <= BitCounter[6:0] + 1'b1;\r
- end\r
- else\r
- BitCounter[6:0] <= 7'h0;\r
- end\r
- end\r
-end\r
-\r
-\r
-// Operation ends when the Bit Counter reaches 63\r
-assign EndOp = BitCounter==63;\r
-\r
-assign ByteSelect[0] = InProgress & ((NoPre & (BitCounter == 7'h0)) | (~NoPre & (BitCounter == 7'h20)));\r
-assign ByteSelect[1] = InProgress & (BitCounter == 7'h28);\r
-assign ByteSelect[2] = InProgress & WriteOp & (BitCounter == 7'h30);\r
-assign ByteSelect[3] = InProgress & WriteOp & (BitCounter == 7'h38);\r
-\r
-\r
-// Latch Byte selects which part of Read Status Data is updated from the shift register\r
-assign LatchByte1_d2 = InProgress & ~WriteOp & BitCounter == 7'h37;\r
-assign LatchByte0_d2 = InProgress & ~WriteOp & BitCounter == 7'h3F;\r
-\r
-wire MdcEn_n;\r
-\r
-// Connecting the Clock Generator Module\r
-eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc) \r
- );\r
-\r
-// Connecting the Shift Register Module\r
-eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad), \r
- .CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte), \r
- .ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)\r
- );\r
-\r
-// Connecting the Output Control Module\r
-eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress), \r
- .ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre), \r
- .Mdo(Mdo), .MdoEn(MdoEn)\r
- );\r
-\r
-endmodule\r
+++ /dev/null
-\r
-// RX side of flow control -- when we are running out of RX space, send a PAUSE\r
-\r
-module flow_ctrl_rx\r
- (input rst,\r
- //host processor\r
- input pause_frame_send_en,\r
- input [15:0] pause_quanta_set,\r
- input [15:0] fc_hwmark,\r
- input [15:0] fc_lwmark,\r
- input [15:0] fc_padtime,\r
- // From MAC_rx_ctrl\r
- input rx_clk,\r
- input [15:0] rx_fifo_space,\r
- // MAC_tx_ctrl\r
- input tx_clk,\r
- output reg xoff_gen,\r
- output reg xon_gen,\r
- input xoff_gen_complete,\r
- input xon_gen_complete\r
- );\r
- \r
- // ****************************************************************************** \r
- // Force our TX to send a PAUSE frame because our RX is nearly full\r
- // ******************************************************************************\r
-\r
- reg xon_int, xoff_int;\r
- reg [21:0] countdown;\r
- \r
- always @(posedge rx_clk or posedge rst)\r
- if(rst)\r
- begin\r
- xon_int <= 0;\r
- xoff_int <= 0;\r
- end\r
- else \r
- begin\r
- xon_int <= 0;\r
- xoff_int <= 0;\r
- if(pause_frame_send_en)\r
- if(countdown == 0)\r
- if(rx_fifo_space < fc_lwmark)\r
- xoff_int <= 1;\r
- else\r
- ;\r
- else\r
- if(rx_fifo_space > fc_hwmark)\r
- xon_int <= 1;\r
- end // else: !if(rst)\r
- \r
- reg xoff_int_d1, xon_int_d1;\r
-\r
- always @(posedge rx_clk)\r
- xon_int_d1 <= xon_int;\r
- always @(posedge rx_clk)\r
- xoff_int_d1 <= xoff_int;\r
- \r
- always @ (posedge tx_clk or posedge rst)\r
- if (rst)\r
- xoff_gen <=0;\r
- else if (xoff_gen_complete)\r
- xoff_gen <=0;\r
- else if (xoff_int | xoff_int_d1)\r
- xoff_gen <=1;\r
- \r
- always @ (posedge tx_clk or posedge rst)\r
- if (rst)\r
- xon_gen <=0;\r
- else if (xon_gen_complete)\r
- xon_gen <=0;\r
- else if (xon_int | xon_int_d1)\r
- xon_gen <=1; \r
-\r
- wire [21:0] pq_reduced = {pause_quanta_set,6'd0} - {6'd0,fc_padtime};\r
- \r
- always @(posedge tx_clk or posedge rst)\r
- if(rst)\r
- countdown <= 0;\r
- else if(xoff_gen)\r
- countdown <= pq_reduced;\r
- else if(xon_gen)\r
- countdown <= 0;\r
- else if(countdown != 0)\r
- countdown <= countdown - 1;\r
- \r
-endmodule // flow_ctrl\r
+++ /dev/null
-\r
-// TX side of flow control -- when other side sends PAUSE, we wait\r
-\r
-module flow_ctrl_tx\r
- (input rst,\r
- input tx_clk,\r
- //host processor\r
- input tx_pause_en,\r
- // From MAC_rx_ctrl\r
- input [15:0] pause_quanta,\r
- input pause_quanta_val,\r
- // MAC_tx_ctrl\r
- output pause_apply,\r
- input pause_quanta_sub);\r
- \r
- // ****************************************************************************** \r
- // Inhibit our TX from transmitting because they sent us a PAUSE frame\r
- // ******************************************************************************\r
-\r
- reg [15:0] pause_quanta_counter;\r
- reg pqval_d1, pqval_d2; \r
-\r
- always @(posedge tx_clk) pqval_d1 <= pause_quanta_val;\r
- always @(posedge tx_clk) pqval_d2 <= pqval_d1;\r
-\r
- always @ (posedge tx_clk or posedge rst)\r
- if (rst)\r
- pause_quanta_counter <= 0;\r
- else if (pqval_d1 & ~pqval_d2)\r
- pause_quanta_counter <= pause_quanta; \r
- else if((pause_quanta_counter!=0) & pause_quanta_sub)\r
- pause_quanta_counter <= pause_quanta_counter - 1;\r
-\r
- assign pause_apply = tx_pause_en & (pause_quanta_counter != 0);\r
- \r
-endmodule // flow_ctrl\r
+++ /dev/null
-`define MAC_SOURCE_REPLACE_EN 1\r
-`define MAC_TARGET_CHECK_EN 1\r
-`define MAC_BROADCAST_FILTER_EN 1\r
-`define MAC_TX_FF_DEPTH 9\r
-`define MAC_RX_FF_DEPTH 9\r
-`define MAC_TARGET_XILINX 1\r
-// `define MAC_TARGET_ALTERA 1\r
+++ /dev/null
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// eth_clockgen.v ////\r
-//// ////\r
-//// This file is part of the Ethernet IP core project ////\r
-//// http://www.opencores.org/projects/ethmac/ ////\r
-//// ////\r
-//// Author(s): ////\r
-//// - Igor Mohor (igorM@opencores.org) ////\r
-//// ////\r
-//// All additional information is avaliable in the Readme.txt ////\r
-//// file. ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// Copyright (C) 2001 Authors ////\r
-//// ////\r
-//// This source file may be used and distributed without ////\r
-//// restriction provided that this copyright statement is not ////\r
-//// removed from the file and that any derivative work contains ////\r
-//// the original copyright notice and the associated disclaimer. ////\r
-//// ////\r
-//// This source file is free software; you can redistribute it ////\r
-//// and/or modify it under the terms of the GNU Lesser General ////\r
-//// Public License as published by the Free Software Foundation; ////\r
-//// either version 2.1 of the License, or (at your option) any ////\r
-//// later version. ////\r
-//// ////\r
-//// This source is distributed in the hope that it will be ////\r
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\r
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\r
-//// PURPOSE. See the GNU Lesser General Public License for more ////\r
-//// details. ////\r
-//// ////\r
-//// You should have received a copy of the GNU Lesser General ////\r
-//// Public License along with this source; if not, download it ////\r
-//// from http://www.opencores.org/lgpl.shtml ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-//\r
-// CVS Revision History\r
-//\r
-// $Log: eth_clockgen.v,v $\r
-// Revision 1.2 2005/12/13 12:54:49 maverickist\r
-// first simulation passed\r
-//\r
-// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator\r
-// no message\r
-//\r
-// Revision 1.2 2005/04/27 15:58:45 Administrator\r
-// no message\r
-//\r
-// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator\r
-// no message\r
-//\r
-// Revision 1.3 2002/01/23 10:28:16 mohor\r
-// Link in the header changed.\r
-//\r
-// Revision 1.2 2001/10/19 08:43:51 mohor\r
-// eth_timescale.v changed to timescale.v This is done because of the\r
-// simulation of the few cores in a one joined project.\r
-//\r
-// Revision 1.1 2001/08/06 14:44:29 mohor\r
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).\r
-// Include files fixed to contain no path.\r
-// File names and module names changed ta have a eth_ prologue in the name.\r
-// File eth_timescale.v is used to define timescale\r
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.\r
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O\r
-// and Mdo_OE. The bidirectional signal must be created on the top level. This\r
-// is done due to the ASIC tools.\r
-//\r
-// Revision 1.1 2001/07/30 21:23:42 mohor\r
-// Directory structure changed. Files checked and joind together.\r
-//\r
-// Revision 1.3 2001/06/01 22:28:55 mohor\r
-// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.\r
-//\r
-//\r
-\r
-module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);\r
-\r
-//parameter Tp=1;\r
-\r
-input Clk; // Input clock (Host clock)\r
-input Reset; // Reset signal\r
-input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0])\r
-\r
-output Mdc; // Output clock\r
-output MdcEn; // Enable signal is asserted for one Clk period before Mdc rises.\r
-output MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.\r
-\r
-reg Mdc;\r
-reg [7:0] Counter;\r
-\r
-wire CountEq0;\r
-wire [7:0] CounterPreset;\r
-wire [7:0] TempDivider;\r
-\r
-\r
-assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2\r
-assign CounterPreset[7:0] = (TempDivider[7:0]>>1) -1; // We are counting half of period\r
-\r
-\r
-// Counter counts half period\r
-always @ (posedge Clk or posedge Reset)\r
-begin\r
- if(Reset)\r
- Counter[7:0] <= 8'h1;\r
- else\r
- begin\r
- if(CountEq0)\r
- begin\r
- Counter[7:0] <= CounterPreset[7:0];\r
- end\r
- else\r
- Counter[7:0] <= Counter - 8'h1;\r
- end\r
-end\r
-\r
-\r
-// Mdc is asserted every other half period\r
-always @ (posedge Clk or posedge Reset)\r
-begin\r
- if(Reset)\r
- Mdc <= 1'b0;\r
- else\r
- begin\r
- if(CountEq0)\r
- Mdc <= ~Mdc;\r
- end\r
-end\r
-\r
-\r
-assign CountEq0 = Counter == 8'h0;\r
-assign MdcEn = CountEq0 & ~Mdc;\r
-assign MdcEn_n = CountEq0 & Mdc;\r
-\r
-endmodule\r
-\r
-\r
+++ /dev/null
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// eth_outputcontrol.v ////\r
-//// ////\r
-//// This file is part of the Ethernet IP core project ////\r
-//// http://www.opencores.org/projects/ethmac/ ////\r
-//// ////\r
-//// Author(s): ////\r
-//// - Igor Mohor (igorM@opencores.org) ////\r
-//// ////\r
-//// All additional information is avaliable in the Readme.txt ////\r
-//// file. ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// Copyright (C) 2001 Authors ////\r
-//// ////\r
-//// This source file may be used and distributed without ////\r
-//// restriction provided that this copyright statement is not ////\r
-//// removed from the file and that any derivative work contains ////\r
-//// the original copyright notice and the associated disclaimer. ////\r
-//// ////\r
-//// This source file is free software; you can redistribute it ////\r
-//// and/or modify it under the terms of the GNU Lesser General ////\r
-//// Public License as published by the Free Software Foundation; ////\r
-//// either version 2.1 of the License, or (at your option) any ////\r
-//// later version. ////\r
-//// ////\r
-//// This source is distributed in the hope that it will be ////\r
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\r
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\r
-//// PURPOSE. See the GNU Lesser General Public License for more ////\r
-//// details. ////\r
-//// ////\r
-//// You should have received a copy of the GNU Lesser General ////\r
-//// Public License along with this source; if not, download it ////\r
-//// from http://www.opencores.org/lgpl.shtml ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-//\r
-// CVS Revision History\r
-//\r
-// $Log: eth_outputcontrol.v,v $\r
-// Revision 1.2 2005/12/13 12:54:49 maverickist\r
-// first simulation passed\r
-//\r
-// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator\r
-// no message\r
-//\r
-// Revision 1.2 2005/04/27 15:58:46 Administrator\r
-// no message\r
-//\r
-// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator\r
-// no message\r
-//\r
-// Revision 1.4 2002/07/09 20:11:59 mohor\r
-// Comment removed.\r
-//\r
-// Revision 1.3 2002/01/23 10:28:16 mohor\r
-// Link in the header changed.\r
-//\r
-// Revision 1.2 2001/10/19 08:43:51 mohor\r
-// eth_timescale.v changed to timescale.v This is done because of the\r
-// simulation of the few cores in a one joined project.\r
-//\r
-// Revision 1.1 2001/08/06 14:44:29 mohor\r
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).\r
-// Include files fixed to contain no path.\r
-// File names and module names changed ta have a eth_ prologue in the name.\r
-// File eth_timescale.v is used to define timescale\r
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.\r
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O\r
-// and Mdo_OE. The bidirectional signal must be created on the top level. This\r
-// is done due to the ASIC tools.\r
-//\r
-// Revision 1.1 2001/07/30 21:23:42 mohor\r
-// Directory structure changed. Files checked and joind together.\r
-//\r
-// Revision 1.3 2001/06/01 22:28:56 mohor\r
-// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.\r
-//\r
-//\r
-\r
-module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn);\r
-\r
-input Clk; // Host Clock\r
-input Reset; // General Reset\r
-input WriteOp; // Write Operation Latch (When asserted, write operation is in progress)\r
-input NoPre; // No Preamble (no 32-bit preamble)\r
-input InProgress; // Operation in progress\r
-input ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal\r
-input [6:0] BitCounter; // Bit Counter\r
-input MdcEn_n; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc falls.\r
-\r
-output Mdo; // MII Management Data Output\r
-output MdoEn; // MII Management Data Output Enable\r
-\r
-wire SerialEn;\r
-\r
-reg MdoEn_2d;\r
-reg MdoEn_d;\r
-reg MdoEn;\r
-\r
-reg Mdo_2d;\r
-reg Mdo_d;\r
-reg Mdo; // MII Management Data Output\r
-\r
-\r
-\r
-// Generation of the Serial Enable signal (enables the serialization of the data)\r
-assign SerialEn = WriteOp & InProgress & ( BitCounter>31 | ( ( BitCounter == 0 ) & NoPre ) )\r
- | ~WriteOp & InProgress & (( BitCounter>31 & BitCounter<46 ) | ( ( BitCounter == 0 ) & NoPre ));\r
-\r
-\r
-// Generation of the MdoEn signal\r
-always @ (posedge Clk or posedge Reset)\r
-begin\r
- if(Reset)\r
- begin\r
- MdoEn_2d <= 1'b0;\r
- MdoEn_d <= 1'b0;\r
- MdoEn <= 1'b0;\r
- end\r
- else\r
- begin\r
- if(MdcEn_n)\r
- begin\r
- MdoEn_2d <= SerialEn | InProgress & BitCounter<32;\r
- MdoEn_d <= MdoEn_2d;\r
- MdoEn <= MdoEn_d;\r
- end\r
- end\r
-end\r
-\r
-\r
-// Generation of the Mdo signal.\r
-always @ (posedge Clk or posedge Reset)\r
-begin\r
- if(Reset)\r
- begin\r
- Mdo_2d <= 1'b0;\r
- Mdo_d <= 1'b0;\r
- Mdo <= 1'b0;\r
- end\r
- else\r
- begin\r
- if(MdcEn_n)\r
- begin\r
- Mdo_2d <= ~SerialEn & BitCounter<32;\r
- Mdo_d <= ShiftedBit | Mdo_2d;\r
- Mdo <= Mdo_d;\r
- end\r
- end\r
-end\r
-\r
-\r
-\r
-endmodule\r
+++ /dev/null
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// eth_shiftreg.v ////\r
-//// ////\r
-//// This file is part of the Ethernet IP core project ////\r
-//// http://www.opencores.org/projects/ethmac/ ////\r
-//// ////\r
-//// Author(s): ////\r
-//// - Igor Mohor (igorM@opencores.org) ////\r
-//// ////\r
-//// All additional information is avaliable in the Readme.txt ////\r
-//// file. ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// Copyright (C) 2001 Authors ////\r
-//// ////\r
-//// This source file may be used and distributed without ////\r
-//// restriction provided that this copyright statement is not ////\r
-//// removed from the file and that any derivative work contains ////\r
-//// the original copyright notice and the associated disclaimer. ////\r
-//// ////\r
-//// This source file is free software; you can redistribute it ////\r
-//// and/or modify it under the terms of the GNU Lesser General ////\r
-//// Public License as published by the Free Software Foundation; ////\r
-//// either version 2.1 of the License, or (at your option) any ////\r
-//// later version. ////\r
-//// ////\r
-//// This source is distributed in the hope that it will be ////\r
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\r
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\r
-//// PURPOSE. See the GNU Lesser General Public License for more ////\r
-//// details. ////\r
-//// ////\r
-//// You should have received a copy of the GNU Lesser General ////\r
-//// Public License along with this source; if not, download it ////\r
-//// from http://www.opencores.org/lgpl.shtml ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-//\r
-// CVS Revision History\r
-//\r
-// $Log: eth_shiftreg.v,v $\r
-// Revision 1.2 2005/12/13 12:54:49 maverickist\r
-// first simulation passed\r
-//\r
-// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator\r
-// no message\r
-//\r
-// Revision 1.2 2005/04/27 15:58:47 Administrator\r
-// no message\r
-//\r
-// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator\r
-// no message\r
-//\r
-// Revision 1.5 2002/08/14 18:16:59 mohor\r
-// LinkFail signal was not latching appropriate bit.\r
-//\r
-// Revision 1.4 2002/03/02 21:06:01 mohor\r
-// LinkFail signal was not latching appropriate bit.\r
-//\r
-// Revision 1.3 2002/01/23 10:28:16 mohor\r
-// Link in the header changed.\r
-//\r
-// Revision 1.2 2001/10/19 08:43:51 mohor\r
-// eth_timescale.v changed to timescale.v This is done because of the\r
-// simulation of the few cores in a one joined project.\r
-//\r
-// Revision 1.1 2001/08/06 14:44:29 mohor\r
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).\r
-// Include files fixed to contain no path.\r
-// File names and module names changed ta have a eth_ prologue in the name.\r
-// File eth_timescale.v is used to define timescale\r
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.\r
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O\r
-// and Mdo_OE. The bidirectional signal must be created on the top level. This\r
-// is done due to the ASIC tools.\r
-//\r
-// Revision 1.1 2001/07/30 21:23:42 mohor\r
-// Directory structure changed. Files checked and joind together.\r
-//\r
-// Revision 1.3 2001/06/01 22:28:56 mohor\r
-// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.\r
-//\r
-//\r
-\r
-module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect, \r
- LatchByte, ShiftedBit, Prsd, LinkFail);\r
-\r
-\r
-input Clk; // Input clock (Host clock)\r
-input Reset; // Reset signal\r
-input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.\r
-input Mdi; // MII input data\r
-input [4:0] Fiad; // PHY address\r
-input [4:0] Rgad; // Register address (within the selected PHY)\r
-input [15:0]CtrlData; // Control data (data to be written to the PHY)\r
-input WriteOp; // The current operation is a PHY register write operation\r
-input [3:0] ByteSelect; // Byte select\r
-input [1:0] LatchByte; // Byte select for latching (read operation)\r
-\r
-output ShiftedBit; // Bit shifted out of the shift register\r
-output[15:0]Prsd; // Read Status Data (data read from the PHY)\r
-output LinkFail; // Link Integrity Signal\r
-\r
-reg [7:0] ShiftReg; // Shift register for shifting the data in and out\r
-reg [15:0]Prsd;\r
-reg LinkFail;\r
-\r
-\r
-\r
-\r
-// ShiftReg[7:0] :: Shift Register Data\r
-always @ (posedge Clk or posedge Reset) \r
-begin\r
- if(Reset)\r
- begin\r
- ShiftReg[7:0] <= 8'h0;\r
- Prsd[15:0] <= 16'h0;\r
- LinkFail <= 1'b0;\r
- end\r
- else\r
- begin\r
- if(MdcEn_n)\r
- begin \r
- if(|ByteSelect)\r
- begin\r
- case (ByteSelect[3:0])\r
- 4'h1 : ShiftReg[7:0] <= {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};\r
- 4'h2 : ShiftReg[7:0] <= {Fiad[0], Rgad[4:0], 2'b10};\r
- 4'h4 : ShiftReg[7:0] <= CtrlData[15:8];\r
- 4'h8 : ShiftReg[7:0] <= CtrlData[7:0];\r
- default : ShiftReg[7:0] <= 8'h0;\r
- endcase\r
- end \r
- else\r
- begin\r
- ShiftReg[7:0] <= {ShiftReg[6:0], Mdi};\r
- if(LatchByte[0])\r
- begin\r
- Prsd[7:0] <= {ShiftReg[6:0], Mdi};\r
- if(Rgad == 5'h01)\r
- LinkFail <= ~ShiftReg[1]; // this is bit [2], because it is not shifted yet\r
- end\r
- else\r
- begin\r
- if(LatchByte[1])\r
- Prsd[15:8] <= {ShiftReg[6:0], Mdi};\r
- end\r
- end\r
- end\r
- end\r
-end\r
-\r
-\r
-assign ShiftedBit = ShiftReg[7];\r
-\r
-\r
-endmodule\r
+++ /dev/null
-
-module rx_prot_engine
- #(parameter FIFO_SIZE=11)
- (input clk, input rst,
-
- input Rx_mac_ra,
- output Rx_mac_rd,
- input [31:0] Rx_mac_data,
- input [1:0] Rx_mac_BE,
- input Rx_mac_pa,
- input Rx_mac_sop,
- input Rx_mac_eop,
- input Rx_mac_err,
-
- output [31:0] wr_dat_o,
- output wr_write_o,
- output wr_done_o,
- output wr_error_o,
- input wr_ready_i,
- input wr_full_i,
- output wr_flag_o,
-
- input set_stb,
- input [7:0] set_addr,
- input [31:0] set_data,
-
- output [15:0] rx_fifo_status,
- output reg [7:0] rx_seqnum,
- output reg [7:0] rx_channel,
- output [7:0] rx_flags
- );
-
- wire read, write, full, empty;
- wire eop_i, err_i, eop_o, err_o, flag_i, sop_i, flag_o, sop_o;
- wire [31:0] dat_i, dat_o;
- reg xfer_active;
-
- wire [3:0] hdr_adr;
- wire [31:0] hdr_dat;
-
- header_ram #(.REGNUM(48),.WIDTH(32)) rx_header_ram
- (.clk(clk),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
- .addr(hdr_adr),.q(hdr_dat));
-
- // Buffer interface side
- always @(posedge clk)
- if(rst)
- xfer_active <= 0;
- else if(wr_ready_i & ~empty)
- xfer_active <= 1;
- else if(eop_o | err_o | wr_full_i)
- xfer_active <= 0;
-
- assign wr_done_o = eop_o & wr_write_o;
- assign wr_error_o = err_o & wr_write_o;
- assign wr_dat_o = dat_o;
- assign wr_write_o = xfer_active & ~empty;
- assign read = wr_write_o;
-
- // FIFO in the middle
- cascadefifo2 #(.WIDTH(36),.SIZE(11)) rx_prot_fifo
- (.clk(clk),.rst(rst),
- .datain({flag_i,sop_i,eop_i,err_i,dat_i}),.write(write),.full(full),
- .dataout({flag_o,sop_o,eop_o,err_o,dat_o}),.read(read),.empty(empty),
- .clear(0),.fifo_space(rx_fifo_status));
-
- // MAC side
- localparam ETH_TYPE = 16'hBEEF;
-
- reg [2:0] prot_state;
- localparam PROT_IDLE = 0;
- localparam PROT_HDR1 = 1;
- localparam PROT_HDR2 = 2;
- localparam PROT_HDR3 = 3;
- localparam PROT_HDR4 = 4;
- localparam PROT_HDR5 = 5;
- localparam PROT_PKT = 6;
-
- // Things to control: flag_i, sop_i, eop_i, err_i, dat_i, write, Rx_mac_rd
- // Inputs to SM: Rx_mac_sop, Rx_mac_eop, Rx_mac_ra, Rx_mac_pa,
- // Rx_mac_BE, Rx_mac_err, full
-
- reg flag;
- assign dat_i = Rx_mac_data;
- assign sop_i = Rx_mac_sop;
- assign eop_i = Rx_mac_eop;
- assign err_i = Rx_mac_err;
- assign flag_i = flag;
- assign wr_flag_o = flag_o;
- assign Rx_mac_rd = (prot_state != PROT_IDLE) && (~full|~Rx_mac_pa);
- assign write = (prot_state != PROT_IDLE) && ~full && Rx_mac_pa;
-
- assign hdr_adr = {1'b0,prot_state[2:0]};
-
- wire [7:0] rx_seqnum_p1 = rx_seqnum + 1;
-
- always @(posedge clk)
- if(rst)
- begin
- prot_state <= PROT_IDLE;
- flag <= 0;
- end
- else if(prot_state == PROT_IDLE)
- begin
- flag <= 0;
- if(Rx_mac_ra)
- prot_state <= PROT_HDR1;
- end
- else if(write)
- case(prot_state)
- PROT_HDR1 :
- begin
- prot_state <= PROT_HDR2;
- if(hdr_dat != Rx_mac_data)
- flag <= 1;
- end
- PROT_HDR2 :
- begin
- prot_state <= PROT_HDR3;
- if(hdr_dat != Rx_mac_data)
- flag <= 1;
- end
- PROT_HDR3 :
- begin
- prot_state <= PROT_HDR4;
- if(hdr_dat != Rx_mac_data)
- flag <= 1;
- end
- PROT_HDR4 :
- begin
- prot_state <= PROT_HDR5;
- if(hdr_dat[31:16] != Rx_mac_data[31:16])
- flag <= 1;
- rx_channel <= hdr_dat[15:8];
- end
- PROT_HDR5 :
- begin
- prot_state <= PROT_PKT;
- if((rx_seqnum_p1) != Rx_mac_data[15:8])
- flag <= 1;
- end
- PROT_PKT :
- if(Rx_mac_eop | Rx_mac_err)
- prot_state <= PROT_IDLE;
- endcase // case(prot_state)
-
- always @(posedge clk)
- if(rst)
- rx_seqnum <= 8'hFF;
- else if(set_stb & (set_addr == 54))
- rx_seqnum <= set_data[7:0];
- else if(write & (prot_state == PROT_HDR5) & ((rx_seqnum_p1) == Rx_mac_data[15:8]) & ~flag)
- rx_seqnum <= rx_seqnum + 1;
-
- // Error cases -- Rx_mac_error, BE != 0
-endmodule // rx_prot_engine
+++ /dev/null
-
-module tx_prot_engine
- (input clk, input rst,
-
- // To MAC
- input Tx_mac_wa,
- output Tx_mac_wr,
- output [31:0] Tx_mac_data,
- output [1:0] Tx_mac_BE,
- output Tx_mac_sop,
- output Tx_mac_eop,
-
- // To buffer interface
- input [31:0] rd_dat_i,
- output rd_read_o,
- output rd_done_o,
- output rd_error_o,
- input rd_sop_i,
- input rd_eop_i,
-
- // To control
- input set_stb,
- input [7:0] set_addr,
- input [31:0] set_data,
-
- // Protocol Stuff
- input [15:0] rx_fifo_status,
- input [7:0] rx_seqnum
- //input [7:0] tx_channel,
- //input [7:0] tx_flags
- );
-
- wire [3:0] hdr_adr;
- wire [31:0] hdr_dat;
- wire [7:0] tx_channel;
-
- header_ram #(.REGNUM(32),.WIDTH(32)) tx_header_ram
- (.clk(clk),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
- .addr(hdr_adr),.q(hdr_dat));
-
- setting_reg #(.my_addr(32)) sr_channel
- (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),.in(set_data),
- .out(tx_channel),.changed());
-
- // Might as well use a shortfifo here since they are basically free
- wire empty, full, sfifo_write, sfifo_read;
- wire [33:0] sfifo_in, sfifo_out;
-
- shortfifo #(.WIDTH(34)) txmac_sfifo
- (.clk(clk),.rst(rst),.clear(0),
- .datain(sfifo_in),.write(sfifo_write),.full(full),
- .dataout(sfifo_out),.read(sfifo_read),.empty(empty));
-
- // MAC side signals
- // Inputs -- Tx_mac_wa, sfifo_out, empty
- // outputs -- sfifo_read, Tx_mac_data, Tx_mac_wr, Tx_mac_BE, Tx_mac_sop, Tx_mac_eop
-
- // We are allowed to do one more write after we are told the FIFO is full
- // This allows us to register the _wa signal and speed up timing.
- reg tx_mac_wa_d1;
- always @(posedge clk)
- tx_mac_wa_d1 <= Tx_mac_wa;
-
- reg [2:0] prot_state;
- localparam PROT_IDLE = 0;
- localparam PROT_HDR1 = 1;
- localparam PROT_HDR2 = 2;
- localparam PROT_HDR3 = 3;
- localparam PROT_HDR4 = 4;
- localparam PROT_HDR5 = 5;
- localparam PROT_PKT = 6;
-
- reg [7:0] tx_seqnum;
- reg all_match;
- always @(posedge clk)
- if(rst)
- tx_seqnum <= 0;
- else if(set_stb & (set_addr == 36))
- tx_seqnum <= set_data[7:0];
- else if(tx_mac_wa_d1 & all_match & (prot_state == PROT_HDR5))
- tx_seqnum <= tx_seqnum + 1;
-
- always @(posedge clk)
- if(rst)
- prot_state <= PROT_IDLE;
- else
- if(tx_mac_wa_d1 & ~empty)
- case(prot_state)
- PROT_IDLE :
- prot_state <= PROT_HDR1;
- PROT_HDR1 :
- prot_state <= PROT_HDR2;
- PROT_HDR2 :
- prot_state <= PROT_HDR3;
- PROT_HDR3 :
- prot_state <= PROT_HDR4;
- PROT_HDR4 :
- prot_state <= PROT_HDR5;
- PROT_HDR5 :
- prot_state <= PROT_PKT;
- PROT_PKT :
- if(sfifo_out[32] & ~empty)
- prot_state <= PROT_IDLE;
- default :
- prot_state <= PROT_IDLE;
- endcase // case(prot_state)
-
- assign hdr_adr = {1'b0,prot_state};
- wire match = (hdr_dat == sfifo_out[31:0]);
- always @(posedge clk)
- if(prot_state == PROT_IDLE)
- all_match <= 1;
- else if(tx_mac_wa_d1 & ~empty &
- ((prot_state==PROT_HDR1)|(prot_state==PROT_HDR2)|(prot_state==PROT_HDR3)))
- all_match <= all_match & match;
-
- localparam ETH_TYPE = 16'hBEEF;
- assign Tx_mac_data =
- ((prot_state == PROT_HDR5) & all_match) ? {rx_fifo_status,tx_seqnum,rx_seqnum} :
- sfifo_out[31:0];
- assign sfifo_read = (prot_state != PROT_IDLE) & ~empty & tx_mac_wa_d1;
- assign Tx_mac_wr = sfifo_read;
- assign Tx_mac_BE = 0; // Since we only deal with packets that are multiples of 32 bits long
- assign Tx_mac_sop = sfifo_out[33];
- assign Tx_mac_eop = sfifo_out[32];
-
- // BUFFER side signals
- reg xfer_active;
- always @(posedge clk)
- if(rst)
- xfer_active <= 0;
- else if(rd_eop_i & ~full)
- xfer_active <= 0;
- else if(rd_sop_i)
- xfer_active <= 1;
-
- assign sfifo_in = {rd_sop_i, rd_eop_i, rd_dat_i};
- assign sfifo_write = xfer_active & ~full;
-
- assign rd_read_o = sfifo_write;
- assign rd_done_o = 0; // Always send everything we're given?
- assign rd_error_o = 0; // No possible error situations?
-
-endmodule // tx_prot_engine
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