Fix for fifo overruns on eth rx in full duplex. Now send re-pause long before pause...

git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10746 221aa14e-8319-0410-a670-987f0aec2ac5

diff --git a/usrp2/fpga/eth/rtl/verilog/MAC_top.v b/usrp2/fpga/eth/rtl/verilog/MAC_top.v
index 13f17aa13b4ac9d54252e55a454ed3c211d2b895..4e5b0db0ad28abc0fb2e99c0b942a937c727cdd0 100644 (file)
--- a/usrp2/fpga/eth/rtl/verilog/MAC_top.v
+++ b/usrp2/fpga/eth/rtl/verilog/MAC_top.v
@@ -137,7 +137,7 @@ module MAC_top
    wire [15:0] rx_fifo_space;\r
    wire        pause_apply, pause_quanta_sub;\r
    wire        xon_gen, xoff_gen, xon_gen_complete, xoff_gen_complete;\r
-   wire [15:0] fc_hwmark, fc_lwmark;\r
+   wire [15:0] fc_hwmark, fc_lwmark, fc_padtime;\r
    \r
   //PHY interface\r
   wire [7:0]  MTxD;\r
@@ -332,6 +332,7 @@ module MAC_top
       .pause_quanta_set         ( pause_quanta_set          ),\r
       .fc_hwmark (fc_hwmark),\r
       .fc_lwmark (fc_lwmark),\r
+      .fc_padtime (fc_padtime),\r
       // From RX side\r
       .rx_clk(MAC_rx_clk_div),\r
       .rx_fifo_space (rx_fifo_space),    // Decide if we need to send a PAUSE\r
@@ -342,7 +343,7 @@ module MAC_top
       .xoff_gen_complete (xoff_gen_complete), \r
       .xon_gen_complete(xon_gen_complete)\r
       );\r
-/*   \r
+\r
   RMON U_RMON(\r
     .Clk                 ( CLK_I                ),\r
     .Reset               ( RST_I                ),\r
@@ -365,7 +366,7 @@ module MAC_top
     .CPU_rd_grant        ( CPU_rd_grant         ),\r
     .CPU_rd_dout         ( CPU_rd_dout          )\r
   );\r
-*/\r
+\r
    Phy_int U_Phy_int(\r
     .rst_mac_rx  ( rst_mac_rx   ),\r
     .rst_mac_tx  ( rst_mac_tx   ),\r
@@ -478,6 +479,7 @@ module MAC_top
     .tx_pause_en              ( tx_pause_en               ),\r
     .fc_hwmark                ( fc_hwmark                 ),\r
     .fc_lwmark                ( fc_lwmark                 ),\r
+    .fc_padtime               ( fc_padtime                ),\r
                    \r
     // RMON host interface\r
     .CPU_rd_addr              ( CPU_rd_addr               ),\r
@@ -507,7 +509,7 @@ module MAC_top
     .UpdateMIIRX_DATAReg      ( UpdateMIIRX_DATAReg       )\r
   );\r
 \r
-   assign     debug0 = {xon_gen, xoff_gen, Tx_en, Rx_dv};\r
+   assign     debug0 = {xon_gen, xoff_gen, xon_gen_complete, xoff_gen_complete, debug_rx[3:0]};\r
    //assign     debug0 = {{debug_rx[3:0], xon_gen, xon_gen_complete, xoff_gen, xoff_gen_complete},\r
    //                  {1'b0,Rx_mac_err,Rx_mac_empty,Rx_mac_rd,Rx_mac_sop,Rx_mac_eop,Rx_mac_BE[1:0]},\r
    //                  {rx_fifo_space}};\r

diff --git a/usrp2/fpga/eth/rtl/verilog/Reg_int.v b/usrp2/fpga/eth/rtl/verilog/Reg_int.v
index f1bea23162d44055686e662c1099137d276f75fb..bdf73d8e528385c4beb116913b033bb3f5441b8c 100644 (file)
--- a/usrp2/fpga/eth/rtl/verilog/Reg_int.v
+++ b/usrp2/fpga/eth/rtl/verilog/Reg_int.v
@@ -43,6 +43,7 @@ module Reg_int (
   output            tx_pause_en,\r
   output [15:0]     fc_hwmark,\r
   output [15:0]     fc_lwmark,\r
+  output [15:0]     fc_padtime,\r
                \r
   // RMON host interface\r
   output [5:0]      CPU_rd_addr,\r
@@ -141,6 +142,9 @@ module Reg_int (
   RegCPUData #( 13 ) U_0_037( MIIADDRESS                   , 7'd037, 13'h0000, RST_I, CLK_I, Wr, ADR_I, DAT_I[12:0] );\r
   RegCPUData #( 16 ) U_0_038( MIITX_DATA                   , 7'd038, 16'h0000, RST_I, CLK_I, Wr, ADR_I, DAT_I[15:0] );\r
 \r
+   // New FC register\r
+  RegCPUData #( 16 ) U_0_041( fc_padtime                   , 7'd041, 1'h0,     RST_I, CLK_I, Wr, ADR_I, DAT_I[15:0] );\r
+\r
   // Asserted in first clock of 2-cycle access, negated otherwise\r
   wire Access = ~ACK_O & STB_I & CYC_I;\r
 \r
@@ -231,6 +235,7 @@ module Reg_int (
             7'd38: DAT_O <= MIITX_DATA;\r
             7'd39: DAT_O <= MIIRX_DATA;\r
             7'd40: DAT_O <= MIISTATUS;\r
+            7'd41: DAT_O <= fc_padtime;\r
           endcase\r
       end\r
 \r

diff --git a/usrp2/fpga/eth/rtl/verilog/flow_ctrl_rx.v b/usrp2/fpga/eth/rtl/verilog/flow_ctrl_rx.v
index 7ded9e08b2c52ac82e9a6ffb9093ab103d8b7d7b..6654c626b561f2bc7fd77bc18c427fba6a647439 100644 (file)
--- a/usrp2/fpga/eth/rtl/verilog/flow_ctrl_rx.v
+++ b/usrp2/fpga/eth/rtl/verilog/flow_ctrl_rx.v
@@ -8,6 +8,7 @@ module flow_ctrl_rx
    input [15:0] pause_quanta_set,\r
    input [15:0] fc_hwmark,\r
    input [15:0] fc_lwmark,\r
+   input [15:0] fc_padtime,\r
    // From MAC_rx_ctrl\r
    input        rx_clk,\r
    input [15:0] rx_fifo_space,\r
@@ -70,13 +71,13 @@ module flow_ctrl_rx
      else if (xon_int | xon_int_d1)\r
        xon_gen     <=1;                     \r
 \r
-   wire [15:0] pq_reduced = pause_quanta_set - 2;\r
+   wire [21:0] pq_reduced = {pause_quanta_set,6'd0} - {6'd0,fc_padtime};\r
    \r
    always @(posedge tx_clk or posedge rst)\r
      if(rst)\r
        countdown <= 0;\r
      else if(xoff_gen)\r
-       countdown <= {pq_reduced,6'd0};\r
+       countdown <= pq_reduced;\r
      else if(xon_gen)\r
        countdown <= 0;\r
      else if(countdown != 0)\r