speed up the diagnostic signals, they were causing timing problems

git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10101 221aa14e-8319-0410-a670-987f0aec2ac5

diff --git a/usrp2/fpga/control_lib/longfifo.v b/usrp2/fpga/control_lib/longfifo.v
index c73cc76f81e4129a6020d246e9614d181148930c..bf3338e0b1e4eccc30963940307d3676f2445832 100644 (file)
--- a/usrp2/fpga/control_lib/longfifo.v
+++ b/usrp2/fpga/control_lib/longfifo.v
@@ -15,8 +15,8 @@ module longfifo
      input clear,
      output full,
      output empty,
-     output [15:0] space,
-     output [15:0] occupied);
+     output reg [15:0] space,
+     output reg [15:0] occupied);
 
    // Read side states
    localparam    EMPTY = 0;
@@ -26,12 +26,6 @@ module longfifo
    reg [SIZE-1:0] wr_addr, rd_addr;
    reg [1:0]     read_state;
 
-   wire [SIZE-1:0] fullness = wr_addr - rd_addr;  // Approximate, for simulation only
-   assign occupied = {{16-SIZE{1'b0}},fullness};
-
-   wire [SIZE-1:0] free_space = rd_addr - wr_addr - 2;  // Approximate, for SERDES flow control
-   assign space = {{16-SIZE{1'b0}},free_space};
-         
    reg           empty_reg, full_reg;
    always @(posedge clk)
      if(rst)
@@ -43,7 +37,7 @@ module longfifo
 
    ram_2port #(.DWIDTH(WIDTH),.AWIDTH(SIZE))
      ram (.clka(clk),
-         .ena(1),
+         .ena(1'b1),
          .wea(write),
          .addra(wr_addr),
          .dia(datain),
@@ -118,5 +112,39 @@ module longfifo
 
    // assign full = ((rd_addr - 1) == wr_addr);
    assign full = full_reg;
+
+   //////////////////////////////////////////////
+   // space and occupied are for diagnostics only
+   // not guaranteed exact
+
+   localparam NUMLINES = (1<<SIZE)-2;
+   always @(posedge clk)
+     if(rst)
+       space <= NUMLINES;
+     else if(clear)
+       space <= NUMLINES;
+     else if(read & ~write)
+       space <= space + 1;
+     else if(write & ~read)
+       space <= space - 1;
+   
+   always @(posedge clk)
+     if(rst)
+       occupied <= 0;
+     else if(clear)
+       occupied <= 0;
+     else if(read & ~write)
+       occupied <= occupied - 1;
+     else if(write & ~read)
+       occupied <= occupied + 1;
+   
+   /*
+   wire [SIZE-1:0] fullness = wr_addr - rd_addr;  // Approximate, for simulation only
+   assign occupied = {{16-SIZE{1'b0}},fullness};
+
+   wire [SIZE-1:0] free_space = rd_addr - wr_addr - 2;  // Approximate, for SERDES flow control
+   assign space = {{16-SIZE{1'b0}},free_space};
+    */  
+
    
 endmodule // longfifo

diff --git a/usrp2/fpga/control_lib/shortfifo.v b/usrp2/fpga/control_lib/shortfifo.v
index 83d2c1980af64a6695328ff58a79288ccb3a92f6..d8ce1428efbaa4a717b62dc8982eae4552ba2b8d 100644 (file)
--- a/usrp2/fpga/control_lib/shortfifo.v
+++ b/usrp2/fpga/control_lib/shortfifo.v
@@ -9,8 +9,8 @@ module shortfifo
      input clear,
      output reg full,
      output reg empty,
-     output [4:0] space,
-     output [4:0] occupied);
+     output reg [4:0] space,
+     output reg [4:0] occupied);
    
    reg [3:0]     a;
    genvar        i;
@@ -57,7 +57,31 @@ module shortfifo
 
    // NOTE will fail if you write into a full fifo or read from an empty one
 
-   assign space = full ? 0 : empty ? 16 : 15-a;
-   assign occupied = empty ? 0 : full ? 16 : a+1;
+   //////////////////////////////////////////////////////////////
+   // space and occupied are used for diagnostics, not 
+   // guaranteed correct
    
+   //assign space = full ? 0 : empty ? 16 : 15-a;
+   //assign occupied = empty ? 0 : full ? 16 : a+1;
+
+   always @(posedge clk)
+     if(rst)
+       space <= 16;
+     else if(clear)
+       space <= 16;
+     else if(read & ~write)
+       space <= space + 1;
+     else if(write & ~read)
+       space <= space - 1;
+   
+   always @(posedge clk)
+     if(rst)
+       occupied <= 0;
+     else if(clear)
+       occupied <= 0;
+     else if(read & ~write)
+       occupied <= occupied - 1;
+     else if(write & ~read)
+       occupied <= occupied + 1;
+      
 endmodule // shortfifo