--- /dev/null
+/*-------------------------------------------------------------------------\r
+ Register Declarations for NXP P89LPC924 and P89LPC925\r
+ (Based on datasheet Rev. 03 \97 15 December 2004)\r
+\r
+ Written By - Jesus Calvino-Fraga / jesusc at ece.ubc.ca (February 2007)\r
+\r
+ This library is free software; you can redistribute it and/or\r
+ modify it under the terms of the GNU Lesser General Public\r
+ License as published by the Free Software Foundation; either\r
+ version 2.1 of the License, or (at your option); any later version\r
+\r
+ This library is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\r
+ Lesser General Public License for more details\r
+\r
+ You should have received a copy of the GNU Lesser General Public\r
+ License along with this library; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ In other words, you are welcome to use, share and improve this program\r
+ You are forbidden to forbid anyone else to use, share and improve\r
+ what you give them. Help stamp out software-hoarding!\r
+-------------------------------------------------------------------------*/\r
+\r
+#ifndef REG_P89LPC925_H\r
+#define REG_P89LPC925_H\r
+\r
+#include <compiler_h>\r
+\r
+SFR(ACC*, 0xE0); // Accumulator\r
+ SBIT(ACC_7, 0xE0, 7);\r
+ SBIT(ACC_6, 0xE0, 6);\r
+ SBIT(ACC_5, 0xE0, 5);\r
+ SBIT(ACC_4, 0xE0, 4);\r
+ SBIT(ACC_3, 0xE0, 3);\r
+ SBIT(ACC_2, 0xE0, 2);\r
+ SBIT(ACC_1, 0xE0, 1);\r
+ SBIT(ACC_0, 0xE0, 0);\r
+\r
+SFR(ADCON1, 0x97); // A/D control register 1\r
+ #define ENBI1 0x80\r
+ #define ENADCI1 0x40\r
+ #define TMM1 0x20\r
+ #define EDGE1 0x10\r
+ #define ADCI1 0x08\r
+ #define ENADC1 0x04\r
+ #define ADCS11 0x02\r
+ #define ADCS10 0x01\r
+\r
+SFR(ADINS, 0xA3); // A/D input select\r
+ #define ADI13 0x80\r
+ #define ADI12 0x40\r
+ #define ADI11 0x20\r
+ #define ADI10 0x10\r
+\r
+SFR(ADMODA, 0xC0); // A/D mode register A\r
+ #define BNDI1 0x80\r
+ #define BURST1 0x40\r
+ #define SCC1 0x20\r
+ #define SCAN1 0x10\r
+\r
+SFR(ADMODB, 0xA1); // A/D mode register B\r
+ #define CLK2 0x80\r
+ #define CLK1 0x40\r
+ #define CLK0 0x20\r
+ #define ENDAC1 0x08\r
+ #define BSA1 0x02\r
+\r
+SFR(AD1BH, 0xC4); // A/D_1 boundary high register\r
+\r
+SFR(AD1BL, 0xBC); // A/D_1 boundary low register\r
+\r
+SFR(AD1DAT0, 0xD5); // A/D_1 data register 0\r
+\r
+SFR(AD1DAT1, 0xD6); // A/D_1 data register 1\r
+\r
+SFR(AD1DAT2, 0xD7); // A/D_1 data register 2\r
+\r
+SFR(AD1DAT3, 0xF5); // A/D_1 data register 3\r
+\r
+SFR(AUXR1, 0xA2); // Auxiliary function register\r
+ #define CLKLP 0x80\r
+ #define EBRR 0x40\r
+ #define ENT1 0x20\r
+ #define ENT0 0x10\r
+ #define SRST 0x08\r
+ #define DPS 0x01\r
+\r
+SFR(B*, 0xF0); // B register\r
+ SBIT(B_7, 0xF0, 7);\r
+ SBIT(B_6, 0xF0, 6);\r
+ SBIT(B_5, 0xF0, 5);\r
+ SBIT(B_4, 0xF0, 4);\r
+ SBIT(B_3, 0xF0, 3);\r
+ SBIT(B_2, 0xF0, 2);\r
+ SBIT(B_1, 0xF0, 1);\r
+ SBIT(B_0, 0xF0, 0);\r
+\r
+SFR(BRGR0, 0xBE); // Baud rate generator rate LOW\r
+\r
+SFR(BRGR1, 0xBF); // Baud rate generator rate HIGH\r
+\r
+SFR(BRGCON, 0xBD); // Baud rate generator control\r
+ #define SBRGS 0x02\r
+ #define BRGEN 0x01\r
+\r
+SFR(CMP1, 0xAC); // Comparator1 control register\r
+ #define CE1 0x20\r
+ #define CP1 0x10\r
+ #define CN1 0x08\r
+ #define OE1 0x04\r
+ #define CO1 0x02\r
+ #define CMF1 0x01\r
+\r
+SFR(CMP2, 0xAD); // Comparator2 control register\r
+ #define CE2 0x20\r
+ #define CP2 0x10\r
+ #define CN2 0x08\r
+ #define OE2 0x04\r
+ #define CO2 0x02\r
+ #define CMF2 0x01\r
+\r
+SFR(DIVM, 0x95); // CPU clock divide-by-M control\r
+\r
+SFR(DPH, 0x83); // Data pointer HIGH\r
+\r
+SFR(DPL, 0x82); // Data pointer LOW\r
+\r
+SFR(FMADRH, 0xE7); // Program Flash address HIGH\r
+\r
+SFR(FMADRL, 0xE6); // Program Flash address LOW\r
+\r
+SFR(FMCON, 0xE4); // Program Flash control (Read)\r
+ #define BUSY 0x80\r
+ #define HVA 0x08\r
+ #define HVE 0x04\r
+ #define SV 0x02\r
+ #define OI 0x01\r
+\r
+SFR(FMCON, 0xE4); // Program Flash control (Write)\r
+ #define FMCMD_7 0x80\r
+ #define FMCMD_6 0x40\r
+ #define FMCMD_5 0x20\r
+ #define FMCMD_4 0x10\r
+ #define FMCMD_3 0x08\r
+ #define FMCMD_2 0x04\r
+ #define FMCMD_1 0x02\r
+ #define FMCMD_0 0x01\r
+\r
+SFR(FMDATA, 0xE5); // Program Flash data\r
+\r
+SFR(I2ADR, 0xDB); // I2C slave address register\r
+ #define I2ADR_6 0x80\r
+ #define I2ADR_5 0x40\r
+ #define I2ADR_4 0x20\r
+ #define I2ADR_3 0x10\r
+ #define I2ADR_2 0x08\r
+ #define I2ADR_1 0x04\r
+ #define I2ADR_0 0x02\r
+ #define GC 0x01\r
+\r
+SFR(I2CON*, 0xD8); // I2C control register\r
+ SBIT(I2EN, 0xD8, 6);\r
+ SBIT(STA, 0xD8, 5);\r
+ SBIT(STO, 0xD8, 4);\r
+ SBIT(SI, 0xD8, 3);\r
+ SBIT(AA, 0xD8, 2);\r
+ SBIT(CRSEL, 0xD8, 0);\r
+\r
+SFR(I2DAT, 0xDA); // I2C data register\r
+\r
+SFR(I2SCLH, 0xDD); // Serial clock generator/SCL duty cycle register HIGH\r
+\r
+SFR(I2SCLL, 0xDC); // Serial clock generator/SCL duty cycle register LOW\r
+\r
+SFR(I2STAT, 0xD9); // I2C status register\r
+ #define STA_4 0x80\r
+ #define STA_3 0x40\r
+ #define STA_2 0x20\r
+ #define STA_1 0x10\r
+ #define STA_0 0x08\r
+\r
+SFR(IEN0*, 0xA8); // Interrupt enable 0\r
+ SBIT(EA, 0xA8, 7);\r
+ SBIT(EWDRT, 0xA8, 6);\r
+ SBIT(EBO, 0xA8, 5);\r
+ SBIT(ES, 0xA8, 4);\r
+ SBIT(ESR, 0xA8, 4);\r
+ SBIT(ET1, 0xA8, 3);\r
+ SBIT(EX1, 0xA8, 2);\r
+ SBIT(ET0, 0xA8, 1);\r
+ SBIT(EX0, 0xA8, 0);\r
+\r
+SFR(IEN1*, 0xE8); // Interrupt enable 1\r
+ SBIT(EAD, 0xE8, 7);\r
+ SBIT(EST, 0xE8, 6);\r
+ SBIT(EC, 0xE8, 2);\r
+ SBIT(EKBI, 0xE8, 1);\r
+ SBIT(EI2C, 0xE8, 0);\r
+\r
+SFR(IP0*, 0xB8); // Interrupt priority 0\r
+ SBIT(PWDRT, 0xB8, 6);\r
+ SBIT(PBO, 0xB8, 5);\r
+ SBIT(PS, 0xB8, 4);\r
+ SBIT(PSR, 0xB8, 4);\r
+ SBIT(PT1, 0xB8, 3);\r
+ SBIT(PX1, 0xB8, 2);\r
+ SBIT(PT0, 0xB8, 1);\r
+ SBIT(PX0, 0xB8, 0);\r
+\r
+SFR(IP0H, 0xB7); // Interrupt priority 0 HIGH\r
+ #define PWDRTH 0x40\r
+ #define PBOH 0x20\r
+ #define PSH 0x10\r
+ #define PSRH 0x10\r
+ #define PT1H 0x08\r
+ #define PX1H 0x04\r
+ #define PT0H 0x02\r
+ #define PX0H 0x01\r
+\r
+SFR(IP1*, 0xF8); // Interrupt priority 1\r
+ SBIT(PAD, 0xF8, 7);\r
+ SBIT(PST, 0xF8, 6);\r
+ SBIT(PC, 0xF8, 2);\r
+ SBIT(PKBI, 0xF8, 1);\r
+ SBIT(PI2C, 0xF8, 0);\r
+\r
+SFR(IP1H, 0xF7); // Interrupt priority 1 HIGH\r
+ #define PADH 0x80\r
+ #define PSTH 0x40\r
+ #define PCH 0x04\r
+ #define PKBIH 0x02\r
+ #define PI2CH 0x01\r
+\r
+SFR(KBCON, 0x94); // Keypad control register\r
+ #define PATN_SEL 0x02 //Pattern Matching Polarity selection\r
+ #define KBIF 0x01 // Keypad Interrupt Flag\r
+\r
+SFR(KBMASK, 0x86); // Keypad interrupt register mask\r
+\r
+SFR(KBPATN, 0x93); // Keypad pattern register\r
+\r
+SFR(P0*, 0x80); // Port 0\r
+ SBIT(P0_7, 0x80, 7);\r
+ SBIT(P0_6, 0x80, 6);\r
+ SBIT(P0_5, 0x80, 5);\r
+ SBIT(P0_4, 0x80, 4);\r
+ SBIT(P0_3, 0x80, 3);\r
+ SBIT(P0_2, 0x80, 2);\r
+ SBIT(P0_1, 0x80, 1);\r
+ SBIT(P0_0, 0x80, 0);\r
+ //P0 alternate pin functions\r
+ SBIT(T1, 0x80, 7);\r
+ SBIT(CMP1, 0x80, 6);\r
+ SBIT(CMPREF, 0x80, 5);\r
+ SBIT(CIN1A, 0x80, 4);\r
+ SBIT(CIN1B, 0x80, 3);\r
+ SBIT(CIN2A, 0x80, 2);\r
+ SBIT(CIN2B, 0x80, 1);\r
+ SBIT(CMP2, 0x80, 0);\r
+ //More P0 alternate pin functions\r
+ SBIT(KB7, 0x80, 7);\r
+ SBIT(KB6, 0x80, 6);\r
+ SBIT(KB5, 0x80, 5);\r
+ SBIT(KB4, 0x80, 4);\r
+ SBIT(KB3, 0x80, 3);\r
+ SBIT(KB2, 0x80, 2);\r
+ SBIT(KB1, 0x80, 1);\r
+ SBIT(KB0, 0x80, 0);\r
+\r
+SFR(P1*, 0x90); // Port 1\r
+ SBIT(P1_5, 0x90, 5);\r
+ SBIT(P1_4, 0x90, 4);\r
+ SBIT(P1_3, 0x90, 3);\r
+ SBIT(P1_2, 0x90, 2);\r
+ SBIT(P1_1, 0x90, 1);\r
+ SBIT(P1_0, 0x90, 0);\r
+ //P1 alternate pin functions\r
+ SBIT(RST, 0x90, 5);\r
+ SBIT(INT1, 0x90, 4);\r
+ SBIT(INT0, 0x90, 3);\r
+ SBIT(SDA, 0x90, 3);\r
+ SBIT(T0, 0x90, 2);\r
+ SBIT(SCL, 0x90, 2);\r
+ SBIT(RXD, 0x90, 1);\r
+ SBIT(TXD, 0x90, 0);\r
+\r
+SFR(P3*, 0xB0); // Port 3\r
+ SBIT(P3_1, 0xB0, 1);\r
+ SBIT(P3_0, 0xB0, 0);\r
+ SBIT(XTAL1, 0xB0, 1);\r
+ SBIT(XTAL2, 0xB0, 0);\r
+\r
+SFR(P0M1, 0x84); // Port0 output mode1\r
+ #define P0M1_7 0x80\r
+ #define P0M1_6 0x40\r
+ #define P0M1_5 0x20\r
+ #define P0M1_4 0x10\r
+ #define P0M1_3 0x08\r
+ #define P0M1_2 0x04\r
+ #define P0M1_1 0x02\r
+ #define P0M1_0 0x01\r
+\r
+SFR(P0M2, 0x85); // Port0 output mode2\r
+ #define P0M2_7 0x80\r
+ #define P0M2_6 0x40\r
+ #define P0M2_5 0x20\r
+ #define P0M2_4 0x10\r
+ #define P0M2_3 0x08\r
+ #define P0M2_2 0x04\r
+ #define P0M2_1 0x02\r
+ #define P0M2_0 0x01\r
+\r
+SFR(P1M1, 0x91); // Port1 output mode1\r
+ #define P1M1_7 0x80\r
+ #define P1M1_6 0x40\r
+ #define P1M1_4 0x10\r
+ #define P1M1_3 0x08\r
+ #define P1M1_2 0x04\r
+ #define P1M1_1 0x02\r
+ #define P1M1_0 0x01\r
+\r
+SFR(P1M2, 0x92); // Port1 output mode2\r
+ #define P1M2_7 0x80\r
+ #define P1M2_6 0x40\r
+ #define P1M2_4 0x10\r
+ #define P1M2_3 0x08\r
+ #define P1M2_2 0x04\r
+ #define P1M2_1 0x02\r
+ #define P1M2_0 0x01\r
+\r
+SFR(P3M1, 0xB1); // Port3 output mode1\r
+ #define P3M1_1 0x02\r
+ #define P3M1_0 0x01\r
+\r
+SFR(P3M2, 0xB2); // Port3 output mode2\r
+ #define P3M2_1 0x02\r
+ #define P3M2_0 0x01\r
+\r
+SFR(PCON, 0x87); // Power control register\r
+ #define SMOD1 0x80\r
+ #define SMOD0 0x40\r
+ #define BOPD 0x20\r
+ #define BOI 0x10\r
+ #define GF1 0x08\r
+ #define GF0 0x04\r
+ #define PMOD1 0x02\r
+ #define PMOD0 0x01\r
+\r
+SFR(PCONA, 0xB5); // Power control register A\r
+ #define RTCPD 0x80\r
+ #define VCPD 0x20\r
+ #define ADPD 0x10\r
+ #define I2PD 0x08\r
+ #define SPD 0x02\r
+\r
+SFR(PSW*, 0xD0); // Program status word\r
+ SBIT(CY, 0xD0, 7);\r
+ SBIT(AC, 0xD0, 6);\r
+ SBIT(F0, 0xD0, 5);\r
+ SBIT(RS1, 0xD0, 4);\r
+ SBIT(RS0, 0xD0, 3);\r
+ SBIT(OV, 0xD0, 2);\r
+ SBIT(F1, 0xD0, 1);\r
+ SBIT(P, 0xD0, 0);\r
+\r
+SFR(PT0AD, 0xF6); // Port0 digital input disable\r
+ #define PT0AD_5 0x20\r
+ #define PT0AD_4 0x10\r
+ #define PT0AD_3 0x08\r
+ #define PT0AD_2 0x04\r
+ #define PT0AD_1 0x02\r
+\r
+SFR(RSTSRC, 0xDF); // Reset source register\r
+ #define BOF 0x20\r
+ #define POF 0x10\r
+ #define R_BK 0x08\r
+ #define R_WD 0x04\r
+ #define R_SF 0x02\r
+ #define R_EX 0x01\r
+\r
+SFR(RTCCON, 0xD1); // Real-time clock control\r
+ #define RTCF 0x80\r
+ #define RTCS1 0x40\r
+ #define RTCS0 0x20\r
+ #define ERTC 0x02\r
+ #define RTCEN 0x01\r
+\r
+SFR(RTCH, 0xD2); // Real-time clock register HIGH\r
+\r
+SFR(RTCL, 0xD3); // Real-time clock register LOW\r
+\r
+SFR(SADDR, 0xA9); // Serial port address register\r
+\r
+SFR(SADEN, 0xB9); // Serial port address enable\r
+\r
+SFR(SBUF, 0x99); // Serial Port data buffer register\r
+\r
+SFR(SCON*, 0x98); // Serial port control\r
+ SBIT(FE, 0x98, 7);\r
+ SBIT(SM0, 0x98, 7);\r
+ SBIT(SM1, 0x98, 6);\r
+ SBIT(SM2, 0x98, 5);\r
+ SBIT(REN, 0x98, 4);\r
+ SBIT(TB8, 0x98, 3);\r
+ SBIT(RB8, 0x98, 2);\r
+ SBIT(TI, 0x98, 1);\r
+ SBIT(RI, 0x98, 0);\r
+\r
+SFR(SSTAT, 0xBA); // Serial port extended status register\r
+ #define DBMOD 0x80\r
+ #define INTLO 0x40\r
+ #define CIDIS 0x20\r
+ #define DBISEL 0x10\r
+ #define FE 0x08\r
+ #define BR 0x04\r
+ #define OE 0x02\r
+ #define STINT 0x01\r
+\r
+SFR(SP, 0x81); // Stack pointer\r
+\r
+SFR(TAMOD, 0x8F); // Timer0 and 1 auxiliary mode\r
+ #define T1M2 0x10\r
+ #define T0M2 0x01\r
+\r
+SFR(TCON*, 0x88); // Timer0 and 1 control\r
+ SBIT(TF1, 0x88, 7);\r
+ SBIT(TR1, 0x88, 6);\r
+ SBIT(TF0, 0x88, 5);\r
+ SBIT(TR0, 0x88, 4);\r
+ SBIT(IE1, 0x88, 3);\r
+ SBIT(IT1, 0x88, 2);\r
+ SBIT(IE0, 0x88, 1);\r
+ SBIT(IT0, 0x88, 0);\r
+\r
+SFR(TH0, 0x8C); // Timer0 HIGH\r
+\r
+SFR(TH1, 0x8D); // Timer 1 HIGH\r
+\r
+SFR(TL0, 0x8A); // Timer 0 LOW\r
+\r
+SFR(TL1, 0x8B); // Timer 1 LOW\r
+\r
+SFR(TMOD, 0x89); // Timer0 and 1 mode\r
+ #define T1GATE 0x80\r
+ #define T1C_T 0x40\r
+ #define T1M1 0x20\r
+ #define T1M0 0x10\r
+ #define T0GATE 0x08\r
+ #define T0C_T 0x04\r
+ #define T0M1 0x02\r
+ #define T0M0 0x01\r
+\r
+SFR(TRIM, 0x96); // Internal oscillator trim register\r
+ #define RCCLK 0x80\r
+ #define ENCLK 0x40\r
+ #define TRIM_5 0x20\r
+ #define TRIM_4 0x10\r
+ #define TRIM_3 0x08\r
+ #define TRIM_2 0x04\r
+ #define TRIM_1 0x02\r
+ #define TRIM_0 0x01\r
+\r
+SFR(WDCON, 0xA7); // Watchdog control register\r
+ #define PRE2 0x80 //Watchdog Prescaler Tap Select bit 2\r
+ #define PRE1 0x40 //Watchdog Prescaler Tap Select bit 1\r
+ #define PRE0 0x20 //Watchdog Prescaler Tap Select bit 0\r
+ #define WDRUN 0x04 //Watchdog Run Control\r
+ #define WDTOF 0x02 //Watchdog Timer Time-Out Flag\r
+ #define WDCLK 0x01 //Watchdog input clock select\r
+\r
+SFR(WDL, 0xC1); // Watchdog load\r
+\r
+SFR(WFEED1, 0xC2); // Watchdog feed 1\r
+\r
+SFR(WFEED2, 0xC3); // Watchdog feed 2\r
+\r
+#endif /*REG_P89LPC925_H*/\r
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