Applied patch from Brett Trotter that stuffs zeros into the head of

the tx signal processing pipeline when the Tx FIFO is empty.

This results in the DACs outputing zeros when there's no data, unless
the tx pipeline is disabled on the host.

git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4287 221aa14e-8319-0410-a670-987f0aec2ac5

diff --git a/usrp/fpga/rbf/rev2/std_2rxhb_2tx.rbf b/usrp/fpga/rbf/rev2/std_2rxhb_2tx.rbf
index 44fd06f776327cef81581b8f863580ca52179304..966bae86571ebe351704d2266efc50bfc8168c8c 100755 (executable)
Binary files a/usrp/fpga/rbf/rev2/std_2rxhb_2tx.rbf and b/usrp/fpga/rbf/rev2/std_2rxhb_2tx.rbf differ

diff --git a/usrp/fpga/rbf/rev2/std_4rx_0tx.rbf b/usrp/fpga/rbf/rev2/std_4rx_0tx.rbf
index e8a8b6ee900a1bcb148fb0bc72e48a1b2cacdbc2..a5a5cf99dc2899a6a753b5d16ccba720af214333 100755 (executable)
Binary files a/usrp/fpga/rbf/rev2/std_4rx_0tx.rbf and b/usrp/fpga/rbf/rev2/std_4rx_0tx.rbf differ

diff --git a/usrp/fpga/rbf/rev4/std_2rxhb_2tx.rbf b/usrp/fpga/rbf/rev4/std_2rxhb_2tx.rbf
index 44fd06f776327cef81581b8f863580ca52179304..966bae86571ebe351704d2266efc50bfc8168c8c 100755 (executable)
Binary files a/usrp/fpga/rbf/rev4/std_2rxhb_2tx.rbf and b/usrp/fpga/rbf/rev4/std_2rxhb_2tx.rbf differ

diff --git a/usrp/fpga/rbf/rev4/std_4rx_0tx.rbf b/usrp/fpga/rbf/rev4/std_4rx_0tx.rbf
index e8a8b6ee900a1bcb148fb0bc72e48a1b2cacdbc2..a5a5cf99dc2899a6a753b5d16ccba720af214333 100755 (executable)
Binary files a/usrp/fpga/rbf/rev4/std_4rx_0tx.rbf and b/usrp/fpga/rbf/rev4/std_4rx_0tx.rbf differ

diff --git a/usrp/fpga/sdr_lib/tx_buffer.v b/usrp/fpga/sdr_lib/tx_buffer.v
index ff8fd839dc4d50b54f5dfb2c22e4e3a7ebb96b7f..63202c9df9b66bcc3d8a6f9239f51962559abdb9 100644 (file)
--- a/usrp/fpga/sdr_lib/tx_buffer.v
+++ b/usrp/fpga/sdr_lib/tx_buffer.v
@@ -66,20 +66,20 @@ module tx_buffer
          load_next <= #1 4'd0;
        end
      else
-       if((load_next != channels) & !tx_empty)
+       if(load_next != channels)
         begin
            load_next <= #1 load_next + 4'd1;
            case(load_next)
-             4'd0 : tx_i_0 <= #1 fifodata;
-             4'd1 : tx_q_0 <= #1 fifodata;
-             4'd2 : tx_i_1 <= #1 fifodata;
-             4'd3 : tx_q_1 <= #1 fifodata;
-             4'd4 : tx_i_2 <= #1 fifodata;
-             4'd5 : tx_q_2 <= #1 fifodata;
-             4'd6 : tx_i_3 <= #1 fifodata;
-             4'd7 : tx_q_3 <= #1 fifodata;
+             4'd0 : tx_i_0 <= #1 tx_empty ? 16'd0 : fifodata;
+             4'd1 : tx_q_0 <= #1 tx_empty ? 16'd0 : fifodata;
+             4'd2 : tx_i_1 <= #1 tx_empty ? 16'd0 : fifodata;
+             4'd3 : tx_q_1 <= #1 tx_empty ? 16'd0 : fifodata;
+             4'd4 : tx_i_2 <= #1 tx_empty ? 16'd0 : fifodata;
+             4'd5 : tx_q_2 <= #1 tx_empty ? 16'd0 : fifodata;
+             4'd6 : tx_i_3 <= #1 tx_empty ? 16'd0 : fifodata;
+             4'd7 : tx_q_3 <= #1 tx_empty ? 16'd0 : fifodata;
            endcase // case(load_next)
-        end // if ((load_next != channels) & !tx_empty)
+        end // if (load_next != channels)
        else if(txstrobe & (load_next == channels))
         begin
            load_next <= #1 4'd0;

diff --git a/usrp/fpga/toplevel/usrp_std/usrp_std.qsf b/usrp/fpga/toplevel/usrp_std/usrp_std.qsf
index 1503c8cc6d7c8f3be394249a1bd36afff37ce4be..8297f0f7bb148c3cf4373221fd0913e52a85b72e 100644 (file)
--- a/usrp/fpga/toplevel/usrp_std/usrp_std.qsf
+++ b/usrp/fpga/toplevel/usrp_std/usrp_std.qsf
@@ -27,7 +27,7 @@
 # ========================
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04  JULY 13, 2003"
-set_global_assignment -name LAST_QUARTUS_VERSION "6.0 SP1"
+set_global_assignment -name LAST_QUARTUS_VERSION 6.1
 
 # Pin & Location Assignments
 # ==========================