Fix warnings, mostly from implicitly defined wires or unspecified widths

diff --git a/usrp2/fpga/serdes/serdes_tx.v b/usrp2/fpga/serdes/serdes_tx.v
index c74414e925cb5f27a88fbd84dcf34375a20e1ec7..2e5e3bd80c20a4bf93a7bda5c819a509eb21ff0c 100644 (file)
--- a/usrp2/fpga/serdes/serdes_tx.v
+++ b/usrp2/fpga/serdes/serdes_tx.v
@@ -84,7 +84,7 @@ module serdes_tx
    wire        rd_eop_i  = rd_flags_i[1];
    wire [1:0]  rd_occ_i = rd_flags_i[3:2];  // Unused
 
-   wire        have_data, empty;
+   wire        have_data, empty, read;
    fifo_cascade #(.WIDTH(34),.SIZE(FIFOSIZE)) serdes_tx_fifo
      (.clk(clk),.reset(rst),.clear(0),
       .datain({rd_sop_i,rd_eop_i,rd_dat_i}), .src_rdy_i(rd_ready_i), .dst_rdy_o(rd_ready_o),

diff --git a/usrp2/fpga/simple_gemac/flow_ctrl_rx.v b/usrp2/fpga/simple_gemac/flow_ctrl_rx.v
index b13334d0ec389583a5214d5c2f23ccd5fce01dac..d09bf377f6f13e87b5070ffb4be03f5b6de1d724 100644 (file)
--- a/usrp2/fpga/simple_gemac/flow_ctrl_rx.v
+++ b/usrp2/fpga/simple_gemac/flow_ctrl_rx.v
@@ -42,6 +42,7 @@ module flow_ctrl_rx
        countdown <= countdown - 1;\r
 \r
    // Cross clock domains\r
+   wire        xon_tx, xoff_tx;\r
    oneshot_2clk send_xon (.clk_in(rx_clk), .in(xon), .clk_out(tx_clk), .out(xon_tx));\r
    oneshot_2clk send_xoff (.clk_in(rx_clk), .in(xoff), .clk_out(tx_clk), .out(xoff_tx));\r
    \r

diff --git a/usrp2/fpga/simple_gemac/simple_gemac.v b/usrp2/fpga/simple_gemac/simple_gemac.v
index 868a668199a43daa411c7f637e5c170f5b1c4019..e7f327358fb8ff7f95da595091477bb0ceb80b40 100644 (file)
--- a/usrp2/fpga/simple_gemac/simple_gemac.v
+++ b/usrp2/fpga/simple_gemac/simple_gemac.v
@@ -26,7 +26,8 @@ module simple_gemac
    reset_sync reset_sync_rx (.clk(rx_clk),.reset_in(reset),.reset_out(rst_rxclk));
 
    wire [15:0] pause_quanta_rcvd;
-
+   wire        pause_rcvd, pause_apply, paused;
+   
    simple_gemac_tx simple_gemac_tx
      (.clk125(clk125),.reset(rst_txclk),
       .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),

diff --git a/usrp2/fpga/simple_gemac/simple_gemac_rx.v b/usrp2/fpga/simple_gemac/simple_gemac_rx.v
index bad43a60704d339f6d35f050710fef21ffff4ba4..45ddd6dfa7f9c282ebcea5da032e486498e16930 100644 (file)
--- a/usrp2/fpga/simple_gemac/simple_gemac_rx.v
+++ b/usrp2/fpga/simple_gemac/simple_gemac_rx.v
@@ -47,7 +47,7 @@ module simple_gemac_rx
 
    localparam DELAY  = 6;
    delay_line #(.WIDTH(10)) rx_delay
-     (.clk(rx_clk), .delay(DELAY), .din({rx_dv_d1,rx_er_d1,rxd_d1}),.dout({rx_dv_del,rx_er_dl,rxd_del}));
+     (.clk(rx_clk), .delay(DELAY), .din({rx_dv_d1,rx_er_d1,rxd_d1}),.dout({rx_dv_del,rx_er_del,rxd_del}));
 
    always @(posedge rx_clk)
      if(reset)

diff --git a/usrp2/fpga/simple_gemac/simple_gemac_wrapper.v b/usrp2/fpga/simple_gemac/simple_gemac_wrapper.v
index 71ad0cf0f7bb7e0e42c2b1f018af48c990ffc49e..efcf89276c690b3f7179d6381bf4fb6df60297a6 100644 (file)
--- a/usrp2/fpga/simple_gemac/simple_gemac_wrapper.v
+++ b/usrp2/fpga/simple_gemac/simple_gemac_wrapper.v
@@ -19,13 +19,15 @@ module simple_gemac_wrapper
     // MIIM
     inout mdio, output mdc,
     output [31:0] debug);
-   
+
+   wire          clear = 0;
    wire [7:0]    rx_data, tx_data;
    wire          tx_clk, tx_valid, tx_error, tx_ack;
    wire          rx_clk, rx_valid, rx_error, rx_ack;
    
    wire [47:0]           ucast_addr, mcast_addr;
    wire          pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all;
+   wire          pause_req;
    wire          pause_request_en, pause_respect_en;
    wire [15:0]           pause_time, pause_thresh, pause_time_req, rx_fifo_space;
    
@@ -75,15 +77,15 @@ module simple_gemac_wrapper
    rxmac_to_ll8 rx_adapt
      (.clk(rx_clk), .reset(rx_reset), .clear(0),
       .rx_data(rx_data), .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack),
-      .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), .ll_error(rx_ll_error),
+      .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), .ll_error(),  // error also encoded in sof/eof
       .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy));
 
    ll8_shortfifo rx_sfifo
      (.clk(rx_clk), .reset(rx_reset), .clear(0),
       .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof),
-      .error_i(rx_ll_error), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy),
+      .error_i(0), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy),
       .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2),
-      .error_o(rx_ll_error2), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2));
+      .error_o(), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2));
 
    assign rx_ll_dst_rdy2  = ~rx_ll_dst_rdy2_n;
    assign rx_ll_src_rdy2_n = ~rx_ll_src_rdy2;

diff --git a/usrp2/fpga/top/u2_core/u2_core.v b/usrp2/fpga/top/u2_core/u2_core.v
index 1f78f6d3d5eb49477dd05f9d229fe7aa2fcda76c..03016e9b3cbaafb46d786a9373049eb6a075ca06 100755 (executable)
--- a/usrp2/fpga/top/u2_core/u2_core.v
+++ b/usrp2/fpga/top/u2_core/u2_core.v
@@ -525,9 +525,11 @@ module u2_core
      (.clk(wb_clk),.rst(wb_rst),
       .sd_clk(sd_clk),.sd_csn(sd_csn),.sd_mosi(sd_mosi),.sd_miso(sd_miso),
       .wb_cyc_i(sd_cyc),.wb_stb_i(sd_stb),.wb_we_i(sd_we),
-      .wb_adr_i(sd_adr[3:2]),.wb_dat_i(sd_dat_o),.wb_dat_o(sd_dat_i),
+      .wb_adr_i(sd_adr[3:2]),.wb_dat_i(sd_dat_o[7:0]),.wb_dat_o(sd_dat_i[7:0]),
       .wb_ack_o(sd_ack) );
 
+   assign sd_dat_i[31:8] = 0;
+
    // /////////////////////////////////////////////////////////////////////////
    // DSP
    wire [31:0]          sample_rx, sample_tx;